//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    z_data_mux.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-05-13      PWY             debug top-level
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module z_data_mux (
//system port
   input         clk                             // System Main Clock
  ,input         rst_n                           // Spi Reset active low
  //---------------from ctrl regfile------------------------------------
  ,input         sel                             // 1'b0 --> mod modem data; 1'b1 --> mod nco data
  //Z dsp data
  ,input  [15:0] z_dsp_data0
  ,input  [15:0] z_dsp_data1
  ,input  [15:0] z_dsp_data2
  ,input  [15:0] z_dsp_data3
  //XY dsp data
  ,input  [15:0] xy_dsp_data0
  ,input  [15:0] xy_dsp_data1
  ,input  [15:0] xy_dsp_data2
  ,input  [15:0] xy_dsp_data3
  //mux out data
  ,output [15:0] mux_data_0
  ,output [15:0] mux_data_1
  ,output [15:0] mux_data_2
  ,output [15:0] mux_data_3
);


wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;

x-special/nautilus-clipboard
copy
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v
sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
endmodule