//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    dacif.v
//  Department            :    
//  Author                :    PWY
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.2         2024-10-09      thfu            modify port from 4 to 8 to fit
//  8 interpolation
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module lsdacif (
   input         clk
  ,input         rstn
  //DAC mode select
  ,input  [1:0]  dac_mode_sel         //2'b00:NRZ mode;2'b01:Double data mode;
                                      //2'b10:Double Double data mode;2'b11:reserve;
  ,input  [1 :0] intp_mode            //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
  //mixer data input 
  ,input  [15:0] din0
  ,input  [15:0] din1
  ,input  [15:0] din2
  ,input  [15:0] din3
  ,input  [15:0] din4
  ,input  [15:0] din5
  ,input  [15:0] din6
  ,input  [15:0] din7

  //data output
  ,output [15:0] dout0
  ,output [15:0] dout1
  ,output [15:0] dout2
  ,output [15:0] dout3
  ,output [15:0] dout4
  ,output [15:0] dout5
  ,output [15:0] dout6
  ,output [15:0] dout7

);

////////////////////////////////////////////////////
// regs
////////////////////////////////////////////////////
reg [15:0] dout0_r ;
reg [15:0] dout1_r ;
reg [15:0] dout2_r ;
reg [15:0] dout3_r ;
reg [15:0] dout4_r ;
reg [15:0] dout5_r ;
reg [15:0] dout6_r ;
reg [15:0] dout7_r ;

////////////////////////////////////////////////////
// intp mode select
////////////////////////////////////////////////////
/*
always@(posedge clk) begin
  case(intp_mode)
    2'b00  : begin
	         	  mux_p_0   <= {~din0[15],din0[14:0]};
			  mux_p_1   <= 16'h0;
			  mux_p_2   <= 16'h0;
			  mux_p_3   <= 16'h0;
	end
    2'b01  : begin
	         	  mux_p_0   <= {~din0[15],din0[14:0]};
			  mux_p_1   <= {~din1[15],din1[14:0]};
			  mux_p_2   <= 16'h0  ;
			  mux_p_3   <= 16'h0  ;
	end
    2'b10  : begin
	         	  mux_p_0   <= {~din0[15],din0[14:0]}  ;
			  mux_p_1   <= {~din1[15],din1[14:0]}  ;
			  mux_p_2   <= {~din2[15],din2[14:0]}  ;
			  mux_p_3   <= {~din3[15],din3[14:0]};
	end
	default : begin
	         	  mux_p_0   <= {~din0[15],din0[14:0]}  ;
			  mux_p_1   <= {~din1[15],din1[14:0]}  ;
			  mux_p_2   <= {~din2[15],din2[14:0]}  ;
			  mux_p_3   <= {~din3[15],din3[14:0]}  ;
	end
  endcase
end  
*/
////////////////////////////////////////////////////
// mode select
////////////////////////////////////////////////////
always @(posedge clk or negedge rstn) begin
  if(rstn == 1'b0) begin
    dout0_r  <= 16'h0;
    dout1_r  <= 16'h0;
    dout2_r  <= 16'h0;
    dout3_r  <= 16'h0; 
    dout4_r  <= 16'h0;
    dout5_r  <= 16'h0;
    dout6_r  <= 16'h0;
    dout7_r  <= 16'h0; 

  end
  else begin
    case(dac_mode_sel)
	  2'b00    : begin
			     dout0_r  <= {~din0[15],din0[14:0]};
		             dout1_r  <= {~din1[15],din1[14:0]};
		             dout2_r  <= {~din2[15],din2[14:0]};
		             dout3_r  <= {~din3[15],din3[14:0]};
 			     dout4_r  <= {~din4[15],din4[14:0]};
		             dout5_r  <= {~din5[15],din5[14:0]};
		             dout6_r  <= {~din6[15],din6[14:0]};
		             dout7_r  <= {~din7[15],din7[14:0]};

		     end
	  2'b01    : begin
			     dout0_r  <= {~din0[15],din0[14:0]};
		             dout1_r  <= {~din0[15],din0[14:0]};
		             dout2_r  <= {~din1[15],din1[14:0]};
		             dout3_r  <= {~din1[15],din1[14:0]};
 			     dout4_r  <= {~din2[15],din2[14:0]};
		             dout5_r  <= {~din2[15],din2[14:0]};
		             dout6_r  <= {~din3[15],din3[14:0]};
		             dout7_r  <= {~din3[15],din3[14:0]};

		     end
	  2'b10    : begin
			     dout0_r  <= {~din0[15],din0[14:0]};
		             dout1_r  <= {~din0[15],din0[14:0]};
		             dout2_r  <= {~din0[15],din0[14:0]};
		             dout3_r  <= {~din0[15],din0[14:0]}; 
			     dout4_r  <= {~din1[15],din1[14:0]};
		             dout5_r  <= {~din1[15],din1[14:0]};
		             dout6_r  <= {~din1[15],din1[14:0]};
		             dout7_r  <= {~din1[15],din1[14:0]}; 

		     end
	  default  : begin
			     dout0_r  <= {~din0[15],din0[14:0]};
		             dout1_r  <= {~din1[15],din1[14:0]};
		             dout2_r  <= {~din2[15],din2[14:0]};
		             dout3_r  <= {~din3[15],din3[14:0]};
  			     dout4_r  <= {~din4[15],din4[14:0]};
		             dout5_r  <= {~din5[15],din5[14:0]};
		             dout6_r  <= {~din6[15],din6[14:0]};
		             dout7_r  <= {~din7[15],din7[14:0]};

		     end
	endcase
  end
end

assign dout0  = dout0_r  ;
assign dout1  = dout1_r  ;
assign dout2  = dout2_r  ;
assign dout3  = dout3_r  ;
assign dout4  = dout4_r  ;
assign dout5  = dout5_r  ;
assign dout6  = dout6_r  ;
assign dout7  = dout7_r  ;

endmodule