*design* DebussyLib (btIdent Verdi_O-2018.09-SP2)
Command arguments:
    +define+verilog
    -f files.f
        ../rtl/Tail/diff.v
        ../rtl/Tail/DW02_mult.v
        ../rtl/Tail/IIR_Filter.v
        ../rtl/Tail/lsdacif.v
        ../rtl/Tail/MeanIntp_8.v
        ../rtl/Tail/mult_C.v
        ../rtl/Tail/TailCorr_top.v
        ../rtl/Tail/sirv_gnrl_dffs.v
        ../rtl/Tail/sirv_gnrl_xchecker.v
        ../rtl/nco/coef_s.v
        ../rtl/nco/nco.v
        ../rtl/nco/coef_c.v
        ../rtl/nco/ph2amp.v
        ../rtl/nco/sin_op.v
        ../rtl/nco/p_nco.v
        ../rtl/nco/pipe_add_48bit.v
        ../rtl/nco/cos_op.v
        ../rtl/nco/pipe_acc_48bit.v
        ../rtl/nco/DW_mult_pipe.v
        ../tb/tb_mean8_top.v
        ../tb/clk_gen.v
    -top
    TB

Highest level modules:
lsdacif
TailCorr_top
sirv_gnrl_dfflrs
sirv_gnrl_dfflr
sirv_gnrl_dfflrd
sirv_gnrl_dffl
sirv_gnrl_dffrs
sirv_gnrl_dffr
sirv_gnrl_ltch
PIPE3_ADD_48BIT
TB

Total	0 error(s),   0 warning(s)