//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : Z_dsp.v // Department : // Author : thfu // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.2 2024-10-09 thfu to fit the addition of 8 interpolation //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module z_dsp ( input rstn ,input clk ,input en //,input tc_bypass ,input [5:0] vldi_coef ,input vldi_data //,input [1:0] intp_mode //,input [1:0] dac_mode_sel ,input signed [15:0] din0 ,input signed [15:0] din1 ,input signed [15:0] din2 ,input signed [15:0] din3 ,input signed [31 :0] a_re [5:0] ,input signed [31 :0] a_im [5:0] ,input signed [31 :0] b_re [5:0] ,input signed [31 :0] b_im [5:0] ,output signed [15:0] dout0 ,output signed [15:0] dout1 ,output signed [15:0] dout2 ,output signed [15:0] dout3 ,output vldo ); wire signed [15:0] IIR_out; wire signed [31:0] ao_re [5:0]; wire signed [31:0] ao_im [5:0]; wire signed [31:0] ab_re [5:0]; wire signed [31:0] ab_im [5:0]; wire signed [31:0] abb_re [5:0]; wire signed [31:0] abb_im [5:0]; wire signed [31:0] ab_pow3_re [5:0]; wire signed [31:0] ab_pow3_im [5:0]; wire signed [31:0] ab_pow4_re [5:0]; wire signed [31:0] ab_pow4_im [5:0]; wire signed [31:0] ab_pow5_re [5:0]; wire signed [31:0] ab_pow5_im [5:0]; wire signed [31:0] ab_pow6_re [5:0]; wire signed [31:0] ab_pow6_im [5:0]; wire signed [31:0] ab_pow7_re [5:0]; wire signed [31:0] ab_pow7_im [5:0]; wire signed [31:0] b_pow8_re [5:0]; wire signed [31:0] b_pow8_im [5:0]; CoefGen inst_CoefGen( .clk (clk ), .rstn (rstn ), .vldi (vldi_coef ), .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .ao_re (ao_re ), .ao_im (ao_im ), .ab_re (ab_re ), .ab_im (ab_im ), .abb_re (abb_re ), .abb_im (abb_im ), .ab_pow3_re (ab_pow3_re ), .ab_pow3_im (ab_pow3_im ), .ab_pow4_re (ab_pow4_re ), .ab_pow4_im (ab_pow4_im ), .ab_pow5_re (ab_pow5_re ), .ab_pow5_im (ab_pow5_im ), .ab_pow6_re (ab_pow6_re ), .ab_pow6_im (ab_pow6_im ), .ab_pow7_re (ab_pow7_re ), .ab_pow7_im (ab_pow7_im ), .b_pow8_re (b_pow8_re ), .b_pow8_im (b_pow8_im ) ); wire signed [15:0] dout_0; wire signed [15:0] dout_1; wire signed [15:0] dout_2; wire signed [15:0] dout_3; wire signed [15:0] dout_4; wire signed [15:0] dout_5; wire signed [15:0] dout_6; wire signed [15:0] dout_7; reg vldo_TC; TailCorr_top inst_TailCorr_top ( .clk (clk ), .en (en ), .rstn (rstn ), .vldi (vldi_data ), // .dac_mode_sel (dac_mode_sel ), // .intp_mode (intp_mode ), .din0 (din0 ), .din1 (din1 ), .din2 (din2 ), .din3 (din3 ), .a_re0 (ao_re[0] ), .a_im0 (ao_im[0] ), .ab_re0 (ab_re[0] ), .ab_im0 (ab_im[0] ), .abb_re0 (abb_re[0] ), .abb_im0 (abb_im[0] ), .ab_pow3_re0 (ab_pow3_re[0]), .ab_pow3_im0 (ab_pow3_im[0]), .ab_pow4_re0 (ab_pow4_re[0]), .ab_pow4_im0 (ab_pow4_im[0]), .ab_pow5_re0 (ab_pow5_re[0]), .ab_pow5_im0 (ab_pow5_im[0]), .ab_pow6_re0 (ab_pow6_re[0]), .ab_pow6_im0 (ab_pow6_im[0]), .ab_pow7_re0 (ab_pow7_re[0]), .ab_pow7_im0 (ab_pow7_im[0]), .b_pow8_re0 (b_pow8_re[0] ), .b_pow8_im0 (b_pow8_im[0] ), .a_re1 (ao_re[1] ), .a_im1 (ao_im[1] ), .ab_re1 (ab_re[1] ), .ab_im1 (ab_im[1] ), .abb_re1 (abb_re[1] ), .abb_im1 (abb_im[1] ), .ab_pow3_re1 (ab_pow3_re[1]), .ab_pow3_im1 (ab_pow3_im[1]), .ab_pow4_re1 (ab_pow4_re[1]), .ab_pow4_im1 (ab_pow4_im[1]), .ab_pow5_re1 (ab_pow5_re[1]), .ab_pow5_im1 (ab_pow5_im[1]), .ab_pow6_re1 (ab_pow6_re[1]), .ab_pow6_im1 (ab_pow6_im[1]), .ab_pow7_re1 (ab_pow7_re[1]), .ab_pow7_im1 (ab_pow7_im[1]), .b_pow8_re1 (b_pow8_re[1] ), .b_pow8_im1 (b_pow8_im[1] ), .a_re2 (ao_re[2] ), .a_im2 (ao_im[2] ), .ab_re2 (ab_re[2] ), .ab_im2 (ab_im[2] ), .abb_re2 (abb_re[2] ), .abb_im2 (abb_im[2] ), .ab_pow3_re2 (ab_pow3_re[2]), .ab_pow3_im2 (ab_pow3_im[2]), .ab_pow4_re2 (ab_pow4_re[2]), .ab_pow4_im2 (ab_pow4_im[2]), .ab_pow5_re2 (ab_pow5_re[2]), .ab_pow5_im2 (ab_pow5_im[2]), .ab_pow6_re2 (ab_pow6_re[2]), .ab_pow6_im2 (ab_pow6_im[2]), .ab_pow7_re2 (ab_pow7_re[2]), .ab_pow7_im2 (ab_pow7_im[2]), .b_pow8_re2 (b_pow8_re[2] ), .b_pow8_im2 (b_pow8_im[2] ), .a_re3 (ao_re[3] ), .a_im3 (ao_im[3] ), .ab_re3 (ab_re[3] ), .ab_im3 (ab_im[3] ), .abb_re3 (abb_re[3] ), .abb_im3 (abb_im[3] ), .ab_pow3_re3 (ab_pow3_re[3]), .ab_pow3_im3 (ab_pow3_im[3]), .ab_pow4_re3 (ab_pow4_re[3]), .ab_pow4_im3 (ab_pow4_im[3]), .ab_pow5_re3 (ab_pow5_re[3]), .ab_pow5_im3 (ab_pow5_im[3]), .ab_pow6_re3 (ab_pow6_re[3]), .ab_pow6_im3 (ab_pow6_im[3]), .ab_pow7_re3 (ab_pow7_re[3]), .ab_pow7_im3 (ab_pow7_im[3]), .b_pow8_re3 (b_pow8_re[3] ), .b_pow8_im3 (b_pow8_im[3] ), .a_re4 (ao_re[4] ), .a_im4 (ao_im[4] ), .ab_re4 (ab_re[4] ), .ab_im4 (ab_im[4] ), .abb_re4 (abb_re[4] ), .abb_im4 (abb_im[4] ), .ab_pow3_re4 (ab_pow3_re[4]), .ab_pow3_im4 (ab_pow3_im[4]), .ab_pow4_re4 (ab_pow4_re[4]), .ab_pow4_im4 (ab_pow4_im[4]), .ab_pow5_re4 (ab_pow5_re[4]), .ab_pow5_im4 (ab_pow5_im[4]), .ab_pow6_re4 (ab_pow6_re[4]), .ab_pow6_im4 (ab_pow6_im[4]), .ab_pow7_re4 (ab_pow7_re[4]), .ab_pow7_im4 (ab_pow7_im[4]), .b_pow8_re4 (b_pow8_re[4] ), .b_pow8_im4 (b_pow8_im[4] ), .a_re5 (ao_re[5] ), .a_im5 (ao_im[5] ), .ab_re5 (ab_re[5] ), .ab_im5 (ab_im[5] ), .abb_re5 (abb_re[5] ), .abb_im5 (abb_im[5] ), .ab_pow3_re5 (ab_pow3_re[5]), .ab_pow3_im5 (ab_pow3_im[5]), .ab_pow4_re5 (ab_pow4_re[5]), .ab_pow4_im5 (ab_pow4_im[5]), .ab_pow5_re5 (ab_pow5_re[5]), .ab_pow5_im5 (ab_pow5_im[5]), .ab_pow6_re5 (ab_pow6_re[5]), .ab_pow6_im5 (ab_pow6_im[5]), .ab_pow7_re5 (ab_pow7_re[5]), .ab_pow7_im5 (ab_pow7_im[5]), .b_pow8_re5 (b_pow8_re[5] ), .b_pow8_im5 (b_pow8_im[5] ), .dout_p0 (dout_0 ), .dout_p1 (dout_1 ), .dout_p2 (dout_2 ), .dout_p3 (dout_3 ), .dout_p4 (dout_4 ), .dout_p5 (dout_5 ), .dout_p6 (dout_6 ), .dout_p7 (dout_7 ), .vldo (vldo_TC ) ); /* parameter Delay = 2; reg [Delay:0] vldo_r; always@(posedge clk or negedge rstn) if(!rstn) begin vldo_r <= 2'b0; end else begin vldo_r <= {vldo_r[Delay:0], vldo_TC};//Delay with 9 clk end */ assign vldo = vldo_TC; reg signed [15:0] doutf_0; reg signed [15:0] doutf_1; reg signed [15:0] doutf_2; reg signed [15:0] doutf_3; always@(posedge clk or negedge rstn) if(!rstn) begin doutf_0 <= 0; doutf_1 <= 0; doutf_2 <= 0; doutf_3 <= 0; end else if(!en) begin doutf_0 <= dout_0; doutf_1 <= dout_1; doutf_2 <= dout_2; doutf_3 <= dout_3; end else begin doutf_0 <= dout_4; doutf_1 <= dout_5; doutf_2 <= dout_6; doutf_3 <= dout_7; end assign dout0 = doutf_0; assign dout1 = doutf_1; assign dout2 = doutf_2; assign dout3 = doutf_3; endmodule