//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : TailCorr_top.v // Department : // Author : thfu // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.3 2024-05-15 thfu //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_top #( parameter temp_var_width = 20 ,parameter data_out_width = 18 ) ( input rstn ,input clk ,input en ,input signed [15 :0] IIRin_p0 // x(8n+9) ,input signed [15 :0] IIRin_p1 // x(8n+10) ,input signed [15 :0] IIRin_p2 // x(8n+11) ,input signed [15 :0] IIRin_p3 // x(8n+12) ,input signed [15 :0] IIRin_p4 // x(8n+13) ,input signed [15 :0] IIRin_p5 // x(8n+14) ,input signed [15 :0] IIRin_p6 // x(8n+15) ,input signed [15 :0] IIRin_p7 // x(8n+16) ,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) ,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) ,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) ,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) ,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) ,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) ,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) ,input signed [31 :0] a_re ,input signed [31 :0] a_im ,input signed [31 :0] b_re ,input signed [31 :0] b_im ,input signed [31 :0] ab_re ,input signed [31 :0] ab_im ,input signed [31 :0] abb_re ,input signed [31 :0] abb_im ,input signed [31 :0] ab_pow3_re ,input signed [31 :0] ab_pow3_im ,input signed [31 :0] ab_pow4_re ,input signed [31 :0] ab_pow4_im ,input signed [31 :0] ab_pow5_re ,input signed [31 :0] ab_pow5_im ,input signed [31 :0] ab_pow6_re ,input signed [31 :0] ab_pow6_im ,input signed [31 :0] ab_pow7_re ,input signed [31 :0] ab_pow7_im ,input signed [31 :0] b_pow8_re ,input signed [31 :0] b_pow8_im ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) ,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38) ,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53) ,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68) ,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) ,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ); wire signed [temp_var_width-1:0] IIRout_p0_re; wire signed [temp_var_width-1:0] IIRout_p1_re; wire signed [temp_var_width-1:0] IIRout_p2_re; wire signed [temp_var_width-1:0] IIRout_p3_re; wire signed [temp_var_width-1:0] IIRout_p4_re; wire signed [temp_var_width-1:0] IIRout_p5_re; wire signed [temp_var_width-1:0] IIRout_p6_re; wire signed [temp_var_width-1:0] IIRout_p7_re; wire signed [temp_var_width-1:0] IIRout_p0_im; wire signed [temp_var_width-1:0] IIRout_p1_im; wire signed [temp_var_width-1:0] IIRout_p2_im; wire signed [temp_var_width-1:0] IIRout_p3_im; wire signed [temp_var_width-1:0] IIRout_p4_im; wire signed [temp_var_width-1:0] IIRout_p5_im; wire signed [temp_var_width-1:0] IIRout_p6_im; wire signed [temp_var_width-1:0] IIRout_p7_im; IIR_Filter_p8 inst_iir_p0 ( .clk (clk ), .rstn (rstn ), .en (en ), .dinp0 (IIRin_p7 ), // x(8n+16) .dinp1 (IIRin_p6 ), // x(8n+15) .dinp2 (IIRin_p5 ), // x(8n+14) .dinp3 (IIRin_p4 ), // x(8n+13) .dinp4 (IIRin_p3 ), // x(8n+12) .dinp5 (IIRin_p2 ), // x(8n+11) .dinp6 (IIRin_p1 ), // x(8n+10) .dinp7 (IIRin_p0 ), // x(8n+9) .a_re (a_re ), .a_im (a_im ), .ab_re (ab_re ), .ab_im (ab_im ), .abb_re (abb_re ), .abb_im (abb_im ), .ab_pow3_re (ab_pow3_re ), .ab_pow3_im (ab_pow3_im ), .ab_pow4_re (ab_pow4_re ), .ab_pow4_im (ab_pow4_im ), .ab_pow5_re (ab_pow5_re ), .ab_pow5_im (ab_pow5_im ), .ab_pow6_re (ab_pow6_re ), .ab_pow6_im (ab_pow6_im ), .ab_pow7_re (ab_pow7_re ), .ab_pow7_im (ab_pow7_im ), .b_pow8_re (b_pow8_re ), .b_pow8_im (b_pow8_im ), .dout_re (IIRout_p0_re ), // Re(y(8n-8)) .dout_im (IIRout_p0_im ) // Im(y(8n-8)) ); IIR_Filter_p1 inst_iir_p1 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p0_r2 ), // x(8n-7) .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) .dout_r1_im (IIRout_p0_im ), // Im(y(8n-8)) .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .dout_re (IIRout_p1_re ), // Re(y(8n-23)) .dout_im (IIRout_p1_im ) // Im(y(8n-23)) ); IIR_Filter_p1 inst_iir_p2 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p1_r4 ), // x(8n-22) .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) .dout_r1_im (IIRout_p1_im ), // Im(y(8n-23)) .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .dout_re (IIRout_p2_re ), // Re(y(8n-38)) .dout_im (IIRout_p2_im ) // Im(y(8n-38)) ); IIR_Filter_p1 inst_iir_p3 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p2_r6 ), // x(8n-37) .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) .dout_r1_im (IIRout_p2_im ), // Im(y(8n-38)) .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .dout_re (IIRout_p3_re ), // Re(y(8n-53)) .dout_im (IIRout_p3_im ) // Im(y(8n-53)) ); IIR_Filter_p1 inst_iir_p4 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p3_r8 ), // x(8n-52) .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) .dout_r1_im (IIRout_p3_im ), // Im(y(8n-53)) .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .dout_re (IIRout_p4_re ), // Re(y(8n-68)) .dout_im (IIRout_p4_im ) // Im(y(8n-68)) ); IIR_Filter_p1 inst_iir_p5 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p4_r10 ), // x(8n-67) .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) .dout_r1_im (IIRout_p4_im ), // Im(y(8n-68)) .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .dout_re (IIRout_p5_re ), // Re(y(8n-83)) .dout_im (IIRout_p5_im ) // Im(y(8n-83)) ); IIR_Filter_p1 inst_iir_p6 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p5_r12 ), // x(8n-82) .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) .dout_r1_im (IIRout_p5_im ), // Im(y(8n-83)) .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .dout_re (IIRout_p6_re ), // Re(y(8n-98)) .dout_im (IIRout_p6_im ) // Im(y(8n-98)) ); IIR_Filter_p1 inst_iir_p7 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p6_r14 ), // x(8n-97) .dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) .dout_r1_im (IIRout_p6_im ), // Im(y(8n-98)) .a_re (a_re ), .a_im (a_im ), .b_re (b_re ), .b_im (b_im ), .dout_re (IIRout_p7_re ), // Re(y(8n-113)) .dout_im (IIRout_p7_im ) // Im(y(8n-113)) ); assign IIRout_p0 = IIRout_p0_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-8) assign IIRout_p1 = IIRout_p1_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-23) assign IIRout_p2 = IIRout_p2_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-38) assign IIRout_p3 = IIRout_p3_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-53) assign IIRout_p4 = IIRout_p4_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-68) assign IIRout_p5 = IIRout_p5_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-83) assign IIRout_p6 = IIRout_p6_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-98) assign IIRout_p7 = IIRout_p7_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-113) endmodule