Compare commits
2 Commits
| Author | SHA1 | Date |
|---|---|---|
 thfu
|
728532bd61 | |
futh0403
|
6e386a2743 |
|
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@ -33,10 +33,12 @@
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//-FHDR--------------------------------------------------------------------------------------------------------
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module IIR_Filter_p1 #(
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parameter coef_width = 32
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,parameter a_width = 18
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,parameter b_width = 18
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,parameter data_in_width = 16
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,parameter cascade_in_width = 37
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,parameter temp_var_width = cascade_in_width - 1
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,parameter data_out_width = cascade_in_width - 2
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,parameter cascade_in_width = 16
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,parameter data_out_width = 16
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,parameter temp_var_width = data_out_width + 1
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)
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//H(z) = a / (1 - b*z^-1)
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(
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@ -72,8 +74,8 @@ wire signed [data_out_width-1:0] y_im_trunc;
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mult_x
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#(
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.A_width (data_in_width )
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,.C_width (coef_width )
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,.D_width (coef_width )
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,.C_width (a_width )
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,.D_width (a_width )
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,.o_width (temp_var_width )
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)
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inst_c1 (
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@ -81,8 +83,8 @@ inst_c1 (
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.rstn (rstn ),
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.en (en ),
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.a (din_re ),
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.c (a_re ),
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.d (a_im ),
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.c (a_re[coef_width-1 : coef_width-a_width]),
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.d (a_im[coef_width-1 : coef_width-a_width]),
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.Re (x1_re ),
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.Im (x1_im )
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);
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@ -94,8 +96,8 @@ mult_C
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#(
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.A_width (cascade_in_width )
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,.B_width (cascade_in_width )
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,.C_width (coef_width )
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,.D_width (coef_width )
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,.C_width (b_width )
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,.D_width (b_width )
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,.o_width (temp_var_width )
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)
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inst_c3 (
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@ -104,8 +106,8 @@ inst_c3 (
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.en (en ),
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.a (dout_r1_re ),
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.b (dout_r1_im ),
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.c (b_re ),
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.d (b_im ),
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.c (b_re[coef_width-1 : coef_width-b_width]),
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.d (b_im[coef_width-1 : coef_width-b_width]),
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.Re (y1_re ),
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.Im (y1_im )
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);
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@ -1,41 +1,10 @@
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : IIR_Filter.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.4 2024-05-28 thfu
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//2024-05-28 10:22:49
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module IIR_Filter_p8 #(
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parameter coef_width = 32
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,parameter b_pow8_width = 29
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,parameter ab_pow_width = 32
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,parameter data_in_width = 16
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,parameter data_out_width = 37
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,parameter temp_var_width = data_out_width+5
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,parameter data_out_width = 16
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,parameter temp_var_width = 29
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)
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// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
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(
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@ -74,9 +43,36 @@ module IIR_Filter_p8 #(
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,output signed [data_out_width-1:0] dout_im // Im(y(8n-8))
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);
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wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0};
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wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re };
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wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im };
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wire signed [data_in_width-1 :0] dinp [7:0];
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assign dinp[7] = dinp7;
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assign dinp[6] = dinp6;
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assign dinp[5] = dinp5;
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assign dinp[4] = dinp4;
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assign dinp[3] = dinp3;
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assign dinp[2] = dinp2;
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assign dinp[1] = dinp1;
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assign dinp[0] = dinp0;
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wire signed [ab_pow_width-1 :0] ab_pow_re [7:0];
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assign ab_pow_re[7] = ab_pow7_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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assign ab_pow_re[6] = ab_pow6_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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assign ab_pow_re[5] = ab_pow5_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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assign ab_pow_re[4] = ab_pow4_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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assign ab_pow_re[3] = ab_pow3_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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assign ab_pow_re[2] = abb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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assign ab_pow_re[1] = ab_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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assign ab_pow_re[0] = a_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
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wire signed [ab_pow_width-1 :0] ab_pow_im [7:0];
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assign ab_pow_im[7] = ab_pow7_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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assign ab_pow_im[6] = ab_pow6_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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assign ab_pow_im[5] = ab_pow5_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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assign ab_pow_im[4] = ab_pow4_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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assign ab_pow_im[3] = ab_pow3_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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assign ab_pow_im[2] = abb_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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assign ab_pow_im[1] = ab_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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assign ab_pow_im[0] = a_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
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wire signed [temp_var_width-1 :0] x_re [0:7];
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wire signed [temp_var_width-1 :0] x_im [0:7];
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@ -88,8 +84,8 @@ reg signed [temp_var_width+3 :0] v1_im;
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wire signed [temp_var_width+3 :0] y_re;
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wire signed [temp_var_width+3 :0] y_im;
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reg signed [temp_var_width+3 :0] y1_re;
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reg signed [temp_var_width+3 :0] y1_im;
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wire signed [temp_var_width+3 :0] y1_re;
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wire signed [temp_var_width+3 :0] y1_im;
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wire signed [data_out_width-1:0] y_re_trunc;
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wire signed [data_out_width-1:0] y_im_trunc;
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@ -107,8 +103,8 @@ generate
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for (i = 0; i < 8; i = i + 1) begin: mult_c_inst
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mult_x #(
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.A_width (data_in_width ),
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.C_width (coef_width ),
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.D_width (coef_width ),
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.C_width (ab_pow_width ),
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.D_width (ab_pow_width ),
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.o_width (temp_var_width )
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) inst_c (
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.clk (clk ),
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@ -152,8 +148,8 @@ mult_C
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#(
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.A_width (temp_var_width+4 )
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,.B_width (temp_var_width+4 )
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,.C_width (coef_width )
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,.D_width (coef_width )
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,.C_width (b_pow8_width )
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,.D_width (b_pow8_width )
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,.o_width (temp_var_width+4 )
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)
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inst_c9 (
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@ -162,8 +158,8 @@ inst_c9 (
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.en (en ),
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.a (y_re ),
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.b (y_im ),
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.c (b_pow8_re ),
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.d (b_pow8_im ),
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.c (b_pow8_re[coef_width-1 : coef_width-b_pow8_width]),//+b_pow8_re[coef_width-b_pow8_width-1]),
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.d (b_pow8_im[coef_width-1 : coef_width-b_pow8_width]),//+b_pow8_im[coef_width-b_pow8_width-1]),
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.Re (y1_re ),
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.Im (y1_im )
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);
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@ -1,39 +1,39 @@
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : TailCorr_top.v
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// Department :
|
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// Author : thfu
|
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.3 2024-05-15 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
|
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
|
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// Clock Domains:
|
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module IIR_top #(
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parameter data_out_width = 23
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,parameter temp_var_width = data_out_width + 14
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parameter data_out_width = 18
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,parameter coef_width = 32
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,parameter a0_width = 32
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,parameter b0_width = 29
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,parameter b0_i_width = 29
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,parameter b0_o_width = 19
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,parameter a1_width = 19
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,parameter b1_width = 19
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,parameter b1_i_width = 19
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,parameter b1_o_width = 19
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,parameter a2_width = 21
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,parameter b2_width = 21
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,parameter b2_i_width = 19
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,parameter b2_o_width = 19
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,parameter a3_width = 21
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,parameter b3_width = 21
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,parameter b3_i_width = 19
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,parameter b3_o_width = 19
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,parameter a4_width = 20
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,parameter b4_width = 20
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,parameter b4_i_width = 19
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,parameter b4_o_width = 18
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,parameter a5_width = 21
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,parameter b5_width = 21
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,parameter b5_i_width = 18
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,parameter b5_o_width = 18
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,parameter a6_width = 21
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,parameter b6_width = 21
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,parameter b6_i_width = 18
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,parameter b6_o_width = 18
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,parameter a7_width = 22
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,parameter b7_width = 22
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,parameter b7_i_width = 18
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,parameter b7_o_width = 18
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)
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(
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input rstn
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@ -85,27 +85,31 @@ module IIR_top #(
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,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
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);
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wire signed [temp_var_width- 1:0] IIRout_p0_re;
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wire signed [temp_var_width- 3:0] IIRout_p1_re;
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wire signed [temp_var_width- 5:0] IIRout_p2_re;
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wire signed [temp_var_width- 7:0] IIRout_p3_re;
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wire signed [temp_var_width- 9:0] IIRout_p4_re;
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wire signed [temp_var_width-11:0] IIRout_p5_re;
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wire signed [temp_var_width-13:0] IIRout_p6_re;
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wire signed [temp_var_width-15:0] IIRout_p7_re;
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wire signed [temp_var_width- 1:0] IIRout_p0_im;
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wire signed [temp_var_width- 3:0] IIRout_p1_im;
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wire signed [temp_var_width- 5:0] IIRout_p2_im;
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wire signed [temp_var_width- 7:0] IIRout_p3_im;
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wire signed [temp_var_width- 9:0] IIRout_p4_im;
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wire signed [temp_var_width-11:0] IIRout_p5_im;
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wire signed [temp_var_width-13:0] IIRout_p6_im;
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wire signed [temp_var_width-15:0] IIRout_p7_im;
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wire signed [b0_o_width- 1:0] IIRout_p0_re;
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wire signed [b1_o_width- 1:0] IIRout_p1_re;
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wire signed [b2_o_width- 1:0] IIRout_p2_re;
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wire signed [b3_o_width- 1:0] IIRout_p3_re;
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wire signed [b4_o_width- 1:0] IIRout_p4_re;
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wire signed [b5_o_width- 1:0] IIRout_p5_re;
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wire signed [b6_o_width- 1:0] IIRout_p6_re;
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wire signed [b7_o_width- 1:0] IIRout_p7_re;
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wire signed [b0_o_width- 1:0] IIRout_p0_im;
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wire signed [b1_o_width- 1:0] IIRout_p1_im;
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wire signed [b2_o_width- 1:0] IIRout_p2_im;
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wire signed [b3_o_width- 1:0] IIRout_p3_im;
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wire signed [b4_o_width- 1:0] IIRout_p4_im;
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wire signed [b5_o_width- 1:0] IIRout_p5_im;
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wire signed [b6_o_width- 1:0] IIRout_p6_im;
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wire signed [b7_o_width- 1:0] IIRout_p7_im;
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IIR_Filter_p8 #(
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.data_out_width (temp_var_width )
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.coef_width (coef_width ),
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.b_pow8_width (b0_width ),
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.ab_pow_width (a0_width ),
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.temp_var_width (b0_i_width ),
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.data_out_width (b0_o_width )
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) inst_iir_p0 (
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.clk (clk ),
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.rstn (rstn ),
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@ -141,7 +145,11 @@ IIR_Filter_p8 #(
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);
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IIR_Filter_p1 #(
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.cascade_in_width (temp_var_width )
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.coef_width (coef_width ),
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.a_width (a1_width ),
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.b_width (b1_width ),
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.cascade_in_width (b1_i_width ),
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.data_out_width (b1_o_width )
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) inst_iir_p1(
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.clk (clk ),
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.rstn (rstn ),
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@ -157,7 +165,11 @@ IIR_Filter_p1 #(
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.dout_im (IIRout_p1_im ) // Im(y(8n-23))
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);
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IIR_Filter_p1 #(
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.cascade_in_width (temp_var_width-2 )
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.coef_width (coef_width ),
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.a_width (a2_width ),
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.b_width (b2_width ),
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.cascade_in_width (b2_i_width ),
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.data_out_width (b2_o_width )
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) inst_iir_p2 (
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.clk (clk ),
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.rstn (rstn ),
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@ -173,7 +185,11 @@ IIR_Filter_p1 #(
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.dout_im (IIRout_p2_im ) // Im(y(8n-38))
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);
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IIR_Filter_p1 #(
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.cascade_in_width (temp_var_width-4 )
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.coef_width (coef_width ),
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.a_width (a3_width ),
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.b_width (b3_width ),
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.cascade_in_width (b3_i_width ),
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.data_out_width (b3_o_width )
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) inst_iir_p3 (
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.clk (clk ),
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.rstn (rstn ),
|
||||
|
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@ -189,7 +205,11 @@ IIR_Filter_p1 #(
|
|||
.dout_im (IIRout_p3_im ) // Im(y(8n-53))
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||||
);
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||||
IIR_Filter_p1 #(
|
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.cascade_in_width (temp_var_width-6 )
|
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.coef_width (coef_width ),
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.a_width (a4_width ),
|
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.b_width (b4_width ),
|
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.cascade_in_width (b4_i_width ),
|
||||
.data_out_width (b4_o_width )
|
||||
) inst_iir_p4 (
|
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.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
|
|
@ -205,7 +225,11 @@ IIR_Filter_p1 #(
|
|||
.dout_im (IIRout_p4_im ) // Im(y(8n-68))
|
||||
);
|
||||
IIR_Filter_p1 #(
|
||||
.cascade_in_width (temp_var_width-8 )
|
||||
.coef_width (coef_width ),
|
||||
.a_width (a5_width ),
|
||||
.b_width (b5_width ),
|
||||
.cascade_in_width (b5_i_width ),
|
||||
.data_out_width (b5_o_width )
|
||||
) inst_iir_p5 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
|
|
@ -221,7 +245,11 @@ IIR_Filter_p1 #(
|
|||
.dout_im (IIRout_p5_im ) // Im(y(8n-83))
|
||||
);
|
||||
IIR_Filter_p1 #(
|
||||
.cascade_in_width (temp_var_width-10 )
|
||||
.coef_width (coef_width ),
|
||||
.a_width (a6_width ),
|
||||
.b_width (b6_width ),
|
||||
.cascade_in_width (b6_i_width ),
|
||||
.data_out_width (b6_o_width )
|
||||
) inst_iir_p6 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
|
|
@ -237,7 +265,11 @@ IIR_Filter_p1 #(
|
|||
.dout_im (IIRout_p6_im ) // Im(y(8n-98))
|
||||
);
|
||||
IIR_Filter_p1 #(
|
||||
.cascade_in_width (temp_var_width-12 )
|
||||
.coef_width (coef_width ),
|
||||
.a_width (a7_width ),
|
||||
.b_width (b7_width ),
|
||||
.cascade_in_width (b7_i_width ),
|
||||
.data_out_width (b7_o_width )
|
||||
) inst_iir_p7 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
|
|
@ -253,14 +285,14 @@ IIR_Filter_p1 #(
|
|||
.dout_im (IIRout_p7_im ) // Im(y(8n-113))
|
||||
);
|
||||
|
||||
assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8)
|
||||
assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23)
|
||||
assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38)
|
||||
assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53)
|
||||
assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68)
|
||||
assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83)
|
||||
assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98)
|
||||
assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113)
|
||||
assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8)
|
||||
assign IIRout_p1 = IIRout_p1_re[b1_o_width-1 : b1_o_width-data_out_width]; // y(8n-23)
|
||||
assign IIRout_p2 = IIRout_p2_re[b2_o_width-1 : b2_o_width-data_out_width]; // y(8n-38)
|
||||
assign IIRout_p3 = IIRout_p3_re[b3_o_width-1 : b3_o_width-data_out_width]; // y(8n-53)
|
||||
assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; // y(8n-68)
|
||||
assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83)
|
||||
assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98)
|
||||
assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113)
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -1,38 +1,6 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2025-02-28 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module TailCorr_top #(
|
||||
parameter temp_var_width = 22
|
||||
parameter temp_var_width = 18
|
||||
)
|
||||
(
|
||||
input rstn
|
||||
|
|
@ -207,14 +175,14 @@ wire signed [temp_var_width+2:0] sum_IIRout_p4;
|
|||
wire signed [temp_var_width+2:0] sum_IIRout_p5;
|
||||
wire signed [temp_var_width+2:0] sum_IIRout_p6;
|
||||
wire signed [temp_var_width+2:0] sum_IIRout_p7;
|
||||
reg signed [15:0] din_p0_r [15:0];
|
||||
reg signed [15:0] din_p1_r [15:0];
|
||||
reg signed [15:0] din_p2_r [15:0];
|
||||
reg signed [15:0] din_p3_r [15:0];
|
||||
reg signed [15:0] din_p4_r [15:0];
|
||||
reg signed [15:0] din_p5_r [15:0];
|
||||
reg signed [15:0] din_p6_r [15:0];
|
||||
reg signed [15:0] din_p7_r [15:0];
|
||||
reg signed [15:0] din_p0_r [16:0];
|
||||
reg signed [15:0] din_p1_r [16:0];
|
||||
reg signed [15:0] din_p2_r [16:0];
|
||||
reg signed [15:0] din_p3_r [16:0];
|
||||
reg signed [15:0] din_p4_r [16:0];
|
||||
reg signed [15:0] din_p5_r [16:0];
|
||||
reg signed [15:0] din_p6_r [16:0];
|
||||
reg signed [15:0] din_p7_r [16:0];
|
||||
reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7)
|
||||
reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22)
|
||||
reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37)
|
||||
|
|
@ -270,7 +238,7 @@ diff_p inst_diff_p (
|
|||
integer i;
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (i = 0; i < 17; i = i + 1) begin
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
din_p0_r[i] <= 'h0;
|
||||
din_p1_r[i] <= 'h0;
|
||||
din_p2_r[i] <= 'h0;
|
||||
|
|
@ -290,7 +258,7 @@ always @(posedge clk or negedge rstn) begin
|
|||
din_p5_r[0] <= din_p5;
|
||||
din_p6_r[0] <= din_p6;
|
||||
din_p7_r[0] <= din_p7;
|
||||
for (i = 0; i < 15; i = i + 1) begin
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
din_p0_r[i+1] <= din_p0_r[i];
|
||||
din_p1_r[i+1] <= din_p1_r[i];
|
||||
din_p2_r[i+1] <= din_p2_r[i];
|
||||
|
|
@ -302,7 +270,121 @@ always @(posedge clk or negedge rstn) begin
|
|||
end
|
||||
end
|
||||
end
|
||||
/*
|
||||
wire signed [15:0] din_p0_r1;
|
||||
wire signed [15:0] din_p1_r1;
|
||||
wire signed [15:0] din_p2_r1;
|
||||
wire signed [15:0] din_p3_r1;
|
||||
wire signed [15:0] din_p4_r1;
|
||||
wire signed [15:0] din_p5_r1;
|
||||
wire signed [15:0] din_p6_r1;
|
||||
wire signed [15:0] din_p7_r1;
|
||||
wire signed [15:0] din_p0_r2;
|
||||
wire signed [15:0] din_p1_r2;
|
||||
wire signed [15:0] din_p2_r2;
|
||||
wire signed [15:0] din_p3_r2;
|
||||
wire signed [15:0] din_p4_r2;
|
||||
wire signed [15:0] din_p5_r2;
|
||||
wire signed [15:0] din_p6_r2;
|
||||
wire signed [15:0] din_p7_r2;
|
||||
wire signed [15:0] din_p0_r3;
|
||||
wire signed [15:0] din_p1_r3;
|
||||
wire signed [15:0] din_p2_r3;
|
||||
wire signed [15:0] din_p3_r3;
|
||||
wire signed [15:0] din_p4_r3;
|
||||
wire signed [15:0] din_p5_r3;
|
||||
wire signed [15:0] din_p6_r3;
|
||||
wire signed [15:0] din_p7_r3;
|
||||
wire signed [15:0] din_p0_r4;
|
||||
wire signed [15:0] din_p1_r4;
|
||||
wire signed [15:0] din_p2_r4;
|
||||
wire signed [15:0] din_p3_r4;
|
||||
wire signed [15:0] din_p4_r4;
|
||||
wire signed [15:0] din_p5_r4;
|
||||
wire signed [15:0] din_p6_r4;
|
||||
wire signed [15:0] din_p7_r4;
|
||||
wire signed [15:0] din_p0_r5;
|
||||
wire signed [15:0] din_p1_r5;
|
||||
wire signed [15:0] din_p2_r5;
|
||||
wire signed [15:0] din_p3_r5;
|
||||
wire signed [15:0] din_p4_r5;
|
||||
wire signed [15:0] din_p5_r5;
|
||||
wire signed [15:0] din_p6_r5;
|
||||
wire signed [15:0] din_p7_r5;
|
||||
wire signed [15:0] din_p0_r6;
|
||||
wire signed [15:0] din_p1_r6;
|
||||
wire signed [15:0] din_p2_r6;
|
||||
wire signed [15:0] din_p3_r6;
|
||||
wire signed [15:0] din_p4_r6;
|
||||
wire signed [15:0] din_p5_r6;
|
||||
wire signed [15:0] din_p6_r6;
|
||||
wire signed [15:0] din_p7_r6;
|
||||
wire signed [15:0] din_p0_r7;
|
||||
wire signed [15:0] din_p1_r7;
|
||||
wire signed [15:0] din_p2_r7;
|
||||
wire signed [15:0] din_p3_r7;
|
||||
wire signed [15:0] din_p4_r7;
|
||||
wire signed [15:0] din_p5_r7;
|
||||
wire signed [15:0] din_p6_r7;
|
||||
wire signed [15:0] din_p7_r7;
|
||||
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_1(en,din_p0, din_p0_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_1(en,din_p1, din_p1_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_1(en,din_p2, din_p2_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_1(en,din_p3, din_p3_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_1(en,din_p4, din_p4_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_1(en,din_p5, din_p5_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_1(en,din_p6, din_p6_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_1(en,din_p7, din_p7_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_2(en,din_p0_r1, din_p0_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_2(en,din_p1_r1, din_p1_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_2(en,din_p2_r1, din_p2_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_2(en,din_p3_r1, din_p3_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_2(en,din_p4_r1, din_p4_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_2(en,din_p5_r1, din_p5_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_2(en,din_p6_r1, din_p6_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_2(en,din_p7_r1, din_p7_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_3(en,din_p0_r2, din_p0_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_3(en,din_p1_r2, din_p1_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_3(en,din_p2_r2, din_p2_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_3(en,din_p3_r2, din_p3_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_3(en,din_p4_r2, din_p4_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_3(en,din_p5_r2, din_p5_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_3(en,din_p6_r2, din_p6_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_3(en,din_p7_r2, din_p7_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_4(en,din_p0_r3, din_p0_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_4(en,din_p1_r3, din_p1_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_4(en,din_p2_r3, din_p2_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_4(en,din_p3_r3, din_p3_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_4(en,din_p4_r3, din_p4_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_4(en,din_p5_r3, din_p5_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_4(en,din_p6_r3, din_p6_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_4(en,din_p7_r3, din_p7_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_5(en,din_p0_r4, din_p0_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_5(en,din_p1_r4, din_p1_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_5(en,din_p2_r4, din_p2_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_5(en,din_p3_r4, din_p3_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_5(en,din_p4_r4, din_p4_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_5(en,din_p5_r4, din_p5_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_5(en,din_p6_r4, din_p6_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_5(en,din_p7_r4, din_p7_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_6(en,din_p0_r5, din_p0_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_6(en,din_p1_r5, din_p1_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_6(en,din_p2_r5, din_p2_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_6(en,din_p3_r5, din_p3_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_6(en,din_p4_r5, din_p4_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_6(en,din_p5_r5, din_p5_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_6(en,din_p6_r5, din_p6_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_6(en,din_p7_r5, din_p7_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_7(en,din_p0_r6, din_p0_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_7(en,din_p1_r6, din_p1_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_7(en,din_p2_r6, din_p2_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_7(en,din_p3_r6, din_p3_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_7(en,din_p4_r6, din_p4_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_7(en,din_p5_r6, din_p5_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_7(en,din_p6_r6, din_p6_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_7(en,din_p7_r6, din_p7_r7 ,clk,rstn);
|
||||
*/
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
|
|
@ -745,14 +827,14 @@ always @(posedge clk or negedge rstn) begin
|
|||
end
|
||||
end
|
||||
|
||||
assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119)
|
||||
assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118)
|
||||
assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117)
|
||||
assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116)
|
||||
assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115)
|
||||
assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114)
|
||||
assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113)
|
||||
assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112)
|
||||
assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119)
|
||||
assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118)
|
||||
assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117)
|
||||
assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116)
|
||||
assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-116)
|
||||
assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114)
|
||||
assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113)
|
||||
assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112)
|
||||
|
||||
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0);
|
||||
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1);
|
||||
|
|
@ -828,7 +910,7 @@ always @(posedge clk or negedge rstn)begin
|
|||
end
|
||||
end
|
||||
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
|
||||
assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ;
|
||||
assign vldo_r0_h = vldo_diff_r[16] == 0 && vldo_diff_r[15] == 1 ;
|
||||
assign vldo = vldo_r0;
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ module trunc #(
|
|||
//,parameter integer dow = msb - (lsb -1)
|
||||
,parameter integer msb = 7
|
||||
,parameter integer lsb = 1
|
||||
,parameter integer half_precision = 0
|
||||
,parameter integer half_precision = 1
|
||||
)
|
||||
(
|
||||
input clk
|
||||
|
|
|
|||
|
|
@ -1,48 +1,16 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module diff_p
|
||||
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input vldi
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,output vldo
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input vldi
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,output vldo
|
||||
,output signed [15:0] dout_p0
|
||||
,output signed [15:0] dout_p1
|
||||
,output signed [15:0] dout_p2
|
||||
|
|
@ -62,89 +30,130 @@ module diff_p
|
|||
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] din_wire [0:3];
|
||||
|
||||
assign din_wire[0] = din0;
|
||||
assign din_wire[1] = din1;
|
||||
assign din_wire[2] = din2;
|
||||
assign din_wire[3] = din3;
|
||||
wire signed [15:0] din_p0_r0;
|
||||
wire signed [15:0] din_p1_r0;
|
||||
wire signed [15:0] din_p2_r0;
|
||||
wire signed [15:0] din_p3_r0;
|
||||
wire signed [15:0] din_p4_r0;
|
||||
wire signed [15:0] din_p5_r0;
|
||||
wire signed [15:0] din_p6_r0;
|
||||
wire signed [15:0] din_p7_r0;
|
||||
wire vldo_0;
|
||||
wire vldo_1;
|
||||
wire vldo_2;
|
||||
wire vldo_3;
|
||||
wire vldo_r0;
|
||||
assign vldo_r0 = vldo_0 || vldo_1 || vldo_2 || vldo_3;
|
||||
sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn);
|
||||
s2p_2 inst1_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din0),
|
||||
.en (vldi),
|
||||
.dout0 (din_p0_r0),
|
||||
.dout1 (din_p4_r0)
|
||||
,.vldo( vldo_0)
|
||||
);
|
||||
s2p_2 inst2_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din1),
|
||||
.en (vldi),
|
||||
.dout0 (din_p1_r0),
|
||||
.dout1 (din_p5_r0)
|
||||
,.vldo( vldo_1)
|
||||
);
|
||||
s2p_2 inst3_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din2),
|
||||
.en (vldi),
|
||||
.dout0 (din_p2_r0),
|
||||
.dout1 (din_p6_r0)
|
||||
,.vldo( vldo_2)
|
||||
);
|
||||
s2p_2 inst4_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din3),
|
||||
.en (vldi),
|
||||
.dout0 (din_p3_r0),
|
||||
.dout1 (din_p7_r0)
|
||||
,.vldo( vldo_3)
|
||||
);
|
||||
|
||||
|
||||
wire [3:0] vldo_temp;
|
||||
wire signed [15:0] dinp_r0 [7:0];
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 4; i = i + 1) begin: s2p_inst
|
||||
s2p_2 inst_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din_wire[i]),
|
||||
.en (vldi),
|
||||
.dout0 (dinp_r0[i]),
|
||||
.dout1 (dinp_r0[i+4]),
|
||||
.vldo (vldo_temp[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
assign vldo = vldo_temp[0];
|
||||
wire signed [15:0] din_p0_r1;
|
||||
wire signed [15:0] din_p1_r1;
|
||||
wire signed [15:0] din_p2_r1;
|
||||
wire signed [15:0] din_p3_r1;
|
||||
wire signed [15:0] din_p4_r1;
|
||||
wire signed [15:0] din_p5_r1;
|
||||
wire signed [15:0] din_p6_r1;
|
||||
wire signed [15:0] din_p7_r1;
|
||||
|
||||
reg signed [15:0] dinp_r1 [0:7];
|
||||
integer j;
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
dinp_r1[j] <= 'h0;
|
||||
end
|
||||
end
|
||||
else if (en) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
dinp_r1[j] <= dinp_r0[j];
|
||||
end
|
||||
end
|
||||
sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn);
|
||||
|
||||
assign dout_p0 = din_p0_r0;
|
||||
assign dout_p1 = din_p1_r0;
|
||||
assign dout_p2 = din_p2_r0;
|
||||
assign dout_p3 = din_p3_r0;
|
||||
assign dout_p4 = din_p4_r0;
|
||||
assign dout_p5 = din_p5_r0;
|
||||
assign dout_p6 = din_p6_r0;
|
||||
assign dout_p7 = din_p7_r0;
|
||||
|
||||
reg signed [15:0] diff_p0_r1;
|
||||
reg signed [15:0] diff_p1_r1;
|
||||
reg signed [15:0] diff_p2_r1;
|
||||
reg signed [15:0] diff_p3_r1;
|
||||
reg signed [15:0] diff_p4_r1;
|
||||
reg signed [15:0] diff_p5_r1;
|
||||
reg signed [15:0] diff_p6_r1;
|
||||
reg signed [15:0] diff_p7_r1;
|
||||
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
diff_p0_r1 <= 0;
|
||||
diff_p1_r1 <= 0;
|
||||
diff_p2_r1 <= 0;
|
||||
diff_p3_r1 <= 0;
|
||||
diff_p4_r1 <= 0;
|
||||
diff_p5_r1 <= 0;
|
||||
diff_p6_r1 <= 0;
|
||||
diff_p7_r1 <= 0;
|
||||
|
||||
end
|
||||
else if(en)begin
|
||||
diff_p0_r1 <= din_p0_r0 - din_p7_r1;
|
||||
diff_p1_r1 <= din_p1_r0 - din_p0_r0;
|
||||
diff_p2_r1 <= din_p2_r0 - din_p1_r0;
|
||||
diff_p3_r1 <= din_p3_r0 - din_p2_r0;
|
||||
diff_p4_r1 <= din_p4_r0 - din_p3_r0;
|
||||
diff_p5_r1 <= din_p5_r0 - din_p4_r0;
|
||||
diff_p6_r1 <= din_p6_r0 - din_p5_r0;
|
||||
diff_p7_r1 <= din_p7_r0 - din_p6_r0;
|
||||
end
|
||||
else begin
|
||||
diff_p0_r1 <= diff_p0_r1;
|
||||
diff_p1_r1 <= diff_p1_r1;
|
||||
diff_p2_r1 <= diff_p2_r1;
|
||||
diff_p3_r1 <= diff_p3_r1;
|
||||
diff_p4_r1 <= diff_p4_r1;
|
||||
diff_p5_r1 <= diff_p5_r1;
|
||||
diff_p6_r1 <= diff_p6_r1;
|
||||
diff_p7_r1 <= diff_p7_r1;
|
||||
end
|
||||
end
|
||||
|
||||
wire signed [15:0] diffp_r0 [0:7];
|
||||
generate
|
||||
for (i = 0; i < 8; i = i + 1) begin: diff_assign
|
||||
if (i == 0)
|
||||
assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
|
||||
else
|
||||
assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign dout_p0 = dinp_r1[0];
|
||||
assign dout_p1 = dinp_r1[1];
|
||||
assign dout_p2 = dinp_r1[2];
|
||||
assign dout_p3 = dinp_r1[3];
|
||||
assign dout_p4 = dinp_r1[4];
|
||||
assign dout_p5 = dinp_r1[5];
|
||||
assign dout_p6 = dinp_r1[6];
|
||||
assign dout_p7 = dinp_r1[7];
|
||||
|
||||
reg signed [15:0] diffp_r1 [0:7];
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
diffp_r1[j] <= 0;
|
||||
end
|
||||
end
|
||||
else if (en) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
diffp_r1[j] <= diffp_r0[j];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign diff_p0 = diffp_r1[0];
|
||||
assign diff_p1 = diffp_r1[1];
|
||||
assign diff_p2 = diffp_r1[2];
|
||||
assign diff_p3 = diffp_r1[3];
|
||||
assign diff_p4 = diffp_r1[4];
|
||||
assign diff_p5 = diffp_r1[5];
|
||||
assign diff_p6 = diffp_r1[6];
|
||||
assign diff_p7 = diffp_r1[7];
|
||||
assign diff_p0 = diff_p0_r1;
|
||||
assign diff_p1 = diff_p1_r1;
|
||||
assign diff_p2 = diff_p2_r1;
|
||||
assign diff_p3 = diff_p3_r1;
|
||||
assign diff_p4 = diff_p4_r1;
|
||||
assign diff_p5 = diff_p5_r1;
|
||||
assign diff_p6 = diff_p6_r1;
|
||||
assign diff_p7 = diff_p7_r1;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -8,21 +8,6 @@ module s2p_2 (
|
|||
output vldo
|
||||
);
|
||||
|
||||
reg en_r1;
|
||||
reg en_r2;
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
en_r1 <= 0;
|
||||
en_r2 <= 0;
|
||||
end
|
||||
else begin
|
||||
en_r1 <= en;
|
||||
en_r2 <= en_r1;
|
||||
end
|
||||
end
|
||||
assign vldo = en_r2;
|
||||
|
||||
reg cnt;
|
||||
wire add_cnt;
|
||||
wire end_cnt;
|
||||
|
|
@ -45,7 +30,8 @@ end
|
|||
assign add_cnt = en == 1'b1;
|
||||
assign end_cnt = add_cnt && cnt== 2 - 1 ;
|
||||
|
||||
|
||||
wire en_r1;
|
||||
wire en_r2;
|
||||
reg [ 15: 0] dout0_r0;
|
||||
reg [ 15: 0] dout1_r0;
|
||||
wire dout0_en;
|
||||
|
|
@ -53,66 +39,45 @@ wire dout1_en;
|
|||
wire dout0_hold;
|
||||
wire dout1_hold;
|
||||
|
||||
always @(*)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(!rst_n)begin
|
||||
dout0_r0 <= 16'b0;
|
||||
dout1_r0 <= 16'b0;
|
||||
end
|
||||
else if(dout0_en)begin
|
||||
dout0_r0 = din;
|
||||
dout0_r0 <= din;
|
||||
end
|
||||
else if(dout1_en)begin
|
||||
dout1_r0 = din;
|
||||
end
|
||||
else begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
|
||||
end
|
||||
end
|
||||
assign dout0_en = add_cnt && cnt == 0;
|
||||
assign dout1_en = add_cnt && cnt == 1;
|
||||
|
||||
reg [ 15: 0] dout0_r1;
|
||||
reg [ 15: 0] dout1_r1;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
else if(en)begin
|
||||
dout0_r1 <= dout0_r0;
|
||||
dout1_r1 <= dout1_r0;
|
||||
dout1_r0 <= din;
|
||||
end
|
||||
else if(dout0_hold)begin
|
||||
dout0_r1 <= dout0_r1;
|
||||
dout1_r1 <= 16'd0;
|
||||
dout0_r0 <= dout0_r0;
|
||||
dout1_r0 <= 16'd0;
|
||||
end
|
||||
else if(dout1_hold)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= dout1_r1;
|
||||
dout0_r0 <= 16'd0;
|
||||
dout1_r0 <= dout1_r0;
|
||||
end
|
||||
else begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
dout0_r0 <= 16'd0;
|
||||
dout1_r0 <= 16'd0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign dout0_en = add_cnt && cnt == 0;
|
||||
assign dout1_en = add_cnt && cnt == 1;
|
||||
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
|
||||
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
|
||||
|
||||
reg [ 15: 0] dout0_r2;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r2 <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
dout0_r2 <= dout0_r1;
|
||||
end
|
||||
end
|
||||
sirv_gnrl_dffr #(1) dff_en_1(en , en_r1 ,clk,rst_n);
|
||||
sirv_gnrl_dffr #(1) dff_en_2(en_r1, en_r2 ,clk,rst_n);
|
||||
assign vldo = en_r2;
|
||||
|
||||
assign dout0 = dout0_r2;
|
||||
assign dout1 = dout1_r1;
|
||||
wire [ 15: 0] dout0_r1;
|
||||
sirv_gnrl_dfflr #(16) dff_dout0_1(1'b1,dout0_r0, dout0_r1 ,clk,rst_n);
|
||||
|
||||
assign dout0 = dout0_r1;
|
||||
assign dout1 = dout1_r0;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,326 @@
|
|||
/*
|
||||
Copyright 2018-2020 Nuclei System Technology, Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//=====================================================================
|
||||
//
|
||||
// Designer : Bob Hu
|
||||
//
|
||||
// Description:
|
||||
// All of the general DFF and Latch modules
|
||||
//
|
||||
// ====================================================================
|
||||
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
`define DISABLE_SV_ASSERTION
|
||||
`define dly #0.2
|
||||
module sirv_gnrl_dfflrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is input
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflrd # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
input [DW-1:0] init,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= init;
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable, no reset
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffl # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : DFFL_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for general latch
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_ltch # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
//input test_mode,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @ *
|
||||
begin : LTCH_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= dnxt;
|
||||
end
|
||||
|
||||
//assign qout = test_mode ? dnxt : qout_r;
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
always_comb
|
||||
begin
|
||||
CHECK_THE_X_VALUE:
|
||||
assert (lden !== 1'bx)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
end
|
||||
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -2,11 +2,14 @@
|
|||
clc;clear;close all
|
||||
% addpath("/data/work/thfu/TailCorr/script_m");
|
||||
data_source = 'matlab';
|
||||
file_path = "/home/thfu/work/TailCorr/sim/z_dsp/";
|
||||
file_path = "/home/thfu/work/TailCorr/sim/";
|
||||
rng('shuffle');
|
||||
|
||||
max_error = zeros(100,1);
|
||||
|
||||
for time = 1:100
|
||||
if strcmp(data_source, 'matlab')
|
||||
in = floor(cat(1,0,3000*randn(4*2579+4,1)));
|
||||
in = floor(cat(1,0,30000*rand(4*2579+4,1)));
|
||||
for i = 0:3
|
||||
filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
|
||||
subset = in(i+1:4:end);
|
||||
|
|
@ -33,14 +36,14 @@ end
|
|||
|
||||
|
||||
cs_wave = [];
|
||||
for i = 0:3
|
||||
for i = 0:7
|
||||
filename = strcat(file_path, "dout", num2str(i), ".dat");
|
||||
dout_data = importdata(filename);
|
||||
if isempty(cs_wave)
|
||||
N = length(dout_data);
|
||||
cs_wave = zeros(4*N, 1);
|
||||
cs_wave = zeros(8*N, 1);
|
||||
end
|
||||
cs_wave(i+1:4:end) = dout_data;
|
||||
cs_wave(i+1:8:end) = dout_data;
|
||||
end
|
||||
|
||||
A = [0.025 0.015*1 0.0002*1 0];
|
||||
|
|
@ -64,17 +67,19 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
|
|||
[cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr");
|
||||
N = min(length(wave_float),length(cs_wave_A));
|
||||
figure()
|
||||
diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
|
||||
max_error(time) = diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
|
||||
|
||||
%% Test of iir filter with no intp
|
||||
end
|
||||
|
||||
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
|
||||
N = min(length(wave_float_A),length(wave_verdi_A));
|
||||
figure()
|
||||
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
|
||||
%%
|
||||
signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
|
||||
%%
|
||||
% %% Test of iir filter with no intp
|
||||
%
|
||||
% [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
|
||||
% N = min(length(wave_float_A),length(wave_verdi_A));
|
||||
% figure()
|
||||
% diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
|
||||
% %%
|
||||
% signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
|
||||
% %%
|
||||
|
||||
a_fix = round(a*2^31);
|
||||
b_fix = round(b*2^31);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
function diff_plot(iir_out, Script_out,leg1,leg2,a)
|
||||
function result = diff_plot(iir_out, Script_out,leg1,leg2,a)
|
||||
|
||||
N = min(length(iir_out),length(Script_out));
|
||||
iir_out = iir_out(1:N);
|
||||
|
|
@ -32,3 +32,5 @@ plot(n(R_mpos_min),diff(R_mpos_min),'r*')
|
|||
|
||||
text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k');
|
||||
text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k');
|
||||
|
||||
result = max(abs(diff(R_mpos_max)),abs(diff(R_mpos_min)));
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
../rtl/z_dsp/s2p_2.v
|
||||
../rtl/z_dsp/IIR_Filter_p8.v
|
||||
../rtl/z_dsp/IIR_Filter_p1.v
|
||||
../rtl/z_dsp/sirv_gnrl_dffs.v
|
||||
../rtl/ref/mult_C.v
|
||||
../rtl/ref/FixRound.v
|
||||
../rtl/ref/TailCorr_top.v
|
||||
|
|
|
|||
Loading…
Reference in New Issue