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Author SHA1 Message Date
thfu 626ff988ce 16路超前计算到1G 
1.16路62.5M输入，1G
2.使用实数乘法器
3.四指数修正
4.使用宏定义控制是否使用复数乘法器，实系数跑通了，但复系数仍需要兼容
 2025-05-17 19:24:59 +08:00
futh0403 6ce1cd456e Squashed commit of the following:系数位宽用最优化方式求解 
commit 728532bd61
Author: thfu <2779155576@qq.com>
Date:   Wed Mar 19 15:17:35 2025 +0800

    降低位宽

    采用求最优解的方法求解位宽；
    不同的系数采用不同的位宽

commit 6e386a2743
Author: futh0403 <futh@mail.ustc.edu.cn>
Date:   Thu Mar 13 21:02:23 2025 +0800

    合并main分支的部分修改
    -尽量避免使用for循环
 2025-03-20 19:34:20 +08:00
thfu 7b521326eb 修正系数为实数 2025-03-17 15:23:05 +08:00
futh0403 e32b5fa523 与b2支路合并 
-TailCorr_top.v需要b系数，其它模块做出对应修改
 2025-03-17 10:36:25 +08:00
futh0403 e297bf11e3 与基于IP核的分支合并，保留全八路并行的IIR滤波器； 
-diff_p.v中的循环展开，并解决vldo悬空的问题；
-锁存调用FF模块，提高代码可读性；
-解决s2p_2.v组合逻辑出现latch的问题；
-解决tb_z_dsp.v没有matlab代码报错的问题
 2025-03-13 15:58:08 +08:00
41 changed files with 5413 additions and 5300 deletions
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2
rtl/define/common_defs.vh Normal file
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//`define COMPLEX 0

2
rtl/define/common_undefs.vh Normal file
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`undef COMPLEX 0

37
rtl/ref/FixRound.v
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module FixRound #(
parameter integer Data_width = 8
,parameter integer Fix_frac_coef_width = 31//division
)
(
input clk
,input rstn
,input en
,input signed [Data_width-1:0] din
,output signed [Data_width-1:0] dout
);
reg signed [Data_width-1:0] din_round;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_round <= 'h0;
end
else if(en) begin
if(din[Data_width-1] == 1'b0)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
end
else if (din[Data_width-1] == 1'b1)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
end
end
else begin
din_round <= din_round;
end
assign dout = din_round;
endmodule

345
rtl/ref/IIR_Filter_p8.v
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p8_ref #(
parameter data_in_width = 16
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1:0] dinp0
,input signed [data_in_width-1:0] dinp1
,input signed [data_in_width-1:0] dinp2
,input signed [data_in_width-1:0] dinp3
,input signed [data_in_width-1:0] dinp4
,input signed [data_in_width-1:0] dinp5
,input signed [data_in_width-1:0] dinp6
,input signed [data_in_width-1:0] dinp7
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] abb_im
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow3_im
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow4_im
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow5_im
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow6_im
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow7_im
,input signed [coef_width-1 :0] b_pow8_re
,input signed [coef_width-1 :0] b_pow8_im
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width+frac_data_out_width:0] x1_re;
wire signed [data_in_width+frac_data_out_width:0] x1_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp0 ),
.b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x*dinp0
.Im (x1_im )
);
wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp1 ),
.b (16'd0 ),
.c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*dinp1
.Im (x2_im )
);
wire signed [data_in_width+frac_data_out_width:0] x3_re;
wire signed [data_in_width+frac_data_out_width:0] x3_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp2 ),
.b (16'd0 ),
.c ({abb_re,{frac_data_out_width{1'b0}}} ),
.d ({abb_im,{frac_data_out_width{1'b0}}} ),
.Re (x3_re ),//a*b*b*dinp2
.Im (x3_im )
);
wire signed [data_in_width+frac_data_out_width:0] x4_re;
wire signed [data_in_width+frac_data_out_width:0] x4_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp3 ),
.b (16'd0 ),
.c ({ab_pow3_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow3_im,{frac_data_out_width{1'b0}}} ),
.Re (x4_re ),//a*b^3*dinp3
.Im (x4_im )
);
wire signed [data_in_width+frac_data_out_width:0] x5_re;
wire signed [data_in_width+frac_data_out_width:0] x5_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp4 ),
.b (16'd0 ),
.c ({ab_pow4_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow4_im,{frac_data_out_width{1'b0}}} ),
.Re (x5_re ),//a*b^4*dinp4
.Im (x5_im )
);
wire signed [data_in_width+frac_data_out_width:0] x6_re;
wire signed [data_in_width+frac_data_out_width:0] x6_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp5 ),
.b (16'd0 ),
.c ({ab_pow5_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow5_im,{frac_data_out_width{1'b0}}} ),
.Re (x6_re ),//a*b^5*dinp5
.Im (x6_im )
);
wire signed [data_in_width+frac_data_out_width:0] x7_re;
wire signed [data_in_width+frac_data_out_width:0] x7_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp6 ),
.b (16'd0 ),
.c ({ab_pow6_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow6_im,{frac_data_out_width{1'b0}}} ),
.Re (x7_re ),//a*b^6*dinp6
.Im (x7_im )
);
wire signed [data_in_width+frac_data_out_width:0] x8_re;
wire signed [data_in_width+frac_data_out_width:0] x8_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c8 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp7 ),
.b (16'd0 ),
.c ({ab_pow7_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow7_im,{frac_data_out_width{1'b0}}} ),
.Re (x8_re ),//a*b^7*dinp7
.Im (x8_im )
);
wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im;
assign v_re = x1_re + x2_re + x3_re + x4_re + x5_re + x6_re + x7_re + x8_re;
assign v_im = x1_im + x2_im + x3_im + x4_im + x5_im + x6_im + x7_im + x8_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re;
reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im;
reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
reg signed [data_in_width-1:0] dout_re;
mult_C_ref
#(
.A_width(data_in_width+frac_data_out_width+2)
,.B_width(data_in_width+frac_data_out_width+2)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c9 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),
.b (y_im ),
.c (b_pow8_re ),
.d (b_pow8_im ),
.Re (y1_re ),//b^8*y(n-1)
.Im (y1_im )
);
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule

379
rtl/ref/IIR_top.v
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@ -1,379 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_top_ref
(
input rstn
,input clk
,input en
,input signed [15:0] IIRin_p0
,input signed [15:0] IIRin_p1
,input signed [15:0] IIRin_p2
,input signed [15:0] IIRin_p3
,input signed [15:0] IIRin_p4
,input signed [15:0] IIRin_p5
,input signed [15:0] IIRin_p6
,input signed [15:0] IIRin_p7
,input signed [31 :0] a_re
,input signed [31 :0] a_im
,input signed [31 :0] ab_re
,input signed [31 :0] ab_im
,input signed [31 :0] abb_re
,input signed [31 :0] abb_im
,input signed [31 :0] ab_pow3_re
,input signed [31 :0] ab_pow3_im
,input signed [31 :0] ab_pow4_re
,input signed [31 :0] ab_pow4_im
,input signed [31 :0] ab_pow5_re
,input signed [31 :0] ab_pow5_im
,input signed [31 :0] ab_pow6_re
,input signed [31 :0] ab_pow6_im
,input signed [31 :0] ab_pow7_re
,input signed [31 :0] ab_pow7_im
,input signed [31 :0] b_pow8_re
,input signed [31 :0] b_pow8_im
,output signed [15:0] IIRout_p0
,output signed [15:0] IIRout_p1
,output signed [15:0] IIRout_p2
,output signed [15:0] IIRout_p3
,output signed [15:0] IIRout_p4
,output signed [15:0] IIRout_p5
,output signed [15:0] IIRout_p6
,output signed [15:0] IIRout_p7
);
reg signed [15:0] IIRin_p0_r1;
reg signed [15:0] IIRin_p1_r1;
reg signed [15:0] IIRin_p2_r1;
reg signed [15:0] IIRin_p3_r1;
reg signed [15:0] IIRin_p4_r1;
reg signed [15:0] IIRin_p5_r1;
reg signed [15:0] IIRin_p6_r1;
reg signed [15:0] IIRin_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
IIRin_p0_r1 <= 'h0;
IIRin_p1_r1 <= 'h0;
IIRin_p2_r1 <= 'h0;
IIRin_p3_r1 <= 'h0;
IIRin_p4_r1 <= 'h0;
IIRin_p5_r1 <= 'h0;
IIRin_p6_r1 <= 'h0;
IIRin_p7_r1 <= 'h0;
end
else if(en)
begin
IIRin_p0_r1 <= IIRin_p0;
IIRin_p1_r1 <= IIRin_p1;
IIRin_p2_r1 <= IIRin_p2;
IIRin_p3_r1 <= IIRin_p3;
IIRin_p4_r1 <= IIRin_p4;
IIRin_p5_r1 <= IIRin_p5;
IIRin_p6_r1 <= IIRin_p6;
IIRin_p7_r1 <= IIRin_p7;
end
else
begin
IIRin_p0_r1 <= IIRin_p0_r1;
IIRin_p1_r1 <= IIRin_p1_r1;
IIRin_p2_r1 <= IIRin_p2_r1;
IIRin_p3_r1 <= IIRin_p3_r1;
IIRin_p4_r1 <= IIRin_p4_r1;
IIRin_p5_r1 <= IIRin_p5_r1;
IIRin_p6_r1 <= IIRin_p6_r1;
IIRin_p7_r1 <= IIRin_p7_r1;
end
IIR_Filter_p8_ref inst_iir_0_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p0 ),
.dinp1 (IIRin_p7_r1 ),
.dinp2 (IIRin_p6_r1 ),
.dinp3 (IIRin_p5_r1 ),
.dinp4 (IIRin_p4_r1 ),
.dinp5 (IIRin_p3_r1 ),
.dinp6 (IIRin_p2_r1 ),
.dinp7 (IIRin_p1_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p0 )
);
IIR_Filter_p8_ref inst_iir_o_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p1 ),
.dinp1 (IIRin_p0 ),
.dinp2 (IIRin_p7_r1 ),
.dinp3 (IIRin_p6_r1 ),
.dinp4 (IIRin_p5_r1 ),
.dinp5 (IIRin_p4_r1 ),
.dinp6 (IIRin_p3_r1 ),
.dinp7 (IIRin_p2_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p1 )
);
IIR_Filter_p8_ref inst_iir_0_p2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p2 ),
.dinp1 (IIRin_p1 ),
.dinp2 (IIRin_p0 ),
.dinp3 (IIRin_p7_r1 ),
.dinp4 (IIRin_p6_r1 ),
.dinp5 (IIRin_p5_r1 ),
.dinp6 (IIRin_p4_r1 ),
.dinp7 (IIRin_p3_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p2 )
);
IIR_Filter_p8_ref inst_iir_0_p3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p3 ),
.dinp1 (IIRin_p2 ),
.dinp2 (IIRin_p1 ),
.dinp3 (IIRin_p0 ),
.dinp4 (IIRin_p7_r1 ),
.dinp5 (IIRin_p6_r1 ),
.dinp6 (IIRin_p5_r1 ),
.dinp7 (IIRin_p4_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p3 )
);
IIR_Filter_p8_ref inst_iir_0_p4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p4 ),
.dinp1 (IIRin_p3 ),
.dinp2 (IIRin_p2 ),
.dinp3 (IIRin_p1 ),
.dinp4 (IIRin_p0 ),
.dinp5 (IIRin_p7_r1 ),
.dinp6 (IIRin_p6_r1 ),
.dinp7 (IIRin_p5_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p4 )
);
IIR_Filter_p8_ref inst_iir_0_p5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p5 ),
.dinp1 (IIRin_p4 ),
.dinp2 (IIRin_p3 ),
.dinp3 (IIRin_p2 ),
.dinp4 (IIRin_p1 ),
.dinp5 (IIRin_p0 ),
.dinp6 (IIRin_p7_r1 ),
.dinp7 (IIRin_p6_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p5 )
);
IIR_Filter_p8_ref inst_iir_0_p6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p6 ),
.dinp1 (IIRin_p5 ),
.dinp2 (IIRin_p4 ),
.dinp3 (IIRin_p3 ),
.dinp4 (IIRin_p2 ),
.dinp5 (IIRin_p1 ),
.dinp6 (IIRin_p0 ),
.dinp7 (IIRin_p7_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p6 )
);
IIR_Filter_p8_ref inst_iir_0_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p7 ),
.dinp1 (IIRin_p6 ),
.dinp2 (IIRin_p5 ),
.dinp3 (IIRin_p4 ),
.dinp4 (IIRin_p3 ),
.dinp5 (IIRin_p2 ),
.dinp6 (IIRin_p1 ),
.dinp7 (IIRin_p0 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p7 )
);
endmodule

900
rtl/ref/TailCorr_top.v
View File

@ -1,900 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2025-02-28 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module TailCorr_top_ref
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [31:0] a_re0
,input signed [31:0] a_im0
,input signed [31:0] ab_re0
,input signed [31:0] ab_im0
,input signed [31:0] abb_re0
,input signed [31:0] abb_im0
,input signed [31:0] ab_pow3_re0
,input signed [31:0] ab_pow3_im0
,input signed [31:0] ab_pow4_re0
,input signed [31:0] ab_pow4_im0
,input signed [31:0] ab_pow5_re0
,input signed [31:0] ab_pow5_im0
,input signed [31:0] ab_pow6_re0
,input signed [31:0] ab_pow6_im0
,input signed [31:0] ab_pow7_re0
,input signed [31:0] ab_pow7_im0
,input signed [31:0] b_pow8_re0
,input signed [31:0] b_pow8_im0
,input signed [31:0] a_re1
,input signed [31:0] a_im1
,input signed [31:0] ab_re1
,input signed [31:0] ab_im1
,input signed [31:0] abb_re1
,input signed [31:0] abb_im1
,input signed [31:0] ab_pow3_re1
,input signed [31:0] ab_pow3_im1
,input signed [31:0] ab_pow4_re1
,input signed [31:0] ab_pow4_im1
,input signed [31:0] ab_pow5_re1
,input signed [31:0] ab_pow5_im1
,input signed [31:0] ab_pow6_re1
,input signed [31:0] ab_pow6_im1
,input signed [31:0] ab_pow7_re1
,input signed [31:0] ab_pow7_im1
,input signed [31:0] b_pow8_re1
,input signed [31:0] b_pow8_im1
,input signed [31:0] a_re2
,input signed [31:0] a_im2
,input signed [31:0] ab_re2
,input signed [31:0] ab_im2
,input signed [31:0] abb_re2
,input signed [31:0] abb_im2
,input signed [31:0] ab_pow3_re2
,input signed [31:0] ab_pow3_im2
,input signed [31:0] ab_pow4_re2
,input signed [31:0] ab_pow4_im2
,input signed [31:0] ab_pow5_re2
,input signed [31:0] ab_pow5_im2
,input signed [31:0] ab_pow6_re2
,input signed [31:0] ab_pow6_im2
,input signed [31:0] ab_pow7_re2
,input signed [31:0] ab_pow7_im2
,input signed [31:0] b_pow8_re2
,input signed [31:0] b_pow8_im2
,input signed [31:0] a_re3
,input signed [31:0] a_im3
,input signed [31:0] ab_re3
,input signed [31:0] ab_im3
,input signed [31:0] abb_re3
,input signed [31:0] abb_im3
,input signed [31:0] ab_pow3_re3
,input signed [31:0] ab_pow3_im3
,input signed [31:0] ab_pow4_re3
,input signed [31:0] ab_pow4_im3
,input signed [31:0] ab_pow5_re3
,input signed [31:0] ab_pow5_im3
,input signed [31:0] ab_pow6_re3
,input signed [31:0] ab_pow6_im3
,input signed [31:0] ab_pow7_re3
,input signed [31:0] ab_pow7_im3
,input signed [31:0] b_pow8_re3
,input signed [31:0] b_pow8_im3
,input signed [31:0] a_re4
,input signed [31:0] a_im4
,input signed [31:0] ab_re4
,input signed [31:0] ab_im4
,input signed [31:0] abb_re4
,input signed [31:0] abb_im4
,input signed [31:0] ab_pow3_re4
,input signed [31:0] ab_pow3_im4
,input signed [31:0] ab_pow4_re4
,input signed [31:0] ab_pow4_im4
,input signed [31:0] ab_pow5_re4
,input signed [31:0] ab_pow5_im4
,input signed [31:0] ab_pow6_re4
,input signed [31:0] ab_pow6_im4
,input signed [31:0] ab_pow7_re4
,input signed [31:0] ab_pow7_im4
,input signed [31:0] b_pow8_re4
,input signed [31:0] b_pow8_im4
,input signed [31:0] a_re5
,input signed [31:0] a_im5
,input signed [31:0] ab_re5
,input signed [31:0] ab_im5
,input signed [31:0] abb_re5
,input signed [31:0] abb_im5
,input signed [31:0] ab_pow3_re5
,input signed [31:0] ab_pow3_im5
,input signed [31:0] ab_pow4_re5
,input signed [31:0] ab_pow4_im5
,input signed [31:0] ab_pow5_re5
,input signed [31:0] ab_pow5_im5
,input signed [31:0] ab_pow6_re5
,input signed [31:0] ab_pow6_im5
,input signed [31:0] ab_pow7_re5
,input signed [31:0] ab_pow7_im5
,input signed [31:0] b_pow8_re5
,input signed [31:0] b_pow8_im5
,output signed [15:0] dout_p0
,output signed [15:0] dout_p1
,output signed [15:0] dout_p2
,output signed [15:0] dout_p3
,output signed [15:0] dout_p4
,output signed [15:0] dout_p5
,output signed [15:0] dout_p6
,output signed [15:0] dout_p7
,output vldo
);
wire signed [15:0] din_p0;
wire signed [15:0] din_p1;
wire signed [15:0] din_p2;
wire signed [15:0] din_p3;
wire signed [15:0] din_p4;
wire signed [15:0] din_p5;
wire signed [15:0] din_p6;
wire signed [15:0] din_p7;
wire signed [15:0] IIRin_p0;
wire signed [15:0] IIRin_p1;
wire signed [15:0] IIRin_p2;
wire signed [15:0] IIRin_p3;
wire signed [15:0] IIRin_p4;
wire signed [15:0] IIRin_p5;
wire signed [15:0] IIRin_p6;
wire signed [15:0] IIRin_p7;
wire vldo_diff;
diff_p_ref inst_diff_p_ref (
.rstn (rstn),
.clk (clk ),
.en (en ),
.vldi (vldi),
.din0 (din0),
.din1 (din1),
.din2 (din2),
.din3 (din3),
.vldo (vldo_diff),
.dout_p0 (din_p0),
.dout_p1 (din_p1),
.dout_p2 (din_p2),
.dout_p3 (din_p3),
.dout_p4 (din_p4),
.dout_p5 (din_p5),
.dout_p6 (din_p6),
.dout_p7 (din_p7),
.diff_p0 (IIRin_p0),
.diff_p1 (IIRin_p1),
.diff_p2 (IIRin_p2),
.diff_p3 (IIRin_p3),
.diff_p4 (IIRin_p4),
.diff_p5 (IIRin_p5),
.diff_p6 (IIRin_p6),
.diff_p7 (IIRin_p7)
);
reg signed [15:0] din_p0_r1;
reg signed [15:0] din_p0_r2;
reg signed [15:0] din_p0_r3;
reg signed [15:0] din_p0_r4;
reg signed [15:0] din_p0_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p0_r1 <= 'h0;
din_p0_r2 <= 'h0;
din_p0_r3 <= 'h0;
din_p0_r4 <= 'h0;
din_p0_r5 <= 'h0;
end
else if(en)
begin
din_p0_r1 <= din_p0;
din_p0_r2 <= din_p0_r1;
din_p0_r3 <= din_p0_r2;
din_p0_r4 <= din_p0_r3;
din_p0_r5 <= din_p0_r4;
end
else
begin
din_p0_r1 <= din_p0_r1;
din_p0_r2 <= din_p0_r2;
din_p0_r3 <= din_p0_r3;
din_p0_r4 <= din_p0_r4;
din_p0_r5 <= din_p0_r5;
end
reg signed [15:0] din_p1_r1;
reg signed [15:0] din_p1_r2;
reg signed [15:0] din_p1_r3;
reg signed [15:0] din_p1_r4;
reg signed [15:0] din_p1_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p1_r1 <= 'h0;
din_p1_r2 <= 'h0;
din_p1_r3 <= 'h0;
din_p1_r4 <= 'h0;
din_p1_r5 <= 'h0;
end
else if(en)
begin
din_p1_r1 <= din_p1;
din_p1_r2 <= din_p1_r1;
din_p1_r3 <= din_p1_r2;
din_p1_r4 <= din_p1_r3;
din_p1_r5 <= din_p1_r4;
end
else
begin
din_p1_r1 <= din_p1_r1;
din_p1_r2 <= din_p1_r2;
din_p1_r3 <= din_p1_r3;
din_p1_r4 <= din_p1_r4;
din_p1_r5 <= din_p1_r5;
end
reg signed [15:0] din_p2_r1;
reg signed [15:0] din_p2_r2;
reg signed [15:0] din_p2_r3;
reg signed [15:0] din_p2_r4;
reg signed [15:0] din_p2_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p2_r1 <= 'h0;
din_p2_r2 <= 'h0;
din_p2_r3 <= 'h0;
din_p2_r4 <= 'h0;
din_p2_r5 <= 'h0;
end
else if(en)
begin
din_p2_r1 <= din_p2;
din_p2_r2 <= din_p2_r1;
din_p2_r3 <= din_p2_r2;
din_p2_r4 <= din_p2_r3;
din_p2_r5 <= din_p2_r4;
end
else
begin
din_p2_r1 <= din_p2_r1;
din_p2_r2 <= din_p2_r2;
din_p2_r3 <= din_p2_r3;
din_p2_r4 <= din_p2_r4;
din_p2_r5 <= din_p2_r5;
end
reg signed [15:0] din_p3_r1;
reg signed [15:0] din_p3_r2;
reg signed [15:0] din_p3_r3;
reg signed [15:0] din_p3_r4;
reg signed [15:0] din_p3_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p3_r1 <= 'h0;
din_p3_r2 <= 'h0;
din_p3_r3 <= 'h0;
din_p3_r4 <= 'h0;
din_p3_r5 <= 'h0;
end
else if(en)
begin
din_p3_r1 <= din_p3;
din_p3_r2 <= din_p3_r1;
din_p3_r3 <= din_p3_r2;
din_p3_r4 <= din_p3_r3;
din_p3_r5 <= din_p3_r4;
end
else
begin
din_p3_r1 <= din_p3_r1;
din_p3_r2 <= din_p3_r2;
din_p3_r3 <= din_p3_r3;
din_p3_r4 <= din_p3_r4;
din_p3_r5 <= din_p3_r5;
end
reg signed [15:0] din_p4_r1;
reg signed [15:0] din_p4_r2;
reg signed [15:0] din_p4_r3;
reg signed [15:0] din_p4_r4;
reg signed [15:0] din_p4_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p4_r1 <= 'h0;
din_p4_r2 <= 'h0;
din_p4_r3 <= 'h0;
din_p4_r4 <= 'h0;
din_p4_r5 <= 'h0;
end
else if(en)
begin
din_p4_r1 <= din_p4;
din_p4_r2 <= din_p4_r1;
din_p4_r3 <= din_p4_r2;
din_p4_r4 <= din_p4_r3;
din_p4_r5 <= din_p4_r4;
end
else
begin
din_p4_r1 <= din_p4_r1;
din_p4_r2 <= din_p4_r2;
din_p4_r3 <= din_p4_r3;
din_p4_r4 <= din_p4_r4;
din_p4_r5 <= din_p4_r5;
end
reg signed [15:0] din_p5_r1;
reg signed [15:0] din_p5_r2;
reg signed [15:0] din_p5_r3;
reg signed [15:0] din_p5_r4;
reg signed [15:0] din_p5_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p5_r1 <= 'h0;
din_p5_r2 <= 'h0;
din_p5_r3 <= 'h0;
din_p5_r4 <= 'h0;
din_p5_r5 <= 'h0;
end
else if(en)
begin
din_p5_r1 <= din_p5;
din_p5_r2 <= din_p5_r1;
din_p5_r3 <= din_p5_r2;
din_p5_r4 <= din_p5_r3;
din_p5_r5 <= din_p5_r4;
end
else
begin
din_p5_r1 <= din_p5_r1;
din_p5_r2 <= din_p5_r2;
din_p5_r3 <= din_p5_r3;
din_p5_r4 <= din_p5_r4;
din_p5_r5 <= din_p5_r5;
end
reg signed [15:0] din_p6_r1;
reg signed [15:0] din_p6_r2;
reg signed [15:0] din_p6_r3;
reg signed [15:0] din_p6_r4;
reg signed [15:0] din_p6_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p6_r1 <= 'h0;
din_p6_r2 <= 'h0;
din_p6_r3 <= 'h0;
din_p6_r4 <= 'h0;
din_p6_r5 <= 'h0;
end
else if(en)
begin
din_p6_r1 <= din_p6;
din_p6_r2 <= din_p6_r1;
din_p6_r3 <= din_p6_r2;
din_p6_r4 <= din_p6_r3;
din_p6_r5 <= din_p6_r4;
end
else
begin
din_p6_r1 <= din_p6_r1;
din_p6_r2 <= din_p6_r2;
din_p6_r3 <= din_p6_r3;
din_p6_r4 <= din_p6_r4;
din_p6_r5 <= din_p6_r5;
end
reg signed [15:0] din_p7_r1;
reg signed [15:0] din_p7_r2;
reg signed [15:0] din_p7_r3;
reg signed [15:0] din_p7_r4;
reg signed [15:0] din_p7_r5;
reg signed [15:0] din_p7_r6;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p7_r1 <= 'h0;
din_p7_r2 <= 'h0;
din_p7_r3 <= 'h0;
din_p7_r4 <= 'h0;
din_p7_r5 <= 'h0;
end
else if(en)
begin
din_p7_r1 <= din_p7;
din_p7_r2 <= din_p7_r1;
din_p7_r3 <= din_p7_r2;
din_p7_r4 <= din_p7_r3;
din_p7_r5 <= din_p7_r4;
end
else
begin
din_p7_r1 <= din_p7_r1;
din_p7_r2 <= din_p7_r2;
din_p7_r3 <= din_p7_r3;
din_p7_r4 <= din_p7_r4;
din_p7_r5 <= din_p7_r5;
end
wire signed [15:0] IIRout0_p0;
wire signed [15:0] IIRout0_p1;
wire signed [15:0] IIRout0_p2;
wire signed [15:0] IIRout0_p3;
wire signed [15:0] IIRout0_p4;
wire signed [15:0] IIRout0_p5;
wire signed [15:0] IIRout0_p6;
wire signed [15:0] IIRout0_p7;
IIR_top_ref inst_IIR_top_ref_0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re0 ),
.a_im (a_im0 ),
.ab_re (ab_re0 ),
.ab_im (ab_im0 ),
.abb_re (abb_re0 ),
.abb_im (abb_im0 ),
.ab_pow3_re (ab_pow3_re0 ),
.ab_pow3_im (ab_pow3_im0 ),
.ab_pow4_re (ab_pow4_re0 ),
.ab_pow4_im (ab_pow4_im0 ),
.ab_pow5_re (ab_pow5_re0 ),
.ab_pow5_im (ab_pow5_im0 ),
.ab_pow6_re (ab_pow6_re0 ),
.ab_pow6_im (ab_pow6_im0 ),
.ab_pow7_re (ab_pow7_re0 ),
.ab_pow7_im (ab_pow7_im0 ),
.b_pow8_re (b_pow8_re0 ),
.b_pow8_im (b_pow8_im0 ),
.IIRout_p0 (IIRout0_p0 ),
.IIRout_p1 (IIRout0_p1 ),
.IIRout_p2 (IIRout0_p2 ),
.IIRout_p3 (IIRout0_p3 ),
.IIRout_p4 (IIRout0_p4 ),
.IIRout_p5 (IIRout0_p5 ),
.IIRout_p6 (IIRout0_p6 ),
.IIRout_p7 (IIRout0_p7 )
);
wire signed [15:0] IIRout1_p0;
wire signed [15:0] IIRout1_p1;
wire signed [15:0] IIRout1_p2;
wire signed [15:0] IIRout1_p3;
wire signed [15:0] IIRout1_p4;
wire signed [15:0] IIRout1_p5;
wire signed [15:0] IIRout1_p6;
wire signed [15:0] IIRout1_p7;
IIR_top_ref inst_IIR_top_ref_1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re1 ),
.a_im (a_im1 ),
.ab_re (ab_re1 ),
.ab_im (ab_im1 ),
.abb_re (abb_re1 ),
.abb_im (abb_im1 ),
.ab_pow3_re (ab_pow3_re1 ),
.ab_pow3_im (ab_pow3_im1 ),
.ab_pow4_re (ab_pow4_re1 ),
.ab_pow4_im (ab_pow4_im1 ),
.ab_pow5_re (ab_pow5_re1 ),
.ab_pow5_im (ab_pow5_im1 ),
.ab_pow6_re (ab_pow6_re1 ),
.ab_pow6_im (ab_pow6_im1 ),
.ab_pow7_re (ab_pow7_re1 ),
.ab_pow7_im (ab_pow7_im1 ),
.b_pow8_re (b_pow8_re1 ),
.b_pow8_im (b_pow8_im1 ),
.IIRout_p0 (IIRout1_p0 ),
.IIRout_p1 (IIRout1_p1 ),
.IIRout_p2 (IIRout1_p2 ),
.IIRout_p3 (IIRout1_p3 ),
.IIRout_p4 (IIRout1_p4 ),
.IIRout_p5 (IIRout1_p5 ),
.IIRout_p6 (IIRout1_p6 ),
.IIRout_p7 (IIRout1_p7 )
);
wire signed [15:0] IIRout2_p0;
wire signed [15:0] IIRout2_p1;
wire signed [15:0] IIRout2_p2;
wire signed [15:0] IIRout2_p3;
wire signed [15:0] IIRout2_p4;
wire signed [15:0] IIRout2_p5;
wire signed [15:0] IIRout2_p6;
wire signed [15:0] IIRout2_p7;
IIR_top_ref inst_IIR_top_ref_2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re2 ),
.a_im (a_im2 ),
.ab_re (ab_re2 ),
.ab_im (ab_im2 ),
.abb_re (abb_re2 ),
.abb_im (abb_im2 ),
.ab_pow3_re (ab_pow3_re2 ),
.ab_pow3_im (ab_pow3_im2 ),
.ab_pow4_re (ab_pow4_re2 ),
.ab_pow4_im (ab_pow4_im2 ),
.ab_pow5_re (ab_pow5_re2 ),
.ab_pow5_im (ab_pow5_im2 ),
.ab_pow6_re (ab_pow6_re2 ),
.ab_pow6_im (ab_pow6_im2 ),
.ab_pow7_re (ab_pow7_re2 ),
.ab_pow7_im (ab_pow7_im2 ),
.b_pow8_re (b_pow8_re2 ),
.b_pow8_im (b_pow8_im2 ),
.IIRout_p0 (IIRout2_p0 ),
.IIRout_p1 (IIRout2_p1 ),
.IIRout_p2 (IIRout2_p2 ),
.IIRout_p3 (IIRout2_p3 ),
.IIRout_p4 (IIRout2_p4 ),
.IIRout_p5 (IIRout2_p5 ),
.IIRout_p6 (IIRout2_p6 ),
.IIRout_p7 (IIRout2_p7 )
);
wire signed [15:0] IIRout3_p0;
wire signed [15:0] IIRout3_p1;
wire signed [15:0] IIRout3_p2;
wire signed [15:0] IIRout3_p3;
wire signed [15:0] IIRout3_p4;
wire signed [15:0] IIRout3_p5;
wire signed [15:0] IIRout3_p6;
wire signed [15:0] IIRout3_p7;
IIR_top_ref inst_IIR_top_ref_3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re3 ),
.a_im (a_im3 ),
.ab_re (ab_re3 ),
.ab_im (ab_im3 ),
.abb_re (abb_re3 ),
.abb_im (abb_im3 ),
.ab_pow3_re (ab_pow3_re3 ),
.ab_pow3_im (ab_pow3_im3 ),
.ab_pow4_re (ab_pow4_re3 ),
.ab_pow4_im (ab_pow4_im3 ),
.ab_pow5_re (ab_pow5_re3 ),
.ab_pow5_im (ab_pow5_im3 ),
.ab_pow6_re (ab_pow6_re3 ),
.ab_pow6_im (ab_pow6_im3 ),
.ab_pow7_re (ab_pow7_re3 ),
.ab_pow7_im (ab_pow7_im3 ),
.b_pow8_re (b_pow8_re3 ),
.b_pow8_im (b_pow8_im3 ),
.IIRout_p0 (IIRout3_p0 ),
.IIRout_p1 (IIRout3_p1 ),
.IIRout_p2 (IIRout3_p2 ),
.IIRout_p3 (IIRout3_p3 ),
.IIRout_p4 (IIRout3_p4 ),
.IIRout_p5 (IIRout3_p5 ),
.IIRout_p6 (IIRout3_p6 ),
.IIRout_p7 (IIRout3_p7 )
);
wire signed [15:0] IIRout4_p0;
wire signed [15:0] IIRout4_p1;
wire signed [15:0] IIRout4_p2;
wire signed [15:0] IIRout4_p3;
wire signed [15:0] IIRout4_p4;
wire signed [15:0] IIRout4_p5;
wire signed [15:0] IIRout4_p6;
wire signed [15:0] IIRout4_p7;
IIR_top_ref inst_IIR_top_ref_4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re4 ),
.a_im (a_im4 ),
.ab_re (ab_re4 ),
.ab_im (ab_im4 ),
.abb_re (abb_re4 ),
.abb_im (abb_im4 ),
.ab_pow3_re (ab_pow3_re4 ),
.ab_pow3_im (ab_pow3_im4 ),
.ab_pow4_re (ab_pow4_re4 ),
.ab_pow4_im (ab_pow4_im4 ),
.ab_pow5_re (ab_pow5_re4 ),
.ab_pow5_im (ab_pow5_im4 ),
.ab_pow6_re (ab_pow6_re4 ),
.ab_pow6_im (ab_pow6_im4 ),
.ab_pow7_re (ab_pow7_re4 ),
.ab_pow7_im (ab_pow7_im4 ),
.b_pow8_re (b_pow8_re4 ),
.b_pow8_im (b_pow8_im4 ),
.IIRout_p0 (IIRout4_p0 ),
.IIRout_p1 (IIRout4_p1 ),
.IIRout_p2 (IIRout4_p2 ),
.IIRout_p3 (IIRout4_p3 ),
.IIRout_p4 (IIRout4_p4 ),
.IIRout_p5 (IIRout4_p5 ),
.IIRout_p6 (IIRout4_p6 ),
.IIRout_p7 (IIRout4_p7 )
);
wire signed [15:0] IIRout5_p0;
wire signed [15:0] IIRout5_p1;
wire signed [15:0] IIRout5_p2;
wire signed [15:0] IIRout5_p3;
wire signed [15:0] IIRout5_p4;
wire signed [15:0] IIRout5_p5;
wire signed [15:0] IIRout5_p6;
wire signed [15:0] IIRout5_p7;
IIR_top_ref inst_IIR_top_ref_5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re5 ),
.a_im (a_im5 ),
.ab_re (ab_re5 ),
.ab_im (ab_im5 ),
.abb_re (abb_re5 ),
.abb_im (abb_im5 ),
.ab_pow3_re (ab_pow3_re5 ),
.ab_pow3_im (ab_pow3_im5 ),
.ab_pow4_re (ab_pow4_re5 ),
.ab_pow4_im (ab_pow4_im5 ),
.ab_pow5_re (ab_pow5_re5 ),
.ab_pow5_im (ab_pow5_im5 ),
.ab_pow6_re (ab_pow6_re5 ),
.ab_pow6_im (ab_pow6_im5 ),
.ab_pow7_re (ab_pow7_re5 ),
.ab_pow7_im (ab_pow7_im5 ),
.b_pow8_re (b_pow8_re5 ),
.b_pow8_im (b_pow8_im5 ),
.IIRout_p0 (IIRout5_p0 ),
.IIRout_p1 (IIRout5_p1 ),
.IIRout_p2 (IIRout5_p2 ),
.IIRout_p3 (IIRout5_p3 ),
.IIRout_p4 (IIRout5_p4 ),
.IIRout_p5 (IIRout5_p5 ),
.IIRout_p6 (IIRout5_p6 ),
.IIRout_p7 (IIRout5_p7 )
);
wire signed [18:0] dout_p0_r0;
wire signed [18:0] dout_p1_r0;
wire signed [18:0] dout_p2_r0;
wire signed [18:0] dout_p3_r0;
wire signed [18:0] dout_p4_r0;
wire signed [18:0] dout_p5_r0;
wire signed [18:0] dout_p6_r0;
wire signed [18:0] dout_p7_r0;
assign dout_p0_r0 = din_p0_r5 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0;
assign dout_p1_r0 = din_p1_r5 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1;
assign dout_p2_r0 = din_p2_r5 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2;
assign dout_p3_r0 = din_p3_r5 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3;
assign dout_p4_r0 = din_p4_r5 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4;
assign dout_p5_r0 = din_p5_r5 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5;
assign dout_p6_r0 = din_p6_r5 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6;
assign dout_p7_r0 = din_p7_r5 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7;
reg signed [18:0] dout_p0_r1;
reg signed [15:0] dout_p [7:0];
wire signed [18:0] dout_p_r0 [0:7];
assign dout_p_r0[0] = dout_p0_r0;
assign dout_p_r0[1] = dout_p1_r0;
assign dout_p_r0[2] = dout_p2_r0;
assign dout_p_r0[3] = dout_p3_r0;
assign dout_p_r0[4] = dout_p4_r0;
assign dout_p_r0[5] = dout_p5_r0;
assign dout_p_r0[6] = dout_p6_r0;
assign dout_p_r0[7] = dout_p7_r0;
integer i;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (i = 0; i < 8; i = i + 1) begin
dout_p[i] <= 'h0;
end
end
else if (en) begin
for (i = 0; i < 8; i = i + 1) begin
if (dout_p_r0[i][16:15] == 2'b01)
dout_p[i] <= 16'd32767;
else if (dout_p_r0[i][16:15] == 2'b10)
dout_p[i] <= -16'd32768;
else
dout_p[i] <= dout_p_r0[i][15:0];
end
end
end
assign dout_p0 = dout_p[0];
assign dout_p1 = dout_p[1];
assign dout_p2 = dout_p[2];
assign dout_p3 = dout_p[3];
assign dout_p4 = dout_p[4];
assign dout_p5 = dout_p[5];
assign dout_p6 = dout_p[6];
assign dout_p7 = dout_p[7];
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_p0_r1 <= 16'd0;
end
else if(en)
begin
dout_p0_r1 <= dout_p0_r0;
end
else
begin
dout_p0_r1 <= dout_p0_r1;
end
reg signed [18:0] dout_p0_r2;
reg signed [18:0] dout_p0_r3;
reg signed [18:0] dout_p0_r4;
reg signed [18:0] dout_p0_r5;
reg signed [18:0] dout_p0_r6;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_p0_r2 <= 16'd0;
dout_p0_r3 <= 16'd0;
dout_p0_r4 <= 16'd0;
dout_p0_r5 <= 16'd0;
dout_p0_r6 <= 16'd0;
end
else if(en)
begin
dout_p0_r2 <= dout_p0_r1;
dout_p0_r3 <= dout_p0_r2;
dout_p0_r4 <= dout_p0_r3;
dout_p0_r5 <= dout_p0_r4;
dout_p0_r6 <= dout_p0_r5;
end
else
begin
dout_p0_r2 <= dout_p0_r2;
dout_p0_r3 <= dout_p0_r3;
dout_p0_r4 <= dout_p0_r4;
dout_p0_r5 <= dout_p0_r5;
dout_p0_r6 <= dout_p0_r6;
end
reg vldo_diff_r1;
reg vldo_diff_r2;
reg vldo_diff_r3;
reg vldo_diff_r4;
reg vldo_diff_r5;
reg vldo_diff_r6;
reg vldo_diff_r7;
reg vldo_diff_r8;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
vldo_diff_r1 <= 16'd0;
vldo_diff_r2 <= 16'd0;
vldo_diff_r3 <= 16'd0;
vldo_diff_r4 <= 16'd0;
vldo_diff_r5 <= 16'd0;
vldo_diff_r6 <= 16'd0;
vldo_diff_r7 <= 16'd0;
vldo_diff_r8 <= 16'd0;
end
else if(en) begin
vldo_diff_r1 <= vldo_diff;
vldo_diff_r2 <= vldo_diff_r1;
vldo_diff_r3 <= vldo_diff_r2;
vldo_diff_r4 <= vldo_diff_r3;
vldo_diff_r5 <= vldo_diff_r4;
vldo_diff_r6 <= vldo_diff_r5;
vldo_diff_r7 <= vldo_diff_r6;
vldo_diff_r8 <= vldo_diff_r7;
end
else begin
vldo_diff_r1 <= vldo_diff_r1;
vldo_diff_r2 <= vldo_diff_r2;
vldo_diff_r3 <= vldo_diff_r3;
vldo_diff_r4 <= vldo_diff_r4;
vldo_diff_r5 <= vldo_diff_r5;
vldo_diff_r6 <= vldo_diff_r6;
vldo_diff_r7 <= vldo_diff_r7;
vldo_diff_r8 <= vldo_diff_r8;
end
end
wire vldo_r0_h;
wire vldo_r0_l;
reg vldo_r0;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
vldo_r0 <= 0;
end
else if(vldo_r0_h)begin
vldo_r0 <= 1;
end
else if(vldo_r0_l)begin
vldo_r0 <= 0;
end
end
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ;
assign vldo = vldo_r0;
endmodule

236
rtl/ref/diff_p.v
View File

@ -1,236 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module diff_p_ref
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,output vldo
,output signed [15:0] dout_p0
,output signed [15:0] dout_p1
,output signed [15:0] dout_p2
,output signed [15:0] dout_p3
,output signed [15:0] dout_p4
,output signed [15:0] dout_p5
,output signed [15:0] dout_p6
,output signed [15:0] dout_p7
,output signed [15:0] diff_p0
,output signed [15:0] diff_p1
,output signed [15:0] diff_p2
,output signed [15:0] diff_p3
,output signed [15:0] diff_p4
,output signed [15:0] diff_p5
,output signed [15:0] diff_p6
,output signed [15:0] diff_p7
);
wire signed [15:0] din_p0_r0;
wire signed [15:0] din_p1_r0;
wire signed [15:0] din_p2_r0;
wire signed [15:0] din_p3_r0;
wire signed [15:0] din_p4_r0;
wire signed [15:0] din_p5_r0;
wire signed [15:0] din_p6_r0;
wire signed [15:0] din_p7_r0;
s2p_2_ref inst1_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din0),
.en (vldi),
.dout0 (din_p0_r0),
.dout1 (din_p4_r0)
,.vldo( vldo)
);
s2p_2_ref inst2_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din1),
.en (vldi),
.dout0 (din_p1_r0),
.dout1 (din_p5_r0)
,.vldo( )
);
s2p_2_ref inst3_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din2),
.en (vldi),
.dout0 (din_p2_r0),
.dout1 (din_p6_r0)
,.vldo( )
);
s2p_2_ref inst4_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din3),
.en (vldi),
.dout0 (din_p3_r0),
.dout1 (din_p7_r0)
,.vldo( )
);
reg signed [15:0] din_p0_r1;
reg signed [15:0] din_p1_r1;
reg signed [15:0] din_p2_r1;
reg signed [15:0] din_p3_r1;
reg signed [15:0] din_p4_r1;
reg signed [15:0] din_p5_r1;
reg signed [15:0] din_p6_r1;
reg signed [15:0] din_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p0_r1 <= 'h0;
din_p1_r1 <= 'h0;
din_p2_r1 <= 'h0;
din_p3_r1 <= 'h0;
din_p4_r1 <= 'h0;
din_p5_r1 <= 'h0;
din_p6_r1 <= 'h0;
din_p7_r1 <= 'h0;
end
else if(en)
begin
din_p0_r1 <= din_p0_r0;
din_p1_r1 <= din_p1_r0;
din_p2_r1 <= din_p2_r0;
din_p3_r1 <= din_p3_r0;
din_p4_r1 <= din_p4_r0;
din_p5_r1 <= din_p5_r0;
din_p6_r1 <= din_p6_r0;
din_p7_r1 <= din_p7_r0;
end
else
begin
din_p0_r1 <= din_p0_r1;
din_p1_r1 <= din_p1_r1;
din_p2_r1 <= din_p2_r1;
din_p3_r1 <= din_p3_r1;
din_p4_r1 <= din_p4_r1;
din_p5_r1 <= din_p5_r1;
din_p6_r1 <= din_p6_r1;
din_p7_r1 <= din_p7_r1;
end
assign dout_p0 = din_p0_r1;
assign dout_p1 = din_p1_r1;
assign dout_p2 = din_p2_r1;
assign dout_p3 = din_p3_r1;
assign dout_p4 = din_p4_r1;
assign dout_p5 = din_p5_r1;
assign dout_p6 = din_p6_r1;
assign dout_p7 = din_p7_r1;
wire signed [15:0] diff_p0_r0;
wire signed [15:0] diff_p1_r0;
wire signed [15:0] diff_p2_r0;
wire signed [15:0] diff_p3_r0;
wire signed [15:0] diff_p4_r0;
wire signed [15:0] diff_p5_r0;
wire signed [15:0] diff_p6_r0;
wire signed [15:0] diff_p7_r0;
assign diff_p0_r0 = din_p0_r0 - din_p7_r1;
assign diff_p1_r0 = din_p1_r0 - din_p0_r0;
assign diff_p2_r0 = din_p2_r0 - din_p1_r0;
assign diff_p3_r0 = din_p3_r0 - din_p2_r0;
assign diff_p4_r0 = din_p4_r0 - din_p3_r0;
assign diff_p5_r0 = din_p5_r0 - din_p4_r0;
assign diff_p6_r0 = din_p6_r0 - din_p5_r0;
assign diff_p7_r0 = din_p7_r0 - din_p6_r0;
reg signed [15:0] diff_p0_r1;
reg signed [15:0] diff_p1_r1;
reg signed [15:0] diff_p2_r1;
reg signed [15:0] diff_p3_r1;
reg signed [15:0] diff_p4_r1;
reg signed [15:0] diff_p5_r1;
reg signed [15:0] diff_p6_r1;
reg signed [15:0] diff_p7_r1;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
diff_p0_r1 <= 0;
diff_p1_r1 <= 0;
diff_p2_r1 <= 0;
diff_p3_r1 <= 0;
diff_p4_r1 <= 0;
diff_p5_r1 <= 0;
diff_p6_r1 <= 0;
diff_p7_r1 <= 0;
end
else if(en)begin
diff_p0_r1 <= diff_p0_r0;
diff_p1_r1 <= diff_p1_r0;
diff_p2_r1 <= diff_p2_r0;
diff_p3_r1 <= diff_p3_r0;
diff_p4_r1 <= diff_p4_r0;
diff_p5_r1 <= diff_p5_r0;
diff_p6_r1 <= diff_p6_r0;
diff_p7_r1 <= diff_p7_r0;
end
else begin
diff_p0_r1 <= diff_p0_r1;
diff_p1_r1 <= diff_p1_r1;
diff_p2_r1 <= diff_p2_r1;
diff_p3_r1 <= diff_p3_r1;
diff_p4_r1 <= diff_p4_r1;
diff_p5_r1 <= diff_p5_r1;
diff_p6_r1 <= diff_p6_r1;
diff_p7_r1 <= diff_p7_r1;
end
end
assign diff_p0 = diff_p0_r1;
assign diff_p1 = diff_p1_r1;
assign diff_p2 = diff_p2_r1;
assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
assign diff_p5 = diff_p5_r1;
assign diff_p6 = diff_p6_r1;
assign diff_p7 = diff_p7_r1;
endmodule

110
rtl/ref/mult_C.v
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@ -1,110 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C_ref #(
parameter integer A_width = 8
,parameter integer B_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division
)
(
clk,
rstn,
en,
a,
b,
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1:0] a;
input signed [B_width-1:0] b;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-frac_coef_width-1:0] Re;
output signed [A_width+D_width-frac_coef_width-1:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc;
wire signed [A_width+C_width:0] Re_round;
wire signed [A_width+D_width:0] Im_round;
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
assign Re = Re_round[A_width+D_width-1:frac_coef_width];
assign Im = Im_round[A_width+D_width-1:frac_coef_width];
endmodule

121
rtl/ref/s2p_2.v
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@ -1,121 +0,0 @@
module s2p_2_ref (
input clk,
input rst_n,
input [15:0] din,
input en,
output [15:0] dout0,
output [15:0] dout1,
output vldo
);
reg en_r1;
reg en_r2;
reg en_r3;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
en_r1 <= 0;
en_r2 <= 0;
en_r3 <= 0;
end
else begin
en_r1 <= en;
en_r2 <= en_r1;
end
end
assign vldo = en_r2;
reg cnt;
wire add_cnt;
wire end_cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 0;
end
else if(add_cnt)begin
if(end_cnt)
cnt <= 0;
else
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
assign add_cnt = en == 1'b1;
assign end_cnt = add_cnt && cnt== 2 - 1 ;
reg [ 15: 0] dout0_r0;
reg [ 15: 0] dout1_r0;
wire dout0_en;
wire dout1_en;
wire dout0_hold;
wire dout1_hold;
always @(*)begin
if(rst_n==1'b0)begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
else if(dout0_en)begin
dout0_r0 = din;
end
else if(dout1_en)begin
dout1_r0 = din;
end
else begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
end
assign dout0_en = add_cnt && cnt == 0;
assign dout1_en = add_cnt && cnt == 1;
reg [ 15: 0] dout0_r1;
reg [ 15: 0] dout1_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
else if(en)begin
dout0_r1 <= dout0_r0;
dout1_r1 <= dout1_r0;
end
else if(dout0_hold)begin
dout0_r1 <= dout0_r1;
dout1_r1 <= 16'd0;
end
else if(dout1_hold)begin
dout0_r1 <= 16'd0;
dout1_r1 <= dout1_r1;
end
else begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
end
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
reg [ 15: 0] dout0_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r2 <= 16'd0;
end
else begin
dout0_r2 <= dout0_r1;
end
end
assign dout0 = dout0_r2;
assign dout1 = dout1_r1;
endmodule

907
rtl/z_dsp/CoefGen.sv Normal file
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@ -0,0 +1,907 @@
module CoefGen #(
parameter data_in_width = 32
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
,parameter COMPLEX = 1 // 1:COMPLEX 0:REAL
)
(
input rstn
,input clk
,input [3:0] vldi
,input signed [31:0] a0_re
,input signed [31:0] b0_re
,input signed [31:0] a1_re
,input signed [31:0] b1_re
,input signed [31:0] a2_re
,input signed [31:0] b2_re
,input signed [31:0] a3_re
,input signed [31:0] b3_re
`ifdef COMPLEX
,input signed [31:0] a0_im
,input signed [31:0] b0_im
,input signed [31:0] a1_im
,input signed [31:0] b1_im
,input signed [31:0] a2_im
,input signed [31:0] b2_im
,input signed [31:0] a3_im
,input signed [31:0] b3_im
`endif
,output reg signed [31:0] a_re0
,output reg signed [31:0] b_re0
,output reg signed [31:0] ab_re0
,output reg signed [31:0] abb_re0
,output reg signed [31:0] ab_pow3_re0
,output reg signed [31:0] ab_pow4_re0
,output reg signed [31:0] ab_pow5_re0
,output reg signed [31:0] ab_pow6_re0
,output reg signed [31:0] ab_pow7_re0
,output reg signed [31:0] ab_pow8_re0
,output reg signed [31:0] ab_pow9_re0
,output reg signed [31:0] ab_powa_re0
,output reg signed [31:0] ab_powb_re0
,output reg signed [31:0] ab_powc_re0
,output reg signed [31:0] ab_powd_re0
,output reg signed [31:0] ab_powe_re0
,output reg signed [31:0] ab_powf_re0
,output reg signed [31:0] b_pow16_re0
,output reg signed [31:0] a_re1
,output reg signed [31:0] b_re1
,output reg signed [31:0] ab_re1
,output reg signed [31:0] abb_re1
,output reg signed [31:0] ab_pow3_re1
,output reg signed [31:0] ab_pow4_re1
,output reg signed [31:0] ab_pow5_re1
,output reg signed [31:0] ab_pow6_re1
,output reg signed [31:0] ab_pow7_re1
,output reg signed [31:0] ab_pow8_re1
,output reg signed [31:0] ab_pow9_re1
,output reg signed [31:0] ab_powa_re1
,output reg signed [31:0] ab_powb_re1
,output reg signed [31:0] ab_powc_re1
,output reg signed [31:0] ab_powd_re1
,output reg signed [31:0] ab_powe_re1
,output reg signed [31:0] ab_powf_re1
,output reg signed [31:0] b_pow16_re1
,output reg signed [31:0] a_re2
,output reg signed [31:0] b_re2
,output reg signed [31:0] ab_re2
,output reg signed [31:0] abb_re2
,output reg signed [31:0] ab_pow3_re2
,output reg signed [31:0] ab_pow4_re2
,output reg signed [31:0] ab_pow5_re2
,output reg signed [31:0] ab_pow6_re2
,output reg signed [31:0] ab_pow7_re2
,output reg signed [31:0] ab_pow8_re2
,output reg signed [31:0] ab_pow9_re2
,output reg signed [31:0] ab_powa_re2
,output reg signed [31:0] ab_powb_re2
,output reg signed [31:0] ab_powc_re2
,output reg signed [31:0] ab_powd_re2
,output reg signed [31:0] ab_powe_re2
,output reg signed [31:0] ab_powf_re2
,output reg signed [31:0] b_pow16_re2
,output reg signed [31:0] a_re3
,output reg signed [31:0] b_re3
,output reg signed [31:0] ab_re3
,output reg signed [31:0] abb_re3
,output reg signed [31:0] ab_pow3_re3
,output reg signed [31:0] ab_pow4_re3
,output reg signed [31:0] ab_pow5_re3
,output reg signed [31:0] ab_pow6_re3
,output reg signed [31:0] ab_pow7_re3
,output reg signed [31:0] ab_pow8_re3
,output reg signed [31:0] ab_pow9_re3
,output reg signed [31:0] ab_powa_re3
,output reg signed [31:0] ab_powb_re3
,output reg signed [31:0] ab_powc_re3
,output reg signed [31:0] ab_powd_re3
,output reg signed [31:0] ab_powe_re3
,output reg signed [31:0] ab_powf_re3
,output reg signed [31:0] b_pow16_re3
`ifdef COMPLEX
output reg signed [31:0] a_im0
,output reg signed [31:0] b_im0
,output reg signed [31:0] ab_im0
,output reg signed [31:0] abb_im0
,output reg signed [31:0] ab_pow3_im0
,output reg signed [31:0] ab_pow4_im0
,output reg signed [31:0] ab_pow5_im0
,output reg signed [31:0] ab_pow6_im0
,output reg signed [31:0] ab_pow7_im0
,output reg signed [31:0] ab_pow8_im0
,output reg signed [31:0] ab_pow9_im0
,output reg signed [31:0] ab_powa_im0
,output reg signed [31:0] ab_powb_im0
,output reg signed [31:0] ab_powc_im0
,output reg signed [31:0] ab_powd_im0
,output reg signed [31:0] ab_powe_im0
,output reg signed [31:0] ab_powf_im0
,output reg signed [31:0] b_pow16_im0
,output reg signed [31:0] a_im1
,output reg signed [31:0] b_im1
,output reg signed [31:0] ab_im1
,output reg signed [31:0] abb_im1
,output reg signed [31:0] ab_pow3_im1
,output reg signed [31:0] ab_pow4_im1
,output reg signed [31:0] ab_pow5_im1
,output reg signed [31:0] ab_pow6_im1
,output reg signed [31:0] ab_pow7_im1
,output reg signed [31:0] ab_pow8_im1
,output reg signed [31:0] ab_pow9_im1
,output reg signed [31:0] ab_powa_im1
,output reg signed [31:0] ab_powb_im1
,output reg signed [31:0] ab_powc_im1
,output reg signed [31:0] ab_powd_im1
,output reg signed [31:0] ab_powe_im1
,output reg signed [31:0] ab_powf_im1
,output reg signed [31:0] b_pow16_im1
,output reg signed [31:0] a_im2
,output reg signed [31:0] b_im2
,output reg signed [31:0] ab_im2
,output reg signed [31:0] abb_im2
,output reg signed [31:0] ab_pow3_im2
,output reg signed [31:0] ab_pow4_im2
,output reg signed [31:0] ab_pow5_im2
,output reg signed [31:0] ab_pow6_im2
,output reg signed [31:0] ab_pow7_im2
,output reg signed [31:0] ab_pow8_im2
,output reg signed [31:0] ab_pow9_im2
,output reg signed [31:0] ab_powa_im2
,output reg signed [31:0] ab_powb_im2
,output reg signed [31:0] ab_powc_im2
,output reg signed [31:0] ab_powd_im2
,output reg signed [31:0] ab_powe_im2
,output reg signed [31:0] ab_powf_im2
,output reg signed [31:0] b_pow16_im2
,output reg signed [31:0] a_im3
,output reg signed [31:0] b_im3
,output reg signed [31:0] ab_im3
,output reg signed [31:0] abb_im3
,output reg signed [31:0] ab_pow3_im3
,output reg signed [31:0] ab_pow4_im3
,output reg signed [31:0] ab_pow5_im3
,output reg signed [31:0] ab_pow6_im3
,output reg signed [31:0] ab_pow7_im3
,output reg signed [31:0] ab_pow8_im3
,output reg signed [31:0] ab_pow9_im3
,output reg signed [31:0] ab_powa_im3
,output reg signed [31:0] ab_powb_im3
,output reg signed [31:0] ab_powc_im3
,output reg signed [31:0] ab_powd_im3
,output reg signed [31:0] ab_powe_im3
,output reg signed [31:0] ab_powf_im3
,output reg signed [31:0] b_pow16_im3
`endif
);
reg vldi_or_r1;
wire vldi_or = | vldi;
sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn);
reg signed [data_in_width-1:0] a_re_r1;
reg signed [data_in_width-1:0] b_re_r1;
`ifdef COMPLEX
reg signed [data_in_width-1:0] a_im_r1;
reg signed [data_in_width-1:0] b_im_r1;
`endif
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
a_re_r1 <= 'h0;
b_re_r1 <= 'h0;
`ifdef COMPLEX
a_im_r1 <= 'h0;
b_im_r1 <= 'h0;
`endif
end
else if(|vldi) begin
case(1'b1)
vldi[0]: begin
a_re_r1 <= a0_re;
b_re_r1 <= b0_re;
`ifdef COMPLEX
a_im_r1 <= a0_im;
b_im_r1 <= b0_im;
`endif
end
vldi[1]: begin
a_re_r1 <= a1_re;
b_re_r1 <= b1_re;
`ifdef COMPLEX
a_im_r1 <= a1_im;
b_im_r1 <= b1_im;
`endif
end
vldi[2]: begin
a_re_r1 <= a2_re;
b_re_r1 <= b2_re;
`ifdef COMPLEX
a_im_r1 <= a2_im;
b_im_r1 <= b2_im;
`endif
end
vldi[3]: begin
a_re_r1 <= a3_re;
b_re_r1 <= b3_re;
`ifdef COMPLEX
a_im_r1 <= a3_im;
b_im_r1 <= b3_im;
`endif
end
endcase
end
end
reg en;
reg en_r1;
sirv_gnrl_dffr #(1) dff_en_1(en, en_r1 ,clk,rstn);
reg [4:0] cnt0;
wire add_cnt0;
wire end_cnt0;
always @(posedge clk or negedge rstn)begin
if(!rstn)begin
cnt0 <= 0;
end
else if(add_cnt0)begin
if(end_cnt0)
cnt0 <= 0;
else
cnt0 <= cnt0 + 1;
end
end
assign add_cnt0 = en;
assign end_cnt0 = add_cnt0 && cnt0== 16-1;
wire en_l;
wire en_h;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else if(en_h)begin
en <= 1;
end
else if(en_l)begin
en <= 0;
end
end
assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
assign en_l = end_cnt0;
reg signed [data_in_width-1:0] bin_re;
wire signed [data_in_width-1:0] bout_re;
`ifdef COMPLEX
reg signed [data_in_width-1:0] bin_im;
wire signed [data_in_width-1:0] bout_im;
`endif
always @(*)begin
if(en_r1) begin
bin_re <= bout_re;
`ifdef COMPLEX
bin_im <= bout_im;
`endif
end
else begin
bin_re <= 32'd2147483647;
`ifdef COMPLEX
bin_im <= 0;
`endif
end
end
wire signed [data_in_width-1:0] abo_re;
`ifdef COMPLEX
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.o_width(data_in_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (b_re_r1 ),
.d (b_im_r1 ),
.Re (bout_re ),
.Im (bout_im )
);
wire signed [data_in_width-1:0] abo_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.o_width(data_in_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (a_re_r1 ),
.d (a_im_r1 ),
.Re (abo_re ),
.Im (abo_im )
);
`else
mult_real
#(
.A_width(data_in_width)
,.C_width(coef_width)
,.o_width(data_in_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (bin_re ),
.coef (b_re_r1 ),
.dout (bout_re )
);
mult_real
#(
.A_width(data_in_width)
,.C_width(coef_width)
,.o_width(data_in_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (bin_re ),
.coef (a_re_r1 ),
.dout (abo_re )
);
`endif
reg signed [coef_width-1 :0] ao_re_r1 ;
reg signed [coef_width-1 :0] ab_re_r1 ;
reg signed [coef_width-1 :0] abb_re_r1 ;
reg signed [coef_width-1 :0] ab_pow3_re_r1;
reg signed [coef_width-1 :0] ab_pow4_re_r1;
reg signed [coef_width-1 :0] ab_pow5_re_r1;
reg signed [coef_width-1 :0] ab_pow6_re_r1;
reg signed [coef_width-1 :0] ab_pow7_re_r1;
reg signed [coef_width-1 :0] ab_pow8_re_r1;
reg signed [coef_width-1 :0] ab_pow9_re_r1;
reg signed [coef_width-1 :0] ab_powa_re_r1;
reg signed [coef_width-1 :0] ab_powb_re_r1;
reg signed [coef_width-1 :0] ab_powc_re_r1;
reg signed [coef_width-1 :0] ab_powd_re_r1;
reg signed [coef_width-1 :0] ab_powe_re_r1;
reg signed [coef_width-1 :0] ab_powf_re_r1;
reg signed [coef_width-1 :0] bo_re_r1 ;
reg signed [coef_width-1 :0] b_pow16_re_r1 ;
`ifdef COMPLEX
reg signed [coef_width-1 :0] ao_im_r1 ;
reg signed [coef_width-1 :0] ab_im_r1 ;
reg signed [coef_width-1 :0] abb_im_r1 ;
reg signed [coef_width-1 :0] ab_pow3_im_r1;
reg signed [coef_width-1 :0] ab_pow4_im_r1;
reg signed [coef_width-1 :0] ab_pow5_im_r1;
reg signed [coef_width-1 :0] ab_pow6_im_r1;
reg signed [coef_width-1 :0] ab_pow7_im_r1;
reg signed [coef_width-1 :0] ab_pow8_im_r1;
reg signed [coef_width-1 :0] ab_pow9_im_r1;
reg signed [coef_width-1 :0] ab_powa_im_r1;
reg signed [coef_width-1 :0] ab_powb_im_r1;
reg signed [coef_width-1 :0] ab_powc_im_r1;
reg signed [coef_width-1 :0] ab_powd_im_r1;
reg signed [coef_width-1 :0] ab_powe_im_r1;
reg signed [coef_width-1 :0] ab_powf_im_r1;
reg signed [coef_width-1 :0] bo_im_r1 ;
reg signed [coef_width-1 :0] b_pow16_im_r1 ;
`endif
always @(posedge clk or negedge rstn)begin
if(!rstn)begin
ao_re_r1 <= 0;
ab_re_r1 <= 0;
abb_re_r1 <= 0;
ab_pow3_re_r1 <= 0;
ab_pow4_re_r1 <= 0;
ab_pow5_re_r1 <= 0;
ab_pow6_re_r1 <= 0;
ab_pow7_re_r1 <= 0;
ab_pow8_re_r1 <= 0;
ab_pow9_re_r1 <= 0;
ab_powa_re_r1 <= 0;
ab_powb_re_r1 <= 0;
ab_powc_re_r1 <= 0;
ab_powd_re_r1 <= 0;
ab_powe_re_r1 <= 0;
ab_powf_re_r1 <= 0;
bo_re_r1 <= 0;
b_pow16_re_r1 <= 0;
`ifdef COMPLEX
ao_im_r1 <= 0;
ab_im_r1 <= 0;
abb_im_r1 <= 0;
ab_pow3_im_r1 <= 0;
ab_pow4_im_r1 <= 0;
ab_pow5_im_r1 <= 0;
ab_pow6_im_r1 <= 0;
ab_pow7_im_r1 <= 0;
ab_pow8_im_r1 <= 0;
ab_pow9_im_r1 <= 0;
ab_powa_im_r1 <= 0;
ab_powb_im_r1 <= 0;
ab_powc_im_r1 <= 0;
ab_powd_im_r1 <= 0;
ab_powe_im_r1 <= 0;
ab_powf_im_r1 <= 0;
bo_im_r1 <= 0;
b_pow16_im_r1 <= 0;
`endif
end
else if(add_cnt0 && cnt0 == 1 && en_r1)begin
ao_re_r1 <= abo_re;
bo_re_r1 <= bin_re;
`ifdef COMPLEX
ao_im_r1 <= abo_im;
bo_im_r1 <= bin_im;
`endif
end
else if(add_cnt0 && cnt0 == 2 && en_r1)begin
ab_re_r1 <= abo_re;
`ifdef COMPLEX
ab_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 3 && en_r1)begin
abb_re_r1 <= abo_re;
`ifdef COMPLEX
abb_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 4 && en_r1)begin
ab_pow3_re_r1 <= abo_re;
`ifdef COMPLEX
ab_pow3_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 5 && en_r1)begin
ab_pow4_re_r1 <= abo_re;
`ifdef COMPLEX
ab_pow4_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 6 && en_r1)begin
ab_pow5_re_r1 <= abo_re;
`ifdef COMPLEX
ab_pow5_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 7 && en_r1)begin
ab_pow6_re_r1 <= abo_re;
`ifdef COMPLEX
ab_pow6_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 8 && en_r1)begin
ab_pow7_re_r1 <= abo_re;
`ifdef COMPLEX
ab_pow7_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 9 && en_r1)begin
ab_pow8_re_r1 <= abo_re;
`ifdef COMPLEX
ab_pow8_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 10 && en_r1)begin
ab_pow9_re_r1 <= abo_re;
`ifdef COMPLEX
ab_pow9_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 11 && en_r1)begin
ab_powa_re_r1 <= abo_re;
`ifdef COMPLEX
ab_powa_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 12 && en_r1)begin
ab_powb_re_r1 <= abo_re;
`ifdef COMPLEX
ab_powb_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 13 && en_r1)begin
ab_powc_re_r1 <= abo_re;
`ifdef COMPLEX
ab_powc_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 14 && en_r1)begin
ab_powd_re_r1 <= abo_re;
`ifdef COMPLEX
ab_powd_im_r1 <= abo_im;
`endif
end
else if(add_cnt0 && cnt0 == 15 && en_r1)begin
ab_powe_re_r1 <= abo_re;
`ifdef COMPLEX
ab_powe_im_r1 <= abo_im;
`endif
end
else if(cnt0 == 0 && en_r1)begin
ab_powf_re_r1 <= abo_re;
b_pow16_re_r1 <= bin_re;
`ifdef COMPLEX
ab_powf_im_r1 <= abo_im;
b_pow16_im_r1 <= bin_im;
`endif
end
end
reg [3:0] vldi_r1;
reg [3:0] vldi_r2;
reg [3:0] vldi_r3;
reg [3:0] vldi_r4;
reg [3:0] vldi_r5;
reg [3:0] vldi_r6;
reg [3:0] vldi_r7;
reg [3:0] vldi_r8;
reg [3:0] vldi_r9;
reg [3:0] vldi_r10;
reg [3:0] vldi_r11;
reg [3:0] vldi_r12;
reg [3:0] vldi_r13;
reg [3:0] vldi_r14;
reg [3:0] vldi_r15;
reg [3:0] vldi_r16;
reg [3:0] vldi_r17;
reg [3:0] vldi_r18;
sirv_gnrl_dffr #(4) dff_vldi_1(vldi,vldi_r1,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_11(vldi_r10, vldi_r11,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_12(vldi_r11, vldi_r12,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_13(vldi_r12, vldi_r13,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_14(vldi_r13, vldi_r14,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_15(vldi_r14, vldi_r15,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_16(vldi_r15, vldi_r16,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_17(vldi_r16, vldi_r17,clk,rstn);
sirv_gnrl_dffr #(4) dff_vldi_18(vldi_r17, vldi_r18,clk,rstn);
always @(posedge clk or negedge rstn) begin
if(!rstn) begin
a_re0 <= 0;
b_re0 <= 0;
ab_re0 <= 0;
abb_re0 <= 0;
ab_pow3_re0 <= 0;
ab_pow4_re0 <= 0;
ab_pow5_re0 <= 0;
ab_pow6_re0 <= 0;
ab_pow7_re0 <= 0;
ab_pow8_re0 <= 0;
ab_pow9_re0 <= 0;
ab_powa_re0 <= 0;
ab_powb_re0 <= 0;
ab_powc_re0 <= 0;
ab_powd_re0 <= 0;
ab_powe_re0 <= 0;
ab_powf_re0 <= 0;
b_pow16_re0 <= 0;
a_re1 <= 0;
b_re1 <= 0;
ab_re1 <= 0;
abb_re1 <= 0;
ab_pow3_re1 <= 0;
ab_pow4_re1 <= 0;
ab_pow5_re1 <= 0;
ab_pow6_re1 <= 0;
ab_pow7_re1 <= 0;
ab_pow8_re1 <= 0;
ab_pow9_re1 <= 0;
ab_powa_re1 <= 0;
ab_powb_re1 <= 0;
ab_powc_re1 <= 0;
ab_powd_re1 <= 0;
ab_powe_re1 <= 0;
ab_powf_re1 <= 0;
b_pow16_re1 <= 0;
a_re2 <= 0;
b_re2 <= 0;
ab_re2 <= 0;
abb_re2 <= 0;
ab_pow3_re2 <= 0;
ab_pow4_re2 <= 0;
ab_pow5_re2 <= 0;
ab_pow6_re2 <= 0;
ab_pow7_re2 <= 0;
ab_pow8_re2 <= 0;
ab_pow9_re2 <= 0;
ab_powa_re2 <= 0;
ab_powb_re2 <= 0;
ab_powc_re2 <= 0;
ab_powd_re2 <= 0;
ab_powe_re2 <= 0;
ab_powf_re2 <= 0;
b_pow16_re2 <= 0;
a_re3 <= 0;
b_re3 <= 0;
ab_re3 <= 0;
abb_re3 <= 0;
ab_pow3_re3 <= 0;
ab_pow4_re3 <= 0;
ab_pow5_re3 <= 0;
ab_pow6_re3 <= 0;
ab_pow7_re3 <= 0;
ab_pow8_re3 <= 0;
ab_pow9_re3 <= 0;
ab_powa_re3 <= 0;
ab_powb_re3 <= 0;
ab_powc_re3 <= 0;
ab_powd_re3 <= 0;
ab_powe_re3 <= 0;
ab_powf_re3 <= 0;
b_pow16_re3 <= 0;
`ifdef COMPLEX
a_im0 <= 0;
b_im0 <= 0;
ab_im0 <= 0;
abb_im0 <= 0;
ab_pow3_im0 <= 0;
ab_pow4_im0 <= 0;
ab_pow5_im0 <= 0;
ab_pow6_im0 <= 0;
ab_pow7_im0 <= 0;
ab_pow8_im0 <= 0;
ab_pow9_im0 <= 0;
ab_powa_im0 <= 0;
ab_powb_im0 <= 0;
ab_powc_im0 <= 0;
ab_powd_im0 <= 0;
ab_powe_im0 <= 0;
ab_powf_im0 <= 0;
b_pow16_im0 <= 0;
a_im1 <= 0;
b_im1 <= 0;
ab_im1 <= 0;
abb_im1 <= 0;
ab_pow3_im1 <= 0;
ab_pow4_im1 <= 0;
ab_pow5_im1 <= 0;
ab_pow6_im1 <= 0;
ab_pow7_im1 <= 0;
ab_pow8_im1 <= 0;
ab_pow9_im1 <= 0;
ab_powa_im1 <= 0;
ab_powb_im1 <= 0;
ab_powc_im1 <= 0;
ab_powd_im1 <= 0;
ab_powe_im1 <= 0;
ab_powf_im1 <= 0;
b_pow16_im1 <= 0;
a_im2 <= 0;
b_im2 <= 0;
ab_im2 <= 0;
abb_im2 <= 0;
ab_pow3_im2 <= 0;
ab_pow4_im2 <= 0;
ab_pow5_im2 <= 0;
ab_pow6_im2 <= 0;
ab_pow7_im2 <= 0;
ab_pow8_im2 <= 0;
ab_pow9_im2 <= 0;
ab_powa_im2 <= 0;
ab_powb_im2 <= 0;
ab_powc_im2 <= 0;
ab_powd_im2 <= 0;
ab_powe_im2 <= 0;
ab_powf_im2 <= 0;
b_pow16_im2 <= 0;
a_im3 <= 0;
b_im3 <= 0;
ab_im3 <= 0;
abb_im3 <= 0;
ab_pow3_im3 <= 0;
ab_pow4_im3 <= 0;
ab_pow5_im3 <= 0;
ab_pow6_im3 <= 0;
ab_pow7_im3 <= 0;
ab_pow8_im3 <= 0;
ab_pow9_im3 <= 0;
ab_powa_im3 <= 0;
ab_powb_im3 <= 0;
ab_powc_im3 <= 0;
ab_powd_im3 <= 0;
ab_powe_im3 <= 0;
ab_powf_im3 <= 0;
b_pow16_im3 <= 0;
`endif
end
else if(|vldi_r18) begin
case(1'b1)
vldi_r18[0]: begin
a_re0 <= ao_re_r1 ;
b_re0 <= bo_re_r1 ;
ab_re0 <= ab_re_r1 ;
abb_re0 <= abb_re_r1 ;
ab_pow3_re0 <= ab_pow3_re_r1;
ab_pow4_re0 <= ab_pow4_re_r1;
ab_pow5_re0 <= ab_pow5_re_r1;
ab_pow6_re0 <= ab_pow6_re_r1;
ab_pow7_re0 <= ab_pow7_re_r1;
ab_pow8_re0 <= ab_pow8_re_r1;
ab_pow9_re0 <= ab_pow9_re_r1;
ab_powa_re0 <= ab_powa_re_r1;
ab_powb_re0 <= ab_powb_re_r1;
ab_powc_re0 <= ab_powc_re_r1;
ab_powd_re0 <= ab_powd_re_r1;
ab_powe_re0 <= ab_powe_re_r1;
ab_powf_re0 <= ab_powf_re_r1;
b_pow16_re0 <= b_pow16_re_r1;
`ifdef COMPLEX
a_im0 <= ao_im_r1 ;
b_im0 <= bo_im_r1 ;
ab_im0 <= ab_im_r1 ;
abb_im0 <= abb_im_r1 ;
ab_pow3_im0 <= ab_pow3_im_r1;
ab_pow4_im0 <= ab_pow4_im_r1;
ab_pow5_im0 <= ab_pow5_im_r1;
ab_pow6_im0 <= ab_pow6_im_r1;
ab_pow7_im0 <= ab_pow7_im_r1;
ab_pow8_im0 <= ab_pow8_im_r1;
ab_pow9_im0 <= ab_pow9_im_r1;
ab_powa_im0 <= ab_powa_im_r1;
ab_powb_im0 <= ab_powb_im_r1;
ab_powc_im0 <= ab_powc_im_r1;
ab_powd_im0 <= ab_powd_im_r1;
ab_powe_im0 <= ab_powe_im_r1;
ab_powf_im0 <= ab_powf_im_r1;
b_pow16_im0 <= b_pow16_im_r1;
`endif
end
vldi_r18[1]: begin
a_re1 <= ao_re_r1 ;
b_re1 <= bo_re_r1 ;
ab_re1 <= ab_re_r1 ;
abb_re1 <= abb_re_r1 ;
ab_pow3_re1 <= ab_pow3_re_r1;
ab_pow4_re1 <= ab_pow4_re_r1;
ab_pow5_re1 <= ab_pow5_re_r1;
ab_pow6_re1 <= ab_pow6_re_r1;
ab_pow7_re1 <= ab_pow7_re_r1;
ab_pow8_re1 <= ab_pow8_re_r1;
ab_pow9_re1 <= ab_pow9_re_r1;
ab_powa_re1 <= ab_powa_re_r1;
ab_powb_re1 <= ab_powb_re_r1;
ab_powc_re1 <= ab_powc_re_r1;
ab_powd_re1 <= ab_powd_re_r1;
ab_powe_re1 <= ab_powe_re_r1;
ab_powf_re1 <= ab_powf_re_r1;
b_pow16_re1 <= b_pow16_re_r1;
`ifdef COMPLEX
a_im1 <= ao_im_r1 ;
b_im1 <= bo_im_r1 ;
ab_im1 <= ab_im_r1 ;
abb_im1 <= abb_im_r1 ;
ab_pow3_im1 <= ab_pow3_im_r1;
ab_pow4_im1 <= ab_pow4_im_r1;
ab_pow5_im1 <= ab_pow5_im_r1;
ab_pow6_im1 <= ab_pow6_im_r1;
ab_pow7_im1 <= ab_pow7_im_r1;
ab_pow8_im1 <= ab_pow8_im_r1;
ab_pow9_im1 <= ab_pow9_im_r1;
ab_powa_im1 <= ab_powa_im_r1;
ab_powb_im1 <= ab_powb_im_r1;
ab_powc_im1 <= ab_powc_im_r1;
ab_powd_im1 <= ab_powd_im_r1;
ab_powe_im1 <= ab_powe_im_r1;
ab_powf_im1 <= ab_powf_im_r1;
b_pow16_im1 <= b_pow16_im_r1;
`endif
end
vldi_r18[2]: begin
a_re2 <= ao_re_r1 ;
b_re2 <= bo_re_r1 ;
ab_re2 <= ab_re_r1 ;
abb_re2 <= abb_re_r1 ;
ab_pow3_re2 <= ab_pow3_re_r1;
ab_pow4_re2 <= ab_pow4_re_r1;
ab_pow5_re2 <= ab_pow5_re_r1;
ab_pow6_re2 <= ab_pow6_re_r1;
ab_pow7_re2 <= ab_pow7_re_r1;
ab_pow8_re2 <= ab_pow8_re_r1;
ab_pow9_re2 <= ab_pow9_re_r1;
ab_powa_re2 <= ab_powa_re_r1;
ab_powb_re2 <= ab_powb_re_r1;
ab_powc_re2 <= ab_powc_re_r1;
ab_powd_re2 <= ab_powd_re_r1;
ab_powe_re2 <= ab_powe_re_r1;
ab_powf_re2 <= ab_powf_re_r1;
b_pow16_re2 <= b_pow16_re_r1;
`ifdef COMPLEX
a_im2 <= ao_im_r1 ;
b_im2 <= bo_im_r1 ;
ab_im2 <= ab_im_r1 ;
abb_im2 <= abb_im_r1 ;
ab_pow3_im2 <= ab_pow3_im_r1;
ab_pow4_im2 <= ab_pow4_im_r1;
ab_pow5_im2 <= ab_pow5_im_r1;
ab_pow6_im2 <= ab_pow6_im_r1;
ab_pow7_im2 <= ab_pow7_im_r1;
ab_pow8_im2 <= ab_pow8_im_r1;
ab_pow9_im2 <= ab_pow9_im_r1;
ab_powa_im2 <= ab_powa_im_r1;
ab_powb_im2 <= ab_powb_im_r1;
ab_powc_im2 <= ab_powc_im_r1;
ab_powd_im2 <= ab_powd_im_r1;
ab_powe_im2 <= ab_powe_im_r1;
ab_powf_im2 <= ab_powf_im_r1;
b_pow16_im2 <= b_pow16_im_r1;
`endif
end
vldi_r18[3]: begin
a_re3 <= ao_re_r1 ;
b_re3 <= bo_re_r1 ;
ab_re3 <= ab_re_r1 ;
abb_re3 <= abb_re_r1 ;
ab_pow3_re3 <= ab_pow3_re_r1;
ab_pow4_re3 <= ab_pow4_re_r1;
ab_pow5_re3 <= ab_pow5_re_r1;
ab_pow6_re3 <= ab_pow6_re_r1;
ab_pow7_re3 <= ab_pow7_re_r1;
ab_pow8_re3 <= ab_pow8_re_r1;
ab_pow9_re3 <= ab_pow9_re_r1;
ab_powa_re3 <= ab_powa_re_r1;
ab_powb_re3 <= ab_powb_re_r1;
ab_powc_re3 <= ab_powc_re_r1;
ab_powd_re3 <= ab_powd_re_r1;
ab_powe_re3 <= ab_powe_re_r1;
ab_powf_re3 <= ab_powf_re_r1;
b_pow16_re3 <= b_pow16_re_r1;
`ifdef COMPLEX
a_im3 <= ao_im_r1 ;
b_im3 <= bo_im_r1 ;
ab_im3 <= ab_im_r1 ;
abb_im3 <= abb_im_r1 ;
ab_pow3_im3 <= ab_pow3_im_r1;
ab_pow4_im3 <= ab_pow4_im_r1;
ab_pow5_im3 <= ab_pow5_im_r1;
ab_pow6_im3 <= ab_pow6_im_r1;
ab_pow7_im3 <= ab_pow7_im_r1;
ab_pow8_im3 <= ab_pow8_im_r1;
ab_pow9_im3 <= ab_pow9_im_r1;
ab_powa_im3 <= ab_powa_im_r1;
ab_powb_im3 <= ab_powb_im_r1;
ab_powc_im3 <= ab_powc_im_r1;
ab_powd_im3 <= ab_powd_im_r1;
ab_powe_im3 <= ab_powe_im_r1;
ab_powf_im3 <= ab_powf_im_r1;
b_pow16_im3 <= b_pow16_im_r1;
`endif
end
endcase
end
end
endmodule

270
rtl/z_dsp/IIR_Filter_p1.v
View File

@ -1,132 +1,138 @@
//+FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p1 #(
// Company: parameter coef_width = 32
//----------------------------------------------------------------------------------------------------------------- ,parameter a_width = 18
// File Name : IIR_Filter_p1.v ,parameter b_width = 18
// Department : ,parameter data_in_width = 16
// Author : hdzhang ,parameter cascade_in_width = 16
// Author's Tel : ,parameter data_out_width = 16
//----------------------------------------------------------------------------------------------------------------- ,parameter temp_var_width = data_out_width + 1
// Relese History )
// Version Date Author Description //H(z) = a / (1 - b*z^-1)
// 0.0 2025-03-09 hdzhang (
//2024-05-28 10:22:49 input rstn
//----------------------------------------------------------------------------------------------------------------- ,input clk
// Keywords : ,input en
// ,input signed [data_in_width-1 :0] din_re // Re(x(t))
//----------------------------------------------------------------------------------------------------------------- ,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1))
// Parameter ,input signed [coef_width-1 :0] a_re
// ,input signed [coef_width-1 :0] b_re
//----------------------------------------------------------------------------------------------------------------- `ifdef COMPLEX
// Purpose : input signed [cascade_in_width-1:0] dout_r1_im; // Im(y(t-1))
// input signed [coef_width-1 :0] a_im;
//----------------------------------------------------------------------------------------------------------------- input signed [coef_width-1 :0] b_im;
// Target Device: output signed [data_out_width-1:0] dout_im; // Im(y(t-16))
// Tool versions: `endif
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues ,output signed [data_out_width-1:0] dout_re // Re(y(t-16))
// Reset Strategy: );
// Clock Domains: wire signed [temp_var_width-1 :0] x1_re;
// Critical Timing: wire signed [temp_var_width-1 :0] y1_re;
// Asynchronous I/F: wire signed [temp_var_width :0] y_re;
// Synthesizable (y/n): wire signed [data_out_width-1:0] y_re_trunc;
// Other: `ifdef COMPLEX
//-FHDR-------------------------------------------------------------------------------------------------------- wire signed [temp_var_width-1 :0] x1_im;
module IIR_Filter_p1 #( wire signed [temp_var_width-1 :0] y1_im;
parameter coef_width = 32 wire signed [temp_var_width :0] y_im;
,parameter data_in_width = 16 wire signed [data_out_width-1:0] y_im_trunc;
,parameter cascade_in_width = 37 // x1 = a * din delay M = a*x(t-8)
,parameter temp_var_width = cascade_in_width - 1 mult_x
,parameter data_out_width = cascade_in_width - 2 #(
) .A_width (data_in_width )
//H(z) = a / (1 - b*z^-1) ,.C_width (coef_width )
( ,.D_width (coef_width )
input rstn ,.o_width (temp_var_width )
,input clk )
,input en inst_c1 (
,input signed [data_in_width-1 :0] din_re // Re(x(t)) .clk (clk ),
,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1)) .rstn (rstn ),
,input signed [cascade_in_width-1:0] dout_r1_im // Im(y(t-1)) .en (en ),
,input signed [coef_width-1 :0] a_re .a (din_re ),
,input signed [coef_width-1 :0] a_im .c (a_re ),
,input signed [coef_width-1 :0] b_re .d (a_im ),
,input signed [coef_width-1 :0] b_im .Re (x1_re ),
.Im (x1_im )
,output signed [data_out_width-1:0] dout_re // Re(y(t-16)) );
,output signed [data_out_width-1:0] dout_im // Im(y(t-16)) // y1 = b * dout_r1 delay M = b*y(t-9)
); mult_C
#(
.A_width (cascade_in_width )
wire signed [temp_var_width-1 :0] x1_re; ,.B_width (cascade_in_width )
wire signed [temp_var_width-1 :0] x1_im; ,.C_width (coef_width )
,.D_width (coef_width )
wire signed [temp_var_width-1 :0] y1_re; ,.o_width (temp_var_width )
wire signed [temp_var_width-1 :0] y1_im; )
wire signed [temp_var_width :0] y_re; inst_c3 (
wire signed [temp_var_width :0] y_im; .clk (clk ),
.rstn (rstn ),
wire signed [data_out_width-1:0] y_re_trunc; .en (en ),
wire signed [data_out_width-1:0] y_im_trunc; .a (dout_r1_re ),
.b (dout_r1_im ),
.c (b_re ),
// x1 = a * din delay M = a*x(t-8) .d (b_im ),
mult_x .Re (y1_re ),
#( .Im (y1_im )
.A_width (data_in_width ) );
,.C_width (coef_width ) assign y_re = x1_re + y1_re;
,.D_width (coef_width ) assign y_im = x1_im + y1_im;
,.o_width (temp_var_width ) // dout = round(y) delay M = round(y(t-16))
) trunc #(
inst_c1 ( .diw (temp_var_width+1 )
.clk (clk ), ,.msb (temp_var_width-1 )
.rstn (rstn ), ,.lsb (temp_var_width-data_out_width )
.en (en ), ) round_u1 (clk, rstn, en, y_re, y_re_trunc);
.a (din_re ), trunc #(
.c (a_re ), .diw (temp_var_width+1 )
.d (a_im ), ,.msb (temp_var_width-1 )
.Re (x1_re ), ,.lsb (temp_var_width-data_out_width )
.Im (x1_im ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc);
); assign dout_re = y_re_trunc;
assign dout_im = y_im_trunc;
`else
// y1 = b * dout_r1 delay M = b*y(t-9) // x1 = a * din delay M = a*x(t-8)
// y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) mult_real
mult_C #(
#( .A_width (data_in_width )
.A_width (cascade_in_width ) ,.C_width (a_width )
,.B_width (cascade_in_width ) ,.o_width (temp_var_width )
,.C_width (coef_width ) )
,.D_width (coef_width ) inst_c1 (
,.o_width (temp_var_width ) .clk (clk ),
) .rstn (rstn ),
inst_c3 ( .en (en ),
.clk (clk ), .din (din_re ),
.rstn (rstn ), .coef (a_re[coef_width-1 : coef_width-a_width]),
.en (en ), .dout (x1_re )
.a (dout_r1_re ), );
.b (dout_r1_im ),
.c (b_re ),
.d (b_im ), // y1 = b * dout_r1 delay M = b*y(t-9)
.Re (y1_re ), // y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8)
.Im (y1_im ) mult_real
); #(
.A_width (cascade_in_width )
assign y_re = x1_re + y1_re; ,.C_width (b_width )
assign y_im = x1_im + y1_im; ,.o_width (temp_var_width )
)
inst_c2 (
// dout = round(y) delay M = round(y(t-16)) .clk (clk ),
trunc #( .rstn (rstn ),
.diw (temp_var_width+1 ) .en (en ),
,.msb (temp_var_width-1 ) .din (dout_r1_re ),
,.lsb (temp_var_width-data_out_width ) .coef (b_re[coef_width-1 : coef_width-b_width]),
) round_u1 (clk, rstn, en, y_re, y_re_trunc); .dout (y1_re )
trunc #( );
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 ) // dout = round(y) delay M = round(y(t-16))
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc); trunc #(
.diw (temp_var_width+1 )
assign dout_re = y_re_trunc; ,.msb (temp_var_width-1 )
assign dout_im = y_im_trunc; ,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
endmodule
`endif
assign y_re = x1_re + y1_re;
assign dout_re = y_re_trunc;
endmodule

272
rtl/z_dsp/IIR_Filter_p16.v Normal file
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@ -0,0 +1,272 @@
module IIR_Filter_p16 #(
parameter coef_width = 32
,parameter b_pow16_width = 29
,parameter ab_pow_width = 32
,parameter data_in_width = 16
,parameter data_out_width = 16
,parameter temp_var_width = 29
)
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1 :0] dinp0 //x(8n+16)
,input signed [data_in_width-1 :0] dinp1 //x(8n+15)
,input signed [data_in_width-1 :0] dinp2 //x(8n+14)
,input signed [data_in_width-1 :0] dinp3 //x(8n+13)
,input signed [data_in_width-1 :0] dinp4 //x(8n+12)
,input signed [data_in_width-1 :0] dinp5 //x(8n+11)
,input signed [data_in_width-1 :0] dinp6 //x(8n+10)
,input signed [data_in_width-1 :0] dinp7 //x(8n+9)
,input signed [data_in_width-1 :0] dinp8
,input signed [data_in_width-1 :0] dinp9
,input signed [data_in_width-1 :0] dinpa
,input signed [data_in_width-1 :0] dinpb
,input signed [data_in_width-1 :0] dinpc
,input signed [data_in_width-1 :0] dinpd
,input signed [data_in_width-1 :0] dinpe
,input signed [data_in_width-1 :0] dinpf
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow8_re
,input signed [coef_width-1 :0] ab_pow9_re
,input signed [coef_width-1 :0] ab_powa_re
,input signed [coef_width-1 :0] ab_powb_re
,input signed [coef_width-1 :0] ab_powc_re
,input signed [coef_width-1 :0] ab_powd_re
,input signed [coef_width-1 :0] ab_powe_re
,input signed [coef_width-1 :0] ab_powf_re
,input signed [coef_width-1 :0] b_pow16_re
,output signed [data_out_width-1:0] dout_re // Re(y(8n-8))
`ifdef COMPLEX
input signed [coef_width-1 :0] a_im;
input signed [coef_width-1 :0] ab_im;
input signed [coef_width-1 :0] abb_im;
input signed [coef_width-1 :0] ab_pow3_im;
input signed [coef_width-1 :0] ab_pow4_im;
input signed [coef_width-1 :0] ab_pow5_im;
input signed [coef_width-1 :0] ab_pow6_im;
input signed [coef_width-1 :0] ab_pow7_im;
input signed [coef_width-1 :0] ab_pow8_im;
input signed [coef_width-1 :0] ab_pow9_im;
input signed [coef_width-1 :0] ab_powa_im;
input signed [coef_width-1 :0] ab_powb_im;
input signed [coef_width-1 :0] ab_powc_im;
input signed [coef_width-1 :0] ab_powd_im;
input signed [coef_width-1 :0] ab_powe_im;
input signed [coef_width-1 :0] ab_powf_im;
input signed [coef_width-1 :0] b_pow16_im;
output signed [data_out_width-1:0] dout_im; // Im(y(8n-8))
`endif
);
wire signed [data_in_width-1 :0] dinp [15:0];
assign dinp[15] = dinpf;
assign dinp[14] = dinpe;
assign dinp[13] = dinpd;
assign dinp[12] = dinpc;
assign dinp[11] = dinpb;
assign dinp[10] = dinpa;
assign dinp[9 ] = dinp9;
assign dinp[8 ] = dinp8;
assign dinp[7 ] = dinp7;
assign dinp[6 ] = dinp6;
assign dinp[5 ] = dinp5;
assign dinp[4 ] = dinp4;
assign dinp[3 ] = dinp3;
assign dinp[2 ] = dinp2;
assign dinp[1 ] = dinp1;
assign dinp[0 ] = dinp0;
wire signed [ab_pow_width-1 :0] ab_pow_re [15:0];
`ifdef COMPLEX
wire signed [ab_pow_width-1 :0] ab_pow_im [15:0];
`endif
assign ab_pow_re[15] = ab_powf_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[14] = ab_powe_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[13] = ab_powd_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[12] = ab_powc_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[11] = ab_powb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[10] = ab_powa_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[9 ] = ab_pow9_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[8 ] = ab_pow8_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[7 ] = ab_pow7_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[6 ] = ab_pow6_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[5 ] = ab_pow5_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[4 ] = ab_pow4_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[3 ] = ab_pow3_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[2 ] = abb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[1 ] = ab_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
assign ab_pow_re[0 ] = a_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1];
`ifdef COMPLEX
assign ab_pow_im[15] = ab_powf_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[14] = ab_powe_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[13] = ab_powd_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[12] = ab_powc_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[11] = ab_powb_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[10] = ab_powa_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[9 ] = ab_pow9_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[8 ] = ab_pow8_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[7 ] = ab_pow7_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[6 ] = ab_pow6_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[5 ] = ab_pow5_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[4 ] = ab_pow4_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[3 ] = ab_pow3_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[2 ] = abb_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[1 ] = ab_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
assign ab_pow_im[0 ] = a_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1];
`endif
wire signed [temp_var_width-1 :0] x_re [0:15];
wire signed [temp_var_width+3 :0] v_re;
reg signed [temp_var_width+3 :0] v1_re;
wire signed [temp_var_width+3 :0] y_re;
wire signed [temp_var_width+3 :0] y1_re;
wire signed [data_out_width-1:0] y_re_trunc;
`ifdef COMPLEX
wire signed [temp_var_width-1 :0] x_im [0:15];
wire signed [temp_var_width+3 :0] v_im;
reg signed [temp_var_width+3 :0] v1_im;
wire signed [temp_var_width+3 :0] y_im;
wire signed [temp_var_width+3 :0] y1_im;
wire signed [data_out_width-1:0] y_im_trunc;
`endif
// x[0] = (dinp0 * a_re) delay M = a*x(8n+8)
// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7)
// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6)
// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5)
// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4)
// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3)
// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2)
// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1)
genvar i;
generate
`ifdef COMPLEX
for (i = 0; i < 16; i = i + 1) begin: mult_c_inst
mult_x #(
.A_width (data_in_width ),
.C_width (coef_width ),
.D_width (coef_width ),
.o_width (temp_var_width )
) inst_c (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp[i] ),
.c (ab_pow_re[i] ),
.d (ab_pow_im[i] ),
.Re (x_re[i] ),
.Im (x_im[i] )
);
end
`else
for (i = 0; i < 16; i = i + 1) begin: mult_c_inst
mult_real #(
.A_width (data_in_width ),
.C_width (coef_width ),
.o_width (temp_var_width )
) inst_c (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (dinp[i] ),
.coef (ab_pow_re[i]),
.dout (x_re[i] )
);
end
`endif
endgenerate
// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)}
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7] + x_re[8] + x_re[9] + x_re[10] + x_re[11] + x_re[12] + x_re[13] + x_re[14] + x_re[15] ;
`ifdef COMPLEX
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7] + x_im[8] + x_im[9] + x_im[10] + x_im[11] + x_im[12] + x_im[13] + x_im[14] + x_im[15] ;
`endif
always @(posedge clk or negedge rstn)
begin
if (!rstn)
begin
v1_re <= 'h0;
`ifdef COMPLEX
v1_im <= 'h0;
`endif
end
else if(en)
begin
v1_re <= v_re;
`ifdef COMPLEX
v1_im <= v_im;
`endif
end
else
begin
v1_re <= v1_re;
`ifdef COMPLEX
v1_im <= v1_im;
`endif
end
end
// y1 = (b^8 * y) delay M = b^8*y(8n-8)
// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n)
mult_real
#(
.A_width (temp_var_width+4 )
,.C_width (b_pow16_width )
,.o_width (temp_var_width+4 )
)
inst_c17 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (y_re ),
.coef (b_pow16_re[coef_width-1 : coef_width-b_pow16_width] ),
.dout (y1_re )
);
assign y_re = v1_re + y1_re;
`ifdef COMPLEX
assign y_im = v1_im + y1_im;
`endif
// dout = round(y) delay M = round(y(8n-8))
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
`ifdef COMPLEX
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
`endif
assign dout_re = y_re_trunc;
`ifdef COMPLEX
assign dout_im = y_im_trunc;
`endif
endmodule

185
rtl/z_dsp/IIR_Filter_p8.v
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@ -1,185 +0,0 @@
module IIR_Filter_p8 #(
parameter coef_width = 32
,parameter data_in_width = 16
,parameter data_out_width = 37
,parameter temp_var_width = data_out_width+5
)
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1 :0] dinp0 //x(8n+16)
,input signed [data_in_width-1 :0] dinp1 //x(8n+15)
,input signed [data_in_width-1 :0] dinp2 //x(8n+14)
,input signed [data_in_width-1 :0] dinp3 //x(8n+13)
,input signed [data_in_width-1 :0] dinp4 //x(8n+12)
,input signed [data_in_width-1 :0] dinp5 //x(8n+11)
,input signed [data_in_width-1 :0] dinp6 //x(8n+10)
,input signed [data_in_width-1 :0] dinp7 //x(8n+9)
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] abb_im
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow3_im
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow4_im
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow5_im
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow6_im
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow7_im
,input signed [coef_width-1 :0] b_pow8_re
,input signed [coef_width-1 :0] b_pow8_im
,output signed [data_out_width-1:0] dout_re // Re(y(8n-8))
,output signed [data_out_width-1:0] dout_im // Im(y(8n-8))
);
wire signed [data_in_width-1 :0] dinp [7:0];
assign dinp[7] = dinp7;
assign dinp[6] = dinp6;
assign dinp[5] = dinp5;
assign dinp[4] = dinp4;
assign dinp[3] = dinp3;
assign dinp[2] = dinp2;
assign dinp[1] = dinp1;
assign dinp[0] = dinp0;
wire signed [coef_width-1 :0] ab_pow_re [7:0];
assign ab_pow_re[7] = ab_pow7_re;
assign ab_pow_re[6] = ab_pow6_re;
assign ab_pow_re[5] = ab_pow5_re;
assign ab_pow_re[4] = ab_pow4_re;
assign ab_pow_re[3] = ab_pow3_re;
assign ab_pow_re[2] = abb_re;
assign ab_pow_re[1] = ab_re;
assign ab_pow_re[0] = a_re;
wire signed [coef_width-1 :0] ab_pow_im [7:0];
assign ab_pow_im[7] = ab_pow7_im;
assign ab_pow_im[6] = ab_pow6_im;
assign ab_pow_im[5] = ab_pow5_im;
assign ab_pow_im[4] = ab_pow4_im;
assign ab_pow_im[3] = ab_pow3_im;
assign ab_pow_im[2] = abb_im;
assign ab_pow_im[1] = ab_im;
assign ab_pow_im[0] = a_im;
wire signed [temp_var_width-1 :0] x_re [0:7];
wire signed [temp_var_width-1 :0] x_im [0:7];
wire signed [temp_var_width+3 :0] v_re;
wire signed [temp_var_width+3 :0] v_im;
reg signed [temp_var_width+3 :0] v1_re;
reg signed [temp_var_width+3 :0] v1_im;
wire signed [temp_var_width+3 :0] y_re;
wire signed [temp_var_width+3 :0] y_im;
wire signed [temp_var_width+3 :0] y1_re;
wire signed [temp_var_width+3 :0] y1_im;
wire signed [data_out_width-1:0] y_re_trunc;
wire signed [data_out_width-1:0] y_im_trunc;
// x[0] = (dinp0 * a_re) delay M = a*x(8n+8)
// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7)
// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6)
// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5)
// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4)
// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3)
// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2)
// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1)
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin: mult_c_inst
mult_x #(
.A_width (data_in_width ),
.C_width (coef_width ),
.D_width (coef_width ),
.o_width (temp_var_width )
) inst_c (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp[i] ),
.c (ab_pow_re[i] ),
.d (ab_pow_im[i] ),
.Re (x_re[i] ),
.Im (x_im[i] )
);
end
endgenerate
// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)}
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7];
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7];
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
// y1 = (b^8 * y) delay M = b^8*y(8n-8)
// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n)
mult_C
#(
.A_width (temp_var_width+4 )
,.B_width (temp_var_width+4 )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (temp_var_width+4 )
)
inst_c9 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),
.b (y_im ),
.c (b_pow8_re ),
.d (b_pow8_im ),
.Re (y1_re ),
.Im (y1_im )
);
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
// dout = round(y) delay M = round(y(8n-8))
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
assign dout_re = y_re_trunc;
assign dout_im = y_im_trunc;
endmodule

889
rtl/z_dsp/IIR_top.v
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@ -1,234 +1,655 @@
module IIR_top #(
module IIR_top #( parameter data_out_width = 18
parameter data_out_width = 23 ,parameter coef_width = 32
,parameter temp_var_width = data_out_width + 14 ,parameter a0_width = 32
) ,parameter b0_width = 29
( ,parameter b0_i_width = 29
input rstn ,parameter b0_o_width = 19
,input clk ,parameter a1_width = 19
,input en ,parameter b1_width = 19
,input signed [15 :0] IIRin_p0 // x(8n+9) ,parameter b1_i_width = 19
,input signed [15 :0] IIRin_p1 // x(8n+10) ,parameter b1_o_width = 19
,input signed [15 :0] IIRin_p2 // x(8n+11) ,parameter a2_width = 21
,input signed [15 :0] IIRin_p3 // x(8n+12) ,parameter b2_width = 21
,input signed [15 :0] IIRin_p4 // x(8n+13) ,parameter b2_i_width = 19
,input signed [15 :0] IIRin_p5 // x(8n+14) ,parameter b2_o_width = 19
,input signed [15 :0] IIRin_p6 // x(8n+15) ,parameter a3_width = 21
,input signed [15 :0] IIRin_p7 // x(8n+16) ,parameter b3_width = 21
,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) ,parameter b3_i_width = 19
,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) ,parameter b3_o_width = 19
,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) ,parameter a4_width = 20
,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) ,parameter b4_width = 20
,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) ,parameter b4_i_width = 19
,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) ,parameter b4_o_width = 18
,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) ,parameter a5_width = 21
,input signed [31 :0] a_re ,parameter b5_width = 21
,input signed [31 :0] a_im ,parameter b5_i_width = 18
,input signed [31 :0] b_re ,parameter b5_o_width = 18
,input signed [31 :0] b_im ,parameter a6_width = 21
,input signed [31 :0] ab_re ,parameter b6_width = 21
,input signed [31 :0] ab_im ,parameter b6_i_width = 18
,input signed [31 :0] abb_re ,parameter b6_o_width = 18
,input signed [31 :0] abb_im ,parameter a7_width = 22
,input signed [31 :0] ab_pow3_re ,parameter b7_width = 22
,input signed [31 :0] ab_pow3_im ,parameter b7_i_width = 18
,input signed [31 :0] ab_pow4_re ,parameter b7_o_width = 18
,input signed [31 :0] ab_pow4_im ,parameter a8_width = 23
,input signed [31 :0] ab_pow5_re ,parameter b8_width = 23
,input signed [31 :0] ab_pow5_im ,parameter b8_i_width = 18
,input signed [31 :0] ab_pow6_re ,parameter b8_o_width = 18
,input signed [31 :0] ab_pow6_im ,parameter a9_width = 24
,input signed [31 :0] ab_pow7_re ,parameter b9_width = 24
,input signed [31 :0] ab_pow7_im ,parameter b9_i_width = 18
,input signed [31 :0] b_pow8_re ,parameter b9_o_width = 18
,input signed [31 :0] b_pow8_im ,parameter a10_width = 25
,parameter b10_width = 25
,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) ,parameter b10_i_width = 18
,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) ,parameter b10_o_width = 18
,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38) ,parameter a11_width = 26
,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53) ,parameter b11_width = 26
,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68) ,parameter b11_i_width = 18
,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) ,parameter b11_o_width = 18
,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) ,parameter a12_width = 27
,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ,parameter b12_width = 27
); ,parameter b12_i_width = 18
,parameter b12_o_width = 18
wire signed [temp_var_width- 1:0] IIRout_p0_re; ,parameter a13_width = 28
wire signed [temp_var_width- 3:0] IIRout_p1_re; ,parameter b13_width = 28
wire signed [temp_var_width- 5:0] IIRout_p2_re; ,parameter b13_i_width = 18
wire signed [temp_var_width- 7:0] IIRout_p3_re; ,parameter b13_o_width = 18
wire signed [temp_var_width- 9:0] IIRout_p4_re; ,parameter a14_width = 29
wire signed [temp_var_width-11:0] IIRout_p5_re; ,parameter b14_width = 29
wire signed [temp_var_width-13:0] IIRout_p6_re; ,parameter b14_i_width = 18
wire signed [temp_var_width-15:0] IIRout_p7_re; ,parameter b14_o_width = 18
wire signed [temp_var_width- 1:0] IIRout_p0_im; ,parameter a15_width = 29
wire signed [temp_var_width- 3:0] IIRout_p1_im; ,parameter b15_width = 29
wire signed [temp_var_width- 5:0] IIRout_p2_im; ,parameter b15_i_width = 18
wire signed [temp_var_width- 7:0] IIRout_p3_im; ,parameter b15_o_width = 18
wire signed [temp_var_width- 9:0] IIRout_p4_im; )
wire signed [temp_var_width-11:0] IIRout_p5_im; (
wire signed [temp_var_width-13:0] IIRout_p6_im; input rstn
wire signed [temp_var_width-15:0] IIRout_p7_im; ,input clk
,input en
,input signed [15 :0] IIRin_p0 // x(8n+9)
,input signed [15 :0] IIRin_p1 // x(8n+10)
IIR_Filter_p8 #( ,input signed [15 :0] IIRin_p2 // x(8n+11)
.data_out_width (temp_var_width ) ,input signed [15 :0] IIRin_p3 // x(8n+12)
) inst_iir_p0 ( ,input signed [15 :0] IIRin_p4 // x(8n+13)
.clk (clk ), ,input signed [15 :0] IIRin_p5 // x(8n+14)
.rstn (rstn ), ,input signed [15 :0] IIRin_p6 // x(8n+15)
.en (en ), ,input signed [15 :0] IIRin_p7 // x(8n+16)
.dinp0 (IIRin_p7 ), // x(8n+16) ,input signed [15 :0] IIRin_p8 // x(8n+9)
.dinp1 (IIRin_p6 ), // x(8n+15) ,input signed [15 :0] IIRin_p9 // x(8n+10)
.dinp2 (IIRin_p5 ), // x(8n+14) ,input signed [15 :0] IIRin_pa // x(8n+11)
.dinp3 (IIRin_p4 ), // x(8n+13) ,input signed [15 :0] IIRin_pb // x(8n+12)
.dinp4 (IIRin_p3 ), // x(8n+12) ,input signed [15 :0] IIRin_pc // x(8n+13)
.dinp5 (IIRin_p2 ), // x(8n+11) ,input signed [15 :0] IIRin_pd // x(8n+14)
.dinp6 (IIRin_p1 ), // x(8n+10) ,input signed [15 :0] IIRin_pe // x(8n+15)
.dinp7 (IIRin_p0 ), // x(8n+9) ,input signed [15 :0] IIRin_pf // x(8n+16)
.a_re (a_re ), ,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7)
.a_im (a_im ), ,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22)
.ab_re (ab_re ), ,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37)
.ab_im (ab_im ), ,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52)
.abb_re (abb_re ), ,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67)
.abb_im (abb_im ), ,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82)
.ab_pow3_re (ab_pow3_re ), ,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97)
.ab_pow3_im (ab_pow3_im ), ,input signed [15 :0] IIRin_p7_r16 // x(8n+16) delay 16M -> x(8n-112)
.ab_pow4_re (ab_pow4_re ), ,input signed [15 :0] IIRin_p8_r18 // x(8n+15) delay 18M -> x(8n-127)
.ab_pow4_im (ab_pow4_im ), ,input signed [15 :0] IIRin_p9_r20 // x(8n+14) delay 20M -> x(8n-142)
.ab_pow5_re (ab_pow5_re ), ,input signed [15 :0] IIRin_pa_r22 // x(8n+13) delay 22M -> x(8n-157)
.ab_pow5_im (ab_pow5_im ), ,input signed [15 :0] IIRin_pb_r24 // x(8n+12) delay 24M -> x(8n-172)
.ab_pow6_re (ab_pow6_re ), ,input signed [15 :0] IIRin_pc_r26 // x(8n+11) delay 26M -> x(8n-187)
.ab_pow6_im (ab_pow6_im ), ,input signed [15 :0] IIRin_pd_r28 // x(8n+10) delay 28M -> x(8n-202)
.ab_pow7_re (ab_pow7_re ), ,input signed [15 :0] IIRin_pe_r30 // x(8n+9) delay 30M -> x(8n-217)
.ab_pow7_im (ab_pow7_im ), ,input signed [31 :0] a_re
.b_pow8_re (b_pow8_re ), ,input signed [31 :0] b_re
.b_pow8_im (b_pow8_im ), ,input signed [31 :0] ab_re
.dout_re (IIRout_p0_re ), // Re(y(8n-8)) ,input signed [31 :0] abb_re
.dout_im (IIRout_p0_im ) // Im(y(8n-8)) ,input signed [31 :0] ab_pow3_re
); ,input signed [31 :0] ab_pow4_re
,input signed [31 :0] ab_pow5_re
IIR_Filter_p1 #( ,input signed [31 :0] ab_pow6_re
.cascade_in_width (temp_var_width ) ,input signed [31 :0] ab_pow7_re
) inst_iir_p1( ,input signed [31 :0] ab_pow8_re
.clk (clk ), ,input signed [31 :0] ab_pow9_re
.rstn (rstn ), ,input signed [31 :0] ab_powa_re
.en (en ), ,input signed [31 :0] ab_powb_re
.din_re (IIRin_p0_r2 ), // x(8n-7) ,input signed [31 :0] ab_powc_re
.dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) ,input signed [31 :0] ab_powd_re
.dout_r1_im (IIRout_p0_im ), // Im(y(8n-8)) ,input signed [31 :0] ab_powe_re
.a_re (a_re ), ,input signed [31 :0] ab_powf_re
.a_im (a_im ), ,input signed [31 :0] b_pow16_re
.b_re (b_re ), `ifdef COMPLEX
.b_im (b_im ), ,input signed [31 :0] a_im
.dout_re (IIRout_p1_re ), // Re(y(8n-23)) ,input signed [31 :0] b_im
.dout_im (IIRout_p1_im ) // Im(y(8n-23)) ,input signed [31 :0] ab_im
); ,input signed [31 :0] abb_im
IIR_Filter_p1 #( ,input signed [31 :0] ab_pow3_im
.cascade_in_width (temp_var_width-2 ) ,input signed [31 :0] ab_pow4_im
) inst_iir_p2 ( ,input signed [31 :0] ab_pow5_im
.clk (clk ), ,input signed [31 :0] ab_pow6_im
.rstn (rstn ), ,input signed [31 :0] ab_pow7_im
.en (en ), ,input signed [31 :0] ab_pow8_im
.din_re (IIRin_p1_r4 ), // x(8n-22) ,input signed [31 :0] ab_pow9_im
.dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) ,input signed [31 :0] ab_powa_im
.dout_r1_im (IIRout_p1_im ), // Im(y(8n-23)) ,input signed [31 :0] ab_powb_im
.a_re (a_re ), ,input signed [31 :0] ab_powc_im
.a_im (a_im ), ,input signed [31 :0] ab_powd_im
.b_re (b_re ), ,input signed [31 :0] ab_powe_im
.b_im (b_im ), ,input signed [31 :0] ab_powf_im
.dout_re (IIRout_p2_re ), // Re(y(8n-38)) ,input signed [31 :0] b_pow16_im
.dout_im (IIRout_p2_im ) // Im(y(8n-38)) `endif
); ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8)
IIR_Filter_p1 #( ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23)
.cascade_in_width (temp_var_width-4 ) ,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38)
) inst_iir_p3 ( ,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53)
.clk (clk ), ,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68)
.rstn (rstn ), ,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83)
.en (en ), ,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98)
.din_re (IIRin_p2_r6 ), // x(8n-37) ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
.dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) ,output signed [data_out_width-1 :0] IIRout_p8 // y(8n-128)
.dout_r1_im (IIRout_p2_im ), // Im(y(8n-38)) ,output signed [data_out_width-1 :0] IIRout_p9 // y(8n-143)
.a_re (a_re ), ,output signed [data_out_width-1 :0] IIRout_pa // y(8n-158)
.a_im (a_im ), ,output signed [data_out_width-1 :0] IIRout_pb // y(8n-173)
.b_re (b_re ), ,output signed [data_out_width-1 :0] IIRout_pc // y(8n-188)
.b_im (b_im ), ,output signed [data_out_width-1 :0] IIRout_pd // y(8n-203)
.dout_re (IIRout_p3_re ), // Re(y(8n-53)) ,output signed [data_out_width-1 :0] IIRout_pe // y(8n-218)
.dout_im (IIRout_p3_im ) // Im(y(8n-53)) ,output signed [data_out_width-1 :0] IIRout_pf // y(8n-233)
); );
IIR_Filter_p1 #(
.cascade_in_width (temp_var_width-6 )
) inst_iir_p4 (
.clk (clk ), wire signed [b0_o_width- 1:0] IIRout_p0_re;
.rstn (rstn ), wire signed [b1_o_width- 1:0] IIRout_p1_re;
.en (en ), wire signed [b2_o_width- 1:0] IIRout_p2_re;
.din_re (IIRin_p3_r8 ), // x(8n-52) wire signed [b3_o_width- 1:0] IIRout_p3_re;
.dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) wire signed [b4_o_width- 1:0] IIRout_p4_re;
.dout_r1_im (IIRout_p3_im ), // Im(y(8n-53)) wire signed [b5_o_width- 1:0] IIRout_p5_re;
.a_re (a_re ), wire signed [b6_o_width- 1:0] IIRout_p6_re;
.a_im (a_im ), wire signed [b7_o_width- 1:0] IIRout_p7_re;
.b_re (b_re ), wire signed [b8_o_width- 1:0] IIRout_p8_re;
.b_im (b_im ), wire signed [b9_o_width- 1:0] IIRout_p9_re;
.dout_re (IIRout_p4_re ), // Re(y(8n-68)) wire signed [b10_o_width- 1:0] IIRout_pa_re;
.dout_im (IIRout_p4_im ) // Im(y(8n-68)) wire signed [b11_o_width- 1:0] IIRout_pb_re;
); wire signed [b12_o_width- 1:0] IIRout_pc_re;
IIR_Filter_p1 #( wire signed [b13_o_width- 1:0] IIRout_pd_re;
.cascade_in_width (temp_var_width-8 ) wire signed [b14_o_width- 1:0] IIRout_pe_re;
) inst_iir_p5 ( wire signed [b15_o_width- 1:0] IIRout_pf_re;
.clk (clk ), `ifdef COMPLEX
.rstn (rstn ), wire signed [b0_o_width- 1:0] IIRout_p0_im;
.en (en ), wire signed [b1_o_width- 1:0] IIRout_p1_im;
.din_re (IIRin_p4_r10 ), // x(8n-67) wire signed [b2_o_width- 1:0] IIRout_p2_im;
.dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) wire signed [b3_o_width- 1:0] IIRout_p3_im;
.dout_r1_im (IIRout_p4_im ), // Im(y(8n-68)) wire signed [b4_o_width- 1:0] IIRout_p4_im;
.a_re (a_re ), wire signed [b5_o_width- 1:0] IIRout_p5_im;
.a_im (a_im ), wire signed [b6_o_width- 1:0] IIRout_p6_im;
.b_re (b_re ), wire signed [b7_o_width- 1:0] IIRout_p7_im;
.b_im (b_im ), wire signed [b8_o_width- 1:0] IIRout_p8_im;
.dout_re (IIRout_p5_re ), // Re(y(8n-83)) wire signed [b9_o_width- 1:0] IIRout_p9_im;
.dout_im (IIRout_p5_im ) // Im(y(8n-83)) wire signed [b10_o_width- 1:0] IIRout_pa_im;
); wire signed [b11_o_width- 1:0] IIRout_pb_im;
IIR_Filter_p1 #( wire signed [b12_o_width- 1:0] IIRout_pc_im;
.cascade_in_width (temp_var_width-10 ) wire signed [b13_o_width- 1:0] IIRout_pd_im;
) inst_iir_p6 ( wire signed [b14_o_width- 1:0] IIRout_pe_im;
.clk (clk ), wire signed [b15_o_width- 1:0] IIRout_pf_im;
.rstn (rstn ), `endif
.en (en ),
.din_re (IIRin_p5_r12 ), // x(8n-82) IIR_Filter_p16#(
.dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) .coef_width ( coef_width )
.dout_r1_im (IIRout_p5_im ), // Im(y(8n-83)) ,.b_pow16_width ( b0_width )
.a_re (a_re ), ,.ab_pow_width ( a0_width )
.a_im (a_im ), ,.temp_var_width ( b0_i_width )
.b_re (b_re ), ,.data_out_width ( b0_o_width )
.b_im (b_im ), )inst_iir_p0(
.dout_re (IIRout_p6_re ), // Re(y(8n-98)) .rstn ( rstn )
.dout_im (IIRout_p6_im ) // Im(y(8n-98)) ,.clk ( clk )
); ,.en ( en )
IIR_Filter_p1 #( ,.dinp0 ( IIRin_pf )
.cascade_in_width (temp_var_width-12 ) ,.dinp1 ( IIRin_pe )
) inst_iir_p7 ( ,.dinp2 ( IIRin_pd )
.clk (clk ), ,.dinp3 ( IIRin_pc )
.rstn (rstn ), ,.dinp4 ( IIRin_pb )
.en (en ), ,.dinp5 ( IIRin_pa )
.din_re (IIRin_p6_r14 ), // x(8n-97) ,.dinp6 ( IIRin_p9 )
.dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) ,.dinp7 ( IIRin_p8 )
.dout_r1_im (IIRout_p6_im ), // Im(y(8n-98)) ,.dinp8 ( IIRin_p7 )
.a_re (a_re ), ,.dinp9 ( IIRin_p6 )
.a_im (a_im ), ,.dinpa ( IIRin_p5 )
.b_re (b_re ), ,.dinpb ( IIRin_p4 )
.b_im (b_im ), ,.dinpc ( IIRin_p3 )
.dout_re (IIRout_p7_re ), // Re(y(8n-113)) ,.dinpd ( IIRin_p2 )
.dout_im (IIRout_p7_im ) // Im(y(8n-113)) ,.dinpe ( IIRin_p1 )
); ,.dinpf ( IIRin_p0 )
,.a_re ( a_re )
assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8) ,.ab_re ( ab_re )
assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23) ,.abb_re ( abb_re )
assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38) ,.ab_pow3_re ( ab_pow3_re )
assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53) ,.ab_pow4_re ( ab_pow4_re )
assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68) ,.ab_pow5_re ( ab_pow5_re )
assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83) ,.ab_pow6_re ( ab_pow6_re )
assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98) ,.ab_pow7_re ( ab_pow7_re )
assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113) ,.ab_pow8_re ( ab_pow8_re )
,.ab_pow9_re ( ab_pow9_re )
endmodule ,.ab_powa_re ( ab_powa_re )
,.ab_powb_re ( ab_powb_re )
,.ab_powc_re ( ab_powc_re )
,.ab_powd_re ( ab_powd_re )
,.ab_powe_re ( ab_powe_re )
,.ab_powf_re ( ab_powf_re )
,.b_pow16_re ( b_pow16_re )
`ifdef COMPLEX
,.a_im ( a_im )
,.ab_im ( ab_im )
,.abb_im ( abb_im )
,.ab_pow3_im ( ab_pow3_im )
,.ab_pow4_im ( ab_pow4_im )
,.ab_pow5_im ( ab_pow5_im )
,.ab_pow6_im ( ab_pow6_im )
,.ab_pow7_im ( ab_pow7_im )
,.ab_pow8_im ( ab_pow8_im )
,.ab_pow9_im ( ab_pow9_im )
,.ab_powa_im ( ab_powa_im )
,.ab_powb_im ( ab_powb_im )
,.ab_powc_im ( ab_powc_im )
,.ab_powd_im ( ab_powd_im )
,.ab_powe_im ( ab_powe_im )
,.ab_powf_im ( ab_powf_im )
,.b_pow16_im ( b_pow16_im )
,.dout_im ( IIRout_p0_im )
`endif
,.dout_re ( IIRout_p0_re )
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a1_width )
,.b_width ( b1_width )
,.cascade_in_width ( b1_i_width )
,.data_out_width ( b1_o_width )
) inst_iir_p1 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p0_r2 ) // x(8n-7)
,.dout_r1_re ( IIRout_p0_re ) // Re(y(8n-8))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p0_im ) // Re(y(8n-8))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p1_re ) // Re(y(8n-23))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p1_im ) // Re(y(8n-23))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a2_width )
,.b_width ( b2_width )
,.cascade_in_width ( b2_i_width )
,.data_out_width ( b2_o_width )
) inst_iir_p2 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p1_r4 ) // x(8n-22)
,.dout_r1_re ( IIRout_p1_re ) // Re(y(8n-23))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p1_im ) // Re(y(8n-23))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p2_re ) // Re(y(8n-38))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p2_im ) // Re(y(8n-38))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a3_width )
,.b_width ( b3_width )
,.cascade_in_width ( b3_i_width )
,.data_out_width ( b3_o_width )
) inst_iir_p3 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p2_r6 ) // x(8n-37)
,.dout_r1_re ( IIRout_p2_re ) // Re(y(8n-38))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p2_im ) // Re(y(8n-38))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p3_re ) // Re(y(8n-53))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p3_im ) // Re(y(8n-53))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a4_width )
,.b_width ( b4_width )
,.cascade_in_width ( b4_i_width )
,.data_out_width ( b4_o_width )
) inst_iir_p4 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p3_r8 ) // x(8n-52)
,.dout_r1_re ( IIRout_p3_re ) // Re(y(8n-53))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p3_im ) // Re(y(8n-53))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p4_re ) // Re(y(8n-68))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p4_im ) // Re(y(8n-68))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a5_width )
,.b_width ( b5_width )
,.cascade_in_width ( b5_i_width )
,.data_out_width ( b5_o_width )
) inst_iir_p5 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p4_r10 ) // x(8n-67)
,.dout_r1_re ( IIRout_p4_re ) // Re(y(8n-68))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p4_im ) // Re(y(8n-68))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p5_re ) // Re(y(8n-83))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p5_im ) // Re(y(8n-83))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a6_width )
,.b_width ( b6_width )
,.cascade_in_width ( b6_i_width )
,.data_out_width ( b6_o_width )
) inst_iir_p6 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p5_r12 ) // x(8n-82)
,.dout_r1_re ( IIRout_p5_re ) // Re(y(8n-83))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p5_im ) // Re(y(8n-83))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p6_re ) // Re(y(8n-98))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p6_im ) // Re(y(8n-98))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a7_width )
,.b_width ( b7_width )
,.cascade_in_width ( b7_i_width )
,.data_out_width ( b7_o_width )
) inst_iir_p7 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p6_r14 ) // x(8n-97)
,.dout_r1_re ( IIRout_p6_re ) // Re(y(8n-98))
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p7_re ) // Re(y(8n-113))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p6_im ) // Re(y(8n-98))
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p7_im ) // Re(y(8n-113))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a8_width )
,.b_width ( b8_width )
,.cascade_in_width ( b8_i_width )
,.data_out_width ( b8_o_width )
) inst_iir_p8 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p7_r16 ) // x(8n-112)
,.dout_r1_re ( IIRout_p7_re ) // Re(y(8n-113))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p7_im ) // Re(y(8n-113))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p8_re ) // Re(y(8n-128))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p8_im ) // Re(y(8n-128))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a9_width )
,.b_width ( b9_width )
,.cascade_in_width ( b9_i_width )
,.data_out_width ( b9_o_width )
) inst_iir_p9 (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p8_r18 ) // x(8n-127)
,.dout_r1_re ( IIRout_p8_re ) // Re(y(8n-128))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p8_im ) // Re(y(8n-128))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_p9_re ) // Re(y(8n-143))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_p9_im ) // Re(y(8n-143))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a10_width )
,.b_width ( b10_width )
,.cascade_in_width ( b10_i_width )
,.data_out_width ( b10_o_width )
) inst_iir_pa (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_p9_r20 ) // x(8n-142)
,.dout_r1_re ( IIRout_p9_re ) // Re(y(8n-143))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_p9_im ) // Re(y(8n-143))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pa_re ) // Re(y(8n-158))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pa_im ) // Re(y(8n-158))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a11_width )
,.b_width ( b11_width )
,.cascade_in_width ( b11_i_width )
,.data_out_width ( b11_o_width )
) inst_iir_pb (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pa_r22 ) // x(8n-157)
,.dout_r1_re ( IIRout_pa_re ) // Re(y(8n-158))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pa_im ) // Re(y(8n-158))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pb_re ) // Re(y(8n-173))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pb_im ) // Re(y(8n-173))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a12_width )
,.b_width ( b12_width )
,.cascade_in_width ( b12_i_width )
,.data_out_width ( b12_o_width )
) inst_iir_pc (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pb_r24 ) // x(8n-172)
,.dout_r1_re ( IIRout_pb_re ) // Re(y(8n-173))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pb_im ) // Re(y(8n-173))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pc_re ) // Re(y(8n-188))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pc_im ) // Re(y(8n-188))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a13_width )
,.b_width ( b13_width )
,.cascade_in_width ( b13_i_width )
,.data_out_width ( b13_o_width )
) inst_iir_pd (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pc_r26 ) // x(8n-187)
,.dout_r1_re ( IIRout_pc_re ) // Re(y(8n-188))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pc_im ) // Re(y(8n-188))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pd_re ) // Re(y(8n-203))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pd_im ) // Re(y(8n-203))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a14_width )
,.b_width ( b14_width )
,.cascade_in_width ( b14_i_width )
,.data_out_width ( b14_o_width )
) inst_iir_pe (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pd_r28 ) // x(8n-202)
,.dout_r1_re ( IIRout_pd_re ) // Re(y(8n-203))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pd_im ) // Re(y(8n-203))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pe_re ) // Re(y(8n-218))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pe_im ) // Re(y(8n-218))
`endif
);
IIR_Filter_p1 #(
.coef_width ( coef_width )
,.a_width ( a15_width )
,.b_width ( b15_width )
,.cascade_in_width ( b15_i_width )
,.data_out_width ( b15_o_width )
) inst_iir_pf (
.clk ( clk )
,.rstn ( rstn )
,.en ( en )
,.din_re ( IIRin_pe_r30 ) // x(8n-217)
,.dout_r1_re ( IIRout_pe_re ) // Re(y(8n-218))
`ifdef COMPLEX
,.dout_r1_im ( IIRout_pe_im ) // Re(y(8n-218))
`endif
,.a_re ( a_re )
,.b_re ( b_re )
,.dout_re ( IIRout_pf_re ) // Re(y(8n-233))
`ifdef COMPLEX
,.a_im ( a_im )
,.b_im ( b_im )
,.dout_im ( IIRout_pf_im ) // Re(y(8n-233))
`endif
);
assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8)
assign IIRout_p1 = IIRout_p1_re[b1_o_width-1 : b1_o_width-data_out_width]; // y(8n-23)
assign IIRout_p2 = IIRout_p2_re[b2_o_width-1 : b2_o_width-data_out_width]; // y(8n-38)
assign IIRout_p3 = IIRout_p3_re[b3_o_width-1 : b3_o_width-data_out_width]; // y(8n-53)
assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; // y(8n-68)
assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83)
assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98)
assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113)
assign IIRout_p8 = IIRout_p8_re[b8_o_width-1 : b8_o_width-data_out_width]; // y(8n-128)
assign IIRout_p9 = IIRout_p9_re[b9_o_width-1 : b9_o_width-data_out_width]; // y(8n-143)
assign IIRout_pa = IIRout_pa_re[b10_o_width-1 : b10_o_width-data_out_width]; // y(8n-158)
assign IIRout_pb = IIRout_pb_re[b11_o_width-1 : b11_o_width-data_out_width]; // y(8n-173)
assign IIRout_pc = IIRout_pc_re[b12_o_width-1 : b12_o_width-data_out_width]; // y(8n-188)
assign IIRout_pd = IIRout_pd_re[b13_o_width-1 : b13_o_width-data_out_width]; // y(8n-203)
assign IIRout_pe = IIRout_pe_re[b14_o_width-1 : b14_o_width-data_out_width]; // y(8n-218)
assign IIRout_pf = IIRout_pf_re[b15_o_width-1 : b15_o_width-data_out_width]; // y(8n-233)
endmodule

2216
rtl/z_dsp/TailCorr_top.v
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112
rtl/z_dsp/Trunc.v
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@ -1,56 +1,56 @@
module trunc #( module trunc #(
parameter integer diw = 8 parameter integer diw = 8
//,parameter integer dow = msb - (lsb -1) //,parameter integer dow = msb - (lsb -1)
,parameter integer msb = 7 ,parameter integer msb = 7
,parameter integer lsb = 1 ,parameter integer lsb = 1
,parameter integer half_precision = 0 ,parameter integer half_precision = 1
) )
( (
input clk input clk
,input rstn ,input rstn
,input en ,input en
,input signed [diw - 1 :0] din ,input signed [diw - 1 :0] din
,output signed [msb - lsb:0] dout ,output signed [msb - lsb:0] dout
); );
reg signed [msb - lsb : 0] d_tmp; reg signed [msb - lsb : 0] d_tmp;
generate generate
if(lsb!=0 && half_precision != 0) begin if(lsb!=0 && half_precision != 0) begin
always @(posedge clk or negedge rstn) begin always @(posedge clk or negedge rstn) begin
if (!rstn) begin if (!rstn) begin
d_tmp <= 'h0; d_tmp <= 'h0;
end end
else if(en) begin else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else else
d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]}; d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]};
end end
else begin else begin
d_tmp <= d_tmp; d_tmp <= d_tmp;
end end
end end
end end
else begin else begin
always @(posedge clk or negedge rstn) begin always @(posedge clk or negedge rstn) begin
if (!rstn) begin if (!rstn) begin
d_tmp <= 'h0; d_tmp <= 'h0;
end end
else if(en) begin else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else else
d_tmp <= din[msb:lsb]; d_tmp <= din[msb:lsb];
end end
else begin else begin
d_tmp <= d_tmp; d_tmp <= d_tmp;
end end
end end
end end
endgenerate endgenerate
assign dout = d_tmp; assign dout = d_tmp;
endmodule endmodule

300
rtl/z_dsp/diff_p.v
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@ -1,159 +1,141 @@
module diff_p module diff_p
(
( input rstn
input rstn ,input clk
,input clk ,input en
,input en ,input vldi
,input vldi ,input signed [15:0] din0
,input signed [15:0] din0 ,input signed [15:0] din1
,input signed [15:0] din1 ,input signed [15:0] din2
,input signed [15:0] din2 ,input signed [15:0] din3
,input signed [15:0] din3 ,input signed [15:0] din4
,output vldo ,input signed [15:0] din5
,output signed [15:0] dout_p0 ,input signed [15:0] din6
,output signed [15:0] dout_p1 ,input signed [15:0] din7
,output signed [15:0] dout_p2 ,input signed [15:0] din8
,output signed [15:0] dout_p3 ,input signed [15:0] din9
,output signed [15:0] dout_p4 ,input signed [15:0] dina
,output signed [15:0] dout_p5 ,input signed [15:0] dinb
,output signed [15:0] dout_p6 ,input signed [15:0] dinc
,output signed [15:0] dout_p7 ,input signed [15:0] dind
,output signed [15:0] diff_p0 ,input signed [15:0] dine
,output signed [15:0] diff_p1 ,input signed [15:0] dinf
,output signed [15:0] diff_p2 ,output vldo
,output signed [15:0] diff_p3 ,output signed [15:0] diff_p0
,output signed [15:0] diff_p4 ,output signed [15:0] diff_p1
,output signed [15:0] diff_p5 ,output signed [15:0] diff_p2
,output signed [15:0] diff_p6 ,output signed [15:0] diff_p3
,output signed [15:0] diff_p7 ,output signed [15:0] diff_p4
,output signed [15:0] diff_p5
); ,output signed [15:0] diff_p6
,output signed [15:0] diff_p7
wire signed [15:0] din_p0_r0; ,output signed [15:0] diff_p8
wire signed [15:0] din_p1_r0; ,output signed [15:0] diff_p9
wire signed [15:0] din_p2_r0; ,output signed [15:0] diff_pa
wire signed [15:0] din_p3_r0; ,output signed [15:0] diff_pb
wire signed [15:0] din_p4_r0; ,output signed [15:0] diff_pc
wire signed [15:0] din_p5_r0; ,output signed [15:0] diff_pd
wire signed [15:0] din_p6_r0; ,output signed [15:0] diff_pe
wire signed [15:0] din_p7_r0; ,output signed [15:0] diff_pf
wire vldo_0;
wire vldo_1; );
wire vldo_2; wire signed [15:0] dinf_r1;
wire vldo_3;
wire vldo_r0; sirv_gnrl_dfflr #(16) din_pf_1(en,dinf, dinf_r1 ,clk,rstn);
assign vldo_r0 = vldo_0 || vldo_1 || vldo_2 || vldo_3;
sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn); reg signed [15:0] diff_p0_r1;
s2p_2 inst1_s2p_2 ( reg signed [15:0] diff_p1_r1;
.clk (clk), reg signed [15:0] diff_p2_r1;
.rst_n (rstn), reg signed [15:0] diff_p3_r1;
.din (din0), reg signed [15:0] diff_p4_r1;
.en (vldi), reg signed [15:0] diff_p5_r1;
.dout0 (din_p0_r0), reg signed [15:0] diff_p6_r1;
.dout1 (din_p4_r0) reg signed [15:0] diff_p7_r1;
,.vldo( vldo_0) reg signed [15:0] diff_p8_r1;
); reg signed [15:0] diff_p9_r1;
s2p_2 inst2_s2p_2 ( reg signed [15:0] diff_pa_r1;
.clk (clk), reg signed [15:0] diff_pb_r1;
.rst_n (rstn), reg signed [15:0] diff_pc_r1;
.din (din1), reg signed [15:0] diff_pd_r1;
.en (vldi), reg signed [15:0] diff_pe_r1;
.dout0 (din_p1_r0), reg signed [15:0] diff_pf_r1;
.dout1 (din_p5_r0)
,.vldo( vldo_1) always @(posedge clk or negedge rstn)begin
); if(rstn==1'b0)begin
s2p_2 inst3_s2p_2 ( diff_p0_r1 <= 0;
.clk (clk), diff_p1_r1 <= 0;
.rst_n (rstn), diff_p2_r1 <= 0;
.din (din2), diff_p3_r1 <= 0;
.en (vldi), diff_p4_r1 <= 0;
.dout0 (din_p2_r0), diff_p5_r1 <= 0;
.dout1 (din_p6_r0) diff_p6_r1 <= 0;
,.vldo( vldo_2) diff_p7_r1 <= 0;
); diff_p8_r1 <= 0;
s2p_2 inst4_s2p_2 ( diff_p9_r1 <= 0;
.clk (clk), diff_pa_r1 <= 0;
.rst_n (rstn), diff_pb_r1 <= 0;
.din (din3), diff_pc_r1 <= 0;
.en (vldi), diff_pd_r1 <= 0;
.dout0 (din_p3_r0), diff_pe_r1 <= 0;
.dout1 (din_p7_r0) diff_pf_r1 <= 0;
,.vldo( vldo_3) end
); else if(en)begin
diff_p0_r1 <= din0 - dinf_r1;
diff_p1_r1 <= din1 - din0;
wire signed [15:0] din_p0_r1; diff_p2_r1 <= din2 - din1;
wire signed [15:0] din_p1_r1; diff_p3_r1 <= din3 - din2;
wire signed [15:0] din_p2_r1; diff_p4_r1 <= din4 - din3;
wire signed [15:0] din_p3_r1; diff_p5_r1 <= din5 - din4;
wire signed [15:0] din_p4_r1; diff_p6_r1 <= din6 - din5;
wire signed [15:0] din_p5_r1; diff_p7_r1 <= din7 - din6;
wire signed [15:0] din_p6_r1; diff_p8_r1 <= din8 - din7;
wire signed [15:0] din_p7_r1; diff_p9_r1 <= din9 - din8 ;
diff_pa_r1 <= dina - din9 ;
sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn); diff_pb_r1 <= dinb - dina;
diff_pc_r1 <= dinc - dinb;
assign dout_p0 = din_p0_r0; diff_pd_r1 <= dind - dinc;
assign dout_p1 = din_p1_r0; diff_pe_r1 <= dine - dind;
assign dout_p2 = din_p2_r0; diff_pf_r1 <= dinf - dine;
assign dout_p3 = din_p3_r0; end
assign dout_p4 = din_p4_r0; else begin
assign dout_p5 = din_p5_r0; diff_p0_r1 <= diff_p0_r1;
assign dout_p6 = din_p6_r0; diff_p1_r1 <= diff_p1_r1;
assign dout_p7 = din_p7_r0; diff_p2_r1 <= diff_p2_r1;
diff_p3_r1 <= diff_p3_r1;
reg signed [15:0] diff_p0_r1; diff_p4_r1 <= diff_p4_r1;
reg signed [15:0] diff_p1_r1; diff_p5_r1 <= diff_p5_r1;
reg signed [15:0] diff_p2_r1; diff_p6_r1 <= diff_p6_r1;
reg signed [15:0] diff_p3_r1; diff_p7_r1 <= diff_p7_r1;
reg signed [15:0] diff_p4_r1; diff_p8_r1 <= diff_p8_r1;
reg signed [15:0] diff_p5_r1; diff_p9_r1 <= diff_p9_r1;
reg signed [15:0] diff_p6_r1; diff_pa_r1 <= diff_pa_r1;
reg signed [15:0] diff_p7_r1; diff_pb_r1 <= diff_pb_r1;
diff_pc_r1 <= diff_pc_r1;
always @(posedge clk or negedge rstn)begin diff_pd_r1 <= diff_pd_r1;
if(rstn==1'b0)begin diff_pe_r1 <= diff_pe_r1;
diff_p0_r1 <= 0; diff_pf_r1 <= diff_pf_r1;
diff_p1_r1 <= 0; end
diff_p2_r1 <= 0; end
diff_p3_r1 <= 0;
diff_p4_r1 <= 0; assign diff_p0 = diff_p0_r1;
diff_p5_r1 <= 0; assign diff_p1 = diff_p1_r1;
diff_p6_r1 <= 0; assign diff_p2 = diff_p2_r1;
diff_p7_r1 <= 0; assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
end assign diff_p5 = diff_p5_r1;
else if(en)begin assign diff_p6 = diff_p6_r1;
diff_p0_r1 <= din_p0_r0 - din_p7_r1; assign diff_p7 = diff_p7_r1;
diff_p1_r1 <= din_p1_r0 - din_p0_r0; assign diff_p8 = diff_p8_r1;
diff_p2_r1 <= din_p2_r0 - din_p1_r0; assign diff_p9 = diff_p9_r1;
diff_p3_r1 <= din_p3_r0 - din_p2_r0; assign diff_pa = diff_pa_r1;
diff_p4_r1 <= din_p4_r0 - din_p3_r0; assign diff_pb = diff_pb_r1;
diff_p5_r1 <= din_p5_r0 - din_p4_r0; assign diff_pc = diff_pc_r1;
diff_p6_r1 <= din_p6_r0 - din_p5_r0; assign diff_pd = diff_pd_r1;
diff_p7_r1 <= din_p7_r0 - din_p6_r0; assign diff_pe = diff_pe_r1;
end assign diff_pf = diff_pf_r1;
else begin
diff_p0_r1 <= diff_p0_r1; sirv_gnrl_dffr #(1) vldo_1(vldi, vldo ,clk,rstn);
diff_p1_r1 <= diff_p1_r1;
diff_p2_r1 <= diff_p2_r1; endmodule
diff_p3_r1 <= diff_p3_r1;
diff_p4_r1 <= diff_p4_r1;
diff_p5_r1 <= diff_p5_r1;
diff_p6_r1 <= diff_p6_r1;
diff_p7_r1 <= diff_p7_r1;
end
end
assign diff_p0 = diff_p0_r1;
assign diff_p1 = diff_p1_r1;
assign diff_p2 = diff_p2_r1;
assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
assign diff_p5 = diff_p5_r1;
assign diff_p6 = diff_p6_r1;
assign diff_p7 = diff_p7_r1;
endmodule

203
rtl/z_dsp/mult_C.v
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@ -1,117 +1,86 @@
//+FHDR-------------------------------------------------------------------------------------------------------- module mult_C #(
// Company: parameter integer A_width = 8
//----------------------------------------------------------------------------------------------------------------- ,parameter integer B_width = 8
// File Name : mult_C.v ,parameter integer C_width = 8
// Department : ,parameter integer D_width = 8
// Author : thfu ,parameter integer o_width = 31//division
// Author's Tel :
//----------------------------------------------------------------------------------------------------------------- )
// Relese History
// Version Date Author Description (
// 0.1 2024-05-28 thfu clk,
//2024-05-28 10:22:18 rstn,
//----------------------------------------------------------------------------------------------------------------- en,
// Keywords : a,
// b,
//----------------------------------------------------------------------------------------------------------------- c,
// Parameter d,
// Re,
//----------------------------------------------------------------------------------------------------------------- Im
// Purpose : );
//
//----------------------------------------------------------------------------------------------------------------- input rstn;
// Target Device: input clk;
// Tool versions: input en;
//----------------------------------------------------------------------------------------------------------------- input signed [A_width-1 :0] a;
// Reuse Issues input signed [B_width-1 :0] b;
// Reset Strategy: input signed [C_width-1 :0] c;
// Clock Domains: input signed [D_width-1 :0] d;
// Critical Timing:
// Asynchronous I/F: output signed [o_width-1 :0] Re;
// Synthesizable (y/n): output signed [o_width-1 :0] Im;
// Other:
//-FHDR-------------------------------------------------------------------------------------------------------- wire signed [A_width+C_width-1:0] ac;
module mult_C #( wire signed [B_width+D_width-1:0] bd;
parameter integer A_width = 8 wire signed [A_width+D_width-1:0] ad;
,parameter integer B_width = 8 wire signed [B_width+C_width-1:0] bc;
,parameter integer C_width = 8 wire signed [A_width+C_width :0] Re_tmp;
,parameter integer D_width = 8 wire signed [A_width+D_width :0] Im_tmp;
,parameter integer o_width = 31//division wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
)
wire signed [A_width:0] sum_ab;
( wire signed [C_width:0] sum_cd;
clk, wire signed [A_width+C_width+1:0] product_of_sums;
rstn,
en, assign sum_ab = a + b;
a, assign sum_cd = c + d;
b,
c,
d, DW02_mult #(A_width,C_width) inst_c1( .A (a ),
Re, .B (c ),
Im .TC (1'b1 ),
); .PRODUCT (ac )
);
input rstn;
input clk; DW02_mult #(B_width,D_width) inst_c2( .A (b ),
input en; .B (d ),
input signed [A_width-1 :0] a; .TC (1'b1 ),
input signed [B_width-1 :0] b; .PRODUCT (bd )
input signed [C_width-1 :0] c; );
input signed [D_width-1 :0] d;
DW02_mult #(A_width+1,D_width+1) inst_c3( .A (sum_ab ),
output signed [o_width-1 :0] Re; .B (sum_cd ),
output signed [o_width-1 :0] Im; .TC (1'b1 ),
.PRODUCT (product_of_sums)
wire signed [A_width+C_width-1:0] ac; );
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad; assign Re_tmp = ac - bd;
wire signed [B_width+C_width-1:0] bc; assign Im_tmp = product_of_sums - ac - bd;
wire signed [A_width+C_width :0] Re_tmp;
wire signed [A_width+D_width :0] Im_tmp; trunc #(
wire signed [o_width-1 :0] Re_trunc; .diw (A_width+C_width+1 )
wire signed [o_width-1 :0] Im_trunc; ,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round1 (clk, rstn, en, Re_tmp, Re_trunc);
DW02_mult #(A_width,C_width) inst_c1( .A (a ), trunc #(
.B (c ), .diw (A_width+D_width+1 )
.TC (1'b1 ), ,.msb (A_width+D_width-2 )
.PRODUCT (ac ) ,.lsb (A_width+C_width-o_width-1 )
); ) u_round2 (clk, rstn, en, Im_tmp, Im_trunc);
DW02_mult #(B_width,D_width) inst_c2( .A (b ), // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
.B (d ), assign Re = Re_trunc;
.TC (1'b1 ), assign Im = Im_trunc;
.PRODUCT (bd )
); endmodule
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc;
trunc #(
.diw (A_width+C_width+1 )
,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round1 (clk, rstn, en, Re_tmp, Re_trunc);
trunc #(
.diw (A_width+D_width+1 )
,.msb (A_width+D_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round2 (clk, rstn, en, Im_tmp, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_trunc;
assign Im = Im_trunc;
endmodule

38
rtl/z_dsp/mult_real.v Normal file
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@ -0,0 +1,38 @@
module mult_real #(
parameter integer A_width = 8
,parameter integer C_width = 8
,parameter integer o_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [A_width-1 :0] din
,input signed [C_width-1 :0] coef
,output signed [o_width-1 :0] dout
);
wire signed [A_width+C_width-1:0] ac;
wire signed [o_width-1 :0] Re_trunc;
DW02_mult #(A_width,C_width) inst_c1 (
.A (din ),
.B (coef ),
.TC (1'b1 ),
.PRODUCT (ac )
);
trunc #(
.diw (A_width+C_width )
,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round1 (clk, rstn, en, ac, Re_trunc);
assign dout = Re_trunc;
endmodule

165
rtl/z_dsp/mult_x.v
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@ -1,99 +1,66 @@
//+FHDR-------------------------------------------------------------------------------------------------------- module mult_x #(
// Company: parameter integer A_width = 8
//----------------------------------------------------------------------------------------------------------------- ,parameter integer C_width = 8
// File Name : mult_C.v ,parameter integer D_width = 8
// Department : ,parameter integer o_width = 31//division
// Author : thfu
// Author's Tel : )
//-----------------------------------------------------------------------------------------------------------------
// Relese History (
// Version Date Author Description clk,
// 0.1 2024-05-28 thfu rstn,
//2024-05-28 10:22:18 en,
//----------------------------------------------------------------------------------------------------------------- a,
// Keywords : c,
// d,
//----------------------------------------------------------------------------------------------------------------- Re,
// Parameter Im
// );
//-----------------------------------------------------------------------------------------------------------------
// Purpose : input rstn;
// input clk;
//----------------------------------------------------------------------------------------------------------------- input en;
// Target Device: input signed [A_width-1 :0] a;
// Tool versions: input signed [C_width-1 :0] c;
//----------------------------------------------------------------------------------------------------------------- input signed [D_width-1 :0] d;
// Reuse Issues
// Reset Strategy: output signed [o_width-1 :0] Re;
// Clock Domains: output signed [o_width-1 :0] Im;
// Critical Timing:
// Asynchronous I/F: wire signed [A_width+C_width-1:0] ac;
// Synthesizable (y/n): wire signed [A_width+D_width-1:0] ad;
// Other: wire signed [o_width-1 :0] Re_trunc;
//-FHDR-------------------------------------------------------------------------------------------------------- wire signed [o_width-1 :0] Im_trunc;
module mult_x #(
parameter integer A_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8 DW02_mult #(A_width,C_width) inst_c1( .A (a ),
,parameter integer o_width = 31//division .B (c ),
.TC (1'b1 ),
) .PRODUCT (ac )
);
(
clk, DW02_mult #(A_width,D_width) inst_c3( .A (a ),
rstn, .B (d ),
en, .TC (1'b1 ),
a, .PRODUCT (ad )
c, );
d,
Re,
Im
); trunc #(
.diw (A_width+C_width )
input rstn; ,.msb (A_width+C_width-2 )
input clk; ,.lsb (A_width+C_width-o_width-1 )
input en; ) u_round1 (clk, rstn, en, ac, Re_trunc);
input signed [A_width-1 :0] a; trunc #(
input signed [C_width-1 :0] c; .diw (A_width+D_width )
input signed [D_width-1 :0] d; ,.msb (A_width+D_width-2 )
,.lsb (A_width+D_width-o_width-1 )
output signed [o_width-1 :0] Re; ) u_round2 (clk, rstn, en, ad, Im_trunc);
output signed [o_width-1 :0] Im;
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
wire signed [A_width+C_width-1:0] ac; assign Re = Re_trunc;
wire signed [A_width+D_width-1:0] ad; assign Im = Im_trunc;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc; endmodule
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
trunc #(
.diw (A_width+C_width )
,.msb (A_width+C_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round1 (clk, rstn, en, ac, Re_trunc);
trunc #(
.diw (A_width+D_width )
,.msb (A_width+D_width-2 )
,.lsb (A_width+D_width-o_width-1 )
) u_round2 (clk, rstn, en, ad, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_trunc;
assign Im = Im_trunc;
endmodule

84
rtl/z_dsp/s2p_2.v
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@ -1,84 +0,0 @@
module s2p_2 (
input clk,
input rst_n,
input [15:0] din,
input en,
output [15:0] dout0,
output [15:0] dout1,
output vldo
);
reg cnt;
wire add_cnt;
wire end_cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 0;
end
else if(add_cnt)begin
if(end_cnt)
cnt <= 0;
else
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
assign add_cnt = en == 1'b1;
assign end_cnt = add_cnt && cnt== 2 - 1 ;
wire en_r1;
wire en_r2;
reg [ 15: 0] dout0_r0;
reg [ 15: 0] dout1_r0;
wire dout0_en;
wire dout1_en;
wire dout0_hold;
wire dout1_hold;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
dout0_r0 <= 16'b0;
dout1_r0 <= 16'b0;
end
else if(dout0_en)begin
dout0_r0 <= din;
end
else if(dout1_en)begin
dout1_r0 <= din;
end
else if(dout0_hold)begin
dout0_r0 <= dout0_r0;
dout1_r0 <= 16'd0;
end
else if(dout1_hold)begin
dout0_r0 <= 16'd0;
dout1_r0 <= dout1_r0;
end
else begin
dout0_r0 <= 16'd0;
dout1_r0 <= 16'd0;
end
end
assign dout0_en = add_cnt && cnt == 0;
assign dout1_en = add_cnt && cnt == 1;
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
sirv_gnrl_dffr #(1) dff_en_1(en , en_r1 ,clk,rst_n);
sirv_gnrl_dffr #(1) dff_en_2(en_r1, en_r2 ,clk,rst_n);
assign vldo = en_r2;
wire [ 15: 0] dout0_r1;
sirv_gnrl_dfflr #(16) dff_dout0_1(1'b1,dout0_r0, dout0_r1 ,clk,rst_n);
assign dout0 = dout0_r1;
assign dout1 = dout1_r0;
endmodule

652
rtl/z_dsp/sirv_gnrl_dffs.v
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@ -1,326 +1,326 @@
/* /*
Copyright 2018-2020 Nuclei System Technology, Inc. Copyright 2018-2020 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
You may obtain a copy of the License at You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0 http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and See the License for the specific language governing permissions and
limitations under the License. limitations under the License.
*/ */
//===================================================================== //=====================================================================
// //
// Designer : Bob Hu // Designer : Bob Hu
// //
// Description: // Description:
// All of the general DFF and Latch modules // All of the general DFF and Latch modules
// //
// ==================================================================== // ====================================================================
// //
// //
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1 // Default reset value is 1
// //
// =========================================================================== // ===========================================================================
`define DISABLE_SV_ASSERTION `define DISABLE_SV_ASSERTION
`define dly #0.2 `define dly #0.2
module sirv_gnrl_dfflrs # ( module sirv_gnrl_dfflrs # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC begin : DFFLRS_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b1}}; qout_r <= {DW{1'b1}};
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0 // Default reset value is 0
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dfflr # ( module sirv_gnrl_dfflr # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC begin : DFFLR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b0}}; qout_r <= {DW{1'b0}};
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset // Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is input // Default reset value is input
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dfflrd # ( module sirv_gnrl_dfflrd # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] init, input [DW-1:0] init,
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC begin : DFFLR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= init; qout_r <= init;
else if (lden == 1'b1) else if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset // Verilog module sirv_gnrl DFF with Load-enable, no reset
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffl # ( module sirv_gnrl_dffl # (
parameter DW = 32 parameter DW = 32
) ( ) (
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk input clk
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk) always @(posedge clk)
begin : DFFL_PROC begin : DFFL_PROC
if (lden == 1'b1) if (lden == 1'b1)
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
sirv_gnrl_xchecker # ( sirv_gnrl_xchecker # (
.DW(1) .DW(1)
) sirv_gnrl_xchecker( ) sirv_gnrl_xchecker(
.i_dat(lden), .i_dat(lden),
.clk (clk) .clk (clk)
); );
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable // Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1 // Default reset value is 1
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffrs # ( module sirv_gnrl_dffrs # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC begin : DFFRS_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b1}}; qout_r <= {DW{1'b1}};
else else
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable // Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0 // Default reset value is 0
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_dffr # ( module sirv_gnrl_dffr # (
parameter DW = 32 parameter DW = 32
) ( ) (
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout, output [DW-1:0] qout,
input clk, input clk,
input rst_n input rst_n
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n) always @(posedge clk or negedge rst_n)
begin : DFFR_PROC begin : DFFR_PROC
if (rst_n == 1'b0) if (rst_n == 1'b0)
qout_r <= {DW{1'b0}}; qout_r <= {DW{1'b0}};
else else
qout_r <= `dly dnxt; qout_r <= `dly dnxt;
end end
assign qout = qout_r; assign qout = qout_r;
endmodule endmodule
// =========================================================================== // ===========================================================================
// //
// Description: // Description:
// Verilog module for general latch // Verilog module for general latch
// //
// =========================================================================== // ===========================================================================
module sirv_gnrl_ltch # ( module sirv_gnrl_ltch # (
parameter DW = 32 parameter DW = 32
) ( ) (
//input test_mode, //input test_mode,
input lden, input lden,
input [DW-1:0] dnxt, input [DW-1:0] dnxt,
output [DW-1:0] qout output [DW-1:0] qout
); );
reg [DW-1:0] qout_r; reg [DW-1:0] qout_r;
always @ * always @ *
begin : LTCH_PROC begin : LTCH_PROC
if (lden == 1'b1) if (lden == 1'b1)
qout_r <= dnxt; qout_r <= dnxt;
end end
//assign qout = test_mode ? dnxt : qout_r; //assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r; assign qout = qout_r;
`ifndef FPGA_SOURCE//{ `ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{ `ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off //synopsys translate_off
always_comb always_comb
begin begin
CHECK_THE_X_VALUE: CHECK_THE_X_VALUE:
assert (lden !== 1'bx) assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end end
//synopsys translate_on //synopsys translate_on
`endif//} `endif//}
`endif//} `endif//}
endmodule endmodule

58
rtl/z_dsp/syncer.v Normal file
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@ -0,0 +1,58 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : syncer.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-03-13 PWY AWG dedicated register file
// 0.2 2024-05-13 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module syncer # (
parameter width = 1
,parameter stage = 2
)
(
input clk_d
,input rstn_d
,input [width-1:0] data_s
,output [width-1:0] data_d
);
generate
genvar i;
wire [width-1:0] data_temp[stage-1:0];
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
for(i=1;i<stage;i=i+1) begin: SYNCER
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
end
endgenerate
assign data_d = data_temp[stage-1];
endmodule

480
rtl/z_dsp/z_dsp.v Normal file
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@ -0,0 +1,480 @@
module z_dsp
(
input rstn
,input clk
,input en
//,input tc_bypass //NC
,input [ 3:0] vldi_coef
,input vldi_data
//,input [1:0] intp_mode //NC
//,input [1:0] dac_mode_sel //NC
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [15:0] din4
,input signed [15:0] din5
,input signed [15:0] din6
,input signed [15:0] din7
,input signed [15:0] din8
,input signed [15:0] din9
,input signed [15:0] dina
,input signed [15:0] dinb
,input signed [15:0] dinc
,input signed [15:0] dind
,input signed [15:0] dine
,input signed [15:0] dinf
,input signed [31:0] a0_re
,input signed [31:0] b0_re
,input signed [31:0] a1_re
,input signed [31:0] b1_re
,input signed [31:0] a2_re
,input signed [31:0] b2_re
,input signed [31:0] a3_re
,input signed [31:0] b3_re
// 复数端口
`ifdef COMPLEX
input signed [31:0] a0_im;
input signed [31:0] b0_im;
input signed [31:0] a1_im;
input signed [31:0] b1_im;
input signed [31:0] a2_im;
input signed [31:0] b2_im;
input signed [31:0] a3_im;
input signed [31:0] b3_im;
`endif
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output signed [15:0] dout4
,output signed [15:0] dout5
,output signed [15:0] dout6
,output signed [15:0] dout7
,output signed [15:0] dout8
,output signed [15:0] dout9
,output signed [15:0] douta
,output signed [15:0] doutb
,output signed [15:0] doutc
,output signed [15:0] doutd
,output signed [15:0] doute
,output signed [15:0] doutf
,output vldo
);
wire signed [15:0] IIR_out;
wire signed [31:0] ao_re [3:0];
wire signed [31:0] ab_re [3:0];
wire signed [31:0] abb_re [3:0];
wire signed [31:0] ab_pow3_re [3:0];
wire signed [31:0] ab_pow4_re [3:0];
wire signed [31:0] ab_pow5_re [3:0];
wire signed [31:0] ab_pow6_re [3:0];
wire signed [31:0] ab_pow7_re [3:0];
wire signed [31:0] ab_pow8_re [3:0];
wire signed [31:0] ab_pow9_re [3:0];
wire signed [31:0] ab_powa_re [3:0];
wire signed [31:0] ab_powb_re [3:0];
wire signed [31:0] ab_powc_re [3:0];
wire signed [31:0] ab_powd_re [3:0];
wire signed [31:0] ab_powe_re [3:0];
wire signed [31:0] ab_powf_re [3:0];
wire signed [31:0] bo_re [3:0];
wire signed [31:0] b_pow16_re [3:0];
// 复数信号
`ifdef COMPLEX
wire signed [31:0] ao_im [3:0];
wire signed [31:0] ab_im [3:0];
wire signed [31:0] abb_im [3:0];
wire signed [31:0] ab_pow3_im [3:0];
wire signed [31:0] ab_pow4_im [3:0];
wire signed [31:0] ab_pow5_im [3:0];
wire signed [31:0] ab_pow6_im [3:0];
wire signed [31:0] ab_pow7_im [3:0];
wire signed [31:0] ab_pow8_im [3:0];
wire signed [31:0] ab_pow9_im [3:0];
wire signed [31:0] ab_powa_im [3:0];
wire signed [31:0] ab_powb_im [3:0];
wire signed [31:0] ab_powc_im [3:0];
wire signed [31:0] ab_powd_im [3:0];
wire signed [31:0] ab_powe_im [3:0];
wire signed [31:0] ab_powf_im [3:0];
wire signed [31:0] bo_im [3:0];
wire signed [31:0] b_pow16_im [3:0];
`endif
CoefGen#(
.data_in_width ( 32 )
,.coef_width ( 32 )
,.frac_data_out_width ( 20 )
,.frac_coef_width ( 31 )
) u_CoefGen(
.rstn ( rstn )
,.clk ( clk )
,.vldi ( vldi_coef )
,.a0_re ( a0_re )
,.b0_re ( b0_re )
,.a1_re ( a1_re )
,.b1_re ( b1_re )
,.a2_re ( a2_re )
,.b2_re ( b2_re )
,.a3_re ( a3_re )
,.b3_re ( b3_re )
`ifdef COMPLEX
,.a0_im ( a0_im )
,.b0_im ( b0_im )
,.a1_im ( a1_im )
,.b1_im ( b1_im )
,.a2_im ( a2_im )
,.b2_im ( b2_im )
,.a3_im ( a3_im )
,.b3_im ( b3_im )
`endif
,.a_re0 ( ao_re[0] )
,.b_re0 ( bo_re[0] )
,.ab_re0 ( ab_re[0] )
,.abb_re0 ( abb_re[0] )
,.ab_pow3_re0 ( ab_pow3_re[0] )
,.ab_pow4_re0 ( ab_pow4_re[0] )
,.ab_pow5_re0 ( ab_pow5_re[0] )
,.ab_pow6_re0 ( ab_pow6_re[0] )
,.ab_pow7_re0 ( ab_pow7_re[0] )
,.ab_pow8_re0 ( ab_pow8_re[0] )
,.ab_pow9_re0 ( ab_pow9_re[0] )
,.ab_powa_re0 ( ab_powa_re[0] )
,.ab_powb_re0 ( ab_powb_re[0] )
,.ab_powc_re0 ( ab_powc_re[0] )
,.ab_powd_re0 ( ab_powd_re[0] )
,.ab_powe_re0 ( ab_powe_re[0] )
,.ab_powf_re0 ( ab_powf_re[0] )
,.b_pow16_re0 ( b_pow16_re[0] )
,.a_re1 ( ao_re[1] )
,.b_re1 ( bo_re[1] )
,.ab_re1 ( ab_re[1] )
,.abb_re1 ( abb_re[1] )
,.ab_pow3_re1 ( ab_pow3_re[1] )
,.ab_pow4_re1 ( ab_pow4_re[1] )
,.ab_pow5_re1 ( ab_pow5_re[1] )
,.ab_pow6_re1 ( ab_pow6_re[1] )
,.ab_pow7_re1 ( ab_pow7_re[1] )
,.ab_pow8_re1 ( ab_pow8_re[1] )
,.ab_pow9_re1 ( ab_pow9_re[1] )
,.ab_powa_re1 ( ab_powa_re[1] )
,.ab_powb_re1 ( ab_powb_re[1] )
,.ab_powc_re1 ( ab_powc_re[1] )
,.ab_powd_re1 ( ab_powd_re[1] )
,.ab_powe_re1 ( ab_powe_re[1] )
,.ab_powf_re1 ( ab_powf_re[1] )
,.b_pow16_re1 ( b_pow16_re[1] )
,.a_re2 ( ao_re[2] )
,.b_re2 ( bo_re[2] )
,.ab_re2 ( ab_re[2] )
,.abb_re2 ( abb_re[2] )
,.ab_pow3_re2 ( ab_pow3_re[2] )
,.ab_pow4_re2 ( ab_pow4_re[2] )
,.ab_pow5_re2 ( ab_pow5_re[2] )
,.ab_pow6_re2 ( ab_pow6_re[2] )
,.ab_pow7_re2 ( ab_pow7_re[2] )
,.ab_pow8_re2 ( ab_pow8_re[2] )
,.ab_pow9_re2 ( ab_pow9_re[2] )
,.ab_powa_re2 ( ab_powa_re[2] )
,.ab_powb_re2 ( ab_powb_re[2] )
,.ab_powc_re2 ( ab_powc_re[2] )
,.ab_powd_re2 ( ab_powd_re[2] )
,.ab_powe_re2 ( ab_powe_re[2] )
,.ab_powf_re2 ( ab_powf_re[2] )
,.b_pow16_re2 ( b_pow16_re[2] )
,.a_re3 ( ao_re[3] )
,.b_re3 ( bo_re[3] )
,.ab_re3 ( ab_re[3] )
,.abb_re3 ( abb_re[3] )
,.ab_pow3_re3 ( ab_pow3_re[3] )
,.ab_pow4_re3 ( ab_pow4_re[3] )
,.ab_pow5_re3 ( ab_pow5_re[3] )
,.ab_pow6_re3 ( ab_pow6_re[3] )
,.ab_pow7_re3 ( ab_pow7_re[3] )
,.ab_pow8_re3 ( ab_pow8_re[3] )
,.ab_pow9_re3 ( ab_pow9_re[3] )
,.ab_powa_re3 ( ab_powa_re[3] )
,.ab_powb_re3 ( ab_powb_re[3] )
,.ab_powc_re3 ( ab_powc_re[3] )
,.ab_powd_re3 ( ab_powd_re[3] )
,.ab_powe_re3 ( ab_powe_re[3] )
,.ab_powf_re3 ( ab_powf_re[3] )
,.b_pow16_re3 ( b_pow16_re[3] )
`ifdef COMPLEX
,.a_im0 ( ao_im[0] )
,.b_im0 ( bo_im[0] )
,.ab_im0 ( ab_im[0] )
,.abb_im0 ( abb_im[0] )
,.ab_pow3_im0 ( ab_pow3_im[0] )
,.ab_pow4_im0 ( ab_pow4_im[0] )
,.ab_pow5_im0 ( ab_pow5_im[0] )
,.ab_pow6_im0 ( ab_pow6_im[0] )
,.ab_pow7_im0 ( ab_pow7_im[0] )
,.ab_pow8_im0 ( ab_pow8_im[0] )
,.ab_pow9_im0 ( ab_pow9_im[0] )
,.ab_powa_im0 ( ab_powa_im[0] )
,.ab_powb_im0 ( ab_powb_im[0] )
,.ab_powc_im0 ( ab_powc_im[0] )
,.ab_powd_im0 ( ab_powd_im[0] )
,.ab_powe_im0 ( ab_powe_im[0] )
,.ab_powf_im0 ( ab_powf_im[0] )
,.b_pow16_im0 ( b_pow16_im[0] )
,.a_im1 ( ao_im[1] )
,.b_im1 ( bo_im[1] )
,.ab_im1 ( ab_im[1] )
,.abb_im1 ( abb_im[1] )
,.ab_pow3_im1 ( ab_pow3_im[1] )
,.ab_pow4_im1 ( ab_pow4_im[1] )
,.ab_pow5_im1 ( ab_pow5_im[1] )
,.ab_pow6_im1 ( ab_pow6_im[1] )
,.ab_pow7_im1 ( ab_pow7_im[1] )
,.ab_pow8_im1 ( ab_pow8_im[1] )
,.ab_pow9_im1 ( ab_pow9_im[1] )
,.ab_powa_im1 ( ab_powa_im[1] )
,.ab_powb_im1 ( ab_powb_im[1] )
,.ab_powc_im1 ( ab_powc_im[1] )
,.ab_powd_im1 ( ab_powd_im[1] )
,.ab_powe_im1 ( ab_powe_im[1] )
,.ab_powf_im1 ( ab_powf_im[1] )
,.b_pow16_im1 ( b_pow16_im[1] )
,.a_im2 ( ao_im[2] )
,.b_im2 ( bo_im[2] )
,.ab_im2 ( ab_im[2] )
,.abb_im2 ( abb_im[2] )
,.ab_pow3_im2 ( ab_pow3_im[2] )
,.ab_pow4_im2 ( ab_pow4_im[2] )
,.ab_pow5_im2 ( ab_pow5_im[2] )
,.ab_pow6_im2 ( ab_pow6_im[2] )
,.ab_pow7_im2 ( ab_pow7_im[2] )
,.ab_pow8_im2 ( ab_pow8_im[2] )
,.ab_pow9_im2 ( ab_pow9_im[2] )
,.ab_powa_im2 ( ab_powa_im[2] )
,.ab_powb_im2 ( ab_powb_im[2] )
,.ab_powc_im2 ( ab_powc_im[2] )
,.ab_powd_im2 ( ab_powd_im[2] )
,.ab_powe_im2 ( ab_powe_im[2] )
,.ab_powf_im2 ( ab_powf_im[2] )
,.b_pow16_im2 ( b_pow16_im[2] )
,.a_im3 ( ao_im[3] )
,.b_im3 ( bo_im[3] )
,.ab_im3 ( ab_im[3] )
,.abb_im3 ( abb_im[3] )
,.ab_pow3_im3 ( ab_pow3_im[3] )
,.ab_pow4_im3 ( ab_pow4_im[3] )
,.ab_pow5_im3 ( ab_pow5_im[3] )
,.ab_pow6_im3 ( ab_pow6_im[3] )
,.ab_pow7_im3 ( ab_pow7_im[3] )
,.ab_pow8_im3 ( ab_pow8_im[3] )
,.ab_pow9_im3 ( ab_pow9_im[3] )
,.ab_powa_im3 ( ab_powa_im[3] )
,.ab_powb_im3 ( ab_powb_im[3] )
,.ab_powc_im3 ( ab_powc_im[3] )
,.ab_powd_im3 ( ab_powd_im[3] )
,.ab_powe_im3 ( ab_powe_im[3] )
,.ab_powf_im3 ( ab_powf_im[3] )
,.b_pow16_im3 ( b_pow16_im[3] )
`endif
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
wire vldo_TC;
TailCorr_top u_TailCorr_top(
.rstn ( rstn )
,.clk ( clk )
,.en ( en )
,.vldi ( vldi_data )
,.din0 ( din0 )
,.din1 ( din1 )
,.din2 ( din2 )
,.din3 ( din3 )
,.din4 ( din4 )
,.din5 ( din5 )
,.din6 ( din6 )
,.din7 ( din7 )
,.din8 ( din8 )
,.din9 ( din9 )
,.dina ( dina )
,.dinb ( dinb )
,.dinc ( dinc )
,.dind ( dind )
,.dine ( dine )
,.dinf ( dinf )
,.a_re0 ( ao_re[0] )
,.b_re0 ( bo_re[0] )
,.ab_re0 ( ab_re[0] )
,.abb_re0 ( abb_re[0] )
,.ab_pow3_re0 ( ab_pow3_re[0] )
,.ab_pow4_re0 ( ab_pow4_re[0] )
,.ab_pow5_re0 ( ab_pow5_re[0] )
,.ab_pow6_re0 ( ab_pow6_re[0] )
,.ab_pow7_re0 ( ab_pow7_re[0] )
,.ab_pow8_re0 ( ab_pow8_re[0] )
,.ab_pow9_re0 ( ab_pow9_re[0] )
,.ab_powa_re0 ( ab_powa_re[0] )
,.ab_powb_re0 ( ab_powb_re[0] )
,.ab_powc_re0 ( ab_powc_re[0] )
,.ab_powd_re0 ( ab_powd_re[0] )
,.ab_powe_re0 ( ab_powe_re[0] )
,.ab_powf_re0 ( ab_powf_re[0] )
,.b_pow16_re0 ( b_pow16_re[0] )
,.a_re1 ( ao_re[1] )
,.b_re1 ( bo_re[1] )
,.ab_re1 ( ab_re[1] )
,.abb_re1 ( abb_re[1] )
,.ab_pow3_re1 ( ab_pow3_re[1] )
,.ab_pow4_re1 ( ab_pow4_re[1] )
,.ab_pow5_re1 ( ab_pow5_re[1] )
,.ab_pow6_re1 ( ab_pow6_re[1] )
,.ab_pow7_re1 ( ab_pow7_re[1] )
,.ab_pow8_re1 ( ab_pow8_re[1] )
,.ab_pow9_re1 ( ab_pow9_re[1] )
,.ab_powa_re1 ( ab_powa_re[1] )
,.ab_powb_re1 ( ab_powb_re[1] )
,.ab_powc_re1 ( ab_powc_re[1] )
,.ab_powd_re1 ( ab_powd_re[1] )
,.ab_powe_re1 ( ab_powe_re[1] )
,.ab_powf_re1 ( ab_powf_re[1] )
,.b_pow16_re1 ( b_pow16_re[1] )
,.a_re2 ( ao_re[2] )
,.b_re2 ( bo_re[2] )
,.ab_re2 ( ab_re[2] )
,.abb_re2 ( abb_re[2] )
,.ab_pow3_re2 ( ab_pow3_re[2] )
,.ab_pow4_re2 ( ab_pow4_re[2] )
,.ab_pow5_re2 ( ab_pow5_re[2] )
,.ab_pow6_re2 ( ab_pow6_re[2] )
,.ab_pow7_re2 ( ab_pow7_re[2] )
,.ab_pow8_re2 ( ab_pow8_re[2] )
,.ab_pow9_re2 ( ab_pow9_re[2] )
,.ab_powa_re2 ( ab_powa_re[2] )
,.ab_powb_re2 ( ab_powb_re[2] )
,.ab_powc_re2 ( ab_powc_re[2] )
,.ab_powd_re2 ( ab_powd_re[2] )
,.ab_powe_re2 ( ab_powe_re[2] )
,.ab_powf_re2 ( ab_powf_re[2] )
,.b_pow16_re2 ( b_pow16_re[2] )
,.a_re3 ( ao_re[3] )
,.b_re3 ( bo_re[3] )
,.ab_re3 ( ab_re[3] )
,.abb_re3 ( abb_re[3] )
,.ab_pow3_re3 ( ab_pow3_re[3] )
,.ab_pow4_re3 ( ab_pow4_re[3] )
,.ab_pow5_re3 ( ab_pow5_re[3] )
,.ab_pow6_re3 ( ab_pow6_re[3] )
,.ab_pow7_re3 ( ab_pow7_re[3] )
,.ab_pow8_re3 ( ab_pow8_re[3] )
,.ab_pow9_re3 ( ab_pow9_re[3] )
,.ab_powa_re3 ( ab_powa_re[3] )
,.ab_powb_re3 ( ab_powb_re[3] )
,.ab_powc_re3 ( ab_powc_re[3] )
,.ab_powd_re3 ( ab_powd_re[3] )
,.ab_powe_re3 ( ab_powe_re[3] )
,.ab_powf_re3 ( ab_powf_re[3] )
,.b_pow16_re3 ( b_pow16_re[3] )
`ifdef COMPLEX
,.a_im0 ( ao_im[0] )
,.b_im0 ( bo_im[0] )
,.ab_im0 ( ab_im[0] )
,.abb_im0 ( abb_im[0] )
,.ab_pow3_im0 ( ab_pow3_im[0] )
,.ab_pow4_im0 ( ab_pow4_im[0] )
,.ab_pow5_im0 ( ab_pow5_im[0] )
,.ab_pow6_im0 ( ab_pow6_im[0] )
,.ab_pow7_im0 ( ab_pow7_im[0] )
,.ab_pow8_im0 ( ab_pow8_im[0] )
,.ab_pow9_im0 ( ab_pow9_im[0] )
,.ab_powa_im0 ( ab_powa_im[0] )
,.ab_powb_im0 ( ab_powb_im[0] )
,.ab_powc_im0 ( ab_powc_im[0] )
,.ab_powd_im0 ( ab_powd_im[0] )
,.ab_powe_im0 ( ab_powe_im[0] )
,.ab_powf_im0 ( ab_powf_im[0] )
,.b_pow16_im0 ( b_pow16_im[0] )
,.a_im1 ( ao_im[1] )
,.b_im1 ( bo_im[1] )
,.ab_im1 ( ab_im[1] )
,.abb_im1 ( abb_im[1] )
,.ab_pow3_im1 ( ab_pow3_im[1] )
,.ab_pow4_im1 ( ab_pow4_im[1] )
,.ab_pow5_im1 ( ab_pow5_im[1] )
,.ab_pow6_im1 ( ab_pow6_im[1] )
,.ab_pow7_im1 ( ab_pow7_im[1] )
,.ab_pow8_im1 ( ab_pow8_im[1] )
,.ab_pow9_im1 ( ab_pow9_im[1] )
,.ab_powa_im1 ( ab_powa_im[1] )
,.ab_powb_im1 ( ab_powb_im[1] )
,.ab_powc_im1 ( ab_powc_im[1] )
,.ab_powd_im1 ( ab_powd_im[1] )
,.ab_powe_im1 ( ab_powe_im[1] )
,.ab_powf_im1 ( ab_powf_im[1] )
,.b_pow16_im1 ( b_pow16_im[1] )
,.a_im2 ( ao_im[2] )
,.b_im2 ( bo_im[2] )
,.ab_im2 ( ab_im[2] )
,.abb_im2 ( abb_im[2] )
,.ab_pow3_im2 ( ab_pow3_im[2] )
,.ab_pow4_im2 ( ab_pow4_im[2] )
,.ab_pow5_im2 ( ab_pow5_im[2] )
,.ab_pow6_im2 ( ab_pow6_im[2] )
,.ab_pow7_im2 ( ab_pow7_im[2] )
,.ab_pow8_im2 ( ab_pow8_im[2] )
,.ab_pow9_im2 ( ab_pow9_im[2] )
,.ab_powa_im2 ( ab_powa_im[2] )
,.ab_powb_im2 ( ab_powb_im[2] )
,.ab_powc_im2 ( ab_powc_im[2] )
,.ab_powd_im2 ( ab_powd_im[2] )
,.ab_powe_im2 ( ab_powe_im[2] )
,.ab_powf_im2 ( ab_powf_im[2] )
,.b_pow16_im2 ( b_pow16_im[2] )
,.a_im3 ( ao_im[3] )
,.b_im3 ( bo_im[3] )
,.ab_im3 ( ab_im[3] )
,.abb_im3 ( abb_im[3] )
,.ab_pow3_im3 ( ab_pow3_im[3] )
,.ab_pow4_im3 ( ab_pow4_im[3] )
,.ab_pow5_im3 ( ab_pow5_im[3] )
,.ab_pow6_im3 ( ab_pow6_im[3] )
,.ab_pow7_im3 ( ab_pow7_im[3] )
,.ab_pow8_im3 ( ab_pow8_im[3] )
,.ab_pow9_im3 ( ab_pow9_im[3] )
,.ab_powa_im3 ( ab_powa_im[3] )
,.ab_powb_im3 ( ab_powb_im[3] )
,.ab_powc_im3 ( ab_powc_im[3] )
,.ab_powd_im3 ( ab_powd_im[3] )
,.ab_powe_im3 ( ab_powe_im[3] )
,.ab_powf_im3 ( ab_powf_im[3] )
,.b_pow16_im3 ( b_pow16_im[3] )
`endif
,.dout_p0 ( dout0 )
,.dout_p1 ( dout1 )
,.dout_p2 ( dout2 )
,.dout_p3 ( dout3 )
,.dout_p4 ( dout4 )
,.dout_p5 ( dout5 )
,.dout_p6 ( dout6 )
,.dout_p7 ( dout7 )
,.dout_p8 ( dout8 )
,.dout_p9 ( dout9 )
,.dout_pa ( douta )
,.dout_pb ( doutb )
,.dout_pc ( doutc )
,.dout_pd ( doutd )
,.dout_pe ( doute )
,.dout_pf ( doutf )
,.vldo ( vldo_TC )
);
assign vldo = vldo_TC;
endmodule

55
script_m/TailCorr_Test_Verdi.m
View File

@ -2,14 +2,17 @@
clc;clear;close all clc;clear;close all
% addpath("/data/work/thfu/TailCorr/script_m"); % addpath("/data/work/thfu/TailCorr/script_m");
data_source = 'matlab'; data_source = 'matlab';
file_path = "/home/thfu/work/TailCorr/sim/"; file_path = "/home/thfu/work/TailCorr/sim/z_dsp/";
rng('shuffle'); rng('shuffle');
max_error = zeros(100,1);
for time = 1
if strcmp(data_source, 'matlab') if strcmp(data_source, 'matlab')
in = floor(cat(1,0,30000*ones(4*2579+4,1))); in = floor(cat(1,0,3000*randn(16*2500-1,1)));
for i = 0:3 for i = 0:15
filename = strcat(file_path, "in", num2str(i), "_matlab.dat"); filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
subset = in(i+1:4:end); subset = in(i+1:16:end);
fileID = fopen(filename, 'w'); fileID = fopen(filename, 'w');
fprintf(fileID, '%d\n', subset); fprintf(fileID, '%d\n', subset);
fclose(fileID); fclose(fileID);
@ -17,7 +20,7 @@ if strcmp(data_source, 'matlab')
in = [in; zeros(6e4,1)]; in = [in; zeros(6e4,1)];
system('make all'); system('make all');
elseif strcmp(data_source, 'verdi') elseif strcmp(data_source, 'verdi')
% system('make all'); system('make all');
in = []; in = [];
for i = 0:3 for i = 0:3
filename = strcat(file_path, "in", num2str(i), ".dat"); filename = strcat(file_path, "in", num2str(i), ".dat");
@ -33,14 +36,14 @@ end
cs_wave = []; cs_wave = [];
for i = 0:7 for i = 0:15
filename = strcat(file_path, "dout", num2str(i), ".dat"); filename = strcat(file_path, "dout", num2str(i), ".dat");
dout_data = importdata(filename); dout_data = importdata(filename);
if isempty(cs_wave) if isempty(cs_wave)
N = length(dout_data); N = length(dout_data);
cs_wave = zeros(8*N, 1); cs_wave = zeros(16*N, 1);
end end
cs_wave(i+1:8:end) = dout_data; cs_wave(i+1:16:end) = dout_data;
end end
A = [0.025 0.015*1 0.0002*1 0]; A = [0.025 0.015*1 0.0002*1 0];
@ -64,17 +67,19 @@ wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),
[cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr"); [cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr");
N = min(length(wave_float),length(cs_wave_A)); N = min(length(wave_float),length(cs_wave_A));
figure() figure()
diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]); max_error(time) = diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
%% Test of iir filter with no intp end
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi); % %% Test of iir filter with no intp
N = min(length(wave_float_A),length(wave_verdi_A)); %
figure() % [wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]); % N = min(length(wave_float_A),length(wave_verdi_A));
%% % figure()
signalAnalyzer(wave_float,wave_verdi,'SampleRate',1); % diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
%% % %%
% signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
% %%
a_fix = round(a*2^31); a_fix = round(a*2^31);
b_fix = round(b*2^31); b_fix = round(b*2^31);
@ -93,12 +98,12 @@ a_bin = dec2bin(a_fix,32);
fprintf('a_fix is %d\n',a_fix); fprintf('a_fix is %d\n',a_fix);
fprintf('b_fix is %d\n',b_fix); fprintf('b_fix is %d\n',b_fix);
fprintf('ab_fix is %d\n',ab_fix); % fprintf('ab_fix is %d\n',ab_fix);
fprintf('ab2_fix is %d\n', ab2_fix); % fprintf('ab2_fix is %d\n', ab2_fix);
fprintf('ab3_fix is %d\n', ab3_fix); % fprintf('ab3_fix is %d\n', ab3_fix);
fprintf('ab4_fix is %d\n', ab4_fix); % fprintf('ab4_fix is %d\n', ab4_fix);
fprintf('ab5_fix is %d\n', ab5_fix); % fprintf('ab5_fix is %d\n', ab5_fix);
fprintf('ab6_fix is %d\n', ab6_fix); % fprintf('ab6_fix is %d\n', ab6_fix);
fprintf('ab7_fix is %d\n', ab7_fix); % fprintf('ab7_fix is %d\n', ab7_fix);
fprintf('b8_fix is %d\n',b8_fix); % fprintf('b8_fix is %d\n',b8_fix);

4
script_m/diff_plot.m
View File

@ -1,4 +1,4 @@
function diff_plot(iir_out, Script_out,leg1,leg2,a) function result = diff_plot(iir_out, Script_out,leg1,leg2,a)
N = min(length(iir_out),length(Script_out)); N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N); iir_out = iir_out(1:N);
@ -32,3 +32,5 @@ plot(n(R_mpos_min),diff(R_mpos_min),'r*')
text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k'); text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k');
text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k'); text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k');
result = max(abs(diff(R_mpos_max)),abs(diff(R_mpos_min)));

565
script_m/z_dsp.m
View File

@ -1,565 +0,0 @@
classdef z_dsp < handle
properties
%input
fs_L;
fs_H;
TargetFrequency;
G;
simulink_time;
intp_mode;
dac_mode_sel;
route_num;
env_num;
%output
Ideal2Low;
Ideal2Target;
wave_pre;
wave_preL;
amp_real;
amp_imag;
time_real;
time_imag;
name;
wave_revised;
wave_revisedL;
DownsamplingBy12GDataAlign;
HardwareMeanIntpDataAlign;
Delay;
Delay_mode;
pause_time;
filename;
rpt_num;
FallingEdge;
Amp;
itv_time; %信号具有周期性时的间隔
end
methods
function obj = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel)
obj.fs_L = fs_L;
obj.fs_H = fs_H;
obj.TargetFrequency = TargetFrequency;
obj.G = G;
obj.simulink_time = simulink_time;
obj.intp_mode = intp_mode;
obj.dac_mode_sel = dac_mode_sel;
obj.Ideal2Low = fs_H/(fs_L/2);
obj.Ideal2Target = fs_H/TargetFrequency;
obj.name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第一组S21参数_acz_持续时间30ns_下降沿",...
"第一组S21参数_acz_持续时间50ns_下降沿";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第二组S21参数_acz_持续时间30ns_下降沿",...
"第二组S21参数_acz_持续时间50ns_下降沿";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第三组S21参数_acz_持续时间30ns_下降沿",...
"第三组S21参数_acz_持续时间50ns_下降沿";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第四组S21参数_acz_持续时间30ns_下降沿",...
"第四组S21参数_acz_持续时间50ns_下降沿";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第五组S21参数_acz_持续时间30ns_下降沿",...
"第五组S21参数_acz_持续时间50ns_下降沿";
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第一组S21参数_acz_持续时间30ns_下降沿后",...
"第一组S21参数_acz_持续时间50ns_下降沿后";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第二组S21参数_acz_持续时间30ns_下降沿后",...
"第二组S21参数_acz_持续时间50ns_下降沿后";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第三组S21参数_acz_持续时间30ns_下降沿后",...
"第三组S21参数_acz_持续时间50ns_下降沿后";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第四组S21参数_acz_持续时间30ns_下降沿后",...
"第四组S21参数_acz_持续时间50ns_下降沿后";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第五组S21参数_acz_持续时间30ns_下降沿后",...
"第五组S21参数_acz_持续时间50ns_下降沿后";
];
obj.pause_time = 0.5;
obj.Amp = 1.5e4;
end
function env(obj)
cd("D:\Work\EnvData\acz");
obj1 = py.importlib.import_module('acz');
py.importlib.reload(obj1);
%按点数产生理想方波
% amp_rect = 1.5e4;
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
%
% for i = 1:2
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
% end
%flattop波
A = 1.5e4;
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
[edge(2), length_flattop(2)] = deal(4,30);
[edge(3), length_flattop(3)] = deal(4,50);
[edge(4), length_flattop(4)] = deal(4,1000);
[edge(5), length_flattop(5)] = deal(100,10000);
for i = 1:length(length_flattop)
[edge_H(i), length_H(i)] = deal(edge(i)*obj.fs_H/1e9,length_flattop(i)*obj.fs_H/1e9);
obj.wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
end
%acz波
amplitude = 1.5e4;
carrierFreq = 0.000000;
carrierPhase = 0.000000;
dragAlpha = 0.000000;
thf = 0.864;
thi = 0.05;
lam2 = -0.18;
lam3 = 0.04;
length_acz(1) = 30;
length_acz(2) = 50;
for i = 1:length(length_acz)
length_acz_H(i) = int32(length_acz(i)*obj.fs_H/1e9);
obj.wave_pre{i+length(length_flattop)} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
end
obj.env_num = length(length_flattop) + length(length_acz);
for i = 1:obj.env_num
obj.wave_pre{i} = cat(2,repmat(cat(2,obj.wave_pre{i},zeros(1,round(30e-9*obj.fs_H))),1,obj.rpt_num),zeros(1,floor(obj.simulink_time*obj.fs_H))); %校正前的高频信号
obj.wave_preL{i} = obj.wave_pre{i}(1:obj.Ideal2Low:end); %校正前的低频信号
end
assignin("base",'wave_preL',obj.wave_preL);
obj.FallingEdge = [30e-9,30e-9,50e-9,1000e-9,10000e-9,30e-9,50e-9];
end
function route(obj)
obj.amp_real{1}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{1}= [0 0 0 0 0 0];
obj.time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{1} = [0 0 0 0 0 0];
obj.amp_real{2}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{2}= [0 0 0 0 0 0];
obj.time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{2} = [0 -1/300 -1/500 0 0 0];
obj.amp_real{3}= [0.025 0.009 0.0002 0.2 0 0];
obj.amp_imag{3}= [0 0.012 0 0 0 0];
obj.time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{3} = [0 -1/300 -1/500 0 0 0];
obj.amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{4}= [0 0 0 0 0 0];
obj.time_real{4} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
obj.time_imag{4} = [0 -1/15 -1/50 0 0 0];
obj.amp_real{5}= [0.025 0.009 0.0002 0.2 0 0];
obj.amp_imag{5}= [0 0.012 0 0 0 0];
obj.time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
obj.time_imag{5} = [0 -1/15 -1/50 0 0 0];
[m,n] = size(obj.amp_real);
obj.route_num = n;
end
function py_cal(obj)
cd("D:\Work\TailCorr_20241008_NoGit");
obj2 = py.importlib.import_module('wave_calculation');
py.importlib.reload(obj2);
cd("D:\Work\TailCorr");
convolve_bound = int8(3);
calibration_time = int32(20e3);
cal_method = int8(1);
sampling_rateL = int64(obj.fs_L/2);
sampling_rate = int64(obj.fs_H);
%校正后的高频信号
for m = 1:obj.route_num
for n = 1:obj.env_num
wave_cal = cell(py.wave_calculation.wave_cal(obj.wave_pre{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rate));
obj.wave_revised{m,n} = double(wave_cal{1,1});
wave_calL = cell(py.wave_calculation.wave_cal(obj.wave_preL{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rateL));
obj.wave_revisedL{m,n} = double(wave_calL{1,1});
end
alpha{m} = double(wave_calL{1,2});
beta{m} = double(wave_calL{1,3});
end
alpha_wideth=32;
beta_width=32;
%定点化系数
for i = 1:obj.route_num
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
end
assignin('base', 'alphaFixRe', alphaFixRe);
assignin('base', 'alphaFixIm', alphaFixIm);
assignin('base', 'betaFixRe' , betaFixRe);
assignin('base', 'betaFixIm' , betaFixIm);
end
function FIL(obj)
for m = 1:obj.route_num
assignin('base', 'm', m);
for n = 1:obj.env_num
assignin('base', 'n', n);
optnons=simset('SrcWorkspace','current');
sim('z_dsp_FIL',[0,obj.simulink_time]);
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
dout0{m,n} = sim2m("dout0");
dout1{m,n} = sim2m("dout1");
dout2{m,n} = sim2m("dout2");
dout3{m,n} = sim2m("dout3");
N = length(dout0{m,n});
cs_wave{m,n} = zeros(4*N,1);
cs_wave{m,n}(1:4:4*N) = dout0{m,n};
cs_wave{m,n}(2:4:4*N) = dout1{m,n};
cs_wave{m,n}(3:4:4*N) = dout2{m,n};
cs_wave{m,n}(4:4:4*N) = dout3{m,n};
HardwareMeanIntpData{m,n} = cs_wave{m,n};%硬件校正后内插
DownsamplingBy12GData{m,n} = obj.wave_revised{m,n}(1:obj.Ideal2Target:end);
[obj.DownsamplingBy12GDataAlign{m,n},obj.HardwareMeanIntpDataAlign{m,n},obj.Delay(m,n)] = ...
alignsignals(DownsamplingBy12GData{m,n}(1:round(obj.TargetFrequency*20e-6)),HardwareMeanIntpData{m,n}(1:round(obj.TargetFrequency*20e-6)),"Method","xcorr");
end
end
obj.Delay_mode = mode(obj.Delay,'all');
fprintf('Delay_mode = %d\n',obj.Delay_mode);
end
function DataShow(obj,save)
close all;
fileID = fopen(obj.filename, 'w');
if fileID == -1
disp('文件打开失败');
else
disp('文件打开成功');
end
start_time = abs(obj.Delay_mode)/(obj.TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
if(obj.rpt_num == 1)
for m = 1:obj.route_num
for n = 1:obj.env_num
edge_Align(n) = obj.FallingEdge(n) + start_time;
tmp(n) = edge_Align(n) + 10e-9;
a{n} = [start_time-5e-9 tmp(n)];%[1/obj.fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
b{n} = [tmp(n) 20e-6];
figure('Units','normalized','Position',[0.0004 0.5174 0.4992 0.4229]);
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',a{n},obj.Amp,edge_Align(n),fileID);
if(save == "save")
savefig(obj.name(m,n));
end
figure('Units','normalized','Position',[0.0004 0.0340 0.4992 0.4229]);
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m+5,n),'硬件与脚本的差值',b{n},obj.Amp,edge_Align(n),fileID);
if(save == "save")
savefig(obj.name(m+5,n));
end
end
end
else
for m = 1:obj.route_num
for n = 1:obj.env_num
figure('Units','normalized','Position',[0 0.0333 1.0000 0.9125]);
title(obj.name(m,n),Interpreter="none");
tiledlayout('vertical','TileSpacing','tight')
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',obj.FallingEdge(n)+obj.itv_time,obj.Amp,start_time,fileID);
if(save == "save")
savefig(obj.name(m,n));
end
end
end
end
fclose(fileID);
end
function RouteShow(obj,save)
t = 0:1/(1e2):10000;
for i = 1:5
amp_routing{i} = obj.amp_real{1,i} + 1j*obj.amp_imag{1,i};
time_routing{i} = obj.time_real{1,i} + 1j*obj.time_imag{1,i};
tau{i} = -1./time_routing{i};
end
figure()
set(gcf,"Position",[1 49 2560 1314])
tiledlayout('flow','TileSpacing','tight');
title_name = ["第一组S_{21}参数","第二组S_{21}参数","第三组S_{21}参数","第四组S_{21}参数","第五组S_{21}参数"];
for m = 1:obj.route_num
for n = 1:1:length(amp_routing{1,m})
S21_time{m}(:,n) = amp_routing{1,m}(n)*exp(time_routing{1,m}(n)*t);
end
nexttile
plot(t*1e-9,real(sum(S21_time{m},2)));
grid on
title(title_name(m));
end
if(save == "save")
savefig("S21线路参数");
end
end
function FigDisplay(obj)
if(obj.rpt_num == 1)
for m = 1:obj.route_num*obj.env_num
figure(2*m-1)
figure(2*m)
pause(obj.pause_time);
end
else
for m = 1:obj.route_num*obj.env_num
figure(m)
pause(obj.pause_time);
end
end
end
function LoadFigAndDisplay(obj)
for n = 1:obj.route_num
for m = 1:obj.env_num
open(strcat(obj.name(n,m),'.fig'));
open(strcat(obj.name(n+5,m),'.fig'));
pause(obj.pause_time);
end
end
end
function ErrAny(obj,save)
fid = fopen(obj.filename,'r');
if(obj.rpt_num == 1)
data = textscan(fid,'Falling edge of 20ns~40ns mean :%s std :%s Falling edge of 1us~1.1us mean :%s std :%s The mean and std stably less than 1e-4 is :%s s');
fclose(fid);
data{1} = cellfun(@str2num,data{1});
data{2} = cellfun(@str2num,data{2});
data{3} = cellfun(@str2num,data{3});
data{4} = cellfun(@str2num,data{4});
data{5} = cellfun(@str2num,data{5});
title_name = ["下降沿后20ns~40ns误差的平均值","下降沿后20ns~40ns误差的标准差","下降沿后1us~1.1us误差的平均值","下降沿后1us~1.1us误差的标准差","加窗参数"];
err_threshold = [1e-3 1e-3 1e-4 3e-4 5e-6];
else
data = textscan(fid,'每个周期拖尾误差均值的标准差 = %s s');
fclose(fid);
data{1} = cellfun(@str2num,data{1});
title_name = ["多周期误差平均值的标准差"];
err_threshold = [0.5e-3];
end
[h,v] = size(data);
figure()
tiledlayout('flow','TileSpacing','tight')
colors = lines(obj.route_num);
set(gcf,'Position', [1 49 2560 1314]);
for m = 1:v
nexttile
hold on
for i = 1:(obj.route_num)
idx = (i-1)*(length(data{m})/obj.route_num) + 1 : i*(length(data{m})/obj.route_num);
plot(idx,abs(data{m}(idx)),'-o','Color', colors(i, :));
end
yline(err_threshold(m),'--r');
title(title_name(m));
set(gca,'YScale','log');
legend("第一组线路","第二组线路","第三组线路","第四组线路","第五组线路",'Location','northwest');
end
if(obj.rpt_num == 1)
if(save == "save")
savefig("单周期误差分析")
end
else
if(save == "save")
savefig("多周期误差分析")
end
end
end
%compare FIL with python script
function diff_plot_py(obj,fs,iir_out, Script_out,title1,title2,a,amp,edge,fileID)
%输入数据长度不等时取其公共部分
N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N);
Script_out = Script_out(1:N);
diff = (iir_out - Script_out)/amp;%求差，并归一化
n = (0:1:N-1)/fs;
%找出关心的数据点
if(obj.rpt_num == 1)
n_edge = find(n>=edge-1e-12);%edge代表下降沿
n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
ne(1) = 1;
window_length = 100e-9*fs;
diff_mean_window = movmean(diff,window_length);
diff_std_window = movstd(diff,window_length);
n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
n_common = max(n_mean_window(end),n_std_window(end));
%原始数据作图
tiledlayout(2,1)
ax1 = nexttile;
plot(n,iir_out,n,Script_out)
legend('硬件','软件');
xlabel('t/s')
xlim(a);
title(title1,Interpreter="none");
grid on
hold on
%差值做图
ax2 = nexttile;
plot(n,diff)
xlabel('t/s')
title('diff')
grid on
hold on
xlim(a)
title('硬件与脚本的差值',Interpreter="none");
linkaxes([ax1,ax2],'x');
plot_p = @(x)[
plot(n(x),diff(x),'r*');
text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
];
ne(1) = 1;
% [diff_max,R_mpos] = max(abs(diff));%误差最大值
% plot_p(R_mpos);
if a(2) <= 5e-6
plot_p(n_edge(1));%下降沿
% plot_p(R_mpos);
elseif a(2) == 20e-6
plot_p(n50(1)); %下降沿20ns
plot_p(n1000(1)); %下降沿1us
plot_p(ne(end)); %误差小于万分之一
fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100)));
% fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
% fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
end
else
n_start = find(n>=edge-1e-12);%edge代表下降沿
% 确定周期长度对应的采样点数量
T = a; %在这种情况下，a这个参数用不到了，使用其传递周期，也就是说a这个参数有两种不同的涵义
samples_per_period = round(T * fs); % 每个周期采样点数
num_periods = obj.rpt_num; % 总周期数
period_means = zeros(1, num_periods); % 存储每周期均值
for i = 1:num_periods
% 提取当前周期的起止索引
start_idx(i) = n_start(1) + (i - 1) * samples_per_period;
end_idx(i) = n_start(1) + i * samples_per_period;
% 提取当前周期的数据
period_data = diff(start_idx(i):end_idx(i));
% 计算当前周期的均值
period_means(i) = mean(period_data);
end
fprintf(fileID,"每个周期拖尾误差均值的标准差 = %.4e s\n",std(period_means));
ax1 = nexttile;
plot(n,iir_out,n,Script_out);
hold on
plot(n(start_idx), Script_out(start_idx), 'r*'); % 标记每个周期的起始点
plot(n(end_idx), Script_out(end_idx), 'g*'); % 标记每个周期的起始点
legend('硬件','软件');
xlabel('t/s');
title(title1,Interpreter="none");
ax2 = nexttile;
hold on
plot(n, diff); hold on; % 原始信号
plot(n(end_idx), diff(end_idx), 'g*'); % 标记每个周期的起始点
xlabel('t/s');
ylabel('归一化误差');
linkaxes([ax1,ax2],'x');
xlim([0,n(end_idx(end)) + 5e-7]);
title(title2,Interpreter="none");
end
end
end
end

66
script_m/z_dsp_top.m
View File

@ -1,66 +0,0 @@
clc;clear;close all
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
fs_L = 0.75e9; %硬件频率
fs_H = 12e9; %以高频近似理想信号
TargetFrequency = 3e9;
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
route_num = 1; %线路个数
env_num = 1; %包络个数
alpha_wideth=32; %滤波器系数定点化
beta_width=32;
G = 1;
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
z_dsp1 = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel);
z_dsp1.filename = 'output.txt';
z_dsp1.rpt_num = 1;
if(z_dsp1.rpt_num > 1)
z_dsp1.name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第一组S21参数_acz_持续时间30ns_重复100次",...
"第一组S21参数_acz_持续时间50ns_重复100次";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第二组S21参数_acz_持续时间30ns_重复100次",...
"第二组S21参数_acz_持续时间50ns_重复100次";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第三组S21参数_acz_持续时间30ns_重复100次",...
"第三组S21参数_acz_持续时间50ns_重复100次";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第四组S21参数_acz_持续时间30ns_重复100次",...
"第四组S21参数_acz_持续时间50ns_重复100次";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第五组S21参数_acz_持续时间30ns_重复100次",...
"第五组S21参数_acz_持续时间50ns_重复100次";
];
z_dsp1.FallingEdge = [30e-9 30e-9 50e-9 30e-9 50e-9];
z_dsp1.itv_time = 30e-9;
end
z_dsp1.env(); %产生理想z信号
z_dsp1.route(); %配置线路参数
% z_dsp1.route_num = 1;
% z_dsp1.env_num = 1;
z_dsp1.py_cal(); %12G采样率，基于python脚本计算校正后的波形
z_dsp1.FIL(); %调用FIL模块计算校正后的波形
z_dsp1.DataShow("save"); %计算结束后展示波形，有save时保存图片
%%
z_dsp1.FigDisplay(); %图片播放
%%
z_dsp1.RouteShow("save"); %可视化线路参数
%%
z_dsp1.ErrAny("save") %对关心的指标进行可视化处理
%%
close all
z_dsp1.pause_time = 0.3;
z_dsp1.LoadFigAndDisplay()

0
sim/Makefile → sim/TailCorr_en/Makefile
View File

14
sim/TailCorr_en/files.f Normal file
View File

@ -0,0 +1,14 @@
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_TailCorr_en.v

187
sim/tb_TailCorr_en.v → sim/TailCorr_en/tb_TailCorr_en.v
View File

@ -1,36 +1,4 @@
module TB(); module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode; reg [1 :0] source_mode;
@ -436,7 +404,7 @@ assign dac_mode_sel = 2'b00;
wire tc_bypass; wire tc_bypass;
wire vldo; wire vldo;
wire vldo_ref; //wire vldo_ref;
assign tc_bypass = 1'b0; assign tc_bypass = 1'b0;
@ -450,7 +418,6 @@ always @(posedge clk or negedge rstn)begin
end end
end end
wire signed [15:0] dout_p[7:0]; wire signed [15:0] dout_p[7:0];
wire signed [15:0] dout_ref_p[7:0];
TailCorr_top inst_TailCorr_top TailCorr_top inst_TailCorr_top
@ -598,152 +565,6 @@ TailCorr_top inst_TailCorr_top
); );
TailCorr_top_ref refm_TailCorr_top
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.vldi (vldi_matlab[0] ),
// .dac_mode_sel (dac_mode_sel ),
// .intp_mode (intp_mode ),
.din0 (iir_in[0]),
.din1 (iir_in[1]),
.din2 (iir_in[2]),
.din3 (iir_in[3]),
.a_re0 (a_re0),
.a_im0 (a_im0),
//.b_re0 (b_re0),
//.b_im0 (b_im0),
.ab_re0 (ab_re0),
.ab_im0 (ab_im0),
.abb_re0 (abb_re0),
.abb_im0 (abb_im0),
.ab_pow3_re0 (ab_pow3_re0),
.ab_pow3_im0 (ab_pow3_im0),
.ab_pow4_re0 (ab_pow4_re0),
.ab_pow4_im0 (ab_pow4_im0),
.ab_pow5_re0 (ab_pow5_re0),
.ab_pow5_im0 (ab_pow5_im0),
.ab_pow6_re0 (ab_pow6_re0),
.ab_pow6_im0 (ab_pow6_im0),
.ab_pow7_re0 (ab_pow7_re0),
.ab_pow7_im0 (ab_pow7_im0),
.b_pow8_re0 (b_pow8_re0),
.b_pow8_im0 (b_pow8_im0),
.a_re1 (a_re1),
.a_im1 (a_im1),
//.b_re1 (b_re1),
//.b_im1 (b_im1),
.ab_re1 (ab_re1),
.ab_im1 (ab_im1),
.abb_re1 (abb_re1),
.abb_im1 (abb_im1),
.ab_pow3_re1 (ab_pow3_re1),
.ab_pow3_im1 (ab_pow3_im1),
.ab_pow4_re1 (ab_pow4_re1),
.ab_pow4_im1 (ab_pow4_im1),
.ab_pow5_re1 (ab_pow5_re1),
.ab_pow5_im1 (ab_pow5_im1),
.ab_pow6_re1 (ab_pow6_re1),
.ab_pow6_im1 (ab_pow6_im1),
.ab_pow7_re1 (ab_pow7_re1),
.ab_pow7_im1 (ab_pow7_im1),
.b_pow8_re1 (b_pow8_re1),
.b_pow8_im1 (b_pow8_im1),
.a_re2 (a_re2),
.a_im2 (a_im2),
//.b_re2 (b_re2),
//.b_im2 (b_im2),
.ab_re2 (ab_re2),
.ab_im2 (ab_im2),
.abb_re2 (abb_re2),
.abb_im2 (abb_im2),
.ab_pow3_re2 (ab_pow3_re2),
.ab_pow3_im2 (ab_pow3_im2),
.ab_pow4_re2 (ab_pow4_re2),
.ab_pow4_im2 (ab_pow4_im2),
.ab_pow5_re2 (ab_pow5_re2),
.ab_pow5_im2 (ab_pow5_im2),
.ab_pow6_re2 (ab_pow6_re2),
.ab_pow6_im2 (ab_pow6_im2),
.ab_pow7_re2 (ab_pow7_re2),
.ab_pow7_im2 (ab_pow7_im2),
.b_pow8_re2 (b_pow8_re2),
.b_pow8_im2 (b_pow8_im2),
.a_re3 (a_re3),
.a_im3 (a_im3),
//.b_re3 (b_re3),
//.b_im3 (b_im3),
.ab_re3 (ab_re3),
.ab_im3 (ab_im3),
.abb_re3 (abb_re3),
.abb_im3 (abb_im3),
.ab_pow3_re3 (ab_pow3_re3),
.ab_pow3_im3 (ab_pow3_im3),
.ab_pow4_re3 (ab_pow4_re3),
.ab_pow4_im3 (ab_pow4_im3),
.ab_pow5_re3 (ab_pow5_re3),
.ab_pow5_im3 (ab_pow5_im3),
.ab_pow6_re3 (ab_pow6_re3),
.ab_pow6_im3 (ab_pow6_im3),
.ab_pow7_re3 (ab_pow7_re3),
.ab_pow7_im3 (ab_pow7_im3),
.b_pow8_re3 (b_pow8_re3),
.b_pow8_im3 (b_pow8_im3),
.a_re4 (a_re4),
.a_im4 (a_im4),
//.b_re4 (b_re4),
//.b_im4 (b_im4),
.ab_re4 (ab_re4),
.ab_im4 (ab_im4),
.abb_re4 (abb_re4),
.abb_im4 (abb_im4),
.ab_pow3_re4 (ab_pow3_re4),
.ab_pow3_im4 (ab_pow3_im4),
.ab_pow4_re4 (ab_pow4_re4),
.ab_pow4_im4 (ab_pow4_im4),
.ab_pow5_re4 (ab_pow5_re4),
.ab_pow5_im4 (ab_pow5_im4),
.ab_pow6_re4 (ab_pow6_re4),
.ab_pow6_im4 (ab_pow6_im4),
.ab_pow7_re4 (ab_pow7_re4),
.ab_pow7_im4 (ab_pow7_im4),
.b_pow8_re4 (b_pow8_re4),
.b_pow8_im4 (b_pow8_im4),
.a_re5 (a_re5),
.a_im5 (a_im5),
//.b_re5 (b_re5),
//.b_im5 (b_im5),
.ab_re5 (ab_re5),
.ab_im5 (ab_im5),
.abb_re5 (abb_re5),
.abb_im5 (abb_im5),
.ab_pow3_re5 (ab_pow3_re5),
.ab_pow3_im5 (ab_pow3_im5),
.ab_pow4_re5 (ab_pow4_re5),
.ab_pow4_im5 (ab_pow4_im5),
.ab_pow5_re5 (ab_pow5_re5),
.ab_pow5_im5 (ab_pow5_im5),
.ab_pow6_re5 (ab_pow6_re5),
.ab_pow6_im5 (ab_pow6_im5),
.ab_pow7_re5 (ab_pow7_re5),
.ab_pow7_im5 (ab_pow7_im5),
.b_pow8_re5 (b_pow8_re5),
.b_pow8_im5 (b_pow8_im5),
.dout_p0 (dout_ref_p[0] ),
.dout_p1 (dout_ref_p[1] ),
.dout_p2 (dout_ref_p[2] ),
.dout_p3 (dout_ref_p[3] ),
.dout_p4 (dout_ref_p[4] ),
.dout_p5 (dout_ref_p[5] ),
.dout_p6 (dout_ref_p[6] ),
.dout_p7 (dout_ref_p[7] ),
.vldo (vldo_ref )
);
integer signed In_fid[0:3]; integer signed In_fid[0:3];
integer signed dout_fid[0:7]; integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
@ -764,9 +585,6 @@ always @(posedge clk) begin
for (int i = 0; i < 4; i = i + 1) begin for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); $fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(In_fid[i]);
// end
end end
end end
@ -775,9 +593,6 @@ always @(posedge clk) begin
for (int i = 0; i < 8; i = i + 1) begin for (int i = 0; i < 8; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(dout_fid[i]);
// end
end end
end end
endmodule endmodule

21
sim/files.f
View File

@ -1,21 +0,0 @@
../rtl/z_dsp/mult_C.v
../rtl/z_dsp/mult_x.v
../rtl/z_dsp/Trunc.v
../rtl/z_dsp/TailCorr_top.v
../rtl/z_dsp/IIR_top.v
../rtl/z_dsp/diff_p.v
../rtl/z_dsp/s2p_2.v
../rtl/z_dsp/IIR_Filter_p8.v
../rtl/z_dsp/IIR_Filter_p1.v
../rtl/z_dsp/sirv_gnrl_dffs.v
../rtl/ref/mult_C.v
../rtl/ref/FixRound.v
../rtl/ref/TailCorr_top.v
../rtl/ref/IIR_top.v
../rtl/ref/diff_p.v
../rtl/ref/s2p_2.v
../rtl/ref/IIR_Filter_p8.v
../rtl/model/DW02_mult.v
tb_TailCorr_en.v

17
sim/s2p_2/Makefile Normal file
View File

@ -0,0 +1,17 @@
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

3
sim/s2p_2/files.f Normal file
View File

@ -0,0 +1,3 @@
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
tb_s2p_2.v

131
sim/s2p_2/tb_s2p_2.v Normal file
View File

@ -0,0 +1,131 @@
`timescale 1ns/1ps
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rst_n;
reg [15:0] din;
reg enable;
reg vldo;
reg [21:0] cnt;
wire [15:0] dout0;
wire [15:0] dout1;
s2p_2 u_s2p_2(
.clk ( clk ),
.rst_n ( rst_n ),
.din ( din ),
.en ( enable ),
.dout0 ( dout0 ),
.dout1 ( dout1 ),
.vldo ( vldo )
);
reg[15:0] din_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
din_r1 <= 0;
end
else begin
din_r1 <= din;
end
end
wire signed [15:0] diff;
assign diff = din - din_r1;
reg[15:0] dout1_r1;
reg[15:0] dout1_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout1_r1 <= 0;
dout1_r2 <= 0;
end
else begin
dout1_r1 <= dout1;
dout1_r2 <= dout1_r1;
end
end
wire signed [15:0] diff12;
wire signed [15:0] diff23;
assign diff12 = dout0 - dout1_r2;
assign diff23 = dout1 - dout0;
initial begin
rst_n = 0;
enable = 0;
clk = 1'b0;
din = 16'h0000;
#20;
rst_n = 1;
#10;
end
always #5 clk = ~clk;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
cnt <= 22'd0;
end else begin
cnt <= cnt + 22'd1;
end
end
reg [15:0] enable_cnt;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
enable <= 0;
din <= 16'd0;
enable_cnt <= 0;
end else begin
if (cnt < 1000) begin
if (enable_cnt == 0) begin
if ($urandom % 2 == 0) begin
enable <= 1;
enable_cnt <= $urandom % 10 + 5;
din <= $urandom;
end else begin
enable <= 0;
din <= 16'd0;
end
end else begin
enable <= 1;
enable_cnt <= enable_cnt - 1;
din <= $urandom;
end
end else begin
enable <= 0;
din <= 16'd0;
end
end
end
initial begin
wait(cnt[11] == 1);
$finish;
end
endmodule

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ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

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../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_CoefGen.v

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`timescale 1 ns/1 ns
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
end
reg clk ;
reg en;
reg [5:0] vldi;
reg rst_n;
reg signed [31:0] a_re [5:0];
reg signed [31:0] a_im [5:0];
reg signed [31:0] b_re [5:0];
reg signed [31:0] b_im [5:0];
wire signed [31:0] ao_re [5:0];
wire signed [31:0] ao_im [5:0];
wire signed [31:0] ab_re [5:0];
wire signed [31:0] ab_im [5:0];
wire signed [31:0] abb_re [5:0];
wire signed [31:0] abb_im [5:0];
wire signed [31:0] ab_pow3_re [5:0];
wire signed [31:0] ab_pow3_im [5:0];
wire signed [31:0] ab_pow4_re [5:0];
wire signed [31:0] ab_pow4_im [5:0];
wire signed [31:0] ab_pow5_re [5:0];
wire signed [31:0] ab_pow5_im [5:0];
wire signed [31:0] ab_pow6_re [5:0];
wire signed [31:0] ab_pow6_im [5:0];
wire signed [31:0] ab_pow7_re [5:0];
wire signed [31:0] ab_pow7_im [5:0];
wire signed [31:0] bo_re [5:0];
wire signed [31:0] bo_im [5:0];
wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0];
parameter CYCLE = 20;
parameter RST_TIME = 3 ;
CoefGen inst_CoefGen(
.clk (clk ),
.rstn (rst_n ),
.vldi (vldi ),
.a0_re (a_re[0] ),
.a0_im (a_im[0] ),
.b0_re (b_re[0] ),
.b0_im (b_im[0] ),
.a1_re (a_re[1] ),
.a1_im (a_im[1] ),
.b1_re (b_re[1] ),
.b1_im (b_im[1] ),
.a2_re (a_re[2] ),
.a2_im (a_im[2] ),
.b2_re (b_re[2] ),
.b2_im (b_im[2] ),
.a3_re (a_re[3] ),
.a3_im (a_im[3] ),
.b3_re (b_re[3] ),
.b3_im (b_im[3] ),
.a4_re (a_re[4] ),
.a4_im (a_im[4] ),
.b4_re (b_re[4] ),
.b4_im (b_im[4] ),
.a5_re (a_re[5] ),
.a5_im (a_im[5] ),
.b5_re (b_re[5] ),
.b5_im (b_im[5] ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] )
);
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg [15:0] st1;
reg [15:0] st2;
reg [15:0] st3;
reg [15:0] st4;
initial begin
rst_n = 0;
vldi <= 0;
st1 = 100;
st2 = 101;
st3 = 110;
st4 = 111;
repeat(3) @(posedge clk);
vldi[0] <= 1;
rst_n = 1;
a_re[0] <= 55007237;
a_im[0] <= 0;
b_re[0] <= 2143083068;
b_im[0] <= 0;
@(posedge clk);
vldi[0] <= 0;
a_re[0] <= 0;
a_im[0] <= 0;
b_re[0] <= 0;
b_im[0] <= 0;
repeat(8) @(posedge clk);
vldi[1] <= 1;
rst_n = 1;
a_re[1] <= 32690030;
a_im[1] <= 0;
b_re[1] <= 2145807236;
b_im[1] <= 0;
@(posedge clk);
vldi[1] <= 0;
a_re[1] <= 0;
a_im[1] <= 0;
b_re[1] <= 0;
b_im[1] <= 0;
repeat(8) @(posedge clk);
vldi[2] <= 1;
rst_n = 1;
a_re[2] <= 429516;
a_im[2] <= 0;
b_re[2] <= 2146812530;
b_im[2] <= 0;
@(posedge clk);
vldi[2] <= 0;
a_re[2] <= 0;
a_im[2] <= 0;
b_re[2] <= 0;
b_im[2] <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
cnt <= 22'd0;
end
else begin
cnt <= cnt + 22'd1;
end
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
endmodule

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ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

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+incdir+./../../rtl/define
../../rtl/z_dsp/z_dsp.v
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/IIR_Filter_p16.v
../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_real.v
../../rtl/z_dsp/syncer.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_z_dsp.v

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`define SYNTHESIS
`timescale 1 ns/1 ns
module TB #(parameter COMPLEX = 1)();
reg [1 :0] source_mode;
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
// $srandom(417492050);
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end
reg rstn;
reg [15:0] din_rect;
reg [ 3:0] vldi_coef;
reg vldi_data;
parameter CYCLE = 20;
reg clk;
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg en;
reg signed [31:0] a_re [3:0];
reg signed [31:0] b_re [3:0];
`ifdef COMPLEX
reg signed [31:0] a_im [3:0];
reg signed [31:0] b_im [3:0];
`endif
initial begin
rstn = 0;
vldi_data <= 0;
vldi_coef <= 0;
din_rect = 16'd0;
a_re[0] <= 0;
b_re[0] <= 0;
a_re[1] <= 0;
b_re[1] <= 0;
a_re[2] <= 0;
b_re[2] <= 0;
a_re[3] <= 0;
b_re[3] <= 0;
`ifdef COMPLEX
a_im[0] <= 0;
b_im[0] <= 0;
a_im[1] <= 0;
b_im[1] <= 0;
a_im[2] <= 0;
b_im[2] <= 0;
a_im[3] <= 0;
b_im[3] <= 0;
`endif
en <= 0;
repeat(3) @(posedge clk);
vldi_coef[0] <= 1;
rstn = 1;
en <= 1;
a_re[0] <= 55007237;
b_re[0] <= 2143083068;
@(posedge clk);
vldi_coef[0] <= 0;
a_re[0] <= 0;
b_re[0] <= 0;
repeat(16) @(posedge clk);
vldi_coef[1] <= 1;
rstn = 1;
a_re[1] <= 32690030;
b_re[1] <= 2145807236;
@(posedge clk);
vldi_coef[1] <= 0;
a_re[1] <= 0;
b_re[1] <= 0;
repeat(16) @(posedge clk);
vldi_coef[2] <= 1;
rstn = 1;
a_re[2] <= 429516;
b_re[2] <= 2146812530;
@(posedge clk);
vldi_coef[2] <= 0;
a_re[2] <= 0;
b_re[2] <= 0;
repeat(108) @(posedge clk);
vldi_data <= 1;
// repeat(10000) @(posedge clk);
// vldi_data <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
reg vldi_data_r1;
always@(posedge clk or negedge rstn)
if(!rstn)
vldi_data_r1 <= 1'b0;
else
begin
vldi_data_r1 <= vldi_data;
end
always@(posedge clk or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(vldi_data)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
reg signed [15:0] random_in [0:15];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 16; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
else if (vldi_data) begin
for (int i = 0; i < 16; i = i + 1) begin
random_in[i] <= $urandom % 30000;
end
end
else begin
for (int i = 0; i < 16; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
end
integer file[15:0];
reg [15:0] data[15:0];
integer status[15:0];
reg [15:0] reg_array[15:0];
string filenames[15:0];
initial begin
if(source_mode == 3) begin
// string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
for (int i = 0; i < 16; i++) begin
$sformat(filenames[i], "in%0d_matlab.dat", i);
end
for (int i = 0; i < 16; i = i + 1) begin
file[i] = $fopen(filenames[i], "r");
if (file[i] == 0) begin
$display("Failed to open file: %s", filenames[i]);
$finish;
end
end
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 16; i = i + 1) begin
reg_array[i] <= 16'd0;
end
end else if(vldi_data && source_mode == 3) begin
for (int i = 0; i < 16; i = i + 1) begin
status[i] = $fscanf(file[i], "%d\n", data[i]);
if (status[i] == 1 ) begin
reg_array[i] <= data[i];
end
else begin
reg_array[i] <= 16'd0;
vldi_data <= 0;
end
end
end
end
reg signed [15:0] iir_in[15:0];
always @(*)
case(source_mode)
2'b01 : begin
for (int i = 0; i < 16; i = i + 1) begin
iir_in[i] = din_rect;
end
end
2'b10 : begin
for (int i = 0; i < 16; i = i + 1) begin
iir_in[i] = random_in[i];
end
end
2'b11 : begin
for (int i = 0; i < 16; i = i + 1) begin
iir_in[i] = reg_array[i];
end
end
endcase
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0;
//always @(posedge clk or negedge rstn)begin
// if(rstn==1'b0)begin
// en <= 1;
// end
// else begin
// en <= ~en;
// end
//end
wire signed [15:0] dout_p[15:0];
z_dsp u_z_dsp(
.rstn ( rstn ),
.clk ( clk ),
.en ( en ),
.vldi_coef ( vldi_coef ),
.vldi_data ( vldi_data && vldi_data_r1 ),
.din0 ( iir_in[0] ),
.din1 ( iir_in[1] ),
.din2 ( iir_in[2] ),
.din3 ( iir_in[3] ),
.din4 ( iir_in[4] ),
.din5 ( iir_in[5] ),
.din6 ( iir_in[6] ),
.din7 ( iir_in[7] ),
.din8 ( iir_in[8] ),
.din9 ( iir_in[9] ),
.dina ( iir_in[10] ),
.dinb ( iir_in[11] ),
.dinc ( iir_in[12] ),
.dind ( iir_in[13] ),
.dine ( iir_in[14] ),
.dinf ( iir_in[15] ),
.a0_re ( a_re[0] ),
.b0_re ( b_re[0] ),
.a1_re ( a_re[1] ),
.b1_re ( b_re[1] ),
.a2_re ( a_re[2] ),
.b2_re ( b_re[2] ),
.a3_re ( a_re[3] ),
.b3_re ( b_re[3] ),
`ifdef COMPLEX
.a0_im ( a_im[0] ),
.b0_im ( b_im[0] ),
.a1_im ( a_im[1] ),
.b1_im ( b_im[1] ),
.a2_im ( a_im[2] ),
.b2_im ( b_im[2] ),
.a3_im ( a_im[3] ),
.b3_im ( b_im[3] ),
`endif
.dout0 ( dout_p[0] ),
.dout1 ( dout_p[1] ),
.dout2 ( dout_p[2] ),
.dout3 ( dout_p[3] ),
.dout4 ( dout_p[4] ),
.dout5 ( dout_p[5] ),
.dout6 ( dout_p[6] ),
.dout7 ( dout_p[7] ),
.dout8 ( dout_p[8] ),
.dout9 ( dout_p[9] ),
.douta ( dout_p[10] ),
.doutb ( dout_p[11] ),
.doutc ( dout_p[12] ),
.doutd ( dout_p[13] ),
.doute ( dout_p[14] ),
.doutf ( dout_p[15] ),
.vldo ( vldo )
);
//integer signed In_fid[0:3];
integer signed dout_fid[0:15];
//string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:15] = {
"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat",
"dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat",
"dout8.dat", "dout9.dat", "dout10.dat", "dout11.dat",
"dout12.dat", "dout13.dat", "dout14.dat", "dout15.dat"
};
initial begin
#0;
// for (int i = 0; i < 4; i = i + 1) begin
// In_fid[i] = $fopen(filenames_in[i]);
// end
for (int i = 0; i < 16; i = i + 1) begin
dout_fid[i] = $fopen(filenames_dout[i]);
end
end
//always @(posedge clk) begin
// if (vldi_data_r1) begin
// for (int i = 0; i < 4; i = i + 1) begin
// $fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
// end
// end
//end
always @(posedge clk) begin
if (vldo) begin
for (int i = 0; i < 16; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
end
end
endmodule