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eba7fac84d
...
6e386a2743
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@ -71,6 +71,7 @@ assign ab_pow_im[2] = abb_im;
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assign ab_pow_im[1] = ab_im;
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assign ab_pow_im[0] = a_im;
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wire signed [temp_var_width-1 :0] x_re [0:7];
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wire signed [temp_var_width-1 :0] x_im [0:7];
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@ -1,5 +1,4 @@
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module IIR_top #(
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parameter data_out_width = 23
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,parameter temp_var_width = data_out_width + 14
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@ -1,5 +1,4 @@
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module TailCorr_top #(
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parameter temp_var_width = 22
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)
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@ -176,7 +175,6 @@ wire signed [temp_var_width+2:0] sum_IIRout_p4;
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wire signed [temp_var_width+2:0] sum_IIRout_p5;
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wire signed [temp_var_width+2:0] sum_IIRout_p6;
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wire signed [temp_var_width+2:0] sum_IIRout_p7;
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reg signed [15:0] din_p0_r [16:0];
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reg signed [15:0] din_p1_r [16:0];
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reg signed [15:0] din_p2_r [16:0];
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@ -185,7 +183,6 @@ reg signed [15:0] din_p4_r [16:0];
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reg signed [15:0] din_p5_r [16:0];
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reg signed [15:0] din_p6_r [16:0];
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reg signed [15:0] din_p7_r [16:0];
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reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7)
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reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22)
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reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37)
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@ -273,7 +270,6 @@ always @(posedge clk or negedge rstn) begin
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end
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end
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end
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/*
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wire signed [15:0] din_p0_r1;
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wire signed [15:0] din_p1_r1;
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@ -1,5 +1,4 @@
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module diff_p
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(
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@ -123,90 +122,38 @@ if(rstn==1'b0)begin
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diff_p5_r1 <= 0;
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diff_p6_r1 <= 0;
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diff_p7_r1 <= 0;
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end
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else if(en)begin
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diff_p0_r1 <= din_p0_r0 - din_p7_r1;
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diff_p1_r1 <= din_p1_r0 - din_p0_r0;
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diff_p2_r1 <= din_p2_r0 - din_p1_r0;
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diff_p3_r1 <= din_p3_r0 - din_p2_r0;
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diff_p4_r1 <= din_p4_r0 - din_p3_r0;
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diff_p5_r1 <= din_p5_r0 - din_p4_r0;
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diff_p6_r1 <= din_p6_r0 - din_p5_r0;
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diff_p7_r1 <= din_p7_r0 - din_p6_r0;
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end
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else begin
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diff_p0_r1 <= diff_p0_r1;
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diff_p1_r1 <= diff_p1_r1;
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diff_p2_r1 <= diff_p2_r1;
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diff_p3_r1 <= diff_p3_r1;
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diff_p4_r1 <= diff_p4_r1;
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diff_p5_r1 <= diff_p5_r1;
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diff_p6_r1 <= diff_p6_r1;
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diff_p7_r1 <= diff_p7_r1;
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end
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end
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wire [15:0] din_wire [0:3];
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assign din_wire[0] = din0;
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assign din_wire[1] = din1;
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assign din_wire[2] = din2;
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assign din_wire[3] = din3;
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wire [3:0] vldo_temp;
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wire signed [15:0] dinp_r0 [7:0];
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin: s2p_inst
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s2p_2 inst_s2p_2 (
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.clk (clk),
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.rst_n (rstn),
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.din (din_wire[i]),
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.en (vldi),
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.dout0 (dinp_r0[i]),
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.dout1 (dinp_r0[i+4]),
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.vldo (vldo_temp[i])
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);
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end
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endgenerate
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assign vldo = vldo_temp[0];
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reg signed [15:0] dinp_r1 [0:7];
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integer j;
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (j = 0; j < 8; j = j + 1) begin
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dinp_r1[j] <= 'h0;
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end
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end
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else if (en) begin
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for (j = 0; j < 8; j = j + 1) begin
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dinp_r1[j] <= dinp_r0[j];
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end
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end
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end
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wire signed [15:0] diffp_r0 [0:7];
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generate
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for (i = 0; i < 8; i = i + 1) begin: diff_assign
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if (i == 0)
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assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
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else
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assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
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end
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endgenerate
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assign dout_p0 = dinp_r1[0];
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assign dout_p1 = dinp_r1[1];
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assign dout_p2 = dinp_r1[2];
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assign dout_p3 = dinp_r1[3];
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assign dout_p4 = dinp_r1[4];
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assign dout_p5 = dinp_r1[5];
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assign dout_p6 = dinp_r1[6];
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assign dout_p7 = dinp_r1[7];
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reg signed [15:0] diffp_r1 [0:7];
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (j = 0; j < 8; j = j + 1) begin
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diffp_r1[j] <= 0;
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end
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end
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else if (en) begin
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for (j = 0; j < 8; j = j + 1) begin
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diffp_r1[j] <= diffp_r0[j];
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end
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end
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end
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assign diff_p0 = diffp_r1[0];
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assign diff_p1 = diffp_r1[1];
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assign diff_p2 = diffp_r1[2];
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assign diff_p3 = diffp_r1[3];
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assign diff_p4 = diffp_r1[4];
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assign diff_p5 = diffp_r1[5];
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assign diff_p6 = diffp_r1[6];
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assign diff_p7 = diffp_r1[7];
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assign diff_p0 = diff_p0_r1;
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assign diff_p1 = diff_p1_r1;
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assign diff_p2 = diff_p2_r1;
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assign diff_p3 = diff_p3_r1;
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assign diff_p4 = diff_p4_r1;
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assign diff_p5 = diff_p5_r1;
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assign diff_p6 = diff_p6_r1;
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assign diff_p7 = diff_p7_r1;
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endmodule
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@ -0,0 +1,326 @@
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/*
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Copyright 2018-2020 Nuclei System Technology, Inc.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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//=====================================================================
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//
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// Designer : Bob Hu
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//
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// Description:
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// All of the general DFF and Latch modules
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//
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// ====================================================================
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//
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//
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable and Reset
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// Default reset value is 1
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//
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// ===========================================================================
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`define DISABLE_SV_ASSERTION
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`define dly #0.2
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module sirv_gnrl_dfflrs # (
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parameter DW = 32
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) (
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFLRS_PROC
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if (rst_n == 1'b0)
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qout_r <= {DW{1'b1}};
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else if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable and Reset
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// Default reset value is 0
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//
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// ===========================================================================
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module sirv_gnrl_dfflr # (
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parameter DW = 32
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) (
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFLR_PROC
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if (rst_n == 1'b0)
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qout_r <= {DW{1'b0}};
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else if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable and Reset
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// Default reset value is input
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//
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// ===========================================================================
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module sirv_gnrl_dfflrd # (
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parameter DW = 32
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) (
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input [DW-1:0] init,
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFLR_PROC
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if (rst_n == 1'b0)
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qout_r <= init;
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else if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable, no reset
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//
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// ===========================================================================
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module sirv_gnrl_dffl # (
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parameter DW = 32
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) (
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk)
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begin : DFFL_PROC
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if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
|
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
|
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`endif//}
|
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|
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|
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endmodule
|
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// ===========================================================================
|
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//
|
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// Description:
|
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// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
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// Default reset value is 1
|
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//
|
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// ===========================================================================
|
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module sirv_gnrl_dffrs # (
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parameter DW = 32
|
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) (
|
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input [DW-1:0] dnxt,
|
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output [DW-1:0] qout,
|
||||
|
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input clk,
|
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input rst_n
|
||||
);
|
||||
|
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reg [DW-1:0] qout_r;
|
||||
|
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always @(posedge clk or negedge rst_n)
|
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begin : DFFRS_PROC
|
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if (rst_n == 1'b0)
|
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qout_r <= {DW{1'b1}};
|
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else
|
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qout_r <= `dly dnxt;
|
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end
|
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|
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assign qout = qout_r;
|
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|
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endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffr # (
|
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parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for general latch
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_ltch # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
//input test_mode,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @ *
|
||||
begin : LTCH_PROC
|
||||
if (lden == 1'b1)
|
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qout_r <= dnxt;
|
||||
end
|
||||
|
||||
//assign qout = test_mode ? dnxt : qout_r;
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
always_comb
|
||||
begin
|
||||
CHECK_THE_X_VALUE:
|
||||
assert (lden !== 1'bx)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
end
|
||||
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
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