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14 Commits
cdea3f4d6a ... 28ac963708

Author SHA1 Message Date
futh0403 28ac963708 与基于IP核的IIR滤波器合并 2025-03-11 20:33:00 +08:00
thfu d126901a8a 将二维数组展开 2025-03-11 17:35:58 +08:00
thfu ad5c6434e2 片上实时产生系数； 
增加了z_dsp.sv;
删除了过去插值的相关文件，整理文件夹的结构；
FPGA消耗资源过多，端口使用二维数组；
提高了IIR_Filter_p8.v的可读性，未来需要进一步提高IIR_top.v的可读性，信号的互联是个问题；
 2025-03-11 17:31:24 +08:00
thfu 8c6c5bb906 八路并行的IIR滤波器； 
未来需要在片上实时生成系数；
需要提高代码可读性
 2025-03-11 16:28:33 +08:00
unknown d48f4fd872 原脚本太长，将其划分为不同功能模块以面向对象的编程方式进行封装管理 
目前已完成功能设计，但通过全局变量传参，未来需要维护；
包络的产生还不够灵活；
这里只是扫描线路参数和波形，但还没有支持对不同的采样率进行扫描

Signed-off-by: thfu
 2025-03-11 16:28:33 +08:00
unknown 418cbe0376 修改z_dsp.m相关函数以批量扫描线路参数和波形 
修改TailCorr_Test的名字便于区分Verdi平台用的脚本和Windows平台

Signed-off-by: unknown <2779155576@qq.com>
 2025-03-11 16:28:32 +08:00
thfu 98f6a41ec9 实现了两路并行的IIR滤波器；增加了将输入分为奇偶两路的模块 2025-03-11 16:28:32 +08:00
unknown bc06605912 .m增加了寻找误差和均方误差均小于万分之一的功能 
修改了z_dsp.m的路径
 2025-03-11 16:28:32 +08:00
thfu 8fe84d2a79 增加了四舍五入的模块，用于复数乘法器，八倍线性插值模块； 
修改了文件夹的结构；
增加了z_dsp.m add和diff_plot_py.m；

对valid信号进行修改；增加了z_dsp.m add和diff_plot_py.m
 2025-03-11 16:28:23 +08:00
thfu 821f1a4149 输出由八路375M转为4路750M；增加了输入输出的valid信号；使能二分频FIL验证 2025-03-11 16:26:08 +08:00
thfu d25f7e4439 参考IP核，将输入系数的位宽都改为32位；使用参数化的方法来控制 2025-03-11 16:26:08 +08:00
thfu 5f445faf9e 验证使能信号为时钟二分频的可能性，FIL验证； 
diff_plot.m选择二者最短的长度进行比较

使能信号二分频后.v文件需要做出一些对应的修改

diff_plot.m选择二者最短的长度进行比较

使能二分频FIL验证
 2025-03-11 16:25:21 +08:00
thfu c99d9baaea 内插模块增加了内插倍数选择模块； 
DAC接口做了对应的修改；
增加了matlab中的八倍内插模块，来验证rtl代码的准确性；
 2025-03-11 16:15:33 +08:00
unknown f67df5f554 增加了八倍内插模块； 
删除了一些重复的.v文件和临时文件，使文件夹更简洁，sim文件夹中只保留了makefile和filelist；
增加了matlab的验证代码，比较rtl代码和matlab代码的结果；

删除了一些重复的.v文件，使文件夹更简洁

删除了无用的临时文件

sim文件夹中只保留了makefile和filelist

增加了matlab的验证代码，比较rtl代码和matlab代码的结果
 2025-03-11 16:12:21 +08:00
29 changed files with 5572 additions and 785 deletions
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99
rtl/model/DW02_mult.v Normal file
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////////////////////////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used only
// as authorized by a licensing agreement from Synopsys Inc.
// In the event of publication, the following notice is applicable:
//
// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized
// copies.
//
// AUTHOR: KB WSFDB June 30, 1994
//
// VERSION: Simulation Architecture
//
// DesignWare_version: 714fe7a9
// DesignWare_release: O-2018.06-DWBB_201806.3
//
////////////////////////////////////////////////////////////////////////////////
//-----------------------------------------------------------------------------------
//
// ABSTRACT: Multiplier
// A_width-Bits * B_width-Bits => A_width+B_width Bits
// Operands A and B can be either both signed (two's complement) or
// both unsigned numbers. TC determines the coding of the input operands.
// ie. TC = '1' => signed multiplication
// TC = '0' => unsigned multiplication
//
// FIXED: by replacement with A tested working version
// that not only doesn't multiplies right it does it
// two times faster!
// RPH 07/17/2002
// Rewrote to comply with the new guidelines
//------------------------------------------------------------------------------
module DW02_mult(A,B,TC,PRODUCT);
parameter integer A_width = 8;
parameter integer B_width = 8;
input [A_width-1:0] A;
input [B_width-1:0] B;
input TC;
output [A_width+B_width-1:0] PRODUCT;
wire [A_width+B_width-1:0] PRODUCT;
wire [A_width-1:0] temp_a;
wire [B_width-1:0] temp_b;
wire [A_width+B_width-2:0] long_temp1,long_temp2;
//-------------------------------------------------------------------------
// Parameter legality check
//-------------------------------------------------------------------------
initial begin : parameter_check
integer param_err_flg;
param_err_flg = 0;
if (A_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)",
A_width );
end
if (B_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)",
B_width );
end
if ( param_err_flg == 1) begin
$display(
"%m :\n Simulation aborted due to invalid parameter value(s)");
$finish;
end
end // parameter_check
assign temp_a = (A[A_width-1])? (~A + 1'b1) : A;
assign temp_b = (B[B_width-1])? (~B + 1'b1) : B;
assign long_temp1 = temp_a * temp_b;
assign long_temp2 = ~(long_temp1 - 1'b1);
assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} :
(TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))?
{1'b1,long_temp2} : {1'b0,long_temp1})
: A * B;
endmodule

695
rtl/z_dsp/CoefGen.sv Normal file
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module CoefGen #(
parameter data_in_width = 32
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input [5:0] vldi
,input signed [31:0] a0_re
,input signed [31:0] a0_im
,input signed [31:0] b0_re
,input signed [31:0] b0_im
,input signed [31:0] a1_re
,input signed [31:0] a1_im
,input signed [31:0] b1_re
,input signed [31:0] b1_im
,input signed [31:0] a2_re
,input signed [31:0] a2_im
,input signed [31:0] b2_re
,input signed [31:0] b2_im
,input signed [31:0] a3_re
,input signed [31:0] a3_im
,input signed [31:0] b3_re
,input signed [31:0] b3_im
,input signed [31:0] a4_re
,input signed [31:0] a4_im
,input signed [31:0] b4_re
,input signed [31:0] b4_im
,input signed [31:0] a5_re
,input signed [31:0] a5_im
,input signed [31:0] b5_re
,input signed [31:0] b5_im
,output reg signed [31:0] a_re0
,output reg signed [31:0] a_im0
,output reg signed [31:0] ab_re0
,output reg signed [31:0] ab_im0
,output reg signed [31:0] abb_re0
,output reg signed [31:0] abb_im0
,output reg signed [31:0] ab_pow3_re0
,output reg signed [31:0] ab_pow3_im0
,output reg signed [31:0] ab_pow4_re0
,output reg signed [31:0] ab_pow4_im0
,output reg signed [31:0] ab_pow5_re0
,output reg signed [31:0] ab_pow5_im0
,output reg signed [31:0] ab_pow6_re0
,output reg signed [31:0] ab_pow6_im0
,output reg signed [31:0] ab_pow7_re0
,output reg signed [31:0] ab_pow7_im0
,output reg signed [31:0] b_pow8_re0
,output reg signed [31:0] b_pow8_im0
,output reg signed [31:0] a_re1
,output reg signed [31:0] a_im1
,output reg signed [31:0] ab_re1
,output reg signed [31:0] ab_im1
,output reg signed [31:0] abb_re1
,output reg signed [31:0] abb_im1
,output reg signed [31:0] ab_pow3_re1
,output reg signed [31:0] ab_pow3_im1
,output reg signed [31:0] ab_pow4_re1
,output reg signed [31:0] ab_pow4_im1
,output reg signed [31:0] ab_pow5_re1
,output reg signed [31:0] ab_pow5_im1
,output reg signed [31:0] ab_pow6_re1
,output reg signed [31:0] ab_pow6_im1
,output reg signed [31:0] ab_pow7_re1
,output reg signed [31:0] ab_pow7_im1
,output reg signed [31:0] b_pow8_re1
,output reg signed [31:0] b_pow8_im1
,output reg signed [31:0] a_re2
,output reg signed [31:0] a_im2
,output reg signed [31:0] ab_re2
,output reg signed [31:0] ab_im2
,output reg signed [31:0] abb_re2
,output reg signed [31:0] abb_im2
,output reg signed [31:0] ab_pow3_re2
,output reg signed [31:0] ab_pow3_im2
,output reg signed [31:0] ab_pow4_re2
,output reg signed [31:0] ab_pow4_im2
,output reg signed [31:0] ab_pow5_re2
,output reg signed [31:0] ab_pow5_im2
,output reg signed [31:0] ab_pow6_re2
,output reg signed [31:0] ab_pow6_im2
,output reg signed [31:0] ab_pow7_re2
,output reg signed [31:0] ab_pow7_im2
,output reg signed [31:0] b_pow8_re2
,output reg signed [31:0] b_pow8_im2
,output reg signed [31:0] a_re3
,output reg signed [31:0] a_im3
,output reg signed [31:0] ab_re3
,output reg signed [31:0] ab_im3
,output reg signed [31:0] abb_re3
,output reg signed [31:0] abb_im3
,output reg signed [31:0] ab_pow3_re3
,output reg signed [31:0] ab_pow3_im3
,output reg signed [31:0] ab_pow4_re3
,output reg signed [31:0] ab_pow4_im3
,output reg signed [31:0] ab_pow5_re3
,output reg signed [31:0] ab_pow5_im3
,output reg signed [31:0] ab_pow6_re3
,output reg signed [31:0] ab_pow6_im3
,output reg signed [31:0] ab_pow7_re3
,output reg signed [31:0] ab_pow7_im3
,output reg signed [31:0] b_pow8_re3
,output reg signed [31:0] b_pow8_im3
,output reg signed [31:0] a_re4
,output reg signed [31:0] a_im4
,output reg signed [31:0] ab_re4
,output reg signed [31:0] ab_im4
,output reg signed [31:0] abb_re4
,output reg signed [31:0] abb_im4
,output reg signed [31:0] ab_pow3_re4
,output reg signed [31:0] ab_pow3_im4
,output reg signed [31:0] ab_pow4_re4
,output reg signed [31:0] ab_pow4_im4
,output reg signed [31:0] ab_pow5_re4
,output reg signed [31:0] ab_pow5_im4
,output reg signed [31:0] ab_pow6_re4
,output reg signed [31:0] ab_pow6_im4
,output reg signed [31:0] ab_pow7_re4
,output reg signed [31:0] ab_pow7_im4
,output reg signed [31:0] b_pow8_re4
,output reg signed [31:0] b_pow8_im4
,output reg signed [31:0] a_re5
,output reg signed [31:0] a_im5
,output reg signed [31:0] ab_re5
,output reg signed [31:0] ab_im5
,output reg signed [31:0] abb_re5
,output reg signed [31:0] abb_im5
,output reg signed [31:0] ab_pow3_re5
,output reg signed [31:0] ab_pow3_im5
,output reg signed [31:0] ab_pow4_re5
,output reg signed [31:0] ab_pow4_im5
,output reg signed [31:0] ab_pow5_re5
,output reg signed [31:0] ab_pow5_im5
,output reg signed [31:0] ab_pow6_re5
,output reg signed [31:0] ab_pow6_im5
,output reg signed [31:0] ab_pow7_re5
,output reg signed [31:0] ab_pow7_im5
,output reg signed [31:0] b_pow8_re5
,output reg signed [31:0] b_pow8_im5
);
reg vldi_or_r1;
wire vldi_or = | vldi;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
vldi_or_r1 <= 'h0;
end
else begin
vldi_or_r1 <= vldi_or;
end
end
reg signed [data_in_width-1:0] a_re_r1;
reg signed [data_in_width-1:0] a_im_r1;
reg signed [data_in_width-1:0] b_re_r1;
reg signed [data_in_width-1:0] b_im_r1;
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
a_re_r1 <= 'h0;
a_im_r1 <= 'h0;
b_re_r1 <= 'h0;
b_im_r1 <= 'h0;
end
else if(|vldi) begin
case(1'b1)
vldi[0]: begin
a_re_r1 <= a0_re;
a_im_r1 <= a0_im;
b_re_r1 <= b0_re;
b_im_r1 <= b0_im;
end
vldi[1]: begin
a_re_r1 <= a1_re;
a_im_r1 <= a1_im;
b_re_r1 <= b1_re;
b_im_r1 <= b1_im;
end
vldi[2]: begin
a_re_r1 <= a2_re;
a_im_r1 <= a2_im;
b_re_r1 <= b2_re;
b_im_r1 <= b2_im;
end
vldi[3]: begin
a_re_r1 <= a3_re;
a_im_r1 <= a3_im;
b_re_r1 <= b3_re;
b_im_r1 <= b3_im;
end
vldi[4]: begin
a_re_r1 <= a4_re;
a_im_r1 <= a4_im;
b_re_r1 <= b4_re;
b_im_r1 <= b4_im;
end
vldi[5]: begin
a_re_r1 <= a5_re;
a_im_r1 <= a5_im;
b_re_r1 <= b5_re;
b_im_r1 <= b5_im;
end
// default: begin
// a_re_r1 <= a_re[0];
// a_im_r1 <= a_im[0];
// b_re_r1 <= b_re[0];
// b_im_r1 <= b_im[0];
// end
endcase
end
end
reg en;
reg en_r1;
reg [3:0] cnt0;
wire add_cnt0;
wire end_cnt0;
always @(posedge clk or negedge rstn)begin
if(!rstn)begin
cnt0 <= 0;
end
else if(add_cnt0)begin
if(end_cnt0)
cnt0 <= 0;
else
cnt0 <= cnt0 + 1;
end
end
assign add_cnt0 = en;
assign end_cnt0 = add_cnt0 && cnt0== 8-1;
wire en_l;
wire en_h;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else if(en_h)begin
en <= 1;
end
else if(en_l)begin
en <= 0;
end
end
assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
assign en_l = end_cnt0;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en_r1 <= 'h0;
end
else begin
en_r1 <= en;
end
end
reg signed [data_in_width-1:0] bin_re;
reg signed [data_in_width-1:0] bin_im;
wire signed [data_in_width-1:0] bout_re;
wire signed [data_in_width-1:0] bout_im;
always @(*)begin
if(en_r1) begin
bin_re <= bout_re;
bin_im <= bout_im;
end
else begin
bin_re <= 32'd2147483647;
bin_im <= 0;
end
end
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (b_re_r1 ),
.d (b_im_r1 ),
.Re (bout_re ),
.Im (bout_im )
);
wire signed [data_in_width-1:0] abo_re;
wire signed [data_in_width-1:0] abo_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (a_re_r1 ),
.d (a_im_r1 ),
.Re (abo_re ),
.Im (abo_im )
);
reg signed [coef_width-1 :0] ao_re_r1 ;
reg signed [coef_width-1 :0] ao_im_r1 ;
reg signed [coef_width-1 :0] ab_re_r1 ;
reg signed [coef_width-1 :0] ab_im_r1 ;
reg signed [coef_width-1 :0] abb_re_r1 ;
reg signed [coef_width-1 :0] abb_im_r1 ;
reg signed [coef_width-1 :0] ab_pow3_re_r1 ;
reg signed [coef_width-1 :0] ab_pow3_im_r1 ;
reg signed [coef_width-1 :0] ab_pow4_re_r1 ;
reg signed [coef_width-1 :0] ab_pow4_im_r1 ;
reg signed [coef_width-1 :0] ab_pow5_re_r1 ;
reg signed [coef_width-1 :0] ab_pow5_im_r1 ;
reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
reg signed [coef_width-1 :0] ab_pow6_im_r1 ;
reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
reg signed [coef_width-1 :0] ab_pow7_im_r1 ;
reg signed [coef_width-1 :0] b_pow8_re_r1 ;
reg signed [coef_width-1 :0] b_pow8_im_r1 ;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
ao_re_r1 <= 0;
ao_im_r1 <= 0;
ab_re_r1 <= 0;
ab_im_r1 <= 0;
abb_re_r1 <= 0;
abb_im_r1 <= 0;
ab_pow3_re_r1 <= 0;
ab_pow3_im_r1 <= 0;
ab_pow4_re_r1 <= 0;
ab_pow4_im_r1 <= 0;
ab_pow5_re_r1 <= 0;
ab_pow5_im_r1 <= 0;
ab_pow6_re_r1 <= 0;
ab_pow6_im_r1 <= 0;
ab_pow7_re_r1 <= 0;
ab_pow7_im_r1 <= 0;
b_pow8_re_r1 <= 0;
b_pow8_im_r1 <= 0;
end
else if(add_cnt0 && cnt0 == 1 && en_r1)begin
ao_re_r1 <= abo_re;
ao_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 2 && en_r1)begin
ab_re_r1 <= abo_re;
ab_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 3 && en_r1)begin
abb_re_r1 <= abo_re;
abb_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 4 && en_r1)begin
ab_pow3_re_r1 <= abo_re;
ab_pow3_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 5 && en_r1)begin
ab_pow4_re_r1 <= abo_re;
ab_pow4_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 6 && en_r1)begin
ab_pow5_re_r1 <= abo_re;
ab_pow5_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 7 && en_r1)begin
ab_pow6_re_r1 <= abo_re;
ab_pow6_im_r1 <= abo_im;
end
else if(cnt0 == 0 && en_r1)begin
ab_pow7_re_r1 <= abo_re;
ab_pow7_im_r1 <= abo_im;
b_pow8_re_r1 <= bin_re;
b_pow8_im_r1 <= bin_im;
end
// else begin
// end
end
reg [5:0] vldi_r10;
syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
a_re0 <= 0;
a_im0 <= 0;
ab_re0 <= 0;
ab_im0 <= 0;
abb_re0 <= 0;
abb_im0 <= 0;
ab_pow3_re0 <= 0;
ab_pow3_im0 <= 0;
ab_pow4_re0 <= 0;
ab_pow4_im0 <= 0;
ab_pow5_re0 <= 0;
ab_pow5_im0 <= 0;
ab_pow6_re0 <= 0;
ab_pow6_im0 <= 0;
ab_pow7_re0 <= 0;
ab_pow7_im0 <= 0;
b_pow8_re0 <= 0;
b_pow8_im0 <= 0;
a_re1 <= 0;
a_im1 <= 0;
ab_re1 <= 0;
ab_im1 <= 0;
abb_re1 <= 0;
abb_im1 <= 0;
ab_pow3_re1 <= 0;
ab_pow3_im1 <= 0;
ab_pow4_re1 <= 0;
ab_pow4_im1 <= 0;
ab_pow5_re1 <= 0;
ab_pow5_im1 <= 0;
ab_pow6_re1 <= 0;
ab_pow6_im1 <= 0;
ab_pow7_re1 <= 0;
ab_pow7_im1 <= 0;
b_pow8_re1 <= 0;
b_pow8_im1 <= 0;
a_re2 <= 0;
a_im2 <= 0;
ab_re2 <= 0;
ab_im2 <= 0;
abb_re2 <= 0;
abb_im2 <= 0;
ab_pow3_re2 <= 0;
ab_pow3_im2 <= 0;
ab_pow4_re2 <= 0;
ab_pow4_im2 <= 0;
ab_pow5_re2 <= 0;
ab_pow5_im2 <= 0;
ab_pow6_re2 <= 0;
ab_pow6_im2 <= 0;
ab_pow7_re2 <= 0;
ab_pow7_im2 <= 0;
b_pow8_re2 <= 0;
b_pow8_im2 <= 0;
a_re3 <= 0;
a_im3 <= 0;
ab_re3 <= 0;
ab_im3 <= 0;
abb_re3 <= 0;
abb_im3 <= 0;
ab_pow3_re3 <= 0;
ab_pow3_im3 <= 0;
ab_pow4_re3 <= 0;
ab_pow4_im3 <= 0;
ab_pow5_re3 <= 0;
ab_pow5_im3 <= 0;
ab_pow6_re3 <= 0;
ab_pow6_im3 <= 0;
ab_pow7_re3 <= 0;
ab_pow7_im3 <= 0;
b_pow8_re3 <= 0;
b_pow8_im3 <= 0;
a_re4 <= 0;
a_im4 <= 0;
ab_re4 <= 0;
ab_im4 <= 0;
abb_re4 <= 0;
abb_im4 <= 0;
ab_pow3_re4 <= 0;
ab_pow3_im4 <= 0;
ab_pow4_re4 <= 0;
ab_pow4_im4 <= 0;
ab_pow5_re4 <= 0;
ab_pow5_im4 <= 0;
ab_pow6_re4 <= 0;
ab_pow6_im4 <= 0;
ab_pow7_re4 <= 0;
ab_pow7_im4 <= 0;
b_pow8_re4 <= 0;
b_pow8_im4 <= 0;
a_re5 <= 0;
a_im5 <= 0;
ab_re5 <= 0;
ab_im5 <= 0;
abb_re5 <= 0;
abb_im5 <= 0;
ab_pow3_re5 <= 0;
ab_pow3_im5 <= 0;
ab_pow4_re5 <= 0;
ab_pow4_im5 <= 0;
ab_pow5_re5 <= 0;
ab_pow5_im5 <= 0;
ab_pow6_re5 <= 0;
ab_pow6_im5 <= 0;
ab_pow7_re5 <= 0;
ab_pow7_im5 <= 0;
b_pow8_re5 <= 0;
b_pow8_im5 <= 0;
end
else if(|vldi_r10) begin
case(1'b1)
vldi_r10[0]: begin
a_re0 <= ao_re_r1 ;
a_im0 <= ao_im_r1 ;
ab_re0 <= ab_re_r1 ;
ab_im0 <= ab_im_r1 ;
abb_re0 <= abb_re_r1 ;
abb_im0 <= abb_im_r1 ;
ab_pow3_re0 <= ab_pow3_re_r1;
ab_pow3_im0 <= ab_pow3_im_r1;
ab_pow4_re0 <= ab_pow4_re_r1;
ab_pow4_im0 <= ab_pow4_im_r1;
ab_pow5_re0 <= ab_pow5_re_r1;
ab_pow5_im0 <= ab_pow5_im_r1;
ab_pow6_re0 <= ab_pow6_re_r1;
ab_pow6_im0 <= ab_pow6_im_r1;
ab_pow7_re0 <= ab_pow7_re_r1;
ab_pow7_im0 <= ab_pow7_im_r1;
b_pow8_re0 <= b_pow8_re_r1 ;
b_pow8_im0 <= b_pow8_im_r1 ;
end
vldi_r10[1]: begin
a_re1 <= ao_re_r1 ;
a_im1 <= ao_im_r1 ;
ab_re1 <= ab_re_r1 ;
ab_im1 <= ab_im_r1 ;
abb_re1 <= abb_re_r1 ;
abb_im1 <= abb_im_r1 ;
ab_pow3_re1 <= ab_pow3_re_r1;
ab_pow3_im1 <= ab_pow3_im_r1;
ab_pow4_re1 <= ab_pow4_re_r1;
ab_pow4_im1 <= ab_pow4_im_r1;
ab_pow5_re1 <= ab_pow5_re_r1;
ab_pow5_im1 <= ab_pow5_im_r1;
ab_pow6_re1 <= ab_pow6_re_r1;
ab_pow6_im1 <= ab_pow6_im_r1;
ab_pow7_re1 <= ab_pow7_re_r1;
ab_pow7_im1 <= ab_pow7_im_r1;
b_pow8_re1 <= b_pow8_re_r1 ;
b_pow8_im1 <= b_pow8_im_r1 ;
end
vldi_r10[2]: begin
a_re2 <= ao_re_r1 ;
a_im2 <= ao_im_r1 ;
ab_re2 <= ab_re_r1 ;
ab_im2 <= ab_im_r1 ;
abb_re2 <= abb_re_r1 ;
abb_im2 <= abb_im_r1 ;
ab_pow3_re2 <= ab_pow3_re_r1;
ab_pow3_im2 <= ab_pow3_im_r1;
ab_pow4_re2 <= ab_pow4_re_r1;
ab_pow4_im2 <= ab_pow4_im_r1;
ab_pow5_re2 <= ab_pow5_re_r1;
ab_pow5_im2 <= ab_pow5_im_r1;
ab_pow6_re2 <= ab_pow6_re_r1;
ab_pow6_im2 <= ab_pow6_im_r1;
ab_pow7_re2 <= ab_pow7_re_r1;
ab_pow7_im2 <= ab_pow7_im_r1;
b_pow8_re2 <= b_pow8_re_r1 ;
b_pow8_im2 <= b_pow8_im_r1 ;
end
vldi_r10[3]: begin
a_re3 <= ao_re_r1 ;
a_im3 <= ao_im_r1 ;
ab_re3 <= ab_re_r1 ;
ab_im3 <= ab_im_r1 ;
abb_re3 <= abb_re_r1 ;
abb_im3 <= abb_im_r1 ;
ab_pow3_re3 <= ab_pow3_re_r1;
ab_pow3_im3 <= ab_pow3_im_r1;
ab_pow4_re3 <= ab_pow4_re_r1;
ab_pow4_im3 <= ab_pow4_im_r1;
ab_pow5_re3 <= ab_pow5_re_r1;
ab_pow5_im3 <= ab_pow5_im_r1;
ab_pow6_re3 <= ab_pow6_re_r1;
ab_pow6_im3 <= ab_pow6_im_r1;
ab_pow7_re3 <= ab_pow7_re_r1;
ab_pow7_im3 <= ab_pow7_im_r1;
b_pow8_re3 <= b_pow8_re_r1 ;
b_pow8_im3 <= b_pow8_im_r1 ;
end
vldi_r10[4]: begin
a_re4 <= ao_re_r1 ;
a_im4 <= ao_im_r1 ;
ab_re4 <= ab_re_r1 ;
ab_im4 <= ab_im_r1 ;
abb_re4 <= abb_re_r1 ;
abb_im4 <= abb_im_r1 ;
ab_pow3_re4 <= ab_pow3_re_r1;
ab_pow3_im4 <= ab_pow3_im_r1;
ab_pow4_re4 <= ab_pow4_re_r1;
ab_pow4_im4 <= ab_pow4_im_r1;
ab_pow5_re4 <= ab_pow5_re_r1;
ab_pow5_im4 <= ab_pow5_im_r1;
ab_pow6_re4 <= ab_pow6_re_r1;
ab_pow6_im4 <= ab_pow6_im_r1;
ab_pow7_re4 <= ab_pow7_re_r1;
ab_pow7_im4 <= ab_pow7_im_r1;
b_pow8_re4 <= b_pow8_re_r1 ;
b_pow8_im4 <= b_pow8_im_r1 ;
end
vldi_r10[5]: begin
a_re5 <= ao_re_r1 ;
a_im5 <= ao_im_r1 ;
ab_re5 <= ab_re_r1 ;
ab_im5 <= ab_im_r1 ;
abb_re5 <= abb_re_r1 ;
abb_im5 <= abb_im_r1 ;
ab_pow3_re5 <= ab_pow3_re_r1;
ab_pow3_im5 <= ab_pow3_im_r1;
ab_pow4_re5 <= ab_pow4_re_r1;
ab_pow4_im5 <= ab_pow4_im_r1;
ab_pow5_re5 <= ab_pow5_re_r1;
ab_pow5_im5 <= ab_pow5_im_r1;
ab_pow6_re5 <= ab_pow6_re_r1;
ab_pow6_im5 <= ab_pow6_im_r1;
ab_pow7_re5 <= ab_pow7_re_r1;
ab_pow7_im5 <= ab_pow7_im_r1;
b_pow8_re5 <= b_pow8_re_r1 ;
b_pow8_im5 <= b_pow8_im_r1 ;
end
// default: begin
// ao_re[0] <= 'h0;
// ao_im[0] <= 'h0;
// ab_re[0] <= 'h0;
// ab_im[0] <= 'h0;
// abb_re[0] <= 'h0;
// abb_im[0] <= 'h0;
// ab_pow3_re[0] <= 'h0;
// ab_pow3_im[0] <= 'h0;
// ab_pow4_re[0] <= 'h0;
// ab_pow4_im[0] <= 'h0;
// ab_pow5_re[0] <= 'h0;
// ab_pow5_im[0] <= 'h0;
// ab_pow6_re[0] <= 'h0;
// ab_pow6_im[0] <= 'h0;
// ab_pow7_re[0] <= 'h0;
// ab_pow7_im[0] <= 'h0;
// b_pow8_re[0] <= 'h0;
// b_pow8_im[0] <= 'h0;
// end
endcase
end
end
endmodule

1
rtl/z_dsp/FixRound.v
View File

@ -35,4 +35,3 @@ always@(posedge clk or negedge rstn)
assign dout = din_round;
endmodule

227
rtl/z_dsp/IIR_Filter_p8.v Normal file
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@ -0,0 +1,227 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p8 #(
parameter data_in_width = 16
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1:0] dinp0
,input signed [data_in_width-1:0] dinp1
,input signed [data_in_width-1:0] dinp2
,input signed [data_in_width-1:0] dinp3
,input signed [data_in_width-1:0] dinp4
,input signed [data_in_width-1:0] dinp5
,input signed [data_in_width-1:0] dinp6
,input signed [data_in_width-1:0] dinp7
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] abb_im
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow3_im
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow4_im
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow5_im
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow6_im
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow7_im
,input signed [coef_width-1 :0] b_pow8_re
,input signed [coef_width-1 :0] b_pow8_im
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width-1 :0] dinp [7:0];
assign dinp[7] = dinp7;
assign dinp[6] = dinp6;
assign dinp[5] = dinp5;
assign dinp[4] = dinp4;
assign dinp[3] = dinp3;
assign dinp[2] = dinp2;
assign dinp[1] = dinp1;
assign dinp[0] = dinp0;
wire signed [coef_width-1 :0] ab_pow_re [7:0];
assign ab_pow_re[7] = ab_pow7_re;
assign ab_pow_re[6] = ab_pow6_re;
assign ab_pow_re[5] = ab_pow5_re;
assign ab_pow_re[4] = ab_pow4_re;
assign ab_pow_re[3] = ab_pow3_re;
assign ab_pow_re[2] = abb_re;
assign ab_pow_re[1] = ab_re;
assign ab_pow_re[0] = a_re;
wire signed [coef_width-1 :0] ab_pow_im [7:0];
assign ab_pow_im[7] = ab_pow7_im;
assign ab_pow_im[6] = ab_pow6_im;
assign ab_pow_im[5] = ab_pow5_im;
assign ab_pow_im[4] = ab_pow4_im;
assign ab_pow_im[3] = ab_pow3_im;
assign ab_pow_im[2] = abb_im;
assign ab_pow_im[1] = ab_im;
assign ab_pow_im[0] = a_im;
wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7];
wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7];
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin: mult_x_inst
mult_x #(
.A_width(data_in_width),
.C_width(coef_width+frac_data_out_width),
.D_width(coef_width+frac_data_out_width),
.frac_coef_width(frac_coef_width)
) inst_mult_x (
.clk (clk),
.rstn (rstn),
.en (en),
.a (dinp[i]),
.c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}),
.d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}),
.Re (x_re[i]),
.Im (x_im[i])
);
end
endgenerate
wire signed [data_in_width+frac_data_out_width+3:0] v_re;
wire signed [data_in_width+frac_data_out_width+3:0] v_im;
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7];
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7];
reg signed [data_in_width+frac_data_out_width+3:0] v1_re;
reg signed [data_in_width+frac_data_out_width+3:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+3:0] y_re;
wire signed [data_in_width+frac_data_out_width+3:0] y_im;
wire signed [data_in_width+frac_data_out_width+3:0] y1_re;
wire signed [data_in_width+frac_data_out_width+3:0] y1_im;
reg signed [data_in_width-1:0] dout_re;
mult_C
#(
.A_width(data_in_width+frac_data_out_width+4)
,.B_width(data_in_width+frac_data_out_width+4)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c9 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),
.b (y_im ),
.c (b_pow8_re ),
.d (b_pow8_im ),
.Re (y1_re ),//b^8*y(n-1)
.Im (y1_im )
);
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+3:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule

360
rtl/z_dsp/IIR_top.v Normal file
View File

@ -0,0 +1,360 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_top
(
input rstn
,input clk
,input en
,input signed [15 :0] IIRin_p0
,input signed [15 :0] IIRin_p1
,input signed [15 :0] IIRin_p2
,input signed [15 :0] IIRin_p3
,input signed [15 :0] IIRin_p4
,input signed [15 :0] IIRin_p5
,input signed [15 :0] IIRin_p6
,input signed [15 :0] IIRin_p7
,input signed [31 :0] a_re
,input signed [31 :0] a_im
,input signed [31 :0] ab_re
,input signed [31 :0] ab_im
,input signed [31 :0] abb_re
,input signed [31 :0] abb_im
,input signed [31 :0] ab_pow3_re
,input signed [31 :0] ab_pow3_im
,input signed [31 :0] ab_pow4_re
,input signed [31 :0] ab_pow4_im
,input signed [31 :0] ab_pow5_re
,input signed [31 :0] ab_pow5_im
,input signed [31 :0] ab_pow6_re
,input signed [31 :0] ab_pow6_im
,input signed [31 :0] ab_pow7_re
,input signed [31 :0] ab_pow7_im
,input signed [31 :0] b_pow8_re
,input signed [31 :0] b_pow8_im
,output signed [15 :0] IIRout_p0
,output signed [15 :0] IIRout_p1
,output signed [15 :0] IIRout_p2
,output signed [15 :0] IIRout_p3
,output signed [15 :0] IIRout_p4
,output signed [15 :0] IIRout_p5
,output signed [15 :0] IIRout_p6
,output signed [15 :0] IIRout_p7
);
reg signed [15:0] IIRin_p_r1 [7:1];
wire signed [15 : 0] IIRin_p [7:0];
assign IIRin_p[7] = IIRin_p7;
assign IIRin_p[6] = IIRin_p6;
assign IIRin_p[5] = IIRin_p5;
assign IIRin_p[4] = IIRin_p4;
assign IIRin_p[3] = IIRin_p3;
assign IIRin_p[2] = IIRin_p2;
assign IIRin_p[1] = IIRin_p1;
assign IIRin_p[0] = IIRin_p0;
integer i;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (i = 1; i < 8; i = i + 1) begin
IIRin_p_r1[i] <= 'h0;
end
end
else if (en) begin
for (i = 1; i < 8; i = i + 1) begin
IIRin_p_r1[i] <= IIRin_p[i];
end
end
end
IIR_Filter_p8 inst_iir_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[0] ),
.dinp1 (IIRin_p_r1[7] ),
.dinp2 (IIRin_p_r1[6] ),
.dinp3 (IIRin_p_r1[5] ),
.dinp4 (IIRin_p_r1[4] ),
.dinp5 (IIRin_p_r1[3] ),
.dinp6 (IIRin_p_r1[2] ),
.dinp7 (IIRin_p_r1[1] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p0 )
);
IIR_Filter_p8 inst_iir_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[1] ),
.dinp1 (IIRin_p[0] ),
.dinp2 (IIRin_p_r1[7] ),
.dinp3 (IIRin_p_r1[6] ),
.dinp4 (IIRin_p_r1[5] ),
.dinp5 (IIRin_p_r1[4] ),
.dinp6 (IIRin_p_r1[3] ),
.dinp7 (IIRin_p_r1[2] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p1 )
);
IIR_Filter_p8 inst_iir_p2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[2] ),
.dinp1 (IIRin_p[1] ),
.dinp2 (IIRin_p[0] ),
.dinp3 (IIRin_p_r1[7] ),
.dinp4 (IIRin_p_r1[6] ),
.dinp5 (IIRin_p_r1[5] ),
.dinp6 (IIRin_p_r1[4] ),
.dinp7 (IIRin_p_r1[3] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p2 )
);
IIR_Filter_p8 inst_iir_p3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[3] ),
.dinp1 (IIRin_p[2] ),
.dinp2 (IIRin_p[1] ),
.dinp3 (IIRin_p[0] ),
.dinp4 (IIRin_p_r1[7] ),
.dinp5 (IIRin_p_r1[6] ),
.dinp6 (IIRin_p_r1[5] ),
.dinp7 (IIRin_p_r1[4] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p3 )
);
IIR_Filter_p8 inst_iir_p4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[4] ),
.dinp1 (IIRin_p[3] ),
.dinp2 (IIRin_p[2] ),
.dinp3 (IIRin_p[1] ),
.dinp4 (IIRin_p[0] ),
.dinp5 (IIRin_p_r1[7] ),
.dinp6 (IIRin_p_r1[6] ),
.dinp7 (IIRin_p_r1[5] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p4 )
);
IIR_Filter_p8 inst_iir_p5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[5] ),
.dinp1 (IIRin_p[4] ),
.dinp2 (IIRin_p[3] ),
.dinp3 (IIRin_p[2] ),
.dinp4 (IIRin_p[1] ),
.dinp5 (IIRin_p[0] ),
.dinp6 (IIRin_p_r1[7] ),
.dinp7 (IIRin_p_r1[6] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p5 )
);
IIR_Filter_p8 inst_iir_p6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[6] ),
.dinp1 (IIRin_p[5] ),
.dinp2 (IIRin_p[4] ),
.dinp3 (IIRin_p[3] ),
.dinp4 (IIRin_p[2] ),
.dinp5 (IIRin_p[1] ),
.dinp6 (IIRin_p[0] ),
.dinp7 (IIRin_p_r1[7] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p6 )
);
IIR_Filter_p8 inst_iir_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[7] ),
.dinp1 (IIRin_p[6] ),
.dinp2 (IIRin_p[5] ),
.dinp3 (IIRin_p[4] ),
.dinp4 (IIRin_p[3] ),
.dinp5 (IIRin_p[2] ),
.dinp6 (IIRin_p[1] ),
.dinp7 (IIRin_p[0] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p7 )
);
endmodule

1326
rtl/z_dsp/TailCorr_top.v
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module diff_p
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,output vldo
,output signed [15:0] dout_p0
,output signed [15:0] dout_p1
,output signed [15:0] dout_p2
,output signed [15:0] dout_p3
,output signed [15:0] dout_p4
,output signed [15:0] dout_p5
,output signed [15:0] dout_p6
,output signed [15:0] dout_p7
,output signed [15:0] diff_p0
,output signed [15:0] diff_p1
,output signed [15:0] diff_p2
,output signed [15:0] diff_p3
,output signed [15:0] diff_p4
,output signed [15:0] diff_p5
,output signed [15:0] diff_p6
,output signed [15:0] diff_p7
);
wire [15:0] din_wire [0:3];
assign din_wire[0] = din0;
assign din_wire[1] = din1;
assign din_wire[2] = din2;
assign din_wire[3] = din3;
wire [3:0] vldo_temp;
wire signed [15:0] dinp_r0 [7:0];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin: s2p_inst
s2p_2 inst_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din_wire[i]),
.en (vldi),
.dout0 (dinp_r0[i]),
.dout1 (dinp_r0[i+4]),
.vldo (vldo_temp[i])
);
end
endgenerate
assign vldo = vldo_temp[0];
reg signed [15:0] dinp_r1 [0:7];
integer j;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (j = 0; j < 8; j = j + 1) begin
dinp_r1[j] <= 'h0;
end
end
else if (en) begin
for (j = 0; j < 8; j = j + 1) begin
dinp_r1[j] <= dinp_r0[j];
end
end
end
wire signed [15:0] diffp_r0 [0:7];
generate
for (i = 0; i < 8; i = i + 1) begin: diff_assign
if (i == 0)
assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
else
assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
end
endgenerate
assign dout_p0 = dinp_r1[0];
assign dout_p1 = dinp_r1[1];
assign dout_p2 = dinp_r1[2];
assign dout_p3 = dinp_r1[3];
assign dout_p4 = dinp_r1[4];
assign dout_p5 = dinp_r1[5];
assign dout_p6 = dinp_r1[6];
assign dout_p7 = dinp_r1[7];
reg signed [15:0] diffp_r1 [0:7];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (j = 0; j < 8; j = j + 1) begin
diffp_r1[j] <= 0;
end
end
else if (en) begin
for (j = 0; j < 8; j = j + 1) begin
diffp_r1[j] <= diffp_r0[j];
end
end
end
assign diff_p0 = diffp_r1[0];
assign diff_p1 = diffp_r1[1];
assign diff_p2 = diffp_r1[2];
assign diff_p3 = diffp_r1[3];
assign diff_p4 = diffp_r1[4];
assign diff_p5 = diffp_r1[5];
assign diff_p6 = diffp_r1[6];
assign diff_p7 = diffp_r1[7];
endmodule

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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C #(
parameter integer A_width = 8
,parameter integer B_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division
)
(
clk,
rstn,
en,
a,
b,
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1:0] a;
input signed [B_width-1:0] b;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-frac_coef_width-2:0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc;
wire signed [A_width+C_width:0] Re_round;
wire signed [A_width+D_width:0] Im_round;
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width];
assign Im = Im_round[A_width+D_width-2:frac_coef_width];
endmodule

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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_x #(
parameter integer A_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division
)
(
clk,
rstn,
en,
a,
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1:0] a;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-frac_coef_width-2:0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [A_width+D_width-1:0] ad;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac;
assign Im_tmp = ad;
wire signed [A_width+C_width:0] Re_round;
wire signed [A_width+D_width:0] Im_round;
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width];
assign Im = Im_round[A_width+D_width-2:frac_coef_width];
endmodule

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module s2p_2 (
input clk,
input rst_n,
input [15:0] din,
input en,
output [15:0] dout0,
output [15:0] dout1,
output vldo
);
reg en_r1;
reg en_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
en_r1 <= 0;
en_r2 <= 0;
end
else begin
en_r1 <= en;
en_r2 <= en_r1;
end
end
assign vldo = en_r2;
reg cnt;
wire add_cnt;
wire end_cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 0;
end
else if(add_cnt)begin
if(end_cnt)
cnt <= 0;
else
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
assign add_cnt = en == 1'b1;
assign end_cnt = add_cnt && cnt== 2 - 1 ;
reg [ 15: 0] dout0_r0;
reg [ 15: 0] dout1_r0;
wire dout0_en;
wire dout1_en;
wire dout0_hold;
wire dout1_hold;
always @(*)begin
if(rst_n==1'b0)begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
else if(dout0_en)begin
dout0_r0 = din;
end
else if(dout1_en)begin
dout1_r0 = din;
end
else begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
end
assign dout0_en = add_cnt && cnt == 0;
assign dout1_en = add_cnt && cnt == 1;
reg [ 15: 0] dout0_r1;
reg [ 15: 0] dout1_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
else if(en)begin
dout0_r1 <= dout0_r0;
dout1_r1 <= dout1_r0;
end
else if(dout0_hold)begin
dout0_r1 <= dout0_r1;
dout1_r1 <= 16'd0;
end
else if(dout1_hold)begin
dout0_r1 <= 16'd0;
dout1_r1 <= dout1_r1;
end
else begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
end
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
reg [ 15: 0] dout0_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r2 <= 16'd0;
end
else begin
dout0_r2 <= dout0_r1;
end
end
assign dout0 = dout0_r2;
assign dout1 = dout1_r1;
endmodule

326
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/*
Copyright 2018-2020 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// All of the general DFF and Latch modules
//
// ====================================================================
//
//
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1
//
// ===========================================================================
`define DISABLE_SV_ASSERTION
`define dly #0.2
module sirv_gnrl_dfflrs # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dfflr # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is input
//
// ===========================================================================
module sirv_gnrl_dfflrd # (
parameter DW = 32
) (
input [DW-1:0] init,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= init;
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset
//
// ===========================================================================
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;
always @(posedge clk)
begin : DFFL_PROC
if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else
qout_r <= `dly dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else
qout_r <= `dly dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module for general latch
//
// ===========================================================================
module sirv_gnrl_ltch # (
parameter DW = 32
) (
//input test_mode,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout
);
reg [DW-1:0] qout_r;
always @ *
begin : LTCH_PROC
if (lden == 1'b1)
qout_r <= dnxt;
end
//assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
always_comb
begin
CHECK_THE_X_VALUE:
assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end
//synopsys translate_on
`endif//}
`endif//}
endmodule

58
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@ -0,0 +1,58 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : syncer.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-03-13 PWY AWG dedicated register file
// 0.2 2024-05-13 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module syncer # (
parameter width = 1
,parameter stage = 2
)
(
input clk_d
,input rstn_d
,input [width-1:0] data_s
,output [width-1:0] data_d
);
generate
genvar i;
wire [width-1:0] data_temp[stage-1:0];
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
for(i=1;i<stage;i=i+1) begin: SYNCER
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
end
endgenerate
assign data_d = data_temp[stage-1];
endmodule

414
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@ -0,0 +1,414 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : Z_dsp.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp
(
input rstn
,input clk
,input en
//,input tc_bypass
,input [ 5:0] vldi_coef
,input vldi_data
//,input [1:0] intp_mode
//,input [1:0] dac_mode_sel
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [31:0] a0_re
,input signed [31:0] a0_im
,input signed [31:0] b0_re
,input signed [31:0] b0_im
,input signed [31:0] a1_re
,input signed [31:0] a1_im
,input signed [31:0] b1_re
,input signed [31:0] b1_im
,input signed [31:0] a2_re
,input signed [31:0] a2_im
,input signed [31:0] b2_re
,input signed [31:0] b2_im
,input signed [31:0] a3_re
,input signed [31:0] a3_im
,input signed [31:0] b3_re
,input signed [31:0] b3_im
,input signed [31:0] a4_re
,input signed [31:0] a4_im
,input signed [31:0] b4_re
,input signed [31:0] b4_im
,input signed [31:0] a5_re
,input signed [31:0] a5_im
,input signed [31:0] b5_re
,input signed [31:0] b5_im
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
);
wire signed [15:0] IIR_out;
reg signed [31:0] ao_re [5:0];
reg signed [31:0] ao_im [5:0];
reg signed [31:0] ab_re [5:0];
reg signed [31:0] ab_im [5:0];
reg signed [31:0] abb_re [5:0];
reg signed [31:0] abb_im [5:0];
reg signed [31:0] ab_pow3_re [5:0];
reg signed [31:0] ab_pow3_im [5:0];
reg signed [31:0] ab_pow4_re [5:0];
reg signed [31:0] ab_pow4_im [5:0];
reg signed [31:0] ab_pow5_re [5:0];
reg signed [31:0] ab_pow5_im [5:0];
reg signed [31:0] ab_pow6_re [5:0];
reg signed [31:0] ab_pow6_im [5:0];
reg signed [31:0] ab_pow7_re [5:0];
reg signed [31:0] ab_pow7_im [5:0];
reg signed [31:0] b_pow8_re [5:0];
reg signed [31:0] b_pow8_im [5:0];
CoefGen inst_CoefGen(
.clk (clk ),
.rstn (rstn ),
.vldi (vldi_coef ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] )
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
reg vldo_TC;
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.vldi (vldi_data ),
// .dac_mode_sel (dac_mode_sel ),
// .intp_mode (intp_mode ),
.din0 (din0 ),
.din1 (din1 ),
.din2 (din2 ),
.din3 (din3 ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] ),
.dout_p0 (dout_0 ),
.dout_p1 (dout_1 ),
.dout_p2 (dout_2 ),
.dout_p3 (dout_3 ),
.dout_p4 (dout_4 ),
.dout_p5 (dout_5 ),
.dout_p6 (dout_6 ),
.dout_p7 (dout_7 ),
.vldo (vldo_TC )
);
assign vldo = vldo_TC;
reg signed [15:0] doutf_0;
reg signed [15:0] doutf_1;
reg signed [15:0] doutf_2;
reg signed [15:0] doutf_3;
always@(posedge clk or negedge rstn)
if(!rstn) begin
doutf_0 <= 0;
doutf_1 <= 0;
doutf_2 <= 0;
doutf_3 <= 0;
end
else if(!en) begin
doutf_0 <= dout_0;
doutf_1 <= dout_1;
doutf_2 <= dout_2;
doutf_3 <= dout_3;
end
else begin
doutf_0 <= dout_4;
doutf_1 <= dout_5;
doutf_2 <= dout_6;
doutf_3 <= dout_7;
end
assign dout0 = doutf_0;
assign dout1 = doutf_1;
assign dout2 = doutf_2;
assign dout3 = doutf_3;
endmodule

104
script_m/TailCorr_Test_Verdi.m Normal file
View File

@ -0,0 +1,104 @@
%in+iir_out with 8 intp
clc;clear;close all
% addpath("/data/work/thfu/TailCorr/script_m");
data_source = 'matlab';
file_path = "/home/thfu/work/TailCorr/sim/z_dsp/";
rng('shuffle');
if strcmp(data_source, 'matlab')
in = floor(cat(1,0,3000*randn(4*2579+4,1)));
for i = 0:3
filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
subset = in(i+1:4:end);
fileID = fopen(filename, 'w');
fprintf(fileID, '%d\n', subset);
fclose(fileID);
end
in = [in; zeros(6e4,1)];
system('make all');
elseif strcmp(data_source, 'verdi')
% system('make all');
in = [];
for i = 0:3
filename = strcat(file_path, "in", num2str(i), ".dat");
in_data = importdata(filename);
if isempty(in)
N = length(in_data);
in = zeros(4*N, 1);
end
in(i+1:4:end) = in_data;
end
else
end
cs_wave = [];
for i = 0:3
filename = strcat(file_path, "dout", num2str(i), ".dat");
dout_data = importdata(filename);
if isempty(cs_wave)
N = length(dout_data);
cs_wave = zeros(4*N, 1);
end
cs_wave(i+1:4:end) = dout_data;
end
A = [0.025 0.015*1 0.0002*1 0];
tau = -[1/250 1/650 1/1600 0];
fs = 2e9;
coef_len = length(A);
for i = 1:coef_len
b(i) = exp(1e9/fs/(1-A(i))*tau(i));
a(i) = A(i)/1/(1-A(i))*exp(1e9/fs/(1-A(i))/2*tau(i));
h_ideal(:,i) = filter(a(i),[1 -b(i)],diff(in));
end
len_in = length(in);
len_h_ideal = length(h_ideal);
in = [in; zeros(1, len_h_ideal - len_in + 1)'];
wave_float = in(2:end)+ sum(h_ideal,2);
wave_float_len = length(wave_float);
wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')';
[cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr");
N = min(length(wave_float),length(cs_wave_A));
figure()
diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
%% Test of iir filter with no intp
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
N = min(length(wave_float_A),length(wave_verdi_A));
figure()
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
%%
signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
%%
a_fix = round(a*2^31);
b_fix = round(b*2^31);
ab_fix = round(a.*b*2^31);
ab2_fix = round(a.*b.^2*2^31);
ab3_fix = round(a.*b.^3*2^31);
ab4_fix = round(a.*b.^4*2^31);
ab5_fix = round(a.*b.^5*2^31);
ab6_fix = round(a.*b.^6*2^31);
ab7_fix = round(a.*b.^7*2^31);
b8_fix = round(b.^8*2^31);
a_hex = dec2hex(a_fix,8);
a_bin = dec2bin(a_fix,32);
fprintf('a_fix is %d\n',a_fix);
fprintf('b_fix is %d\n',b_fix);
fprintf('ab_fix is %d\n',ab_fix);
fprintf('ab2_fix is %d\n', ab2_fix);
fprintf('ab3_fix is %d\n', ab3_fix);
fprintf('ab4_fix is %d\n', ab4_fix);
fprintf('ab5_fix is %d\n', ab5_fix);
fprintf('ab6_fix is %d\n', ab6_fix);
fprintf('ab7_fix is %d\n', ab7_fix);
fprintf('b8_fix is %d\n',b8_fix);

3
script_m/diff_plot.m
View File

@ -31,4 +31,5 @@ plot(n(R_mpos_max),diff(R_mpos_max),'r*')
plot(n(R_mpos_min),diff(R_mpos_min),'r*')
text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k');
text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k');
text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k');

857
script_m/z_dsp.m
View File

@ -1,305 +1,564 @@
clc;clear;close all
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
%%配置参数
fs_L = 0.75e9; %硬件频率
fs_H = 12e9; %以高频近似理想信号
TargetFrequency = 3e9;
G = 1;
DownSample = 2;
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
route_num = 5;
env_num = 7;
Ideal2Low = fs_H/(fs_L/2);
Ideal2Target = fs_H/TargetFrequency;
%% 添加路径、产生包络、配置S21参数、使用脚本计算
%%添加路径
% addpath(genpath('D:\Work\EnvData'));
% addpath(genpath('D:\Work\EnvData\data-v2'));
% addpath(genpath('D:\Work\TailCorr_20241008_NoGit'));
% addpath('D:\Work\TailCorr\script_m');
cd("D:\Work\EnvData\acz");
obj1 = py.importlib.import_module('acz');
py.importlib.reload(obj1);
cd("D:\Work\TailCorr_20241008_NoGit");
obj2 = py.importlib.import_module('wave_calculation');
py.importlib.reload(obj2);
cd("D:\Work\TailCorr");
%%产生包络
%按点数产生理想方波
% amp_rect = 1.5e4;
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
%
% for i = 1:2
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
% end
%flattop波
A = 1.5e4;
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
[edge(2), length_flattop(2)] = deal(4,30);
[edge(3), length_flattop(3)] = deal(4,50);
[edge(4), length_flattop(4)] = deal(4,1000);
[edge(5), length_flattop(5)] = deal(100,10000);
for i = 1:5
[edge_H(i), length_H(i)] = deal(edge(i)*fs_H/1e9,length_flattop(i)*fs_H/1e9);
wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
end
%acz波
amplitude = 1.5e4;
carrierFreq = 0.000000;
carrierPhase = 0.000000;
dragAlpha = 0.000000;
thf = 0.864;
thi = 0.05;
lam2 = -0.18;
lam3 = 0.04;
length_acz(1) = 30;
length_acz(2) = 50;
for i = 1:2
length_acz_H(i) = int32(length_acz(i)*fs_H/1e9);
wave_pre{i+5} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
end
for i = 1:7
wave_pre{i} = cat(2,wave_pre{i},zeros(1,floor(simulink_time*fs_H))); %校正前的高频信号
wave_preL{i} = wave_pre{i}(1:Ideal2Low:end); %校正前的低频信号
end
%%S21参数
amp_real{1} = [0.025 0.015 0.0002 0.2 0 0];
amp_imag{1} = [0 0 0 0 0 0];
time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
time_imag{1} = [0 -1/300 -1/500 0 0 0];
amp_real{2} = [0.025 0.015 0.0002 0.2 0 0];
amp_imag{2} = [0 0 0 0 0 0];
time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
time_imag{2} = [0 -1/300 -1/500 0 0 0];
amp_real{3} = [0.025 0.009 0.0002 0.2 0 0];
amp_imag{3} = [0 0.012 0 0 0 0];
time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
time_imag{3} = [0 -1/300 -1/500 0 0 0];
amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
amp_imag{4}= [0 0 0 0 0 0];
time_real{4}= [-1/250, -1/2000, -1/1600 -1/20 0 0];
time_imag{4}= [0 -1/15 -1/50 0 0 0];
amp_real{5} = [0.025 0.009 0.0002 0.2 0 0];
amp_imag{5} = [0 0.012 0 0 0 0];
time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
time_imag{5} = [0 -1/15 -1/50 0 0 0];
for i = 1:5
amp_routing{i} = amp_real{1,i} + 1j*amp_imag{1,i};
time_routing{i} = time_real{1,i} + 1j*time_imag{1,i};
tau{i} = -1./time_routing{i};
end
%%python脚本校正结果
convolve_bound = int8(3);
calibration_time = int32(20e3);
cal_method = int8(1);
sampling_rateL = int64(fs_L/2);
sampling_rate = int64(fs_H);
%校正后的高频信号
for j = 1:route_num
for i = 1:env_num
wave_cal = cell(py.wave_calculation.wave_cal(wave_pre{1,i}, amp_real{1,j}, amp_imag{1,j}, time_real{1,j}, time_imag{1,j}, convolve_bound, calibration_time, cal_method, sampling_rate));
wave_revised{j,i} = double(wave_cal{1,1});
wave_calL = cell(py.wave_calculation.wave_cal(wave_preL{1,i}, amp_real{1,j}, amp_imag{1,j}, time_real{1,j}, time_imag{1,j}, convolve_bound, calibration_time, cal_method, sampling_rateL));
wave_revisedL{j,i} = double(wave_calL{1,1});
end
alpha{j} = double(wave_calL{1,2});
beta{j} = double(wave_calL{1,3});
end
% signalAnalyzer(wave_pre{1,1},'SampleRate',fs_H);
%校正后的低频信号
alpha_wideth=32;
beta_width=32;
%定点化系数
for i = 1:route_num
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
end
%% 仿真
for j = 1:route_num
for i = 1:env_num
options=simset('SrcWorkspace','current');
sim('z_dsp',[0,simulink_time]);
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
dout0{j,i} = sim2m("dout0");
dout1{j,i} = sim2m("dout1");
dout2{j,i} = sim2m("dout2");
dout3{j,i} = sim2m("dout3");
N = length(dout0{j,i});
cs_wave{j,i} = zeros(4*N,1);
classdef z_dsp < handle
properties
%input
fs_L;
fs_H;
TargetFrequency;
G;
simulink_time;
intp_mode;
dac_mode_sel;
route_num;
env_num;
cs_wave{j,i}(1:4:4*N) = dout0{j,i};
cs_wave{j,i}(2:4:4*N) = dout1{j,i};
cs_wave{j,i}(3:4:4*N) = dout2{j,i};
cs_wave{j,i}(4:4:4*N) = dout3{j,i};
%output
Ideal2Low;
Ideal2Target;
wave_pre;
wave_preL;
amp_real;
amp_imag;
time_real;
time_imag;
name;
wave_revised;
wave_revisedL;
DownsamplingBy12GDataAlign;
HardwareMeanIntpDataAlign;
Delay;
Delay_mode;
pause_time;
filename;
rpt_num;
FallingEdge;
Amp;
itv_time; %信号具有周期性时的间隔
end
methods
function obj = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel)
obj.fs_L = fs_L;
obj.fs_H = fs_H;
obj.TargetFrequency = TargetFrequency;
obj.G = G;
obj.simulink_time = simulink_time;
obj.intp_mode = intp_mode;
obj.dac_mode_sel = dac_mode_sel;
obj.Ideal2Low = fs_H/(fs_L/2);
obj.Ideal2Target = fs_H/TargetFrequency;
obj.name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第一组S21参数_acz_持续时间30ns_下降沿",...
"第一组S21参数_acz_持续时间50ns_下降沿";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第二组S21参数_acz_持续时间30ns_下降沿",...
"第二组S21参数_acz_持续时间50ns_下降沿";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第三组S21参数_acz_持续时间30ns_下降沿",...
"第三组S21参数_acz_持续时间50ns_下降沿";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第四组S21参数_acz_持续时间30ns_下降沿",...
"第四组S21参数_acz_持续时间50ns_下降沿";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第五组S21参数_acz_持续时间30ns_下降沿",...
"第五组S21参数_acz_持续时间50ns_下降沿";
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第一组S21参数_acz_持续时间30ns_下降沿后",...
"第一组S21参数_acz_持续时间50ns_下降沿后";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第二组S21参数_acz_持续时间30ns_下降沿后",...
"第二组S21参数_acz_持续时间50ns_下降沿后";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第三组S21参数_acz_持续时间30ns_下降沿后",...
"第三组S21参数_acz_持续时间50ns_下降沿后";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第四组S21参数_acz_持续时间30ns_下降沿后",...
"第四组S21参数_acz_持续时间50ns_下降沿后";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第五组S21参数_acz_持续时间30ns_下降沿后",...
"第五组S21参数_acz_持续时间50ns_下降沿后";
];
obj.pause_time = 0.5;
obj.Amp = 1.5e4;
end
function env(obj)
cd("D:\Work\EnvData\acz");
obj1 = py.importlib.import_module('acz');
py.importlib.reload(obj1);
%按点数产生理想方波
% amp_rect = 1.5e4;
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
%
% for i = 1:2
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
% end
%flattop波
A = 1.5e4;
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
[edge(2), length_flattop(2)] = deal(4,30);
[edge(3), length_flattop(3)] = deal(4,50);
[edge(4), length_flattop(4)] = deal(4,1000);
[edge(5), length_flattop(5)] = deal(100,10000);
for i = 1:length(length_flattop)
[edge_H(i), length_H(i)] = deal(edge(i)*obj.fs_H/1e9,length_flattop(i)*obj.fs_H/1e9);
obj.wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
end
%acz波
amplitude = 1.5e4;
carrierFreq = 0.000000;
carrierPhase = 0.000000;
dragAlpha = 0.000000;
thf = 0.864;
thi = 0.05;
lam2 = -0.18;
lam3 = 0.04;
length_acz(1) = 30;
length_acz(2) = 50;
for i = 1:length(length_acz)
length_acz_H(i) = int32(length_acz(i)*obj.fs_H/1e9);
obj.wave_pre{i+length(length_flattop)} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
end
obj.env_num = length(length_flattop) + length(length_acz);
for i = 1:obj.env_num
obj.wave_pre{i} = cat(2,repmat(cat(2,obj.wave_pre{i},zeros(1,round(30e-9*obj.fs_H))),1,obj.rpt_num),zeros(1,floor(obj.simulink_time*obj.fs_H))); %校正前的高频信号
obj.wave_preL{i} = obj.wave_pre{i}(1:obj.Ideal2Low:end); %校正前的低频信号
end
assignin("base",'wave_preL',obj.wave_preL);
obj.FallingEdge = [30e-9,30e-9,50e-9,1000e-9,10000e-9,30e-9,50e-9];
end
function route(obj)
obj.amp_real{1}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{1}= [0 0 0 0 0 0];
obj.time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{1} = [0 0 0 0 0 0];
obj.amp_real{2}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{2}= [0 0 0 0 0 0];
obj.time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{2} = [0 -1/300 -1/500 0 0 0];
obj.amp_real{3}= [0.025 0.009 0.0002 0.2 0 0];
obj.amp_imag{3}= [0 0.012 0 0 0 0];
obj.time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{3} = [0 -1/300 -1/500 0 0 0];
obj.amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{4}= [0 0 0 0 0 0];
obj.time_real{4} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
obj.time_imag{4} = [0 -1/15 -1/50 0 0 0];
obj.amp_real{5}= [0.025 0.009 0.0002 0.2 0 0];
obj.amp_imag{5}= [0 0.012 0 0 0 0];
obj.time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
obj.time_imag{5} = [0 -1/15 -1/50 0 0 0];
[m,n] = size(obj.amp_real);
obj.route_num = n;
end
function py_cal(obj)
cd("D:\Work\TailCorr_20241008_NoGit");
obj2 = py.importlib.import_module('wave_calculation');
py.importlib.reload(obj2);
cd("D:\Work\TailCorr");
convolve_bound = int8(3);
calibration_time = int32(20e3);
cal_method = int8(1);
sampling_rateL = int64(obj.fs_L/2);
sampling_rate = int64(obj.fs_H);
%校正后的高频信号
for m = 1:obj.route_num
for n = 1:obj.env_num
wave_cal = cell(py.wave_calculation.wave_cal(obj.wave_pre{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rate));
obj.wave_revised{m,n} = double(wave_cal{1,1});
wave_calL = cell(py.wave_calculation.wave_cal(obj.wave_preL{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rateL));
obj.wave_revisedL{m,n} = double(wave_calL{1,1});
end
alpha{m} = double(wave_calL{1,2});
beta{m} = double(wave_calL{1,3});
end
alpha_wideth=32;
beta_width=32;
%定点化系数
for i = 1:obj.route_num
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
end
assignin('base', 'alphaFixRe', alphaFixRe);
assignin('base', 'alphaFixIm', alphaFixIm);
assignin('base', 'betaFixRe' , betaFixRe);
assignin('base', 'betaFixIm' , betaFixIm);
end
function FIL(obj)
for m = 1:obj.route_num
assignin('base', 'm', m);
for n = 1:obj.env_num
assignin('base', 'n', n);
optnons=simset('SrcWorkspace','current');
sim('z_dsp_FIL',[0,obj.simulink_time]);
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
dout0{m,n} = sim2m("dout0");
dout1{m,n} = sim2m("dout1");
dout2{m,n} = sim2m("dout2");
dout3{m,n} = sim2m("dout3");
N = length(dout0{m,n});
cs_wave{m,n} = zeros(4*N,1);
cs_wave{m,n}(1:4:4*N) = dout0{m,n};
cs_wave{m,n}(2:4:4*N) = dout1{m,n};
cs_wave{m,n}(3:4:4*N) = dout2{m,n};
cs_wave{m,n}(4:4:4*N) = dout3{m,n};
HardwareMeanIntpData{m,n} = cs_wave{m,n};%硬件校正后内插
DownsamplingBy12GData{m,n} = obj.wave_revised{m,n}(1:obj.Ideal2Target:end);
[obj.DownsamplingBy12GDataAlign{m,n},obj.HardwareMeanIntpDataAlign{m,n},obj.Delay(m,n)] = ...
alignsignals(DownsamplingBy12GData{m,n}(1:round(obj.TargetFrequency*20e-6)),HardwareMeanIntpData{m,n}(1:round(obj.TargetFrequency*20e-6)),"Method","xcorr");
end
end
obj.Delay_mode = mode(obj.Delay,'all');
fprintf('Delay_mode = %d\n',obj.Delay_mode);
end
function DataShow(obj,save)
close all;
fileID = fopen(obj.filename, 'w');
if fileID == -1
disp('文件打开失败');
else
disp('文件打开成功');
end
start_time = abs(obj.Delay_mode)/(obj.TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
if(obj.rpt_num == 1)
for m = 1:obj.route_num
for n = 1:obj.env_num
edge_Align(n) = obj.FallingEdge(n) + start_time;
tmp(n) = edge_Align(n) + 10e-9;
a{n} = [start_time-5e-9 tmp(n)];%[1/obj.fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
b{n} = [tmp(n) 20e-6];
figure('Units','normalized','Position',[0.0004 0.5174 0.4992 0.4229]);
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',a{n},obj.Amp,edge_Align(n),fileID);
if(save == "save")
savefig(obj.name(m,n));
end
figure('Units','normalized','Position',[0.0004 0.0340 0.4992 0.4229]);
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m+5,n),'硬件与脚本的差值',b{n},obj.Amp,edge_Align(n),fileID);
if(save == "save")
savefig(obj.name(m+5,n));
end
end
end
else
for m = 1:obj.route_num
for n = 1:obj.env_num
figure('Units','normalized','Position',[0 0.0333 1.0000 0.9125]);
title(obj.name(m,n),Interpreter="none");
tiledlayout('vertical','TileSpacing','tight')
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',obj.FallingEdge(n)+obj.itv_time,obj.Amp,start_time,fileID);
if(save == "save")
savefig(obj.name(m,n));
end
end
end
end
fclose(fileID);
end
HardwareMeanIntpData{j,i} = cs_wave{j,i};%硬件校正后内插
DownsamplingBy12GData{j,i} = wave_revised{j,i}(1:Ideal2Target:end);
[DownsamplingBy12GDataAlign{j,i},HardwareMeanIntpDataAlign{j,i},Delay(j,i)] = ...
alignsignals(DownsamplingBy12GData{j,i}(1:round(TargetFrequency*20e-6)),HardwareMeanIntpData{j,i}(1:round(TargetFrequency*20e-6)),"Method","xcorr");
function RouteShow(obj,save)
t = 0:1/(1e2):10000;
for i = 1:5
amp_routing{i} = obj.amp_real{1,i} + 1j*obj.amp_imag{1,i};
time_routing{i} = obj.time_real{1,i} + 1j*obj.time_imag{1,i};
tau{i} = -1./time_routing{i};
end
figure()
set(gcf,"Position",[1 49 2560 1314])
tiledlayout('flow','TileSpacing','tight');
title_name = ["第一组S_{21}参数","第二组S_{21}参数","第三组S_{21}参数","第四组S_{21}参数","第五组S_{21}参数"];
for m = 1:obj.route_num
for n = 1:1:length(amp_routing{1,m})
S21_time{m}(:,n) = amp_routing{1,m}(n)*exp(time_routing{1,m}(n)*t);
end
nexttile
plot(t*1e-9,real(sum(S21_time{m},2)));
grid on
title(title_name(m));
end
if(save == "save")
savefig("S21线路参数");
end
end
function FigDisplay(obj)
if(obj.rpt_num == 1)
for m = 1:obj.route_num*obj.env_num
figure(2*m-1)
figure(2*m)
pause(obj.pause_time);
end
else
for m = 1:obj.route_num*obj.env_num
figure(m)
pause(obj.pause_time);
end
end
end
function LoadFigAndDisplay(obj)
for n = 1:obj.route_num
for m = 1:obj.env_num
open(strcat(obj.name(n,m),'.fig'));
open(strcat(obj.name(n+5,m),'.fig'));
pause(obj.pause_time);
end
end
end
function ErrAny(obj,save)
fid = fopen(obj.filename,'r');
if(obj.rpt_num == 1)
data = textscan(fid,'Falling edge of 20ns~40ns mean :%s std :%s Falling edge of 1us~1.1us mean :%s std :%s The mean and std stably less than 1e-4 is :%s s');
fclose(fid);
data{1} = cellfun(@str2num,data{1});
data{2} = cellfun(@str2num,data{2});
data{3} = cellfun(@str2num,data{3});
data{4} = cellfun(@str2num,data{4});
data{5} = cellfun(@str2num,data{5});
title_name = ["下降沿后20ns~40ns误差的平均值","下降沿后20ns~40ns误差的标准差","下降沿后1us~1.1us误差的平均值","下降沿后1us~1.1us误差的标准差","加窗参数"];
err_threshold = [1e-3 1e-3 1e-4 3e-4 5e-6];
else
data = textscan(fid,'每个周期拖尾误差均值的标准差 = %s s');
fclose(fid);
data{1} = cellfun(@str2num,data{1});
title_name = ["多周期误差平均值的标准差"];
err_threshold = [0.5e-3];
end
[h,v] = size(data);
figure()
tiledlayout('flow','TileSpacing','tight')
colors = lines(obj.route_num);
set(gcf,'Position', [1 49 2560 1314]);
for m = 1:v
nexttile
hold on
for i = 1:(obj.route_num)
idx = (i-1)*(length(data{m})/obj.route_num) + 1 : i*(length(data{m})/obj.route_num);
plot(idx,abs(data{m}(idx)),'-o','Color', colors(i, :));
end
yline(err_threshold(m),'--r');
title(title_name(m));
set(gca,'YScale','log');
legend("第一组线路","第二组线路","第三组线路","第四组线路","第五组线路",'Location','northwest');
end
if(obj.rpt_num == 1)
if(save == "save")
savefig("单周期误差分析")
end
else
if(save == "save")
savefig("多周期误差分析")
end
end
end
%compare FIL with python script
function diff_plot_py(obj,fs,iir_out, Script_out,title1,title2,a,amp,edge,fileID)
%输入数据长度不等时取其公共部分
N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N);
Script_out = Script_out(1:N);
diff = (iir_out - Script_out)/amp;%求差，并归一化
n = (0:1:N-1)/fs;
%找出关心的数据点
if(obj.rpt_num == 1)
n_edge = find(n>=edge-1e-12);%edge代表下降沿
n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
ne(1) = 1;
window_length = 100e-9*fs;
diff_mean_window = movmean(diff,window_length);
diff_std_window = movstd(diff,window_length);
n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
n_common = max(n_mean_window(end),n_std_window(end));
%原始数据作图
tiledlayout(2,1)
ax1 = nexttile;
plot(n,iir_out,n,Script_out)
legend('硬件','软件');
xlabel('t/s')
xlim(a);
title(title1,Interpreter="none");
grid on
hold on
%差值做图
ax2 = nexttile;
plot(n,diff)
xlabel('t/s')
title('diff')
grid on
hold on
xlim(a)
title('硬件与脚本的差值',Interpreter="none");
linkaxes([ax1,ax2],'x');
plot_p = @(x)[
plot(n(x),diff(x),'r*');
text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
];
ne(1) = 1;
% [diff_max,R_mpos] = max(abs(diff));%误差最大值
% plot_p(R_mpos);
if a(2) <= 5e-6
plot_p(n_edge(1));%下降沿
% plot_p(R_mpos);
elseif a(2) == 20e-6
plot_p(n50(1)); %下降沿20ns
plot_p(n1000(1)); %下降沿1us
plot_p(ne(end)); %误差小于万分之一
fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100)));
% fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
% fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
end
else
n_start = find(n>=edge-1e-12);%edge代表下降沿
% 确定周期长度对应的采样点数量
T = a; %在这种情况下，a这个参数用不到了，使用其传递周期，也就是说a这个参数有两种不同的涵义
samples_per_period = round(T * fs); % 每个周期采样点数
num_periods = obj.rpt_num; % 总周期数
period_means = zeros(1, num_periods); % 存储每周期均值
for i = 1:num_periods
% 提取当前周期的起止索引
start_idx(i) = n_start(1) + (i - 1) * samples_per_period;
end_idx(i) = n_start(1) + i * samples_per_period;
% 提取当前周期的数据
period_data = diff(start_idx(i):end_idx(i));
% 计算当前周期的均值
period_means(i) = mean(period_data);
end
fprintf(fileID,"每个周期拖尾误差均值的标准差 = %.4e s\n",std(period_means));
ax1 = nexttile;
plot(n,iir_out,n,Script_out);
hold on
plot(n(start_idx), Script_out(start_idx), 'r*'); % 标记每个周期的起始点
plot(n(end_idx), Script_out(end_idx), 'g*'); % 标记每个周期的起始点
legend('硬件','软件');
xlabel('t/s');
title(title1,Interpreter="none");
ax2 = nexttile;
hold on
plot(n, diff); hold on; % 原始信号
plot(n(end_idx), diff(end_idx), 'g*'); % 标记每个周期的起始点
xlabel('t/s');
ylabel('归一化误差');
linkaxes([ax1,ax2],'x');
xlim([0,n(end_idx(end)) + 5e-7]);
title(title2,Interpreter="none");
end
end
end
end
% signalAnalyzer(DownsamplingBy12GDataAlign{1},HardwareMeanIntpDataAlign{1},'SampleRate',3e9);
%% 绘图并保存
close all;
Amp = 1.5e4;
FallingEdge = [
% 150e-9,4050e-9,...%矩形波
30e-9,30e-9,50e-9,1000e-9,10000e-9,...%flattop
30e-9,50e-9%acz
];
name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第一组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第一组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第二组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第二组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第三组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第三组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第四组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第四组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第五组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第五组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第一组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第一组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第二组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第二组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第三组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第三组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第四组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第四组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第五组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第五组S21参数_acz_持续时间50ns_下降沿后1us.fig";
];
Delay_mode = mode(Delay,'all');
fileID = fopen('20241223_output.txt', 'w');
if fileID == -1
disp('文件打开失败');
else
end
for j = 1:route_num
for i = 1:env_num
start_time(i) = abs(Delay_mode)/(TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
edge_Align(i) = FallingEdge(i) + start_time(i);
tmp(i) = edge_Align(i) + 10e-9;
a{i} = [start_time(i)-5e-9 tmp(i)];%[1/fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
b{i} = [tmp(i) 20e-6];
fig1 = figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',a{i},Amp,edge_Align(i),fileID);
title(name(i,1),Interpreter="none");
savefig(name(j,i));
fig2 = figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]);
diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',b{i},Amp,edge_Align(i),fileID);
title(name(i,2),Interpreter="none");
savefig(name(j+5,i));
end
end
fclose(fileID);
%% 可视化S21参数
t = 0:1/(1e2):10000;
for i = 1:1:length(amp_routing)
S21_time(:,i) = amp_routing(i)*exp(time_routing(i)*t);
end
figure
plot(t*1e-9,real(sum(S21_time,2)));
grid on
title("s(t)");
% savefig("S21参数");
% signalAnalyzer(real(sum(S21_time,2)),'SampleRate',1e11);%时间是1ns，还得加上采样率
% rmpath(genpath('D:\Work\EnvData'));
% rmpath(genpath('D:\Work\EnvData\data-v2'));
% rmpath(genpath('D:\Work\TailCorr_20241008_NoGit'));
%% 图像可视化
cd("D:\Work\TailCorr\仿真结果\20241101_125M八倍内插至1G_第1组S21参数")
for i = 1:8
close all
open(name(i,1));
open(name(i,2));
pause()
end

66
script_m/z_dsp_top.m Normal file
View File

@ -0,0 +1,66 @@
clc;clear;close all
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
fs_L = 0.75e9; %硬件频率
fs_H = 12e9; %以高频近似理想信号
TargetFrequency = 3e9;
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
route_num = 1; %线路个数
env_num = 1; %包络个数
alpha_wideth=32; %滤波器系数定点化
beta_width=32;
G = 1;
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
z_dsp1 = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel);
z_dsp1.filename = 'output.txt';
z_dsp1.rpt_num = 1;
if(z_dsp1.rpt_num > 1)
z_dsp1.name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第一组S21参数_acz_持续时间30ns_重复100次",...
"第一组S21参数_acz_持续时间50ns_重复100次";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第二组S21参数_acz_持续时间30ns_重复100次",...
"第二组S21参数_acz_持续时间50ns_重复100次";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第三组S21参数_acz_持续时间30ns_重复100次",...
"第三组S21参数_acz_持续时间50ns_重复100次";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第四组S21参数_acz_持续时间30ns_重复100次",...
"第四组S21参数_acz_持续时间50ns_重复100次";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第五组S21参数_acz_持续时间30ns_重复100次",...
"第五组S21参数_acz_持续时间50ns_重复100次";
];
z_dsp1.FallingEdge = [30e-9 30e-9 50e-9 30e-9 50e-9];
z_dsp1.itv_time = 30e-9;
end
z_dsp1.env(); %产生理想z信号
z_dsp1.route(); %配置线路参数
% z_dsp1.route_num = 1;
% z_dsp1.env_num = 1;
z_dsp1.py_cal(); %12G采样率，基于python脚本计算校正后的波形
z_dsp1.FIL(); %调用FIL模块计算校正后的波形
z_dsp1.DataShow("save"); %计算结束后展示波形，有save时保存图片
%%
z_dsp1.FigDisplay(); %图片播放
%%
z_dsp1.RouteShow("save"); %可视化线路参数
%%
z_dsp1.ErrAny("save") %对关心的指标进行可视化处理
%%
close all
z_dsp1.pause_time = 0.3;
z_dsp1.LoadFigAndDisplay()

24
sim/TailCorr_en/Makefile Normal file
View File

@ -0,0 +1,24 @@
ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

11
sim/TailCorr_en/files.f Normal file
View File

@ -0,0 +1,11 @@
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/model/DW02_mult.v
tb_TailCorr_en.v

601
sim/TailCorr_en/tb_TailCorr_en.v Normal file
View File

@ -0,0 +1,601 @@
module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode;
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
// $srandom(417492050);
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end
reg rstn;
reg [31:0] a_re0;
reg [31:0] a_im0;
reg [31:0] ab_re0;
reg [31:0] ab_im0;
reg [31:0] abb_re0;
reg [31:0] abb_im0;
reg [31:0] ab_pow3_re0;
reg [31:0] ab_pow3_im0;
reg [31:0] ab_pow4_re0;
reg [31:0] ab_pow4_im0;
reg [31:0] ab_pow5_re0;
reg [31:0] ab_pow5_im0;
reg [31:0] ab_pow6_re0;
reg [31:0] ab_pow6_im0;
reg [31:0] ab_pow7_re0;
reg [31:0] ab_pow7_im0;
reg [31:0] b_pow8_re0;
reg [31:0] b_pow8_im0;
reg [31:0] a_re1;
reg [31:0] a_im1;
reg [31:0] ab_re1;
reg [31:0] ab_im1;
reg [31:0] abb_re1;
reg [31:0] abb_im1;
reg [31:0] ab_pow3_re1;
reg [31:0] ab_pow3_im1;
reg [31:0] ab_pow4_re1;
reg [31:0] ab_pow4_im1;
reg [31:0] ab_pow5_re1;
reg [31:0] ab_pow5_im1;
reg [31:0] ab_pow6_re1;
reg [31:0] ab_pow6_im1;
reg [31:0] ab_pow7_re1;
reg [31:0] ab_pow7_im1;
reg [31:0] b_pow8_re1;
reg [31:0] b_pow8_im1;
reg [31:0] a_re2;
reg [31:0] a_im2;
reg [31:0] ab_re2;
reg [31:0] ab_im2;
reg [31:0] abb_re2;
reg [31:0] abb_im2;
reg [31:0] ab_pow3_re2;
reg [31:0] ab_pow3_im2;
reg [31:0] ab_pow4_re2;
reg [31:0] ab_pow4_im2;
reg [31:0] ab_pow5_re2;
reg [31:0] ab_pow5_im2;
reg [31:0] ab_pow6_re2;
reg [31:0] ab_pow6_im2;
reg [31:0] ab_pow7_re2;
reg [31:0] ab_pow7_im2;
reg [31:0] b_pow8_re2;
reg [31:0] b_pow8_im2;
reg [31:0] a_re3;
reg [31:0] a_im3;
reg [31:0] ab_re3;
reg [31:0] ab_im3;
reg [31:0] abb_re3;
reg [31:0] abb_im3;
reg [31:0] ab_pow3_re3;
reg [31:0] ab_pow3_im3;
reg [31:0] ab_pow4_re3;
reg [31:0] ab_pow4_im3;
reg [31:0] ab_pow5_re3;
reg [31:0] ab_pow5_im3;
reg [31:0] ab_pow6_re3;
reg [31:0] ab_pow6_im3;
reg [31:0] ab_pow7_re3;
reg [31:0] ab_pow7_im3;
reg [31:0] b_pow8_re3;
reg [31:0] b_pow8_im3;
reg [31:0] a_re4;
reg [31:0] a_im4;
reg [31:0] ab_re4;
reg [31:0] ab_im4;
reg [31:0] abb_re4;
reg [31:0] abb_im4;
reg [31:0] ab_pow3_re4;
reg [31:0] ab_pow3_im4;
reg [31:0] ab_pow4_re4;
reg [31:0] ab_pow4_im4;
reg [31:0] ab_pow5_re4;
reg [31:0] ab_pow5_im4;
reg [31:0] ab_pow6_re4;
reg [31:0] ab_pow6_im4;
reg [31:0] ab_pow7_re4;
reg [31:0] ab_pow7_im4;
reg [31:0] b_pow8_re4;
reg [31:0] b_pow8_im4;
reg [31:0] a_re5;
reg [31:0] a_im5;
reg [31:0] ab_re5;
reg [31:0] ab_im5;
reg [31:0] abb_re5;
reg [31:0] abb_im5;
reg [31:0] ab_pow3_re5;
reg [31:0] ab_pow3_im5;
reg [31:0] ab_pow4_re5;
reg [31:0] ab_pow4_im5;
reg [31:0] ab_pow5_re5;
reg [31:0] ab_pow5_im5;
reg [31:0] ab_pow6_re5;
reg [31:0] ab_pow6_im5;
reg [31:0] ab_pow7_re5;
reg [31:0] ab_pow7_im5;
reg [31:0] b_pow8_re5;
reg [31:0] b_pow8_im5;
reg [15:0] din_rect;
reg clk;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
a_re0 = 32'd55007237;
a_re1 = 32'd32690030;
a_re2 = 32'd429516;
a_re3 = 32'd0;
a_re4 = 32'd0;
a_re5 = 32'd0;
a_im0 = 32'd0;
a_im1 = 32'd0;
a_im2 = 32'd0;
a_im3 = 32'd0;
a_im4 = 32'd0;
a_im5 = 32'd0;
ab_re0 = 32'd54894517;
ab_re1 = 32'd32664510;
ab_re2 = 32'd429381 ;
ab_re3 = 32'd0;
ab_re4 = 32'd0;
ab_re5 = 32'd0;
ab_im0 = 32'd0;
ab_im1 = 32'd0;
ab_im2 = 32'd0;
ab_im3 = 32'd0;
ab_im4 = 32'd0;
ab_im5 = 32'd0;
abb_re0 = 32'd54782028;
abb_re1 = 32'd32639011;
abb_re2 = 32'd429247 ;
abb_re3 = 32'd0;
abb_re4 = 32'd0;
abb_re5 = 32'd0;
abb_im0 = 32'd0;
abb_im1 = 32'd0;
abb_im2 = 32'd0;
abb_im3 = 32'd0;
abb_im4 = 32'd0;
abb_im5 = 32'd0;
ab_pow3_re0 = 32'd54669770;
ab_pow3_re1 = 32'd32613532;
ab_pow3_re2 = 32'd429113 ;
ab_pow3_re3 = 32'd0;
ab_pow3_re4 = 32'd0;
ab_pow3_re5 = 32'd0;
ab_pow3_im0 = 32'd0;
ab_pow3_im1 = 32'd0;
ab_pow3_im2 = 32'd0;
ab_pow3_im3 = 32'd0;
ab_pow3_im4 = 32'd0;
ab_pow3_im5 = 32'd0;
ab_pow4_re0 = 32'd54557742;
ab_pow4_re1 = 32'd32588072;
ab_pow4_re2 = 32'd428979 ;
ab_pow4_re3 = 32'd0;
ab_pow4_re4 = 32'd0;
ab_pow4_re5 = 32'd0;
ab_pow4_im0 = 32'd0;
ab_pow4_im1 = 32'd0;
ab_pow4_im2 = 32'd0;
ab_pow4_im3 = 32'd0;
ab_pow4_im4 = 32'd0;
ab_pow4_im5 = 32'd0;
ab_pow5_re0 = 32'd54445943;
ab_pow5_re1 = 32'd32562633;
ab_pow5_re2 = 32'd428845 ;
ab_pow5_re3 = 32'd0;
ab_pow5_re4 = 32'd0;
ab_pow5_re5 = 32'd0;
ab_pow5_im0 = 32'd0;
ab_pow5_im1 = 32'd0;
ab_pow5_im2 = 32'd0;
ab_pow5_im3 = 32'd0;
ab_pow5_im4 = 32'd0;
ab_pow5_im5 = 32'd0;
ab_pow6_re0 = 32'd54334374;
ab_pow6_re1 = 32'd32537213;
ab_pow6_re2 = 32'd428711 ;
ab_pow6_re3 = 32'd0;
ab_pow6_re4 = 32'd0;
ab_pow6_re5 = 32'd0;
ab_pow6_im0 = 32'd0;
ab_pow6_im1 = 32'd0;
ab_pow6_im2 = 32'd0;
ab_pow6_im3 = 32'd0;
ab_pow6_im4 = 32'd0;
ab_pow6_im5 = 32'd0;
ab_pow7_re0 = 32'd54223033;
ab_pow7_re1 = 32'd32511813;
ab_pow7_re2 = 32'd428577 ;
ab_pow7_re3 = 32'd0;
ab_pow7_re4 = 32'd0;
ab_pow7_re5 = 32'd0;
ab_pow7_im0 = 32'd0;
ab_pow7_im1 = 32'd0;
ab_pow7_im2 = 32'd0;
ab_pow7_im3 = 32'd0;
ab_pow7_im4 = 32'd0;
ab_pow7_im5 = 32'd0;
b_pow8_re0 = 32'd2112530470;
b_pow8_re1 = 32'd2134108939;
b_pow8_re2 = 32'd2142120573;
b_pow8_re3 = 32'd0;
b_pow8_re4 = 32'd0;
b_pow8_re5 = 32'd0;
b_pow8_im0 = 32'd0;
b_pow8_im1 = 32'd0;
b_pow8_im2 = 32'd0;
b_pow8_im3 = 32'd0;
b_pow8_im4 = 32'd0;
b_pow8_im5 = 32'd0;
din_rect = 16'd0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
reg [21:0] cnt;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
wire vldi;
assign vldi = cnt >= 100 && cnt <=10100;
reg vldi_r1;
always@(posedge clk or negedge rstn)
if(!rstn)
vldi_r1 <= 1'b0;
else
begin
vldi_r1 <= vldi;
end
always@(posedge clk or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(vldi)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
reg signed [15:0] random_in [0:3];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
else if (vldi) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= $urandom % 30000;
end
end
else begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
end
integer file[3:0];
reg [15:0] data[3:0];
integer status[3:0];
reg [15:0] reg_array[3:0];
initial begin
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
for (int i = 0; i < 4; i = i + 1) begin
file[i] = $fopen(filenames[i], "r");
if (file[i] == 0) begin
$display("Failed to open file: %s", filenames[i]);
$finish;
end
end
end
reg [0:0] vldi_matlab [3:0];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
reg_array[i] <= 16'd0;
vldi_matlab[i] <= 16'd0;
end
end else begin
for (int i = 0; i < 4; i = i + 1) begin
status[i] = $fscanf(file[i], "%d\n", data[i]);
vldi_matlab[i] <= 16'd0;
if (status[i] == 1 ) begin
reg_array[i] <= data[i];
vldi_matlab[i] <= 1'b1;
end
else begin
reg_array[i] <= 16'd0;
vldi_matlab[i] <= 1'b0;
end
end
end
end
reg signed [15:0] iir_in[3:0];
always @(*)
case(source_mode)
2'b01 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = din_rect;
end
end
2'b10 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = random_in[i];
end
end
2'b11 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = reg_array[i];
end
end
endcase
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0;
reg en;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else begin
en <= ~en;
end
end
wire signed [15:0] dout_p[7:0];
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.vldi (vldi_matlab[0] ),
// .dac_mode_sel (dac_mode_sel ),
// .intp_mode (intp_mode ),
.din0 (iir_in[0]),
.din1 (iir_in[1]),
.din2 (iir_in[2]),
.din3 (iir_in[3]),
.a_re0 (a_re0),
.a_im0 (a_im0),
.ab_re0 (ab_re0),
.ab_im0 (ab_im0),
.abb_re0 (abb_re0),
.abb_im0 (abb_im0),
.ab_pow3_re0 (ab_pow3_re0),
.ab_pow3_im0 (ab_pow3_im0),
.ab_pow4_re0 (ab_pow4_re0),
.ab_pow4_im0 (ab_pow4_im0),
.ab_pow5_re0 (ab_pow5_re0),
.ab_pow5_im0 (ab_pow5_im0),
.ab_pow6_re0 (ab_pow6_re0),
.ab_pow6_im0 (ab_pow6_im0),
.ab_pow7_re0 (ab_pow7_re0),
.ab_pow7_im0 (ab_pow7_im0),
.b_pow8_re0 (b_pow8_re0),
.b_pow8_im0 (b_pow8_im0),
.a_re1 (a_re1),
.a_im1 (a_im1),
.ab_re1 (ab_re1),
.ab_im1 (ab_im1),
.abb_re1 (abb_re1),
.abb_im1 (abb_im1),
.ab_pow3_re1 (ab_pow3_re1),
.ab_pow3_im1 (ab_pow3_im1),
.ab_pow4_re1 (ab_pow4_re1),
.ab_pow4_im1 (ab_pow4_im1),
.ab_pow5_re1 (ab_pow5_re1),
.ab_pow5_im1 (ab_pow5_im1),
.ab_pow6_re1 (ab_pow6_re1),
.ab_pow6_im1 (ab_pow6_im1),
.ab_pow7_re1 (ab_pow7_re1),
.ab_pow7_im1 (ab_pow7_im1),
.b_pow8_re1 (b_pow8_re1),
.b_pow8_im1 (b_pow8_im1),
.a_re2 (a_re2),
.a_im2 (a_im2),
.ab_re2 (ab_re2),
.ab_im2 (ab_im2),
.abb_re2 (abb_re2),
.abb_im2 (abb_im2),
.ab_pow3_re2 (ab_pow3_re2),
.ab_pow3_im2 (ab_pow3_im2),
.ab_pow4_re2 (ab_pow4_re2),
.ab_pow4_im2 (ab_pow4_im2),
.ab_pow5_re2 (ab_pow5_re2),
.ab_pow5_im2 (ab_pow5_im2),
.ab_pow6_re2 (ab_pow6_re2),
.ab_pow6_im2 (ab_pow6_im2),
.ab_pow7_re2 (ab_pow7_re2),
.ab_pow7_im2 (ab_pow7_im2),
.b_pow8_re2 (b_pow8_re2),
.b_pow8_im2 (b_pow8_im2),
.a_re3 (a_re3),
.a_im3 (a_im3),
.ab_re3 (ab_re3),
.ab_im3 (ab_im3),
.abb_re3 (abb_re3),
.abb_im3 (abb_im3),
.ab_pow3_re3 (ab_pow3_re3),
.ab_pow3_im3 (ab_pow3_im3),
.ab_pow4_re3 (ab_pow4_re3),
.ab_pow4_im3 (ab_pow4_im3),
.ab_pow5_re3 (ab_pow5_re3),
.ab_pow5_im3 (ab_pow5_im3),
.ab_pow6_re3 (ab_pow6_re3),
.ab_pow6_im3 (ab_pow6_im3),
.ab_pow7_re3 (ab_pow7_re3),
.ab_pow7_im3 (ab_pow7_im3),
.b_pow8_re3 (b_pow8_re3),
.b_pow8_im3 (b_pow8_im3),
.a_re4 (a_re4),
.a_im4 (a_im4),
.ab_re4 (ab_re4),
.ab_im4 (ab_im4),
.abb_re4 (abb_re4),
.abb_im4 (abb_im4),
.ab_pow3_re4 (ab_pow3_re4),
.ab_pow3_im4 (ab_pow3_im4),
.ab_pow4_re4 (ab_pow4_re4),
.ab_pow4_im4 (ab_pow4_im4),
.ab_pow5_re4 (ab_pow5_re4),
.ab_pow5_im4 (ab_pow5_im4),
.ab_pow6_re4 (ab_pow6_re4),
.ab_pow6_im4 (ab_pow6_im4),
.ab_pow7_re4 (ab_pow7_re4),
.ab_pow7_im4 (ab_pow7_im4),
.b_pow8_re4 (b_pow8_re4),
.b_pow8_im4 (b_pow8_im4),
.a_re5 (a_re5),
.a_im5 (a_im5),
.ab_re5 (ab_re5),
.ab_im5 (ab_im5),
.abb_re5 (abb_re5),
.abb_im5 (abb_im5),
.ab_pow3_re5 (ab_pow3_re5),
.ab_pow3_im5 (ab_pow3_im5),
.ab_pow4_re5 (ab_pow4_re5),
.ab_pow4_im5 (ab_pow4_im5),
.ab_pow5_re5 (ab_pow5_re5),
.ab_pow5_im5 (ab_pow5_im5),
.ab_pow6_re5 (ab_pow6_re5),
.ab_pow6_im5 (ab_pow6_im5),
.ab_pow7_re5 (ab_pow7_re5),
.ab_pow7_im5 (ab_pow7_im5),
.b_pow8_re5 (b_pow8_re5),
.b_pow8_im5 (b_pow8_im5),
.dout_p0 (dout_p[0] ),
.dout_p1 (dout_p[1] ),
.dout_p2 (dout_p[2] ),
.dout_p3 (dout_p[3] ),
.dout_p4 (dout_p[4] ),
.dout_p5 (dout_p[5] ),
.dout_p6 (dout_p[6] ),
.dout_p7 (dout_p[7] ),
.vldo (vldo )
);
integer signed In_fid[0:3];
integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
initial begin
#0;
for (int i = 0; i < 4; i = i + 1) begin
In_fid[i] = $fopen(filenames_in[i]);
end
for (int i = 0; i < 8; i = i + 1) begin
dout_fid[i] = $fopen(filenames_dout[i]);
end
end
always @(posedge clk) begin
if (cnt >= 90) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(In_fid[i]);
// end
end
end
always @(posedge clk) begin
if (vldo && en) begin
for (int i = 0; i < 8; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(dout_fid[i]);
// end
end
end
endmodule

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sim/s2p_2/Makefile Normal file
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VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +fsdb+delta
SIMV = ./simv -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

2
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../../rtl/z_dsp/s2p_2.v
tb_s2p_2.v

130
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`timescale 1ns/1ps
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rst_n;
reg [15:0] din;
reg enable;
reg [21:0] cnt;
wire [15:0] dout0;
wire [15:0] dout1;
s2p_2 uut (
.clk (clk),
.rst_n (rst_n),
.din (din),
.en (enable),
.dout0 (dout0),
.dout1 (dout1)
);
reg[15:0] din_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
din_r1 <= 0;
end
else begin
din_r1 <= din;
end
end
wire signed [15:0] diff;
assign diff = din - din_r1;
reg[15:0] dout1_r1;
reg[15:0] dout1_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout1_r1 <= 0;
dout1_r2 <= 0;
end
else begin
dout1_r1 <= dout1;
dout1_r2 <= dout1_r1;
end
end
wire signed [15:0] diff12;
wire signed [15:0] diff23;
assign diff12 = dout0 - dout1_r2;
assign diff23 = dout1 - dout0;
initial begin
rst_n = 0;
enable = 0;
clk = 1'b0;
din = 16'h0000;
#20;
rst_n = 1;
#10;
end
always #5 clk = ~clk;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
cnt <= 22'd0;
end else begin
cnt <= cnt + 22'd1;
end
end
reg [15:0] enable_cnt;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
enable <= 0;
din <= 16'd0;
enable_cnt <= 0;
end else begin
if (cnt < 1000) begin
if (enable_cnt == 0) begin
if ($urandom % 2 == 0) begin
enable <= 1;
enable_cnt <= $urandom % 10 + 5;
din <= $urandom;
end else begin
enable <= 0;
din <= 16'd0;
end
end else begin
enable <= 1;
enable_cnt <= enable_cnt - 1;
din <= $urandom;
end
end else begin
enable <= 0;
din <= 16'd0;
end
end
end
initial begin
wait(cnt[11] == 1);
$finish;
end
endmodule

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ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

6
sim/tb_CoefGen/files.f Normal file
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../../rtl/z_dsp/CoefGen.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/mult_C.v
../../rtl/model/DW02_mult.v
tb_CoefGen.v

162
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`timescale 1 ns/1 ns
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
end
reg clk ;
reg en;
reg [5:0] vldi;
reg rst_n;
reg signed [31:0] a_re [5:0];
reg signed [31:0] a_im [5:0];
reg signed [31:0] b_re [5:0];
reg signed [31:0] b_im [5:0];
wire signed [31:0] ao_re [5:0];
wire signed [31:0] ao_im [5:0];
wire signed [31:0] ab_re [5:0];
wire signed [31:0] ab_im [5:0];
wire signed [31:0] abb_re [5:0];
wire signed [31:0] abb_im [5:0];
wire signed [31:0] ab_pow3_re [5:0];
wire signed [31:0] ab_pow3_im [5:0];
wire signed [31:0] ab_pow4_re [5:0];
wire signed [31:0] ab_pow4_im [5:0];
wire signed [31:0] ab_pow5_re [5:0];
wire signed [31:0] ab_pow5_im [5:0];
wire signed [31:0] ab_pow6_re [5:0];
wire signed [31:0] ab_pow6_im [5:0];
wire signed [31:0] ab_pow7_re [5:0];
wire signed [31:0] ab_pow7_im [5:0];
wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0];
parameter CYCLE = 20;
parameter RST_TIME = 3 ;
CoefGen uut(
.clk (clk ),
.rstn (rst_n ),
.vldi (vldi ),
.a_re (a_re ),
.a_im (a_im ),
.b_re (b_re ),
.b_im (b_im ),
.ao_re (ao_re ),
.ao_im (ao_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im )
);
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg [15:0] st1;
reg [15:0] st2;
reg [15:0] st3;
reg [15:0] st4;
initial begin
rst_n = 0;
vldi <= 0;
st1 = 100;
st2 = 101;
st3 = 110;
st4 = 111;
repeat(3) @(posedge clk);
vldi[0] <= 1;
rst_n = 1;
a_re[0] <= 55007237;
a_im[0] <= 0;
b_re[0] <= 2143083068;
b_im[0] <= 0;
@(posedge clk);
vldi[0] <= 0;
a_re[0] <= 0;
a_im[0] <= 0;
b_re[0] <= 0;
b_im[0] <= 0;
repeat(8) @(posedge clk);
vldi[1] <= 1;
rst_n = 1;
a_re[1] <= 32690030;
a_im[1] <= 0;
b_re[1] <= 2145807236;
b_im[1] <= 0;
@(posedge clk);
vldi[1] <= 0;
a_re[1] <= 0;
a_im[1] <= 0;
b_re[1] <= 0;
b_im[1] <= 0;
repeat(8) @(posedge clk);
vldi[2] <= 1;
rst_n = 1;
a_re[2] <= 429516;
a_im[2] <= 0;
b_re[2] <= 2146812530;
b_im[2] <= 0;
@(posedge clk);
vldi[2] <= 0;
a_re[2] <= 0;
a_im[2] <= 0;
b_re[2] <= 0;
b_im[2] <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
cnt <= 22'd0;
end
else begin
cnt <= cnt + 22'd1;
end
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
endmodule

24
sim/z_dsp/Makefile Normal file
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ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

15
sim/z_dsp/files.f Normal file
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../../rtl/z_dsp/z_dsp.sv
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/syncer.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_z_dsp.v

328
sim/z_dsp/tb_z_dsp.v Normal file
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`timescale 1 ns/1 ns
module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode;
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
// $srandom(417492050);
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end
reg rstn;
reg [15:0] din_rect;
reg [ 5:0] vldi_coef;
reg vldi_data;
parameter CYCLE = 20;
reg clk;
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg signed [31:0] a_re [5:0];
reg signed [31:0] a_im [5:0];
reg signed [31:0] b_re [5:0];
reg signed [31:0] b_im [5:0];
initial begin
rstn = 0;
vldi_data <= 0;
vldi_coef <= 0;
din_rect = 16'd0;
repeat(3) @(posedge clk);
vldi_coef[0] <= 1;
rstn = 1;
a_re[0] <= 55007237;
a_im[0] <= 0;
b_re[0] <= 2143083068;
b_im[0] <= 0;
@(posedge clk);
vldi_coef[0] <= 0;
a_re[0] <= 0;
a_im[0] <= 0;
b_re[0] <= 0;
b_im[0] <= 0;
repeat(8) @(posedge clk);
vldi_coef[1] <= 1;
rstn = 1;
a_re[1] <= 32690030;
a_im[1] <= 0;
b_re[1] <= 2145807236;
b_im[1] <= 0;
@(posedge clk);
vldi_coef[1] <= 0;
a_re[1] <= 0;
a_im[1] <= 0;
b_re[1] <= 0;
b_im[1] <= 0;
repeat(8) @(posedge clk);
vldi_coef[2] <= 1;
rstn = 1;
a_re[2] <= 429516;
a_im[2] <= 0;
b_re[2] <= 2146812530;
b_im[2] <= 0;
@(posedge clk);
vldi_coef[2] <= 0;
a_re[2] <= 0;
a_im[2] <= 0;
b_re[2] <= 0;
b_im[2] <= 0;
repeat(108) @(posedge clk);
vldi_data <= 1;
// repeat(10000) @(posedge clk);
// vldi_data <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
reg vldi_data_r1;
always@(posedge clk or negedge rstn)
if(!rstn)
vldi_data_r1 <= 1'b0;
else
begin
vldi_data_r1 <= vldi_data;
end
always@(posedge clk or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(vldi_data)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
reg signed [15:0] random_in [0:3];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
else if (vldi_data) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= $urandom % 30000;
end
end
else begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
end
integer file[3:0];
reg [15:0] data[3:0];
integer status[3:0];
reg [15:0] reg_array[3:0];
initial begin
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
for (int i = 0; i < 4; i = i + 1) begin
file[i] = $fopen(filenames[i], "r");
if (file[i] == 0) begin
$display("Failed to open file: %s", filenames[i]);
$finish;
end
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
reg_array[i] <= 16'd0;
end
end else if(vldi_data) begin
for (int i = 0; i < 4; i = i + 1) begin
status[i] = $fscanf(file[i], "%d\n", data[i]);
if (status[i] == 1 ) begin
reg_array[i] <= data[i];
end
else begin
reg_array[i] <= 16'd0;
vldi_data <= 0;
end
end
end
end
reg signed [15:0] iir_in[3:0];
always @(*)
case(source_mode)
2'b01 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = din_rect;
end
end
2'b10 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = random_in[i];
end
end
2'b11 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = reg_array[i];
end
end
endcase
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0;
reg en;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 1;
end
else begin
en <= ~en;
end
end
wire signed [15:0] dout_p[7:0];
z_dsp inst_z_dsp(
.rstn (rstn ),
.clk (clk ),
.en (en ),
// .tc_bypass (tc_bypass ),
.vldi_coef (vldi_coef ),
.vldi_data (vldi_data_r1 ),
// .intp_mode (intp_mode ),
// .dac_mode_sel (dac_mode_sel ),
.din0 (iir_in[0] ),
.din1 (iir_in[1] ),
.din2 (iir_in[2] ),
.din3 (iir_in[3] ),
.a0_re (a_re[0] ),
.a0_im (a_im[0] ),
.b0_re (b_re[0] ),
.b0_im (b_im[0] ),
.a1_re (a_re[1] ),
.a1_im (a_im[1] ),
.b1_re (b_re[1] ),
.b1_im (b_im[1] ),
.a2_re (a_re[2] ),
.a2_im (a_im[2] ),
.b2_re (b_re[2] ),
.b2_im (b_im[2] ),
.a3_re (a_re[3] ),
.a3_im (a_im[3] ),
.b3_re (b_re[3] ),
.b3_im (b_im[3] ),
.a4_re (a_re[4] ),
.a4_im (a_im[4] ),
.b4_re (b_re[4] ),
.b4_im (b_im[4] ),
.a5_re (a_re[5] ),
.a5_im (a_im[5] ),
.b5_re (b_re[5] ),
.b5_im (b_im[5] ),
.dout0 (dout_p[0] ),
.dout1 (dout_p[1] ),
.dout2 (dout_p[2] ),
.dout3 (dout_p[3] ),
.vldo ( vldo )
);
integer signed In_fid[0:3];
integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
initial begin
#0;
for (int i = 0; i < 4; i = i + 1) begin
In_fid[i] = $fopen(filenames_in[i]);
end
for (int i = 0; i < 4; i = i + 1) begin
dout_fid[i] = $fopen(filenames_dout[i]);
end
end
always @(posedge clk) begin
if (vldi_data_r1) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end
end
end
always @(posedge clk) begin
if (vldo) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
end
end
endmodule