Compare commits
3 Commits
| Author | SHA1 | Date |
|---|---|---|
futh0403
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ad84ffcd89 | |
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futh0403
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0cfe0c75ce | |
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futh0403
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e297bf11e3 |
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@ -1,37 +0,0 @@
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module FixRound #(
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parameter integer Data_width = 8
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,parameter integer Fix_frac_coef_width = 31//division
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)
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(
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input clk
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,input rstn
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,input en
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,input signed [Data_width-1:0] din
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,output signed [Data_width-1:0] dout
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);
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reg signed [Data_width-1:0] din_round;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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din_round <= 'h0;
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end
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else if(en) begin
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if(din[Data_width-1] == 1'b0)
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begin
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din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
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end
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else if (din[Data_width-1] == 1'b1)
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begin
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din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
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end
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end
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else begin
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din_round <= din_round;
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end
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assign dout = din_round;
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endmodule
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@ -1,345 +0,0 @@
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : IIR_Filter.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.4 2024-05-28 thfu
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//2024-05-28 10:22:49
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module IIR_Filter_p8_ref #(
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parameter data_in_width = 16
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,parameter coef_width = 32
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,parameter frac_data_out_width = 20//X for in,5
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,parameter frac_coef_width = 31//division
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)
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(
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input rstn
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,input clk
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,input en
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,input signed [data_in_width-1:0] dinp0
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,input signed [data_in_width-1:0] dinp1
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,input signed [data_in_width-1:0] dinp2
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,input signed [data_in_width-1:0] dinp3
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,input signed [data_in_width-1:0] dinp4
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,input signed [data_in_width-1:0] dinp5
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,input signed [data_in_width-1:0] dinp6
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,input signed [data_in_width-1:0] dinp7
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,input signed [coef_width-1 :0] a_re
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,input signed [coef_width-1 :0] a_im
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,input signed [coef_width-1 :0] ab_re
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,input signed [coef_width-1 :0] ab_im
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,input signed [coef_width-1 :0] abb_re
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,input signed [coef_width-1 :0] abb_im
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,input signed [coef_width-1 :0] ab_pow3_re
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,input signed [coef_width-1 :0] ab_pow3_im
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,input signed [coef_width-1 :0] ab_pow4_re
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,input signed [coef_width-1 :0] ab_pow4_im
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,input signed [coef_width-1 :0] ab_pow5_re
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,input signed [coef_width-1 :0] ab_pow5_im
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,input signed [coef_width-1 :0] ab_pow6_re
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,input signed [coef_width-1 :0] ab_pow6_im
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,input signed [coef_width-1 :0] ab_pow7_re
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,input signed [coef_width-1 :0] ab_pow7_im
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,input signed [coef_width-1 :0] b_pow8_re
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,input signed [coef_width-1 :0] b_pow8_im
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,output signed [data_in_width-1:0] dout
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);
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wire signed [data_in_width+frac_data_out_width:0] x1_re;
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wire signed [data_in_width+frac_data_out_width:0] x1_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c1 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (dinp0 ),
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.b (16'b0 ),
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.c ({a_re,{frac_data_out_width{1'b0}}}),
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.d ({a_im,{frac_data_out_width{1'b0}}}),
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.Re (x1_re ),//a*x*dinp0
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.Im (x1_im )
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);
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wire signed [data_in_width+frac_data_out_width:0] x2_re;
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wire signed [data_in_width+frac_data_out_width:0] x2_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c2 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (dinp1 ),
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.b (16'd0 ),
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.c ({ab_re,{frac_data_out_width{1'b0}}} ),
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.d ({ab_im,{frac_data_out_width{1'b0}}} ),
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.Re (x2_re ),//a*b*dinp1
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.Im (x2_im )
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);
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wire signed [data_in_width+frac_data_out_width:0] x3_re;
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wire signed [data_in_width+frac_data_out_width:0] x3_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c3 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (dinp2 ),
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.b (16'd0 ),
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.c ({abb_re,{frac_data_out_width{1'b0}}} ),
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.d ({abb_im,{frac_data_out_width{1'b0}}} ),
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.Re (x3_re ),//a*b*b*dinp2
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.Im (x3_im )
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);
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wire signed [data_in_width+frac_data_out_width:0] x4_re;
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wire signed [data_in_width+frac_data_out_width:0] x4_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c4 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (dinp3 ),
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.b (16'd0 ),
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.c ({ab_pow3_re,{frac_data_out_width{1'b0}}} ),
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.d ({ab_pow3_im,{frac_data_out_width{1'b0}}} ),
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.Re (x4_re ),//a*b^3*dinp3
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.Im (x4_im )
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);
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wire signed [data_in_width+frac_data_out_width:0] x5_re;
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wire signed [data_in_width+frac_data_out_width:0] x5_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c5 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (dinp4 ),
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.b (16'd0 ),
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.c ({ab_pow4_re,{frac_data_out_width{1'b0}}} ),
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.d ({ab_pow4_im,{frac_data_out_width{1'b0}}} ),
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.Re (x5_re ),//a*b^4*dinp4
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.Im (x5_im )
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);
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wire signed [data_in_width+frac_data_out_width:0] x6_re;
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wire signed [data_in_width+frac_data_out_width:0] x6_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c6 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (dinp5 ),
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.b (16'd0 ),
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.c ({ab_pow5_re,{frac_data_out_width{1'b0}}} ),
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.d ({ab_pow5_im,{frac_data_out_width{1'b0}}} ),
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.Re (x6_re ),//a*b^5*dinp5
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.Im (x6_im )
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);
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wire signed [data_in_width+frac_data_out_width:0] x7_re;
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wire signed [data_in_width+frac_data_out_width:0] x7_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c7 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (dinp6 ),
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.b (16'd0 ),
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.c ({ab_pow6_re,{frac_data_out_width{1'b0}}} ),
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.d ({ab_pow6_im,{frac_data_out_width{1'b0}}} ),
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.Re (x7_re ),//a*b^6*dinp6
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.Im (x7_im )
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);
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wire signed [data_in_width+frac_data_out_width:0] x8_re;
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wire signed [data_in_width+frac_data_out_width:0] x8_im;
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mult_C_ref
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width+frac_data_out_width)
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,.D_width(coef_width+frac_data_out_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c8 (
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.clk (clk ),
|
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.rstn (rstn ),
|
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.en (en ),
|
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.a (dinp7 ),
|
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.b (16'd0 ),
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.c ({ab_pow7_re,{frac_data_out_width{1'b0}}} ),
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.d ({ab_pow7_im,{frac_data_out_width{1'b0}}} ),
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.Re (x8_re ),//a*b^7*dinp7
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.Im (x8_im )
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);
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wire signed [data_in_width+frac_data_out_width+1:0] v_re;
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wire signed [data_in_width+frac_data_out_width+1:0] v_im;
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assign v_re = x1_re + x2_re + x3_re + x4_re + x5_re + x6_re + x7_re + x8_re;
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assign v_im = x1_im + x2_im + x3_im + x4_im + x5_im + x6_im + x7_im + x8_im;
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reg signed [data_in_width+frac_data_out_width+1:0] v1_re;
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reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
|
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always @(posedge clk or negedge rstn)
|
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if (!rstn)
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begin
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v1_re <= 'h0;
|
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v1_im <= 'h0;
|
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end
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else if(en)
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begin
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v1_re <= v_re;
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v1_im <= v_im;
|
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end
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else
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begin
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v1_re <= v1_re;
|
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v1_im <= v1_im;
|
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end
|
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|
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wire signed [data_in_width+frac_data_out_width+1:0] y_re;
|
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wire signed [data_in_width+frac_data_out_width+1:0] y_im;
|
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reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
|
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reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
|
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|
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reg signed [data_in_width-1:0] dout_re;
|
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|
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mult_C_ref
|
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#(
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.A_width(data_in_width+frac_data_out_width+2)
|
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,.B_width(data_in_width+frac_data_out_width+2)
|
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,.C_width(coef_width)
|
||||
,.D_width(coef_width)
|
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,.frac_coef_width(frac_coef_width)
|
||||
)
|
||||
inst_c9 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (y_re ),
|
||||
.b (y_im ),
|
||||
.c (b_pow8_re ),
|
||||
.d (b_pow8_im ),
|
||||
.Re (y1_re ),//b^8*y(n-1)
|
||||
.Im (y1_im )
|
||||
);
|
||||
|
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assign y_re = v1_re + y1_re;
|
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assign y_im = v1_im + y1_im;
|
||||
|
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wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
|
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|
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FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
|
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|
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always @(posedge clk or negedge rstn)
|
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if (!rstn)
|
||||
begin
|
||||
dout_re <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
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dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_re <= dout_re;
|
||||
end
|
||||
|
||||
reg signed [data_in_width-1:0] dout_clip;
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
dout_clip <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
|
||||
dout_clip <= 16'd32767;
|
||||
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
|
||||
dout_clip <= -16'd32768;
|
||||
else
|
||||
dout_clip <= dout_re;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_clip <= dout_clip;
|
||||
end
|
||||
|
||||
assign dout = dout_clip;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,379 +0,0 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module IIR_top_ref
|
||||
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input signed [15:0] IIRin_p0
|
||||
,input signed [15:0] IIRin_p1
|
||||
,input signed [15:0] IIRin_p2
|
||||
,input signed [15:0] IIRin_p3
|
||||
,input signed [15:0] IIRin_p4
|
||||
,input signed [15:0] IIRin_p5
|
||||
,input signed [15:0] IIRin_p6
|
||||
,input signed [15:0] IIRin_p7
|
||||
,input signed [31 :0] a_re
|
||||
,input signed [31 :0] a_im
|
||||
,input signed [31 :0] ab_re
|
||||
,input signed [31 :0] ab_im
|
||||
,input signed [31 :0] abb_re
|
||||
,input signed [31 :0] abb_im
|
||||
,input signed [31 :0] ab_pow3_re
|
||||
,input signed [31 :0] ab_pow3_im
|
||||
,input signed [31 :0] ab_pow4_re
|
||||
,input signed [31 :0] ab_pow4_im
|
||||
,input signed [31 :0] ab_pow5_re
|
||||
,input signed [31 :0] ab_pow5_im
|
||||
,input signed [31 :0] ab_pow6_re
|
||||
,input signed [31 :0] ab_pow6_im
|
||||
,input signed [31 :0] ab_pow7_re
|
||||
,input signed [31 :0] ab_pow7_im
|
||||
,input signed [31 :0] b_pow8_re
|
||||
,input signed [31 :0] b_pow8_im
|
||||
|
||||
,output signed [15:0] IIRout_p0
|
||||
,output signed [15:0] IIRout_p1
|
||||
,output signed [15:0] IIRout_p2
|
||||
,output signed [15:0] IIRout_p3
|
||||
,output signed [15:0] IIRout_p4
|
||||
,output signed [15:0] IIRout_p5
|
||||
,output signed [15:0] IIRout_p6
|
||||
,output signed [15:0] IIRout_p7
|
||||
);
|
||||
|
||||
reg signed [15:0] IIRin_p0_r1;
|
||||
reg signed [15:0] IIRin_p1_r1;
|
||||
reg signed [15:0] IIRin_p2_r1;
|
||||
reg signed [15:0] IIRin_p3_r1;
|
||||
reg signed [15:0] IIRin_p4_r1;
|
||||
reg signed [15:0] IIRin_p5_r1;
|
||||
reg signed [15:0] IIRin_p6_r1;
|
||||
reg signed [15:0] IIRin_p7_r1;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
IIRin_p0_r1 <= 'h0;
|
||||
IIRin_p1_r1 <= 'h0;
|
||||
IIRin_p2_r1 <= 'h0;
|
||||
IIRin_p3_r1 <= 'h0;
|
||||
IIRin_p4_r1 <= 'h0;
|
||||
IIRin_p5_r1 <= 'h0;
|
||||
IIRin_p6_r1 <= 'h0;
|
||||
IIRin_p7_r1 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
IIRin_p0_r1 <= IIRin_p0;
|
||||
IIRin_p1_r1 <= IIRin_p1;
|
||||
IIRin_p2_r1 <= IIRin_p2;
|
||||
IIRin_p3_r1 <= IIRin_p3;
|
||||
IIRin_p4_r1 <= IIRin_p4;
|
||||
IIRin_p5_r1 <= IIRin_p5;
|
||||
IIRin_p6_r1 <= IIRin_p6;
|
||||
IIRin_p7_r1 <= IIRin_p7;
|
||||
end
|
||||
else
|
||||
begin
|
||||
IIRin_p0_r1 <= IIRin_p0_r1;
|
||||
IIRin_p1_r1 <= IIRin_p1_r1;
|
||||
IIRin_p2_r1 <= IIRin_p2_r1;
|
||||
IIRin_p3_r1 <= IIRin_p3_r1;
|
||||
IIRin_p4_r1 <= IIRin_p4_r1;
|
||||
IIRin_p5_r1 <= IIRin_p5_r1;
|
||||
IIRin_p6_r1 <= IIRin_p6_r1;
|
||||
IIRin_p7_r1 <= IIRin_p7_r1;
|
||||
end
|
||||
|
||||
IIR_Filter_p8_ref inst_iir_0_p0 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p0 ),
|
||||
.dinp1 (IIRin_p7_r1 ),
|
||||
.dinp2 (IIRin_p6_r1 ),
|
||||
.dinp3 (IIRin_p5_r1 ),
|
||||
.dinp4 (IIRin_p4_r1 ),
|
||||
.dinp5 (IIRin_p3_r1 ),
|
||||
.dinp6 (IIRin_p2_r1 ),
|
||||
.dinp7 (IIRin_p1_r1 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p0 )
|
||||
);
|
||||
|
||||
IIR_Filter_p8_ref inst_iir_o_p1 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p1 ),
|
||||
.dinp1 (IIRin_p0 ),
|
||||
.dinp2 (IIRin_p7_r1 ),
|
||||
.dinp3 (IIRin_p6_r1 ),
|
||||
.dinp4 (IIRin_p5_r1 ),
|
||||
.dinp5 (IIRin_p4_r1 ),
|
||||
.dinp6 (IIRin_p3_r1 ),
|
||||
.dinp7 (IIRin_p2_r1 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p1 )
|
||||
);
|
||||
IIR_Filter_p8_ref inst_iir_0_p2 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p2 ),
|
||||
.dinp1 (IIRin_p1 ),
|
||||
.dinp2 (IIRin_p0 ),
|
||||
.dinp3 (IIRin_p7_r1 ),
|
||||
.dinp4 (IIRin_p6_r1 ),
|
||||
.dinp5 (IIRin_p5_r1 ),
|
||||
.dinp6 (IIRin_p4_r1 ),
|
||||
.dinp7 (IIRin_p3_r1 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p2 )
|
||||
);
|
||||
IIR_Filter_p8_ref inst_iir_0_p3 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p3 ),
|
||||
.dinp1 (IIRin_p2 ),
|
||||
.dinp2 (IIRin_p1 ),
|
||||
.dinp3 (IIRin_p0 ),
|
||||
.dinp4 (IIRin_p7_r1 ),
|
||||
.dinp5 (IIRin_p6_r1 ),
|
||||
.dinp6 (IIRin_p5_r1 ),
|
||||
.dinp7 (IIRin_p4_r1 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p3 )
|
||||
);
|
||||
IIR_Filter_p8_ref inst_iir_0_p4 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p4 ),
|
||||
.dinp1 (IIRin_p3 ),
|
||||
.dinp2 (IIRin_p2 ),
|
||||
.dinp3 (IIRin_p1 ),
|
||||
.dinp4 (IIRin_p0 ),
|
||||
.dinp5 (IIRin_p7_r1 ),
|
||||
.dinp6 (IIRin_p6_r1 ),
|
||||
.dinp7 (IIRin_p5_r1 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p4 )
|
||||
);
|
||||
IIR_Filter_p8_ref inst_iir_0_p5 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p5 ),
|
||||
.dinp1 (IIRin_p4 ),
|
||||
.dinp2 (IIRin_p3 ),
|
||||
.dinp3 (IIRin_p2 ),
|
||||
.dinp4 (IIRin_p1 ),
|
||||
.dinp5 (IIRin_p0 ),
|
||||
.dinp6 (IIRin_p7_r1 ),
|
||||
.dinp7 (IIRin_p6_r1 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p5 )
|
||||
);
|
||||
IIR_Filter_p8_ref inst_iir_0_p6 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p6 ),
|
||||
.dinp1 (IIRin_p5 ),
|
||||
.dinp2 (IIRin_p4 ),
|
||||
.dinp3 (IIRin_p3 ),
|
||||
.dinp4 (IIRin_p2 ),
|
||||
.dinp5 (IIRin_p1 ),
|
||||
.dinp6 (IIRin_p0 ),
|
||||
.dinp7 (IIRin_p7_r1 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p6 )
|
||||
);
|
||||
IIR_Filter_p8_ref inst_iir_0_p7 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p7 ),
|
||||
.dinp1 (IIRin_p6 ),
|
||||
.dinp2 (IIRin_p5 ),
|
||||
.dinp3 (IIRin_p4 ),
|
||||
.dinp4 (IIRin_p3 ),
|
||||
.dinp5 (IIRin_p2 ),
|
||||
.dinp6 (IIRin_p1 ),
|
||||
.dinp7 (IIRin_p0 ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p7 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,900 +0,0 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2025-02-28 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module TailCorr_top_ref
|
||||
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input vldi
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,input signed [31:0] a_re0
|
||||
,input signed [31:0] a_im0
|
||||
,input signed [31:0] ab_re0
|
||||
,input signed [31:0] ab_im0
|
||||
,input signed [31:0] abb_re0
|
||||
,input signed [31:0] abb_im0
|
||||
,input signed [31:0] ab_pow3_re0
|
||||
,input signed [31:0] ab_pow3_im0
|
||||
,input signed [31:0] ab_pow4_re0
|
||||
,input signed [31:0] ab_pow4_im0
|
||||
,input signed [31:0] ab_pow5_re0
|
||||
,input signed [31:0] ab_pow5_im0
|
||||
,input signed [31:0] ab_pow6_re0
|
||||
,input signed [31:0] ab_pow6_im0
|
||||
,input signed [31:0] ab_pow7_re0
|
||||
,input signed [31:0] ab_pow7_im0
|
||||
,input signed [31:0] b_pow8_re0
|
||||
,input signed [31:0] b_pow8_im0
|
||||
,input signed [31:0] a_re1
|
||||
,input signed [31:0] a_im1
|
||||
,input signed [31:0] ab_re1
|
||||
,input signed [31:0] ab_im1
|
||||
,input signed [31:0] abb_re1
|
||||
,input signed [31:0] abb_im1
|
||||
,input signed [31:0] ab_pow3_re1
|
||||
,input signed [31:0] ab_pow3_im1
|
||||
,input signed [31:0] ab_pow4_re1
|
||||
,input signed [31:0] ab_pow4_im1
|
||||
,input signed [31:0] ab_pow5_re1
|
||||
,input signed [31:0] ab_pow5_im1
|
||||
,input signed [31:0] ab_pow6_re1
|
||||
,input signed [31:0] ab_pow6_im1
|
||||
,input signed [31:0] ab_pow7_re1
|
||||
,input signed [31:0] ab_pow7_im1
|
||||
,input signed [31:0] b_pow8_re1
|
||||
,input signed [31:0] b_pow8_im1
|
||||
,input signed [31:0] a_re2
|
||||
,input signed [31:0] a_im2
|
||||
,input signed [31:0] ab_re2
|
||||
,input signed [31:0] ab_im2
|
||||
,input signed [31:0] abb_re2
|
||||
,input signed [31:0] abb_im2
|
||||
,input signed [31:0] ab_pow3_re2
|
||||
,input signed [31:0] ab_pow3_im2
|
||||
,input signed [31:0] ab_pow4_re2
|
||||
,input signed [31:0] ab_pow4_im2
|
||||
,input signed [31:0] ab_pow5_re2
|
||||
,input signed [31:0] ab_pow5_im2
|
||||
,input signed [31:0] ab_pow6_re2
|
||||
,input signed [31:0] ab_pow6_im2
|
||||
,input signed [31:0] ab_pow7_re2
|
||||
,input signed [31:0] ab_pow7_im2
|
||||
,input signed [31:0] b_pow8_re2
|
||||
,input signed [31:0] b_pow8_im2
|
||||
,input signed [31:0] a_re3
|
||||
,input signed [31:0] a_im3
|
||||
,input signed [31:0] ab_re3
|
||||
,input signed [31:0] ab_im3
|
||||
,input signed [31:0] abb_re3
|
||||
,input signed [31:0] abb_im3
|
||||
,input signed [31:0] ab_pow3_re3
|
||||
,input signed [31:0] ab_pow3_im3
|
||||
,input signed [31:0] ab_pow4_re3
|
||||
,input signed [31:0] ab_pow4_im3
|
||||
,input signed [31:0] ab_pow5_re3
|
||||
,input signed [31:0] ab_pow5_im3
|
||||
,input signed [31:0] ab_pow6_re3
|
||||
,input signed [31:0] ab_pow6_im3
|
||||
,input signed [31:0] ab_pow7_re3
|
||||
,input signed [31:0] ab_pow7_im3
|
||||
,input signed [31:0] b_pow8_re3
|
||||
,input signed [31:0] b_pow8_im3
|
||||
,input signed [31:0] a_re4
|
||||
,input signed [31:0] a_im4
|
||||
,input signed [31:0] ab_re4
|
||||
,input signed [31:0] ab_im4
|
||||
,input signed [31:0] abb_re4
|
||||
,input signed [31:0] abb_im4
|
||||
,input signed [31:0] ab_pow3_re4
|
||||
,input signed [31:0] ab_pow3_im4
|
||||
,input signed [31:0] ab_pow4_re4
|
||||
,input signed [31:0] ab_pow4_im4
|
||||
,input signed [31:0] ab_pow5_re4
|
||||
,input signed [31:0] ab_pow5_im4
|
||||
,input signed [31:0] ab_pow6_re4
|
||||
,input signed [31:0] ab_pow6_im4
|
||||
,input signed [31:0] ab_pow7_re4
|
||||
,input signed [31:0] ab_pow7_im4
|
||||
,input signed [31:0] b_pow8_re4
|
||||
,input signed [31:0] b_pow8_im4
|
||||
,input signed [31:0] a_re5
|
||||
,input signed [31:0] a_im5
|
||||
,input signed [31:0] ab_re5
|
||||
,input signed [31:0] ab_im5
|
||||
,input signed [31:0] abb_re5
|
||||
,input signed [31:0] abb_im5
|
||||
,input signed [31:0] ab_pow3_re5
|
||||
,input signed [31:0] ab_pow3_im5
|
||||
,input signed [31:0] ab_pow4_re5
|
||||
,input signed [31:0] ab_pow4_im5
|
||||
,input signed [31:0] ab_pow5_re5
|
||||
,input signed [31:0] ab_pow5_im5
|
||||
,input signed [31:0] ab_pow6_re5
|
||||
,input signed [31:0] ab_pow6_im5
|
||||
,input signed [31:0] ab_pow7_re5
|
||||
,input signed [31:0] ab_pow7_im5
|
||||
,input signed [31:0] b_pow8_re5
|
||||
,input signed [31:0] b_pow8_im5
|
||||
|
||||
,output signed [15:0] dout_p0
|
||||
,output signed [15:0] dout_p1
|
||||
,output signed [15:0] dout_p2
|
||||
,output signed [15:0] dout_p3
|
||||
,output signed [15:0] dout_p4
|
||||
,output signed [15:0] dout_p5
|
||||
,output signed [15:0] dout_p6
|
||||
,output signed [15:0] dout_p7
|
||||
,output vldo
|
||||
);
|
||||
|
||||
wire signed [15:0] din_p0;
|
||||
wire signed [15:0] din_p1;
|
||||
wire signed [15:0] din_p2;
|
||||
wire signed [15:0] din_p3;
|
||||
wire signed [15:0] din_p4;
|
||||
wire signed [15:0] din_p5;
|
||||
wire signed [15:0] din_p6;
|
||||
wire signed [15:0] din_p7;
|
||||
wire signed [15:0] IIRin_p0;
|
||||
wire signed [15:0] IIRin_p1;
|
||||
wire signed [15:0] IIRin_p2;
|
||||
wire signed [15:0] IIRin_p3;
|
||||
wire signed [15:0] IIRin_p4;
|
||||
wire signed [15:0] IIRin_p5;
|
||||
wire signed [15:0] IIRin_p6;
|
||||
wire signed [15:0] IIRin_p7;
|
||||
wire vldo_diff;
|
||||
diff_p_ref inst_diff_p_ref (
|
||||
.rstn (rstn),
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
.vldi (vldi),
|
||||
.din0 (din0),
|
||||
.din1 (din1),
|
||||
.din2 (din2),
|
||||
.din3 (din3),
|
||||
.vldo (vldo_diff),
|
||||
.dout_p0 (din_p0),
|
||||
.dout_p1 (din_p1),
|
||||
.dout_p2 (din_p2),
|
||||
.dout_p3 (din_p3),
|
||||
.dout_p4 (din_p4),
|
||||
.dout_p5 (din_p5),
|
||||
.dout_p6 (din_p6),
|
||||
.dout_p7 (din_p7),
|
||||
.diff_p0 (IIRin_p0),
|
||||
.diff_p1 (IIRin_p1),
|
||||
.diff_p2 (IIRin_p2),
|
||||
.diff_p3 (IIRin_p3),
|
||||
.diff_p4 (IIRin_p4),
|
||||
.diff_p5 (IIRin_p5),
|
||||
.diff_p6 (IIRin_p6),
|
||||
.diff_p7 (IIRin_p7)
|
||||
);
|
||||
|
||||
reg signed [15:0] din_p0_r1;
|
||||
reg signed [15:0] din_p0_r2;
|
||||
reg signed [15:0] din_p0_r3;
|
||||
reg signed [15:0] din_p0_r4;
|
||||
reg signed [15:0] din_p0_r5;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p0_r1 <= 'h0;
|
||||
din_p0_r2 <= 'h0;
|
||||
din_p0_r3 <= 'h0;
|
||||
din_p0_r4 <= 'h0;
|
||||
din_p0_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p0_r1 <= din_p0;
|
||||
din_p0_r2 <= din_p0_r1;
|
||||
din_p0_r3 <= din_p0_r2;
|
||||
din_p0_r4 <= din_p0_r3;
|
||||
din_p0_r5 <= din_p0_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p0_r1 <= din_p0_r1;
|
||||
din_p0_r2 <= din_p0_r2;
|
||||
din_p0_r3 <= din_p0_r3;
|
||||
din_p0_r4 <= din_p0_r4;
|
||||
din_p0_r5 <= din_p0_r5;
|
||||
end
|
||||
reg signed [15:0] din_p1_r1;
|
||||
reg signed [15:0] din_p1_r2;
|
||||
reg signed [15:0] din_p1_r3;
|
||||
reg signed [15:0] din_p1_r4;
|
||||
reg signed [15:0] din_p1_r5;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p1_r1 <= 'h0;
|
||||
din_p1_r2 <= 'h0;
|
||||
din_p1_r3 <= 'h0;
|
||||
din_p1_r4 <= 'h0;
|
||||
din_p1_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p1_r1 <= din_p1;
|
||||
din_p1_r2 <= din_p1_r1;
|
||||
din_p1_r3 <= din_p1_r2;
|
||||
din_p1_r4 <= din_p1_r3;
|
||||
din_p1_r5 <= din_p1_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p1_r1 <= din_p1_r1;
|
||||
din_p1_r2 <= din_p1_r2;
|
||||
din_p1_r3 <= din_p1_r3;
|
||||
din_p1_r4 <= din_p1_r4;
|
||||
din_p1_r5 <= din_p1_r5;
|
||||
end
|
||||
reg signed [15:0] din_p2_r1;
|
||||
reg signed [15:0] din_p2_r2;
|
||||
reg signed [15:0] din_p2_r3;
|
||||
reg signed [15:0] din_p2_r4;
|
||||
reg signed [15:0] din_p2_r5;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p2_r1 <= 'h0;
|
||||
din_p2_r2 <= 'h0;
|
||||
din_p2_r3 <= 'h0;
|
||||
din_p2_r4 <= 'h0;
|
||||
din_p2_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p2_r1 <= din_p2;
|
||||
din_p2_r2 <= din_p2_r1;
|
||||
din_p2_r3 <= din_p2_r2;
|
||||
din_p2_r4 <= din_p2_r3;
|
||||
din_p2_r5 <= din_p2_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p2_r1 <= din_p2_r1;
|
||||
din_p2_r2 <= din_p2_r2;
|
||||
din_p2_r3 <= din_p2_r3;
|
||||
din_p2_r4 <= din_p2_r4;
|
||||
din_p2_r5 <= din_p2_r5;
|
||||
end
|
||||
reg signed [15:0] din_p3_r1;
|
||||
reg signed [15:0] din_p3_r2;
|
||||
reg signed [15:0] din_p3_r3;
|
||||
reg signed [15:0] din_p3_r4;
|
||||
reg signed [15:0] din_p3_r5;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p3_r1 <= 'h0;
|
||||
din_p3_r2 <= 'h0;
|
||||
din_p3_r3 <= 'h0;
|
||||
din_p3_r4 <= 'h0;
|
||||
din_p3_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p3_r1 <= din_p3;
|
||||
din_p3_r2 <= din_p3_r1;
|
||||
din_p3_r3 <= din_p3_r2;
|
||||
din_p3_r4 <= din_p3_r3;
|
||||
din_p3_r5 <= din_p3_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p3_r1 <= din_p3_r1;
|
||||
din_p3_r2 <= din_p3_r2;
|
||||
din_p3_r3 <= din_p3_r3;
|
||||
din_p3_r4 <= din_p3_r4;
|
||||
din_p3_r5 <= din_p3_r5;
|
||||
end
|
||||
reg signed [15:0] din_p4_r1;
|
||||
reg signed [15:0] din_p4_r2;
|
||||
reg signed [15:0] din_p4_r3;
|
||||
reg signed [15:0] din_p4_r4;
|
||||
reg signed [15:0] din_p4_r5;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p4_r1 <= 'h0;
|
||||
din_p4_r2 <= 'h0;
|
||||
din_p4_r3 <= 'h0;
|
||||
din_p4_r4 <= 'h0;
|
||||
din_p4_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p4_r1 <= din_p4;
|
||||
din_p4_r2 <= din_p4_r1;
|
||||
din_p4_r3 <= din_p4_r2;
|
||||
din_p4_r4 <= din_p4_r3;
|
||||
din_p4_r5 <= din_p4_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p4_r1 <= din_p4_r1;
|
||||
din_p4_r2 <= din_p4_r2;
|
||||
din_p4_r3 <= din_p4_r3;
|
||||
din_p4_r4 <= din_p4_r4;
|
||||
din_p4_r5 <= din_p4_r5;
|
||||
end
|
||||
reg signed [15:0] din_p5_r1;
|
||||
reg signed [15:0] din_p5_r2;
|
||||
reg signed [15:0] din_p5_r3;
|
||||
reg signed [15:0] din_p5_r4;
|
||||
reg signed [15:0] din_p5_r5;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p5_r1 <= 'h0;
|
||||
din_p5_r2 <= 'h0;
|
||||
din_p5_r3 <= 'h0;
|
||||
din_p5_r4 <= 'h0;
|
||||
din_p5_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p5_r1 <= din_p5;
|
||||
din_p5_r2 <= din_p5_r1;
|
||||
din_p5_r3 <= din_p5_r2;
|
||||
din_p5_r4 <= din_p5_r3;
|
||||
din_p5_r5 <= din_p5_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p5_r1 <= din_p5_r1;
|
||||
din_p5_r2 <= din_p5_r2;
|
||||
din_p5_r3 <= din_p5_r3;
|
||||
din_p5_r4 <= din_p5_r4;
|
||||
din_p5_r5 <= din_p5_r5;
|
||||
end
|
||||
reg signed [15:0] din_p6_r1;
|
||||
reg signed [15:0] din_p6_r2;
|
||||
reg signed [15:0] din_p6_r3;
|
||||
reg signed [15:0] din_p6_r4;
|
||||
reg signed [15:0] din_p6_r5;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p6_r1 <= 'h0;
|
||||
din_p6_r2 <= 'h0;
|
||||
din_p6_r3 <= 'h0;
|
||||
din_p6_r4 <= 'h0;
|
||||
din_p6_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p6_r1 <= din_p6;
|
||||
din_p6_r2 <= din_p6_r1;
|
||||
din_p6_r3 <= din_p6_r2;
|
||||
din_p6_r4 <= din_p6_r3;
|
||||
din_p6_r5 <= din_p6_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p6_r1 <= din_p6_r1;
|
||||
din_p6_r2 <= din_p6_r2;
|
||||
din_p6_r3 <= din_p6_r3;
|
||||
din_p6_r4 <= din_p6_r4;
|
||||
din_p6_r5 <= din_p6_r5;
|
||||
end
|
||||
reg signed [15:0] din_p7_r1;
|
||||
reg signed [15:0] din_p7_r2;
|
||||
reg signed [15:0] din_p7_r3;
|
||||
reg signed [15:0] din_p7_r4;
|
||||
reg signed [15:0] din_p7_r5;
|
||||
reg signed [15:0] din_p7_r6;
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p7_r1 <= 'h0;
|
||||
din_p7_r2 <= 'h0;
|
||||
din_p7_r3 <= 'h0;
|
||||
din_p7_r4 <= 'h0;
|
||||
din_p7_r5 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p7_r1 <= din_p7;
|
||||
din_p7_r2 <= din_p7_r1;
|
||||
din_p7_r3 <= din_p7_r2;
|
||||
din_p7_r4 <= din_p7_r3;
|
||||
din_p7_r5 <= din_p7_r4;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p7_r1 <= din_p7_r1;
|
||||
din_p7_r2 <= din_p7_r2;
|
||||
din_p7_r3 <= din_p7_r3;
|
||||
din_p7_r4 <= din_p7_r4;
|
||||
din_p7_r5 <= din_p7_r5;
|
||||
end
|
||||
|
||||
wire signed [15:0] IIRout0_p0;
|
||||
wire signed [15:0] IIRout0_p1;
|
||||
wire signed [15:0] IIRout0_p2;
|
||||
wire signed [15:0] IIRout0_p3;
|
||||
wire signed [15:0] IIRout0_p4;
|
||||
wire signed [15:0] IIRout0_p5;
|
||||
wire signed [15:0] IIRout0_p6;
|
||||
wire signed [15:0] IIRout0_p7;
|
||||
IIR_top_ref inst_IIR_top_ref_0 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.IIRin_p0 (IIRin_p0 ),
|
||||
.IIRin_p1 (IIRin_p1 ),
|
||||
.IIRin_p2 (IIRin_p2 ),
|
||||
.IIRin_p3 (IIRin_p3 ),
|
||||
.IIRin_p4 (IIRin_p4 ),
|
||||
.IIRin_p5 (IIRin_p5 ),
|
||||
.IIRin_p6 (IIRin_p6 ),
|
||||
.IIRin_p7 (IIRin_p7 ),
|
||||
.a_re (a_re0 ),
|
||||
.a_im (a_im0 ),
|
||||
.ab_re (ab_re0 ),
|
||||
.ab_im (ab_im0 ),
|
||||
.abb_re (abb_re0 ),
|
||||
.abb_im (abb_im0 ),
|
||||
.ab_pow3_re (ab_pow3_re0 ),
|
||||
.ab_pow3_im (ab_pow3_im0 ),
|
||||
.ab_pow4_re (ab_pow4_re0 ),
|
||||
.ab_pow4_im (ab_pow4_im0 ),
|
||||
.ab_pow5_re (ab_pow5_re0 ),
|
||||
.ab_pow5_im (ab_pow5_im0 ),
|
||||
.ab_pow6_re (ab_pow6_re0 ),
|
||||
.ab_pow6_im (ab_pow6_im0 ),
|
||||
.ab_pow7_re (ab_pow7_re0 ),
|
||||
.ab_pow7_im (ab_pow7_im0 ),
|
||||
.b_pow8_re (b_pow8_re0 ),
|
||||
.b_pow8_im (b_pow8_im0 ),
|
||||
.IIRout_p0 (IIRout0_p0 ),
|
||||
.IIRout_p1 (IIRout0_p1 ),
|
||||
.IIRout_p2 (IIRout0_p2 ),
|
||||
.IIRout_p3 (IIRout0_p3 ),
|
||||
.IIRout_p4 (IIRout0_p4 ),
|
||||
.IIRout_p5 (IIRout0_p5 ),
|
||||
.IIRout_p6 (IIRout0_p6 ),
|
||||
.IIRout_p7 (IIRout0_p7 )
|
||||
);
|
||||
wire signed [15:0] IIRout1_p0;
|
||||
wire signed [15:0] IIRout1_p1;
|
||||
wire signed [15:0] IIRout1_p2;
|
||||
wire signed [15:0] IIRout1_p3;
|
||||
wire signed [15:0] IIRout1_p4;
|
||||
wire signed [15:0] IIRout1_p5;
|
||||
wire signed [15:0] IIRout1_p6;
|
||||
wire signed [15:0] IIRout1_p7;
|
||||
IIR_top_ref inst_IIR_top_ref_1 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.IIRin_p0 (IIRin_p0 ),
|
||||
.IIRin_p1 (IIRin_p1 ),
|
||||
.IIRin_p2 (IIRin_p2 ),
|
||||
.IIRin_p3 (IIRin_p3 ),
|
||||
.IIRin_p4 (IIRin_p4 ),
|
||||
.IIRin_p5 (IIRin_p5 ),
|
||||
.IIRin_p6 (IIRin_p6 ),
|
||||
.IIRin_p7 (IIRin_p7 ),
|
||||
.a_re (a_re1 ),
|
||||
.a_im (a_im1 ),
|
||||
.ab_re (ab_re1 ),
|
||||
.ab_im (ab_im1 ),
|
||||
.abb_re (abb_re1 ),
|
||||
.abb_im (abb_im1 ),
|
||||
.ab_pow3_re (ab_pow3_re1 ),
|
||||
.ab_pow3_im (ab_pow3_im1 ),
|
||||
.ab_pow4_re (ab_pow4_re1 ),
|
||||
.ab_pow4_im (ab_pow4_im1 ),
|
||||
.ab_pow5_re (ab_pow5_re1 ),
|
||||
.ab_pow5_im (ab_pow5_im1 ),
|
||||
.ab_pow6_re (ab_pow6_re1 ),
|
||||
.ab_pow6_im (ab_pow6_im1 ),
|
||||
.ab_pow7_re (ab_pow7_re1 ),
|
||||
.ab_pow7_im (ab_pow7_im1 ),
|
||||
.b_pow8_re (b_pow8_re1 ),
|
||||
.b_pow8_im (b_pow8_im1 ),
|
||||
.IIRout_p0 (IIRout1_p0 ),
|
||||
.IIRout_p1 (IIRout1_p1 ),
|
||||
.IIRout_p2 (IIRout1_p2 ),
|
||||
.IIRout_p3 (IIRout1_p3 ),
|
||||
.IIRout_p4 (IIRout1_p4 ),
|
||||
.IIRout_p5 (IIRout1_p5 ),
|
||||
.IIRout_p6 (IIRout1_p6 ),
|
||||
.IIRout_p7 (IIRout1_p7 )
|
||||
);
|
||||
wire signed [15:0] IIRout2_p0;
|
||||
wire signed [15:0] IIRout2_p1;
|
||||
wire signed [15:0] IIRout2_p2;
|
||||
wire signed [15:0] IIRout2_p3;
|
||||
wire signed [15:0] IIRout2_p4;
|
||||
wire signed [15:0] IIRout2_p5;
|
||||
wire signed [15:0] IIRout2_p6;
|
||||
wire signed [15:0] IIRout2_p7;
|
||||
IIR_top_ref inst_IIR_top_ref_2 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.IIRin_p0 (IIRin_p0 ),
|
||||
.IIRin_p1 (IIRin_p1 ),
|
||||
.IIRin_p2 (IIRin_p2 ),
|
||||
.IIRin_p3 (IIRin_p3 ),
|
||||
.IIRin_p4 (IIRin_p4 ),
|
||||
.IIRin_p5 (IIRin_p5 ),
|
||||
.IIRin_p6 (IIRin_p6 ),
|
||||
.IIRin_p7 (IIRin_p7 ),
|
||||
.a_re (a_re2 ),
|
||||
.a_im (a_im2 ),
|
||||
.ab_re (ab_re2 ),
|
||||
.ab_im (ab_im2 ),
|
||||
.abb_re (abb_re2 ),
|
||||
.abb_im (abb_im2 ),
|
||||
.ab_pow3_re (ab_pow3_re2 ),
|
||||
.ab_pow3_im (ab_pow3_im2 ),
|
||||
.ab_pow4_re (ab_pow4_re2 ),
|
||||
.ab_pow4_im (ab_pow4_im2 ),
|
||||
.ab_pow5_re (ab_pow5_re2 ),
|
||||
.ab_pow5_im (ab_pow5_im2 ),
|
||||
.ab_pow6_re (ab_pow6_re2 ),
|
||||
.ab_pow6_im (ab_pow6_im2 ),
|
||||
.ab_pow7_re (ab_pow7_re2 ),
|
||||
.ab_pow7_im (ab_pow7_im2 ),
|
||||
.b_pow8_re (b_pow8_re2 ),
|
||||
.b_pow8_im (b_pow8_im2 ),
|
||||
.IIRout_p0 (IIRout2_p0 ),
|
||||
.IIRout_p1 (IIRout2_p1 ),
|
||||
.IIRout_p2 (IIRout2_p2 ),
|
||||
.IIRout_p3 (IIRout2_p3 ),
|
||||
.IIRout_p4 (IIRout2_p4 ),
|
||||
.IIRout_p5 (IIRout2_p5 ),
|
||||
.IIRout_p6 (IIRout2_p6 ),
|
||||
.IIRout_p7 (IIRout2_p7 )
|
||||
);
|
||||
wire signed [15:0] IIRout3_p0;
|
||||
wire signed [15:0] IIRout3_p1;
|
||||
wire signed [15:0] IIRout3_p2;
|
||||
wire signed [15:0] IIRout3_p3;
|
||||
wire signed [15:0] IIRout3_p4;
|
||||
wire signed [15:0] IIRout3_p5;
|
||||
wire signed [15:0] IIRout3_p6;
|
||||
wire signed [15:0] IIRout3_p7;
|
||||
IIR_top_ref inst_IIR_top_ref_3 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.IIRin_p0 (IIRin_p0 ),
|
||||
.IIRin_p1 (IIRin_p1 ),
|
||||
.IIRin_p2 (IIRin_p2 ),
|
||||
.IIRin_p3 (IIRin_p3 ),
|
||||
.IIRin_p4 (IIRin_p4 ),
|
||||
.IIRin_p5 (IIRin_p5 ),
|
||||
.IIRin_p6 (IIRin_p6 ),
|
||||
.IIRin_p7 (IIRin_p7 ),
|
||||
.a_re (a_re3 ),
|
||||
.a_im (a_im3 ),
|
||||
.ab_re (ab_re3 ),
|
||||
.ab_im (ab_im3 ),
|
||||
.abb_re (abb_re3 ),
|
||||
.abb_im (abb_im3 ),
|
||||
.ab_pow3_re (ab_pow3_re3 ),
|
||||
.ab_pow3_im (ab_pow3_im3 ),
|
||||
.ab_pow4_re (ab_pow4_re3 ),
|
||||
.ab_pow4_im (ab_pow4_im3 ),
|
||||
.ab_pow5_re (ab_pow5_re3 ),
|
||||
.ab_pow5_im (ab_pow5_im3 ),
|
||||
.ab_pow6_re (ab_pow6_re3 ),
|
||||
.ab_pow6_im (ab_pow6_im3 ),
|
||||
.ab_pow7_re (ab_pow7_re3 ),
|
||||
.ab_pow7_im (ab_pow7_im3 ),
|
||||
.b_pow8_re (b_pow8_re3 ),
|
||||
.b_pow8_im (b_pow8_im3 ),
|
||||
.IIRout_p0 (IIRout3_p0 ),
|
||||
.IIRout_p1 (IIRout3_p1 ),
|
||||
.IIRout_p2 (IIRout3_p2 ),
|
||||
.IIRout_p3 (IIRout3_p3 ),
|
||||
.IIRout_p4 (IIRout3_p4 ),
|
||||
.IIRout_p5 (IIRout3_p5 ),
|
||||
.IIRout_p6 (IIRout3_p6 ),
|
||||
.IIRout_p7 (IIRout3_p7 )
|
||||
);
|
||||
wire signed [15:0] IIRout4_p0;
|
||||
wire signed [15:0] IIRout4_p1;
|
||||
wire signed [15:0] IIRout4_p2;
|
||||
wire signed [15:0] IIRout4_p3;
|
||||
wire signed [15:0] IIRout4_p4;
|
||||
wire signed [15:0] IIRout4_p5;
|
||||
wire signed [15:0] IIRout4_p6;
|
||||
wire signed [15:0] IIRout4_p7;
|
||||
IIR_top_ref inst_IIR_top_ref_4 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.IIRin_p0 (IIRin_p0 ),
|
||||
.IIRin_p1 (IIRin_p1 ),
|
||||
.IIRin_p2 (IIRin_p2 ),
|
||||
.IIRin_p3 (IIRin_p3 ),
|
||||
.IIRin_p4 (IIRin_p4 ),
|
||||
.IIRin_p5 (IIRin_p5 ),
|
||||
.IIRin_p6 (IIRin_p6 ),
|
||||
.IIRin_p7 (IIRin_p7 ),
|
||||
.a_re (a_re4 ),
|
||||
.a_im (a_im4 ),
|
||||
.ab_re (ab_re4 ),
|
||||
.ab_im (ab_im4 ),
|
||||
.abb_re (abb_re4 ),
|
||||
.abb_im (abb_im4 ),
|
||||
.ab_pow3_re (ab_pow3_re4 ),
|
||||
.ab_pow3_im (ab_pow3_im4 ),
|
||||
.ab_pow4_re (ab_pow4_re4 ),
|
||||
.ab_pow4_im (ab_pow4_im4 ),
|
||||
.ab_pow5_re (ab_pow5_re4 ),
|
||||
.ab_pow5_im (ab_pow5_im4 ),
|
||||
.ab_pow6_re (ab_pow6_re4 ),
|
||||
.ab_pow6_im (ab_pow6_im4 ),
|
||||
.ab_pow7_re (ab_pow7_re4 ),
|
||||
.ab_pow7_im (ab_pow7_im4 ),
|
||||
.b_pow8_re (b_pow8_re4 ),
|
||||
.b_pow8_im (b_pow8_im4 ),
|
||||
.IIRout_p0 (IIRout4_p0 ),
|
||||
.IIRout_p1 (IIRout4_p1 ),
|
||||
.IIRout_p2 (IIRout4_p2 ),
|
||||
.IIRout_p3 (IIRout4_p3 ),
|
||||
.IIRout_p4 (IIRout4_p4 ),
|
||||
.IIRout_p5 (IIRout4_p5 ),
|
||||
.IIRout_p6 (IIRout4_p6 ),
|
||||
.IIRout_p7 (IIRout4_p7 )
|
||||
);
|
||||
wire signed [15:0] IIRout5_p0;
|
||||
wire signed [15:0] IIRout5_p1;
|
||||
wire signed [15:0] IIRout5_p2;
|
||||
wire signed [15:0] IIRout5_p3;
|
||||
wire signed [15:0] IIRout5_p4;
|
||||
wire signed [15:0] IIRout5_p5;
|
||||
wire signed [15:0] IIRout5_p6;
|
||||
wire signed [15:0] IIRout5_p7;
|
||||
IIR_top_ref inst_IIR_top_ref_5 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.IIRin_p0 (IIRin_p0 ),
|
||||
.IIRin_p1 (IIRin_p1 ),
|
||||
.IIRin_p2 (IIRin_p2 ),
|
||||
.IIRin_p3 (IIRin_p3 ),
|
||||
.IIRin_p4 (IIRin_p4 ),
|
||||
.IIRin_p5 (IIRin_p5 ),
|
||||
.IIRin_p6 (IIRin_p6 ),
|
||||
.IIRin_p7 (IIRin_p7 ),
|
||||
.a_re (a_re5 ),
|
||||
.a_im (a_im5 ),
|
||||
.ab_re (ab_re5 ),
|
||||
.ab_im (ab_im5 ),
|
||||
.abb_re (abb_re5 ),
|
||||
.abb_im (abb_im5 ),
|
||||
.ab_pow3_re (ab_pow3_re5 ),
|
||||
.ab_pow3_im (ab_pow3_im5 ),
|
||||
.ab_pow4_re (ab_pow4_re5 ),
|
||||
.ab_pow4_im (ab_pow4_im5 ),
|
||||
.ab_pow5_re (ab_pow5_re5 ),
|
||||
.ab_pow5_im (ab_pow5_im5 ),
|
||||
.ab_pow6_re (ab_pow6_re5 ),
|
||||
.ab_pow6_im (ab_pow6_im5 ),
|
||||
.ab_pow7_re (ab_pow7_re5 ),
|
||||
.ab_pow7_im (ab_pow7_im5 ),
|
||||
.b_pow8_re (b_pow8_re5 ),
|
||||
.b_pow8_im (b_pow8_im5 ),
|
||||
.IIRout_p0 (IIRout5_p0 ),
|
||||
.IIRout_p1 (IIRout5_p1 ),
|
||||
.IIRout_p2 (IIRout5_p2 ),
|
||||
.IIRout_p3 (IIRout5_p3 ),
|
||||
.IIRout_p4 (IIRout5_p4 ),
|
||||
.IIRout_p5 (IIRout5_p5 ),
|
||||
.IIRout_p6 (IIRout5_p6 ),
|
||||
.IIRout_p7 (IIRout5_p7 )
|
||||
);
|
||||
|
||||
|
||||
wire signed [18:0] dout_p0_r0;
|
||||
wire signed [18:0] dout_p1_r0;
|
||||
wire signed [18:0] dout_p2_r0;
|
||||
wire signed [18:0] dout_p3_r0;
|
||||
wire signed [18:0] dout_p4_r0;
|
||||
wire signed [18:0] dout_p5_r0;
|
||||
wire signed [18:0] dout_p6_r0;
|
||||
wire signed [18:0] dout_p7_r0;
|
||||
|
||||
assign dout_p0_r0 = din_p0_r5 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0;
|
||||
assign dout_p1_r0 = din_p1_r5 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1;
|
||||
assign dout_p2_r0 = din_p2_r5 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2;
|
||||
assign dout_p3_r0 = din_p3_r5 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3;
|
||||
assign dout_p4_r0 = din_p4_r5 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4;
|
||||
assign dout_p5_r0 = din_p5_r5 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5;
|
||||
assign dout_p6_r0 = din_p6_r5 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6;
|
||||
assign dout_p7_r0 = din_p7_r5 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7;
|
||||
|
||||
reg signed [18:0] dout_p0_r1;
|
||||
|
||||
reg signed [15:0] dout_p [7:0];
|
||||
wire signed [18:0] dout_p_r0 [0:7];
|
||||
assign dout_p_r0[0] = dout_p0_r0;
|
||||
assign dout_p_r0[1] = dout_p1_r0;
|
||||
assign dout_p_r0[2] = dout_p2_r0;
|
||||
assign dout_p_r0[3] = dout_p3_r0;
|
||||
assign dout_p_r0[4] = dout_p4_r0;
|
||||
assign dout_p_r0[5] = dout_p5_r0;
|
||||
assign dout_p_r0[6] = dout_p6_r0;
|
||||
assign dout_p_r0[7] = dout_p7_r0;
|
||||
|
||||
integer i;
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (i = 0; i < 8; i = i + 1) begin
|
||||
dout_p[i] <= 'h0;
|
||||
end
|
||||
end
|
||||
else if (en) begin
|
||||
for (i = 0; i < 8; i = i + 1) begin
|
||||
if (dout_p_r0[i][16:15] == 2'b01)
|
||||
dout_p[i] <= 16'd32767;
|
||||
else if (dout_p_r0[i][16:15] == 2'b10)
|
||||
dout_p[i] <= -16'd32768;
|
||||
else
|
||||
dout_p[i] <= dout_p_r0[i][15:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign dout_p0 = dout_p[0];
|
||||
assign dout_p1 = dout_p[1];
|
||||
assign dout_p2 = dout_p[2];
|
||||
assign dout_p3 = dout_p[3];
|
||||
assign dout_p4 = dout_p[4];
|
||||
assign dout_p5 = dout_p[5];
|
||||
assign dout_p6 = dout_p[6];
|
||||
assign dout_p7 = dout_p[7];
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
dout_p0_r1 <= 16'd0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
dout_p0_r1 <= dout_p0_r0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_p0_r1 <= dout_p0_r1;
|
||||
end
|
||||
|
||||
reg signed [18:0] dout_p0_r2;
|
||||
reg signed [18:0] dout_p0_r3;
|
||||
reg signed [18:0] dout_p0_r4;
|
||||
reg signed [18:0] dout_p0_r5;
|
||||
reg signed [18:0] dout_p0_r6;
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
dout_p0_r2 <= 16'd0;
|
||||
dout_p0_r3 <= 16'd0;
|
||||
dout_p0_r4 <= 16'd0;
|
||||
dout_p0_r5 <= 16'd0;
|
||||
dout_p0_r6 <= 16'd0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
dout_p0_r2 <= dout_p0_r1;
|
||||
dout_p0_r3 <= dout_p0_r2;
|
||||
dout_p0_r4 <= dout_p0_r3;
|
||||
dout_p0_r5 <= dout_p0_r4;
|
||||
dout_p0_r6 <= dout_p0_r5;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_p0_r2 <= dout_p0_r2;
|
||||
dout_p0_r3 <= dout_p0_r3;
|
||||
dout_p0_r4 <= dout_p0_r4;
|
||||
dout_p0_r5 <= dout_p0_r5;
|
||||
dout_p0_r6 <= dout_p0_r6;
|
||||
end
|
||||
|
||||
reg vldo_diff_r1;
|
||||
reg vldo_diff_r2;
|
||||
reg vldo_diff_r3;
|
||||
reg vldo_diff_r4;
|
||||
reg vldo_diff_r5;
|
||||
reg vldo_diff_r6;
|
||||
reg vldo_diff_r7;
|
||||
reg vldo_diff_r8;
|
||||
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
vldo_diff_r1 <= 16'd0;
|
||||
vldo_diff_r2 <= 16'd0;
|
||||
vldo_diff_r3 <= 16'd0;
|
||||
vldo_diff_r4 <= 16'd0;
|
||||
vldo_diff_r5 <= 16'd0;
|
||||
vldo_diff_r6 <= 16'd0;
|
||||
vldo_diff_r7 <= 16'd0;
|
||||
vldo_diff_r8 <= 16'd0;
|
||||
end
|
||||
else if(en) begin
|
||||
vldo_diff_r1 <= vldo_diff;
|
||||
vldo_diff_r2 <= vldo_diff_r1;
|
||||
vldo_diff_r3 <= vldo_diff_r2;
|
||||
vldo_diff_r4 <= vldo_diff_r3;
|
||||
vldo_diff_r5 <= vldo_diff_r4;
|
||||
vldo_diff_r6 <= vldo_diff_r5;
|
||||
vldo_diff_r7 <= vldo_diff_r6;
|
||||
vldo_diff_r8 <= vldo_diff_r7;
|
||||
end
|
||||
else begin
|
||||
vldo_diff_r1 <= vldo_diff_r1;
|
||||
vldo_diff_r2 <= vldo_diff_r2;
|
||||
vldo_diff_r3 <= vldo_diff_r3;
|
||||
vldo_diff_r4 <= vldo_diff_r4;
|
||||
vldo_diff_r5 <= vldo_diff_r5;
|
||||
vldo_diff_r6 <= vldo_diff_r6;
|
||||
vldo_diff_r7 <= vldo_diff_r7;
|
||||
vldo_diff_r8 <= vldo_diff_r8;
|
||||
end
|
||||
end
|
||||
wire vldo_r0_h;
|
||||
wire vldo_r0_l;
|
||||
reg vldo_r0;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
vldo_r0 <= 0;
|
||||
end
|
||||
else if(vldo_r0_h)begin
|
||||
vldo_r0 <= 1;
|
||||
end
|
||||
else if(vldo_r0_l)begin
|
||||
vldo_r0 <= 0;
|
||||
end
|
||||
end
|
||||
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
|
||||
assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ;
|
||||
assign vldo = vldo_r0;
|
||||
endmodule
|
||||
|
||||
236
rtl/ref/diff_p.v
236
rtl/ref/diff_p.v
|
|
@ -1,236 +0,0 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module diff_p_ref
|
||||
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input vldi
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,output vldo
|
||||
,output signed [15:0] dout_p0
|
||||
,output signed [15:0] dout_p1
|
||||
,output signed [15:0] dout_p2
|
||||
,output signed [15:0] dout_p3
|
||||
,output signed [15:0] dout_p4
|
||||
,output signed [15:0] dout_p5
|
||||
,output signed [15:0] dout_p6
|
||||
,output signed [15:0] dout_p7
|
||||
,output signed [15:0] diff_p0
|
||||
,output signed [15:0] diff_p1
|
||||
,output signed [15:0] diff_p2
|
||||
,output signed [15:0] diff_p3
|
||||
,output signed [15:0] diff_p4
|
||||
,output signed [15:0] diff_p5
|
||||
,output signed [15:0] diff_p6
|
||||
,output signed [15:0] diff_p7
|
||||
|
||||
);
|
||||
|
||||
wire signed [15:0] din_p0_r0;
|
||||
wire signed [15:0] din_p1_r0;
|
||||
wire signed [15:0] din_p2_r0;
|
||||
wire signed [15:0] din_p3_r0;
|
||||
wire signed [15:0] din_p4_r0;
|
||||
wire signed [15:0] din_p5_r0;
|
||||
wire signed [15:0] din_p6_r0;
|
||||
wire signed [15:0] din_p7_r0;
|
||||
|
||||
s2p_2_ref inst1_s2p_2_ref (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din0),
|
||||
.en (vldi),
|
||||
.dout0 (din_p0_r0),
|
||||
.dout1 (din_p4_r0)
|
||||
,.vldo( vldo)
|
||||
);
|
||||
s2p_2_ref inst2_s2p_2_ref (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din1),
|
||||
.en (vldi),
|
||||
.dout0 (din_p1_r0),
|
||||
.dout1 (din_p5_r0)
|
||||
,.vldo( )
|
||||
);
|
||||
s2p_2_ref inst3_s2p_2_ref (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din2),
|
||||
.en (vldi),
|
||||
.dout0 (din_p2_r0),
|
||||
.dout1 (din_p6_r0)
|
||||
,.vldo( )
|
||||
);
|
||||
s2p_2_ref inst4_s2p_2_ref (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din3),
|
||||
.en (vldi),
|
||||
.dout0 (din_p3_r0),
|
||||
.dout1 (din_p7_r0)
|
||||
,.vldo( )
|
||||
);
|
||||
|
||||
|
||||
reg signed [15:0] din_p0_r1;
|
||||
reg signed [15:0] din_p1_r1;
|
||||
reg signed [15:0] din_p2_r1;
|
||||
reg signed [15:0] din_p3_r1;
|
||||
reg signed [15:0] din_p4_r1;
|
||||
reg signed [15:0] din_p5_r1;
|
||||
reg signed [15:0] din_p6_r1;
|
||||
reg signed [15:0] din_p7_r1;
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
din_p0_r1 <= 'h0;
|
||||
din_p1_r1 <= 'h0;
|
||||
din_p2_r1 <= 'h0;
|
||||
din_p3_r1 <= 'h0;
|
||||
din_p4_r1 <= 'h0;
|
||||
din_p5_r1 <= 'h0;
|
||||
din_p6_r1 <= 'h0;
|
||||
din_p7_r1 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_p0_r1 <= din_p0_r0;
|
||||
din_p1_r1 <= din_p1_r0;
|
||||
din_p2_r1 <= din_p2_r0;
|
||||
din_p3_r1 <= din_p3_r0;
|
||||
din_p4_r1 <= din_p4_r0;
|
||||
din_p5_r1 <= din_p5_r0;
|
||||
din_p6_r1 <= din_p6_r0;
|
||||
din_p7_r1 <= din_p7_r0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_p0_r1 <= din_p0_r1;
|
||||
din_p1_r1 <= din_p1_r1;
|
||||
din_p2_r1 <= din_p2_r1;
|
||||
din_p3_r1 <= din_p3_r1;
|
||||
din_p4_r1 <= din_p4_r1;
|
||||
din_p5_r1 <= din_p5_r1;
|
||||
din_p6_r1 <= din_p6_r1;
|
||||
din_p7_r1 <= din_p7_r1;
|
||||
end
|
||||
|
||||
assign dout_p0 = din_p0_r1;
|
||||
assign dout_p1 = din_p1_r1;
|
||||
assign dout_p2 = din_p2_r1;
|
||||
assign dout_p3 = din_p3_r1;
|
||||
assign dout_p4 = din_p4_r1;
|
||||
assign dout_p5 = din_p5_r1;
|
||||
assign dout_p6 = din_p6_r1;
|
||||
assign dout_p7 = din_p7_r1;
|
||||
|
||||
wire signed [15:0] diff_p0_r0;
|
||||
wire signed [15:0] diff_p1_r0;
|
||||
wire signed [15:0] diff_p2_r0;
|
||||
wire signed [15:0] diff_p3_r0;
|
||||
wire signed [15:0] diff_p4_r0;
|
||||
wire signed [15:0] diff_p5_r0;
|
||||
wire signed [15:0] diff_p6_r0;
|
||||
wire signed [15:0] diff_p7_r0;
|
||||
|
||||
assign diff_p0_r0 = din_p0_r0 - din_p7_r1;
|
||||
assign diff_p1_r0 = din_p1_r0 - din_p0_r0;
|
||||
assign diff_p2_r0 = din_p2_r0 - din_p1_r0;
|
||||
assign diff_p3_r0 = din_p3_r0 - din_p2_r0;
|
||||
assign diff_p4_r0 = din_p4_r0 - din_p3_r0;
|
||||
assign diff_p5_r0 = din_p5_r0 - din_p4_r0;
|
||||
assign diff_p6_r0 = din_p6_r0 - din_p5_r0;
|
||||
assign diff_p7_r0 = din_p7_r0 - din_p6_r0;
|
||||
|
||||
reg signed [15:0] diff_p0_r1;
|
||||
reg signed [15:0] diff_p1_r1;
|
||||
reg signed [15:0] diff_p2_r1;
|
||||
reg signed [15:0] diff_p3_r1;
|
||||
reg signed [15:0] diff_p4_r1;
|
||||
reg signed [15:0] diff_p5_r1;
|
||||
reg signed [15:0] diff_p6_r1;
|
||||
reg signed [15:0] diff_p7_r1;
|
||||
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
diff_p0_r1 <= 0;
|
||||
diff_p1_r1 <= 0;
|
||||
diff_p2_r1 <= 0;
|
||||
diff_p3_r1 <= 0;
|
||||
diff_p4_r1 <= 0;
|
||||
diff_p5_r1 <= 0;
|
||||
diff_p6_r1 <= 0;
|
||||
diff_p7_r1 <= 0;
|
||||
|
||||
end
|
||||
else if(en)begin
|
||||
diff_p0_r1 <= diff_p0_r0;
|
||||
diff_p1_r1 <= diff_p1_r0;
|
||||
diff_p2_r1 <= diff_p2_r0;
|
||||
diff_p3_r1 <= diff_p3_r0;
|
||||
diff_p4_r1 <= diff_p4_r0;
|
||||
diff_p5_r1 <= diff_p5_r0;
|
||||
diff_p6_r1 <= diff_p6_r0;
|
||||
diff_p7_r1 <= diff_p7_r0;
|
||||
end
|
||||
else begin
|
||||
diff_p0_r1 <= diff_p0_r1;
|
||||
diff_p1_r1 <= diff_p1_r1;
|
||||
diff_p2_r1 <= diff_p2_r1;
|
||||
diff_p3_r1 <= diff_p3_r1;
|
||||
diff_p4_r1 <= diff_p4_r1;
|
||||
diff_p5_r1 <= diff_p5_r1;
|
||||
diff_p6_r1 <= diff_p6_r1;
|
||||
diff_p7_r1 <= diff_p7_r1;
|
||||
end
|
||||
end
|
||||
|
||||
assign diff_p0 = diff_p0_r1;
|
||||
assign diff_p1 = diff_p1_r1;
|
||||
assign diff_p2 = diff_p2_r1;
|
||||
assign diff_p3 = diff_p3_r1;
|
||||
assign diff_p4 = diff_p4_r1;
|
||||
assign diff_p5 = diff_p5_r1;
|
||||
assign diff_p6 = diff_p6_r1;
|
||||
assign diff_p7 = diff_p7_r1;
|
||||
|
||||
endmodule
|
||||
|
||||
110
rtl/ref/mult_C.v
110
rtl/ref/mult_C.v
|
|
@ -1,110 +0,0 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : mult_C.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-28 thfu
|
||||
//2024-05-28 10:22:18
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module mult_C_ref #(
|
||||
parameter integer A_width = 8
|
||||
,parameter integer B_width = 8
|
||||
,parameter integer C_width = 8
|
||||
,parameter integer D_width = 8
|
||||
,parameter integer frac_coef_width = 31//division
|
||||
|
||||
)
|
||||
|
||||
(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
a,
|
||||
b,
|
||||
c,
|
||||
d,
|
||||
Re,
|
||||
Im
|
||||
);
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input signed [A_width-1:0] a;
|
||||
input signed [B_width-1:0] b;
|
||||
input signed [C_width-1:0] c;
|
||||
input signed [D_width-1:0] d;
|
||||
|
||||
output signed [A_width+C_width-frac_coef_width-1:0] Re;
|
||||
output signed [A_width+D_width-frac_coef_width-1:0] Im;
|
||||
|
||||
wire signed [A_width+C_width-1:0] ac;
|
||||
wire signed [B_width+D_width-1:0] bd;
|
||||
wire signed [A_width+D_width-1:0] ad;
|
||||
wire signed [B_width+C_width-1:0] bc;
|
||||
|
||||
|
||||
|
||||
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ac )
|
||||
);
|
||||
|
||||
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bd )
|
||||
);
|
||||
|
||||
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ad )
|
||||
);
|
||||
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bc )
|
||||
);
|
||||
wire signed [A_width+C_width:0] Re_tmp;
|
||||
wire signed [A_width+D_width:0] Im_tmp;
|
||||
|
||||
assign Re_tmp = ac - bd;
|
||||
assign Im_tmp = ad + bc;
|
||||
|
||||
wire signed [A_width+C_width:0] Re_round;
|
||||
wire signed [A_width+D_width:0] Im_round;
|
||||
|
||||
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
|
||||
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
|
||||
|
||||
assign Re = Re_round[A_width+D_width-1:frac_coef_width];
|
||||
assign Im = Im_round[A_width+D_width-1:frac_coef_width];
|
||||
|
||||
endmodule
|
||||
121
rtl/ref/s2p_2.v
121
rtl/ref/s2p_2.v
|
|
@ -1,121 +0,0 @@
|
|||
module s2p_2_ref (
|
||||
input clk,
|
||||
input rst_n,
|
||||
input [15:0] din,
|
||||
input en,
|
||||
output [15:0] dout0,
|
||||
output [15:0] dout1,
|
||||
output vldo
|
||||
);
|
||||
|
||||
reg en_r1;
|
||||
reg en_r2;
|
||||
reg en_r3;
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
en_r1 <= 0;
|
||||
en_r2 <= 0;
|
||||
en_r3 <= 0;
|
||||
end
|
||||
else begin
|
||||
en_r1 <= en;
|
||||
en_r2 <= en_r1;
|
||||
end
|
||||
end
|
||||
assign vldo = en_r2;
|
||||
|
||||
reg cnt;
|
||||
wire add_cnt;
|
||||
wire end_cnt;
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(!rst_n)begin
|
||||
cnt <= 0;
|
||||
end
|
||||
else if(add_cnt)begin
|
||||
if(end_cnt)
|
||||
cnt <= 0;
|
||||
else
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
else begin
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign add_cnt = en == 1'b1;
|
||||
assign end_cnt = add_cnt && cnt== 2 - 1 ;
|
||||
|
||||
|
||||
reg [ 15: 0] dout0_r0;
|
||||
reg [ 15: 0] dout1_r0;
|
||||
wire dout0_en;
|
||||
wire dout1_en;
|
||||
wire dout0_hold;
|
||||
wire dout1_hold;
|
||||
|
||||
always @(*)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
end
|
||||
else if(dout0_en)begin
|
||||
dout0_r0 = din;
|
||||
end
|
||||
else if(dout1_en)begin
|
||||
dout1_r0 = din;
|
||||
end
|
||||
else begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
|
||||
end
|
||||
end
|
||||
assign dout0_en = add_cnt && cnt == 0;
|
||||
assign dout1_en = add_cnt && cnt == 1;
|
||||
|
||||
reg [ 15: 0] dout0_r1;
|
||||
reg [ 15: 0] dout1_r1;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
else if(en)begin
|
||||
dout0_r1 <= dout0_r0;
|
||||
dout1_r1 <= dout1_r0;
|
||||
end
|
||||
else if(dout0_hold)begin
|
||||
dout0_r1 <= dout0_r1;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
else if(dout1_hold)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= dout1_r1;
|
||||
end
|
||||
else begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
|
||||
end
|
||||
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
|
||||
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
|
||||
|
||||
reg [ 15: 0] dout0_r2;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r2 <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
dout0_r2 <= dout0_r1;
|
||||
end
|
||||
end
|
||||
|
||||
assign dout0 = dout0_r2;
|
||||
assign dout1 = dout1_r1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,706 @@
|
|||
module CoefGen #(
|
||||
parameter data_in_width = 32
|
||||
,parameter coef_width = 32
|
||||
,parameter frac_data_out_width = 20//X for in,5
|
||||
,parameter frac_coef_width = 31//division
|
||||
)
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input [5:0] vldi
|
||||
,input signed [31:0] a0_re
|
||||
,input signed [31:0] a0_im
|
||||
,input signed [31:0] b0_re
|
||||
,input signed [31:0] b0_im
|
||||
,input signed [31:0] a1_re
|
||||
,input signed [31:0] a1_im
|
||||
,input signed [31:0] b1_re
|
||||
,input signed [31:0] b1_im
|
||||
,input signed [31:0] a2_re
|
||||
,input signed [31:0] a2_im
|
||||
,input signed [31:0] b2_re
|
||||
,input signed [31:0] b2_im
|
||||
,input signed [31:0] a3_re
|
||||
,input signed [31:0] a3_im
|
||||
,input signed [31:0] b3_re
|
||||
,input signed [31:0] b3_im
|
||||
,input signed [31:0] a4_re
|
||||
,input signed [31:0] a4_im
|
||||
,input signed [31:0] b4_re
|
||||
,input signed [31:0] b4_im
|
||||
,input signed [31:0] a5_re
|
||||
,input signed [31:0] a5_im
|
||||
,input signed [31:0] b5_re
|
||||
,input signed [31:0] b5_im
|
||||
,output reg signed [31:0] a_re0
|
||||
,output reg signed [31:0] a_im0
|
||||
,output reg signed [31:0] b_re0
|
||||
,output reg signed [31:0] b_im0
|
||||
,output reg signed [31:0] ab_re0
|
||||
,output reg signed [31:0] ab_im0
|
||||
,output reg signed [31:0] abb_re0
|
||||
,output reg signed [31:0] abb_im0
|
||||
,output reg signed [31:0] ab_pow3_re0
|
||||
,output reg signed [31:0] ab_pow3_im0
|
||||
,output reg signed [31:0] ab_pow4_re0
|
||||
,output reg signed [31:0] ab_pow4_im0
|
||||
,output reg signed [31:0] ab_pow5_re0
|
||||
,output reg signed [31:0] ab_pow5_im0
|
||||
,output reg signed [31:0] ab_pow6_re0
|
||||
,output reg signed [31:0] ab_pow6_im0
|
||||
,output reg signed [31:0] ab_pow7_re0
|
||||
,output reg signed [31:0] ab_pow7_im0
|
||||
,output reg signed [31:0] b_pow8_re0
|
||||
,output reg signed [31:0] b_pow8_im0
|
||||
,output reg signed [31:0] a_re1
|
||||
,output reg signed [31:0] a_im1
|
||||
,output reg signed [31:0] b_re1
|
||||
,output reg signed [31:0] b_im1
|
||||
,output reg signed [31:0] ab_re1
|
||||
,output reg signed [31:0] ab_im1
|
||||
,output reg signed [31:0] abb_re1
|
||||
,output reg signed [31:0] abb_im1
|
||||
,output reg signed [31:0] ab_pow3_re1
|
||||
,output reg signed [31:0] ab_pow3_im1
|
||||
,output reg signed [31:0] ab_pow4_re1
|
||||
,output reg signed [31:0] ab_pow4_im1
|
||||
,output reg signed [31:0] ab_pow5_re1
|
||||
,output reg signed [31:0] ab_pow5_im1
|
||||
,output reg signed [31:0] ab_pow6_re1
|
||||
,output reg signed [31:0] ab_pow6_im1
|
||||
,output reg signed [31:0] ab_pow7_re1
|
||||
,output reg signed [31:0] ab_pow7_im1
|
||||
,output reg signed [31:0] b_pow8_re1
|
||||
,output reg signed [31:0] b_pow8_im1
|
||||
,output reg signed [31:0] a_re2
|
||||
,output reg signed [31:0] a_im2
|
||||
,output reg signed [31:0] b_re2
|
||||
,output reg signed [31:0] b_im2
|
||||
,output reg signed [31:0] ab_re2
|
||||
,output reg signed [31:0] ab_im2
|
||||
,output reg signed [31:0] abb_re2
|
||||
,output reg signed [31:0] abb_im2
|
||||
,output reg signed [31:0] ab_pow3_re2
|
||||
,output reg signed [31:0] ab_pow3_im2
|
||||
,output reg signed [31:0] ab_pow4_re2
|
||||
,output reg signed [31:0] ab_pow4_im2
|
||||
,output reg signed [31:0] ab_pow5_re2
|
||||
,output reg signed [31:0] ab_pow5_im2
|
||||
,output reg signed [31:0] ab_pow6_re2
|
||||
,output reg signed [31:0] ab_pow6_im2
|
||||
,output reg signed [31:0] ab_pow7_re2
|
||||
,output reg signed [31:0] ab_pow7_im2
|
||||
,output reg signed [31:0] b_pow8_re2
|
||||
,output reg signed [31:0] b_pow8_im2
|
||||
,output reg signed [31:0] a_re3
|
||||
,output reg signed [31:0] a_im3
|
||||
,output reg signed [31:0] b_re3
|
||||
,output reg signed [31:0] b_im3
|
||||
,output reg signed [31:0] ab_re3
|
||||
,output reg signed [31:0] ab_im3
|
||||
,output reg signed [31:0] abb_re3
|
||||
,output reg signed [31:0] abb_im3
|
||||
,output reg signed [31:0] ab_pow3_re3
|
||||
,output reg signed [31:0] ab_pow3_im3
|
||||
,output reg signed [31:0] ab_pow4_re3
|
||||
,output reg signed [31:0] ab_pow4_im3
|
||||
,output reg signed [31:0] ab_pow5_re3
|
||||
,output reg signed [31:0] ab_pow5_im3
|
||||
,output reg signed [31:0] ab_pow6_re3
|
||||
,output reg signed [31:0] ab_pow6_im3
|
||||
,output reg signed [31:0] ab_pow7_re3
|
||||
,output reg signed [31:0] ab_pow7_im3
|
||||
,output reg signed [31:0] b_pow8_re3
|
||||
,output reg signed [31:0] b_pow8_im3
|
||||
,output reg signed [31:0] a_re4
|
||||
,output reg signed [31:0] a_im4
|
||||
,output reg signed [31:0] b_re4
|
||||
,output reg signed [31:0] b_im4
|
||||
,output reg signed [31:0] ab_re4
|
||||
,output reg signed [31:0] ab_im4
|
||||
,output reg signed [31:0] abb_re4
|
||||
,output reg signed [31:0] abb_im4
|
||||
,output reg signed [31:0] ab_pow3_re4
|
||||
,output reg signed [31:0] ab_pow3_im4
|
||||
,output reg signed [31:0] ab_pow4_re4
|
||||
,output reg signed [31:0] ab_pow4_im4
|
||||
,output reg signed [31:0] ab_pow5_re4
|
||||
,output reg signed [31:0] ab_pow5_im4
|
||||
,output reg signed [31:0] ab_pow6_re4
|
||||
,output reg signed [31:0] ab_pow6_im4
|
||||
,output reg signed [31:0] ab_pow7_re4
|
||||
,output reg signed [31:0] ab_pow7_im4
|
||||
,output reg signed [31:0] b_pow8_re4
|
||||
,output reg signed [31:0] b_pow8_im4
|
||||
,output reg signed [31:0] a_re5
|
||||
,output reg signed [31:0] a_im5
|
||||
,output reg signed [31:0] b_re5
|
||||
,output reg signed [31:0] b_im5
|
||||
,output reg signed [31:0] ab_re5
|
||||
,output reg signed [31:0] ab_im5
|
||||
,output reg signed [31:0] abb_re5
|
||||
,output reg signed [31:0] abb_im5
|
||||
,output reg signed [31:0] ab_pow3_re5
|
||||
,output reg signed [31:0] ab_pow3_im5
|
||||
,output reg signed [31:0] ab_pow4_re5
|
||||
,output reg signed [31:0] ab_pow4_im5
|
||||
,output reg signed [31:0] ab_pow5_re5
|
||||
,output reg signed [31:0] ab_pow5_im5
|
||||
,output reg signed [31:0] ab_pow6_re5
|
||||
,output reg signed [31:0] ab_pow6_im5
|
||||
,output reg signed [31:0] ab_pow7_re5
|
||||
,output reg signed [31:0] ab_pow7_im5
|
||||
,output reg signed [31:0] b_pow8_re5
|
||||
,output reg signed [31:0] b_pow8_im5
|
||||
);
|
||||
|
||||
|
||||
reg vldi_or_r1;
|
||||
wire vldi_or = | vldi;
|
||||
sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn);
|
||||
|
||||
reg signed [data_in_width-1:0] a_re_r1;
|
||||
reg signed [data_in_width-1:0] a_im_r1;
|
||||
reg signed [data_in_width-1:0] b_re_r1;
|
||||
reg signed [data_in_width-1:0] b_im_r1;
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(rstn == 1'b0) begin
|
||||
a_re_r1 <= 'h0;
|
||||
a_im_r1 <= 'h0;
|
||||
b_re_r1 <= 'h0;
|
||||
b_im_r1 <= 'h0;
|
||||
end
|
||||
else if(|vldi) begin
|
||||
case(1'b1)
|
||||
vldi[0]: begin
|
||||
a_re_r1 <= a0_re;
|
||||
a_im_r1 <= a0_im;
|
||||
b_re_r1 <= b0_re;
|
||||
b_im_r1 <= b0_im;
|
||||
end
|
||||
vldi[1]: begin
|
||||
a_re_r1 <= a1_re;
|
||||
a_im_r1 <= a1_im;
|
||||
b_re_r1 <= b1_re;
|
||||
b_im_r1 <= b1_im;
|
||||
end
|
||||
vldi[2]: begin
|
||||
a_re_r1 <= a2_re;
|
||||
a_im_r1 <= a2_im;
|
||||
b_re_r1 <= b2_re;
|
||||
b_im_r1 <= b2_im;
|
||||
end
|
||||
vldi[3]: begin
|
||||
a_re_r1 <= a3_re;
|
||||
a_im_r1 <= a3_im;
|
||||
b_re_r1 <= b3_re;
|
||||
b_im_r1 <= b3_im;
|
||||
end
|
||||
vldi[4]: begin
|
||||
a_re_r1 <= a4_re;
|
||||
a_im_r1 <= a4_im;
|
||||
b_re_r1 <= b4_re;
|
||||
b_im_r1 <= b4_im;
|
||||
end
|
||||
vldi[5]: begin
|
||||
a_re_r1 <= a5_re;
|
||||
a_im_r1 <= a5_im;
|
||||
b_re_r1 <= b5_re;
|
||||
b_im_r1 <= b5_im;
|
||||
end
|
||||
// default: begin
|
||||
// a_re_r1 <= a_re[0];
|
||||
// a_im_r1 <= a_im[0];
|
||||
// b_re_r1 <= b_re[0];
|
||||
// b_im_r1 <= b_im[0];
|
||||
// end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg en;
|
||||
reg en_r1;
|
||||
sirv_gnrl_dffr #(1) dff_en_1(en, en_r1 ,clk,rstn);
|
||||
|
||||
reg [3:0] cnt0;
|
||||
wire add_cnt0;
|
||||
wire end_cnt0;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(!rstn)begin
|
||||
cnt0 <= 0;
|
||||
end
|
||||
else if(add_cnt0)begin
|
||||
if(end_cnt0)
|
||||
cnt0 <= 0;
|
||||
else
|
||||
cnt0 <= cnt0 + 1;
|
||||
end
|
||||
end
|
||||
|
||||
assign add_cnt0 = en;
|
||||
assign end_cnt0 = add_cnt0 && cnt0== 8-1;
|
||||
|
||||
wire en_l;
|
||||
wire en_h;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
en <= 0;
|
||||
end
|
||||
else if(en_h)begin
|
||||
en <= 1;
|
||||
end
|
||||
else if(en_l)begin
|
||||
en <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
|
||||
assign en_l = end_cnt0;
|
||||
|
||||
reg signed [data_in_width-1:0] bin_re;
|
||||
reg signed [data_in_width-1:0] bin_im;
|
||||
wire signed [data_in_width-1:0] bout_re;
|
||||
wire signed [data_in_width-1:0] bout_im;
|
||||
always @(*)begin
|
||||
if(en_r1) begin
|
||||
bin_re <= bout_re;
|
||||
bin_im <= bout_im;
|
||||
end
|
||||
else begin
|
||||
bin_re <= 32'd2147483647;
|
||||
bin_im <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
mult_C
|
||||
#(
|
||||
.A_width(data_in_width)
|
||||
,.B_width(data_in_width)
|
||||
,.C_width(coef_width)
|
||||
,.D_width(coef_width)
|
||||
,.o_width(data_in_width)
|
||||
)
|
||||
inst_c1 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (bin_re ),
|
||||
.b (bin_im ),
|
||||
.c (b_re_r1 ),
|
||||
.d (b_im_r1 ),
|
||||
.Re (bout_re ),
|
||||
.Im (bout_im )
|
||||
);
|
||||
|
||||
|
||||
wire signed [data_in_width-1:0] abo_re;
|
||||
wire signed [data_in_width-1:0] abo_im;
|
||||
mult_C
|
||||
#(
|
||||
.A_width(data_in_width)
|
||||
,.B_width(data_in_width)
|
||||
,.C_width(coef_width)
|
||||
,.D_width(coef_width)
|
||||
,.o_width(data_in_width)
|
||||
)
|
||||
inst_c2 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (bin_re ),
|
||||
.b (bin_im ),
|
||||
.c (a_re_r1 ),
|
||||
.d (a_im_r1 ),
|
||||
.Re (abo_re ),
|
||||
.Im (abo_im )
|
||||
);
|
||||
|
||||
reg signed [coef_width-1 :0] ao_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ao_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_im_r1 ;
|
||||
reg signed [coef_width-1 :0] abb_re_r1 ;
|
||||
reg signed [coef_width-1 :0] abb_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow3_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow3_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow4_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow4_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow5_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow5_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow6_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow7_im_r1 ;
|
||||
reg signed [coef_width-1 :0] bo_re_r1 ;
|
||||
reg signed [coef_width-1 :0] bo_im_r1 ;
|
||||
reg signed [coef_width-1 :0] b_pow8_re_r1 ;
|
||||
reg signed [coef_width-1 :0] b_pow8_im_r1 ;
|
||||
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(!rstn)begin
|
||||
ao_re_r1 <= 0;
|
||||
ao_im_r1 <= 0;
|
||||
ab_re_r1 <= 0;
|
||||
ab_im_r1 <= 0;
|
||||
abb_re_r1 <= 0;
|
||||
abb_im_r1 <= 0;
|
||||
ab_pow3_re_r1 <= 0;
|
||||
ab_pow3_im_r1 <= 0;
|
||||
ab_pow4_re_r1 <= 0;
|
||||
ab_pow4_im_r1 <= 0;
|
||||
ab_pow5_re_r1 <= 0;
|
||||
ab_pow5_im_r1 <= 0;
|
||||
ab_pow6_re_r1 <= 0;
|
||||
ab_pow6_im_r1 <= 0;
|
||||
ab_pow7_re_r1 <= 0;
|
||||
ab_pow7_im_r1 <= 0;
|
||||
bo_re_r1 <= 0;
|
||||
bo_im_r1 <= 0;
|
||||
b_pow8_re_r1 <= 0;
|
||||
b_pow8_im_r1 <= 0;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 1 && en_r1)begin
|
||||
ao_re_r1 <= abo_re;
|
||||
ao_im_r1 <= abo_im;
|
||||
bo_re_r1 <= bin_re;
|
||||
bo_im_r1 <= bin_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 2 && en_r1)begin
|
||||
ab_re_r1 <= abo_re;
|
||||
ab_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 3 && en_r1)begin
|
||||
abb_re_r1 <= abo_re;
|
||||
abb_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 4 && en_r1)begin
|
||||
ab_pow3_re_r1 <= abo_re;
|
||||
ab_pow3_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 5 && en_r1)begin
|
||||
ab_pow4_re_r1 <= abo_re;
|
||||
ab_pow4_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 6 && en_r1)begin
|
||||
ab_pow5_re_r1 <= abo_re;
|
||||
ab_pow5_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 7 && en_r1)begin
|
||||
ab_pow6_re_r1 <= abo_re;
|
||||
ab_pow6_im_r1 <= abo_im;
|
||||
end
|
||||
else if(cnt0 == 0 && en_r1)begin
|
||||
ab_pow7_re_r1 <= abo_re;
|
||||
ab_pow7_im_r1 <= abo_im;
|
||||
b_pow8_re_r1 <= bin_re;
|
||||
b_pow8_im_r1 <= bin_im;
|
||||
end
|
||||
// else begin
|
||||
// end
|
||||
end
|
||||
|
||||
reg [5:0] vldi_r1;
|
||||
reg [5:0] vldi_r2;
|
||||
reg [5:0] vldi_r3;
|
||||
reg [5:0] vldi_r4;
|
||||
reg [5:0] vldi_r5;
|
||||
reg [5:0] vldi_r6;
|
||||
reg [5:0] vldi_r7;
|
||||
reg [5:0] vldi_r8;
|
||||
reg [5:0] vldi_r9;
|
||||
reg [5:0] vldi_r10;
|
||||
//syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_1(vldi,vldi_r1,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn);
|
||||
sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn);
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(!rstn) begin
|
||||
a_re0 <= 0;
|
||||
a_im0 <= 0;
|
||||
b_re0 <= 0;
|
||||
b_im0 <= 0;
|
||||
ab_re0 <= 0;
|
||||
ab_im0 <= 0;
|
||||
abb_re0 <= 0;
|
||||
abb_im0 <= 0;
|
||||
ab_pow3_re0 <= 0;
|
||||
ab_pow3_im0 <= 0;
|
||||
ab_pow4_re0 <= 0;
|
||||
ab_pow4_im0 <= 0;
|
||||
ab_pow5_re0 <= 0;
|
||||
ab_pow5_im0 <= 0;
|
||||
ab_pow6_re0 <= 0;
|
||||
ab_pow6_im0 <= 0;
|
||||
ab_pow7_re0 <= 0;
|
||||
ab_pow7_im0 <= 0;
|
||||
b_pow8_re0 <= 0;
|
||||
b_pow8_im0 <= 0;
|
||||
a_re1 <= 0;
|
||||
a_im1 <= 0;
|
||||
b_re1 <= 0;
|
||||
b_im1 <= 0;
|
||||
ab_re1 <= 0;
|
||||
ab_im1 <= 0;
|
||||
abb_re1 <= 0;
|
||||
abb_im1 <= 0;
|
||||
ab_pow3_re1 <= 0;
|
||||
ab_pow3_im1 <= 0;
|
||||
ab_pow4_re1 <= 0;
|
||||
ab_pow4_im1 <= 0;
|
||||
ab_pow5_re1 <= 0;
|
||||
ab_pow5_im1 <= 0;
|
||||
ab_pow6_re1 <= 0;
|
||||
ab_pow6_im1 <= 0;
|
||||
ab_pow7_re1 <= 0;
|
||||
ab_pow7_im1 <= 0;
|
||||
b_pow8_re1 <= 0;
|
||||
b_pow8_im1 <= 0;
|
||||
a_re2 <= 0;
|
||||
a_im2 <= 0;
|
||||
b_re2 <= 0;
|
||||
b_im2 <= 0;
|
||||
ab_re2 <= 0;
|
||||
ab_im2 <= 0;
|
||||
abb_re2 <= 0;
|
||||
abb_im2 <= 0;
|
||||
ab_pow3_re2 <= 0;
|
||||
ab_pow3_im2 <= 0;
|
||||
ab_pow4_re2 <= 0;
|
||||
ab_pow4_im2 <= 0;
|
||||
ab_pow5_re2 <= 0;
|
||||
ab_pow5_im2 <= 0;
|
||||
ab_pow6_re2 <= 0;
|
||||
ab_pow6_im2 <= 0;
|
||||
ab_pow7_re2 <= 0;
|
||||
ab_pow7_im2 <= 0;
|
||||
b_pow8_re2 <= 0;
|
||||
b_pow8_im2 <= 0;
|
||||
a_re3 <= 0;
|
||||
a_im3 <= 0;
|
||||
b_re3 <= 0;
|
||||
b_im3 <= 0;
|
||||
ab_re3 <= 0;
|
||||
ab_im3 <= 0;
|
||||
abb_re3 <= 0;
|
||||
abb_im3 <= 0;
|
||||
ab_pow3_re3 <= 0;
|
||||
ab_pow3_im3 <= 0;
|
||||
ab_pow4_re3 <= 0;
|
||||
ab_pow4_im3 <= 0;
|
||||
ab_pow5_re3 <= 0;
|
||||
ab_pow5_im3 <= 0;
|
||||
ab_pow6_re3 <= 0;
|
||||
ab_pow6_im3 <= 0;
|
||||
ab_pow7_re3 <= 0;
|
||||
ab_pow7_im3 <= 0;
|
||||
b_pow8_re3 <= 0;
|
||||
b_pow8_im3 <= 0;
|
||||
a_re4 <= 0;
|
||||
a_im4 <= 0;
|
||||
b_re4 <= 0;
|
||||
b_im4 <= 0;
|
||||
ab_re4 <= 0;
|
||||
ab_im4 <= 0;
|
||||
abb_re4 <= 0;
|
||||
abb_im4 <= 0;
|
||||
ab_pow3_re4 <= 0;
|
||||
ab_pow3_im4 <= 0;
|
||||
ab_pow4_re4 <= 0;
|
||||
ab_pow4_im4 <= 0;
|
||||
ab_pow5_re4 <= 0;
|
||||
ab_pow5_im4 <= 0;
|
||||
ab_pow6_re4 <= 0;
|
||||
ab_pow6_im4 <= 0;
|
||||
ab_pow7_re4 <= 0;
|
||||
ab_pow7_im4 <= 0;
|
||||
b_pow8_re4 <= 0;
|
||||
b_pow8_im4 <= 0;
|
||||
a_re5 <= 0;
|
||||
a_im5 <= 0;
|
||||
b_re5 <= 0;
|
||||
b_im5 <= 0;
|
||||
ab_re5 <= 0;
|
||||
ab_im5 <= 0;
|
||||
abb_re5 <= 0;
|
||||
abb_im5 <= 0;
|
||||
ab_pow3_re5 <= 0;
|
||||
ab_pow3_im5 <= 0;
|
||||
ab_pow4_re5 <= 0;
|
||||
ab_pow4_im5 <= 0;
|
||||
ab_pow5_re5 <= 0;
|
||||
ab_pow5_im5 <= 0;
|
||||
ab_pow6_re5 <= 0;
|
||||
ab_pow6_im5 <= 0;
|
||||
ab_pow7_re5 <= 0;
|
||||
ab_pow7_im5 <= 0;
|
||||
b_pow8_re5 <= 0;
|
||||
b_pow8_im5 <= 0;
|
||||
end
|
||||
else if(|vldi_r10) begin
|
||||
case(1'b1)
|
||||
vldi_r10[0]: begin
|
||||
a_re0 <= ao_re_r1 ;
|
||||
a_im0 <= ao_im_r1 ;
|
||||
b_re0 <= bo_re_r1 ;
|
||||
b_im0 <= bo_im_r1 ;
|
||||
ab_re0 <= ab_re_r1 ;
|
||||
ab_im0 <= ab_im_r1 ;
|
||||
abb_re0 <= abb_re_r1 ;
|
||||
abb_im0 <= abb_im_r1 ;
|
||||
ab_pow3_re0 <= ab_pow3_re_r1;
|
||||
ab_pow3_im0 <= ab_pow3_im_r1;
|
||||
ab_pow4_re0 <= ab_pow4_re_r1;
|
||||
ab_pow4_im0 <= ab_pow4_im_r1;
|
||||
ab_pow5_re0 <= ab_pow5_re_r1;
|
||||
ab_pow5_im0 <= ab_pow5_im_r1;
|
||||
ab_pow6_re0 <= ab_pow6_re_r1;
|
||||
ab_pow6_im0 <= ab_pow6_im_r1;
|
||||
ab_pow7_re0 <= ab_pow7_re_r1;
|
||||
ab_pow7_im0 <= ab_pow7_im_r1;
|
||||
b_pow8_re0 <= b_pow8_re_r1 ;
|
||||
b_pow8_im0 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[1]: begin
|
||||
a_re1 <= ao_re_r1 ;
|
||||
a_im1 <= ao_im_r1 ;
|
||||
b_re1 <= bo_re_r1 ;
|
||||
b_im1 <= bo_im_r1 ;
|
||||
ab_re1 <= ab_re_r1 ;
|
||||
ab_im1 <= ab_im_r1 ;
|
||||
abb_re1 <= abb_re_r1 ;
|
||||
abb_im1 <= abb_im_r1 ;
|
||||
ab_pow3_re1 <= ab_pow3_re_r1;
|
||||
ab_pow3_im1 <= ab_pow3_im_r1;
|
||||
ab_pow4_re1 <= ab_pow4_re_r1;
|
||||
ab_pow4_im1 <= ab_pow4_im_r1;
|
||||
ab_pow5_re1 <= ab_pow5_re_r1;
|
||||
ab_pow5_im1 <= ab_pow5_im_r1;
|
||||
ab_pow6_re1 <= ab_pow6_re_r1;
|
||||
ab_pow6_im1 <= ab_pow6_im_r1;
|
||||
ab_pow7_re1 <= ab_pow7_re_r1;
|
||||
ab_pow7_im1 <= ab_pow7_im_r1;
|
||||
b_pow8_re1 <= b_pow8_re_r1 ;
|
||||
b_pow8_im1 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[2]: begin
|
||||
a_re2 <= ao_re_r1 ;
|
||||
a_im2 <= ao_im_r1 ;
|
||||
b_re2 <= bo_re_r1 ;
|
||||
b_im2 <= bo_im_r1 ;
|
||||
ab_re2 <= ab_re_r1 ;
|
||||
ab_im2 <= ab_im_r1 ;
|
||||
abb_re2 <= abb_re_r1 ;
|
||||
abb_im2 <= abb_im_r1 ;
|
||||
ab_pow3_re2 <= ab_pow3_re_r1;
|
||||
ab_pow3_im2 <= ab_pow3_im_r1;
|
||||
ab_pow4_re2 <= ab_pow4_re_r1;
|
||||
ab_pow4_im2 <= ab_pow4_im_r1;
|
||||
ab_pow5_re2 <= ab_pow5_re_r1;
|
||||
ab_pow5_im2 <= ab_pow5_im_r1;
|
||||
ab_pow6_re2 <= ab_pow6_re_r1;
|
||||
ab_pow6_im2 <= ab_pow6_im_r1;
|
||||
ab_pow7_re2 <= ab_pow7_re_r1;
|
||||
ab_pow7_im2 <= ab_pow7_im_r1;
|
||||
b_pow8_re2 <= b_pow8_re_r1 ;
|
||||
b_pow8_im2 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[3]: begin
|
||||
a_re3 <= ao_re_r1 ;
|
||||
a_im3 <= ao_im_r1 ;
|
||||
b_re3 <= bo_re_r1 ;
|
||||
b_im3 <= bo_im_r1 ;
|
||||
ab_re3 <= ab_re_r1 ;
|
||||
ab_im3 <= ab_im_r1 ;
|
||||
abb_re3 <= abb_re_r1 ;
|
||||
abb_im3 <= abb_im_r1 ;
|
||||
ab_pow3_re3 <= ab_pow3_re_r1;
|
||||
ab_pow3_im3 <= ab_pow3_im_r1;
|
||||
ab_pow4_re3 <= ab_pow4_re_r1;
|
||||
ab_pow4_im3 <= ab_pow4_im_r1;
|
||||
ab_pow5_re3 <= ab_pow5_re_r1;
|
||||
ab_pow5_im3 <= ab_pow5_im_r1;
|
||||
ab_pow6_re3 <= ab_pow6_re_r1;
|
||||
ab_pow6_im3 <= ab_pow6_im_r1;
|
||||
ab_pow7_re3 <= ab_pow7_re_r1;
|
||||
ab_pow7_im3 <= ab_pow7_im_r1;
|
||||
b_pow8_re3 <= b_pow8_re_r1 ;
|
||||
b_pow8_im3 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[4]: begin
|
||||
a_re4 <= ao_re_r1 ;
|
||||
a_im4 <= ao_im_r1 ;
|
||||
b_re4 <= bo_re_r1 ;
|
||||
b_im4 <= bo_im_r1 ;
|
||||
ab_re4 <= ab_re_r1 ;
|
||||
ab_im4 <= ab_im_r1 ;
|
||||
abb_re4 <= abb_re_r1 ;
|
||||
abb_im4 <= abb_im_r1 ;
|
||||
ab_pow3_re4 <= ab_pow3_re_r1;
|
||||
ab_pow3_im4 <= ab_pow3_im_r1;
|
||||
ab_pow4_re4 <= ab_pow4_re_r1;
|
||||
ab_pow4_im4 <= ab_pow4_im_r1;
|
||||
ab_pow5_re4 <= ab_pow5_re_r1;
|
||||
ab_pow5_im4 <= ab_pow5_im_r1;
|
||||
ab_pow6_re4 <= ab_pow6_re_r1;
|
||||
ab_pow6_im4 <= ab_pow6_im_r1;
|
||||
ab_pow7_re4 <= ab_pow7_re_r1;
|
||||
ab_pow7_im4 <= ab_pow7_im_r1;
|
||||
b_pow8_re4 <= b_pow8_re_r1 ;
|
||||
b_pow8_im4 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[5]: begin
|
||||
a_re5 <= ao_re_r1 ;
|
||||
a_im5 <= ao_im_r1 ;
|
||||
b_re5 <= bo_re_r1 ;
|
||||
b_im5 <= bo_im_r1 ;
|
||||
ab_re5 <= ab_re_r1 ;
|
||||
ab_im5 <= ab_im_r1 ;
|
||||
abb_re5 <= abb_re_r1 ;
|
||||
abb_im5 <= abb_im_r1 ;
|
||||
ab_pow3_re5 <= ab_pow3_re_r1;
|
||||
ab_pow3_im5 <= ab_pow3_im_r1;
|
||||
ab_pow4_re5 <= ab_pow4_re_r1;
|
||||
ab_pow4_im5 <= ab_pow4_im_r1;
|
||||
ab_pow5_re5 <= ab_pow5_re_r1;
|
||||
ab_pow5_im5 <= ab_pow5_im_r1;
|
||||
ab_pow6_re5 <= ab_pow6_re_r1;
|
||||
ab_pow6_im5 <= ab_pow6_im_r1;
|
||||
ab_pow7_re5 <= ab_pow7_re_r1;
|
||||
ab_pow7_im5 <= ab_pow7_im_r1;
|
||||
b_pow8_re5 <= b_pow8_re_r1 ;
|
||||
b_pow8_im5 <= b_pow8_im_r1 ;
|
||||
end
|
||||
// default: begin
|
||||
// ao_re[0] <= 'h0;
|
||||
// ao_im[0] <= 'h0;
|
||||
// ab_re[0] <= 'h0;
|
||||
// ab_im[0] <= 'h0;
|
||||
// abb_re[0] <= 'h0;
|
||||
// abb_im[0] <= 'h0;
|
||||
// ab_pow3_re[0] <= 'h0;
|
||||
// ab_pow3_im[0] <= 'h0;
|
||||
// ab_pow4_re[0] <= 'h0;
|
||||
// ab_pow4_im[0] <= 'h0;
|
||||
// ab_pow5_re[0] <= 'h0;
|
||||
// ab_pow5_im[0] <= 'h0;
|
||||
// ab_pow6_re[0] <= 'h0;
|
||||
// ab_pow6_im[0] <= 'h0;
|
||||
// ab_pow7_re[0] <= 'h0;
|
||||
// ab_pow7_im[0] <= 'h0;
|
||||
// b_pow8_re[0] <= 'h0;
|
||||
// b_pow8_im[0] <= 'h0;
|
||||
// end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,36 +1,3 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : IIR_Filter.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.4 2024-05-28 thfu
|
||||
//2024-05-28 10:22:49
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module IIR_Filter_p8 #(
|
||||
parameter coef_width = 32
|
||||
,parameter data_in_width = 16
|
||||
|
|
@ -74,9 +41,36 @@ module IIR_Filter_p8 #(
|
|||
,output signed [data_out_width-1:0] dout_im // Im(y(8n-8))
|
||||
);
|
||||
|
||||
wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0};
|
||||
wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re };
|
||||
wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im };
|
||||
wire signed [data_in_width-1 :0] dinp [7:0];
|
||||
assign dinp[7] = dinp7;
|
||||
assign dinp[6] = dinp6;
|
||||
assign dinp[5] = dinp5;
|
||||
assign dinp[4] = dinp4;
|
||||
assign dinp[3] = dinp3;
|
||||
assign dinp[2] = dinp2;
|
||||
assign dinp[1] = dinp1;
|
||||
assign dinp[0] = dinp0;
|
||||
|
||||
wire signed [coef_width-1 :0] ab_pow_re [7:0];
|
||||
assign ab_pow_re[7] = ab_pow7_re;
|
||||
assign ab_pow_re[6] = ab_pow6_re;
|
||||
assign ab_pow_re[5] = ab_pow5_re;
|
||||
assign ab_pow_re[4] = ab_pow4_re;
|
||||
assign ab_pow_re[3] = ab_pow3_re;
|
||||
assign ab_pow_re[2] = abb_re;
|
||||
assign ab_pow_re[1] = ab_re;
|
||||
assign ab_pow_re[0] = a_re;
|
||||
|
||||
wire signed [coef_width-1 :0] ab_pow_im [7:0];
|
||||
assign ab_pow_im[7] = ab_pow7_im;
|
||||
assign ab_pow_im[6] = ab_pow6_im;
|
||||
assign ab_pow_im[5] = ab_pow5_im;
|
||||
assign ab_pow_im[4] = ab_pow4_im;
|
||||
assign ab_pow_im[3] = ab_pow3_im;
|
||||
assign ab_pow_im[2] = abb_im;
|
||||
assign ab_pow_im[1] = ab_im;
|
||||
assign ab_pow_im[0] = a_im;
|
||||
|
||||
|
||||
wire signed [temp_var_width-1 :0] x_re [0:7];
|
||||
wire signed [temp_var_width-1 :0] x_im [0:7];
|
||||
|
|
@ -88,8 +82,8 @@ reg signed [temp_var_width+3 :0] v1_im;
|
|||
|
||||
wire signed [temp_var_width+3 :0] y_re;
|
||||
wire signed [temp_var_width+3 :0] y_im;
|
||||
reg signed [temp_var_width+3 :0] y1_re;
|
||||
reg signed [temp_var_width+3 :0] y1_im;
|
||||
wire signed [temp_var_width+3 :0] y1_re;
|
||||
wire signed [temp_var_width+3 :0] y1_im;
|
||||
|
||||
wire signed [data_out_width-1:0] y_re_trunc;
|
||||
wire signed [data_out_width-1:0] y_im_trunc;
|
||||
|
|
|
|||
|
|
@ -1,35 +1,3 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module IIR_top #(
|
||||
parameter data_out_width = 23
|
||||
|
|
|
|||
|
|
@ -1,35 +1,3 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2025-02-28 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module TailCorr_top #(
|
||||
parameter temp_var_width = 22
|
||||
|
|
@ -207,14 +175,14 @@ wire signed [temp_var_width+2:0] sum_IIRout_p4;
|
|||
wire signed [temp_var_width+2:0] sum_IIRout_p5;
|
||||
wire signed [temp_var_width+2:0] sum_IIRout_p6;
|
||||
wire signed [temp_var_width+2:0] sum_IIRout_p7;
|
||||
reg signed [15:0] din_p0_r [15:0];
|
||||
reg signed [15:0] din_p1_r [15:0];
|
||||
reg signed [15:0] din_p2_r [15:0];
|
||||
reg signed [15:0] din_p3_r [15:0];
|
||||
reg signed [15:0] din_p4_r [15:0];
|
||||
reg signed [15:0] din_p5_r [15:0];
|
||||
reg signed [15:0] din_p6_r [15:0];
|
||||
reg signed [15:0] din_p7_r [15:0];
|
||||
reg signed [15:0] din_p0_r [16:0];
|
||||
reg signed [15:0] din_p1_r [16:0];
|
||||
reg signed [15:0] din_p2_r [16:0];
|
||||
reg signed [15:0] din_p3_r [16:0];
|
||||
reg signed [15:0] din_p4_r [16:0];
|
||||
reg signed [15:0] din_p5_r [16:0];
|
||||
reg signed [15:0] din_p6_r [16:0];
|
||||
reg signed [15:0] din_p7_r [16:0];
|
||||
reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7)
|
||||
reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22)
|
||||
reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37)
|
||||
|
|
@ -290,7 +258,7 @@ always @(posedge clk or negedge rstn) begin
|
|||
din_p5_r[0] <= din_p5;
|
||||
din_p6_r[0] <= din_p6;
|
||||
din_p7_r[0] <= din_p7;
|
||||
for (i = 0; i < 15; i = i + 1) begin
|
||||
for (i = 0; i < 16; i = i + 1) begin
|
||||
din_p0_r[i+1] <= din_p0_r[i];
|
||||
din_p1_r[i+1] <= din_p1_r[i];
|
||||
din_p2_r[i+1] <= din_p2_r[i];
|
||||
|
|
@ -302,7 +270,121 @@ always @(posedge clk or negedge rstn) begin
|
|||
end
|
||||
end
|
||||
end
|
||||
/*
|
||||
wire signed [15:0] din_p0_r1;
|
||||
wire signed [15:0] din_p1_r1;
|
||||
wire signed [15:0] din_p2_r1;
|
||||
wire signed [15:0] din_p3_r1;
|
||||
wire signed [15:0] din_p4_r1;
|
||||
wire signed [15:0] din_p5_r1;
|
||||
wire signed [15:0] din_p6_r1;
|
||||
wire signed [15:0] din_p7_r1;
|
||||
wire signed [15:0] din_p0_r2;
|
||||
wire signed [15:0] din_p1_r2;
|
||||
wire signed [15:0] din_p2_r2;
|
||||
wire signed [15:0] din_p3_r2;
|
||||
wire signed [15:0] din_p4_r2;
|
||||
wire signed [15:0] din_p5_r2;
|
||||
wire signed [15:0] din_p6_r2;
|
||||
wire signed [15:0] din_p7_r2;
|
||||
wire signed [15:0] din_p0_r3;
|
||||
wire signed [15:0] din_p1_r3;
|
||||
wire signed [15:0] din_p2_r3;
|
||||
wire signed [15:0] din_p3_r3;
|
||||
wire signed [15:0] din_p4_r3;
|
||||
wire signed [15:0] din_p5_r3;
|
||||
wire signed [15:0] din_p6_r3;
|
||||
wire signed [15:0] din_p7_r3;
|
||||
wire signed [15:0] din_p0_r4;
|
||||
wire signed [15:0] din_p1_r4;
|
||||
wire signed [15:0] din_p2_r4;
|
||||
wire signed [15:0] din_p3_r4;
|
||||
wire signed [15:0] din_p4_r4;
|
||||
wire signed [15:0] din_p5_r4;
|
||||
wire signed [15:0] din_p6_r4;
|
||||
wire signed [15:0] din_p7_r4;
|
||||
wire signed [15:0] din_p0_r5;
|
||||
wire signed [15:0] din_p1_r5;
|
||||
wire signed [15:0] din_p2_r5;
|
||||
wire signed [15:0] din_p3_r5;
|
||||
wire signed [15:0] din_p4_r5;
|
||||
wire signed [15:0] din_p5_r5;
|
||||
wire signed [15:0] din_p6_r5;
|
||||
wire signed [15:0] din_p7_r5;
|
||||
wire signed [15:0] din_p0_r6;
|
||||
wire signed [15:0] din_p1_r6;
|
||||
wire signed [15:0] din_p2_r6;
|
||||
wire signed [15:0] din_p3_r6;
|
||||
wire signed [15:0] din_p4_r6;
|
||||
wire signed [15:0] din_p5_r6;
|
||||
wire signed [15:0] din_p6_r6;
|
||||
wire signed [15:0] din_p7_r6;
|
||||
wire signed [15:0] din_p0_r7;
|
||||
wire signed [15:0] din_p1_r7;
|
||||
wire signed [15:0] din_p2_r7;
|
||||
wire signed [15:0] din_p3_r7;
|
||||
wire signed [15:0] din_p4_r7;
|
||||
wire signed [15:0] din_p5_r7;
|
||||
wire signed [15:0] din_p6_r7;
|
||||
wire signed [15:0] din_p7_r7;
|
||||
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_1(en,din_p0, din_p0_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_1(en,din_p1, din_p1_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_1(en,din_p2, din_p2_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_1(en,din_p3, din_p3_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_1(en,din_p4, din_p4_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_1(en,din_p5, din_p5_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_1(en,din_p6, din_p6_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_1(en,din_p7, din_p7_r1 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_2(en,din_p0_r1, din_p0_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_2(en,din_p1_r1, din_p1_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_2(en,din_p2_r1, din_p2_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_2(en,din_p3_r1, din_p3_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_2(en,din_p4_r1, din_p4_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_2(en,din_p5_r1, din_p5_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_2(en,din_p6_r1, din_p6_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_2(en,din_p7_r1, din_p7_r2 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_3(en,din_p0_r2, din_p0_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_3(en,din_p1_r2, din_p1_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_3(en,din_p2_r2, din_p2_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_3(en,din_p3_r2, din_p3_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_3(en,din_p4_r2, din_p4_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_3(en,din_p5_r2, din_p5_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_3(en,din_p6_r2, din_p6_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_3(en,din_p7_r2, din_p7_r3 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_4(en,din_p0_r3, din_p0_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_4(en,din_p1_r3, din_p1_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_4(en,din_p2_r3, din_p2_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_4(en,din_p3_r3, din_p3_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_4(en,din_p4_r3, din_p4_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_4(en,din_p5_r3, din_p5_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_4(en,din_p6_r3, din_p6_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_4(en,din_p7_r3, din_p7_r4 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_5(en,din_p0_r4, din_p0_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_5(en,din_p1_r4, din_p1_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_5(en,din_p2_r4, din_p2_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_5(en,din_p3_r4, din_p3_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_5(en,din_p4_r4, din_p4_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_5(en,din_p5_r4, din_p5_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_5(en,din_p6_r4, din_p6_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_5(en,din_p7_r4, din_p7_r5 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_6(en,din_p0_r5, din_p0_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_6(en,din_p1_r5, din_p1_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_6(en,din_p2_r5, din_p2_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_6(en,din_p3_r5, din_p3_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_6(en,din_p4_r5, din_p4_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_6(en,din_p5_r5, din_p5_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_6(en,din_p6_r5, din_p6_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_6(en,din_p7_r5, din_p7_r6 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p0_7(en,din_p0_r6, din_p0_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p1_7(en,din_p1_r6, din_p1_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p2_7(en,din_p2_r6, din_p2_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p3_7(en,din_p3_r6, din_p3_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p4_7(en,din_p4_r6, din_p4_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p5_7(en,din_p5_r6, din_p5_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p6_7(en,din_p6_r6, din_p6_r7 ,clk,rstn);
|
||||
sirv_gnrl_dfflr #(16) dff_din_p7_7(en,din_p7_r6, din_p7_r7 ,clk,rstn);
|
||||
*/
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
|
|
@ -745,14 +827,14 @@ always @(posedge clk or negedge rstn) begin
|
|||
end
|
||||
end
|
||||
|
||||
assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119)
|
||||
assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118)
|
||||
assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117)
|
||||
assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116)
|
||||
assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115)
|
||||
assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114)
|
||||
assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113)
|
||||
assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112)
|
||||
assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119)
|
||||
assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118)
|
||||
assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117)
|
||||
assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116)
|
||||
assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-116)
|
||||
assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114)
|
||||
assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113)
|
||||
assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112)
|
||||
|
||||
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0);
|
||||
trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1);
|
||||
|
|
@ -828,7 +910,7 @@ always @(posedge clk or negedge rstn)begin
|
|||
end
|
||||
end
|
||||
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
|
||||
assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ;
|
||||
assign vldo_r0_h = vldo_diff_r[17] == 0 && vldo_diff_r[16] == 1 ;
|
||||
assign vldo = vldo_r0;
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -1,48 +1,16 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module diff_p
|
||||
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input vldi
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,output vldo
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input vldi
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,output vldo
|
||||
,output signed [15:0] dout_p0
|
||||
,output signed [15:0] dout_p1
|
||||
,output signed [15:0] dout_p2
|
||||
|
|
@ -62,89 +30,130 @@ module diff_p
|
|||
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] din_wire [0:3];
|
||||
|
||||
assign din_wire[0] = din0;
|
||||
assign din_wire[1] = din1;
|
||||
assign din_wire[2] = din2;
|
||||
assign din_wire[3] = din3;
|
||||
wire signed [15:0] din_p0_r0;
|
||||
wire signed [15:0] din_p1_r0;
|
||||
wire signed [15:0] din_p2_r0;
|
||||
wire signed [15:0] din_p3_r0;
|
||||
wire signed [15:0] din_p4_r0;
|
||||
wire signed [15:0] din_p5_r0;
|
||||
wire signed [15:0] din_p6_r0;
|
||||
wire signed [15:0] din_p7_r0;
|
||||
wire vldo_0;
|
||||
wire vldo_1;
|
||||
wire vldo_2;
|
||||
wire vldo_3;
|
||||
wire vldo_r0;
|
||||
assign vldo_r0 = vldo_0 || vldo_1 || vldo_2 || vldo_3;
|
||||
sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn);
|
||||
s2p_2 inst1_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din0),
|
||||
.en (vldi),
|
||||
.dout0 (din_p0_r0),
|
||||
.dout1 (din_p4_r0)
|
||||
,.vldo( vldo_0)
|
||||
);
|
||||
s2p_2 inst2_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din1),
|
||||
.en (vldi),
|
||||
.dout0 (din_p1_r0),
|
||||
.dout1 (din_p5_r0)
|
||||
,.vldo( vldo_1)
|
||||
);
|
||||
s2p_2 inst3_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din2),
|
||||
.en (vldi),
|
||||
.dout0 (din_p2_r0),
|
||||
.dout1 (din_p6_r0)
|
||||
,.vldo( vldo_2)
|
||||
);
|
||||
s2p_2 inst4_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din3),
|
||||
.en (vldi),
|
||||
.dout0 (din_p3_r0),
|
||||
.dout1 (din_p7_r0)
|
||||
,.vldo( vldo_3)
|
||||
);
|
||||
|
||||
|
||||
wire [3:0] vldo_temp;
|
||||
wire signed [15:0] dinp_r0 [7:0];
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 4; i = i + 1) begin: s2p_inst
|
||||
s2p_2 inst_s2p_2 (
|
||||
.clk (clk),
|
||||
.rst_n (rstn),
|
||||
.din (din_wire[i]),
|
||||
.en (vldi),
|
||||
.dout0 (dinp_r0[i]),
|
||||
.dout1 (dinp_r0[i+4]),
|
||||
.vldo (vldo_temp[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
assign vldo = vldo_temp[0];
|
||||
wire signed [15:0] din_p0_r1;
|
||||
wire signed [15:0] din_p1_r1;
|
||||
wire signed [15:0] din_p2_r1;
|
||||
wire signed [15:0] din_p3_r1;
|
||||
wire signed [15:0] din_p4_r1;
|
||||
wire signed [15:0] din_p5_r1;
|
||||
wire signed [15:0] din_p6_r1;
|
||||
wire signed [15:0] din_p7_r1;
|
||||
|
||||
reg signed [15:0] dinp_r1 [0:7];
|
||||
integer j;
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
dinp_r1[j] <= 'h0;
|
||||
end
|
||||
end
|
||||
else if (en) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
dinp_r1[j] <= dinp_r0[j];
|
||||
end
|
||||
end
|
||||
sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn);
|
||||
|
||||
assign dout_p0 = din_p0_r0;
|
||||
assign dout_p1 = din_p1_r0;
|
||||
assign dout_p2 = din_p2_r0;
|
||||
assign dout_p3 = din_p3_r0;
|
||||
assign dout_p4 = din_p4_r0;
|
||||
assign dout_p5 = din_p5_r0;
|
||||
assign dout_p6 = din_p6_r0;
|
||||
assign dout_p7 = din_p7_r0;
|
||||
|
||||
reg signed [15:0] diff_p0_r1;
|
||||
reg signed [15:0] diff_p1_r1;
|
||||
reg signed [15:0] diff_p2_r1;
|
||||
reg signed [15:0] diff_p3_r1;
|
||||
reg signed [15:0] diff_p4_r1;
|
||||
reg signed [15:0] diff_p5_r1;
|
||||
reg signed [15:0] diff_p6_r1;
|
||||
reg signed [15:0] diff_p7_r1;
|
||||
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
diff_p0_r1 <= 0;
|
||||
diff_p1_r1 <= 0;
|
||||
diff_p2_r1 <= 0;
|
||||
diff_p3_r1 <= 0;
|
||||
diff_p4_r1 <= 0;
|
||||
diff_p5_r1 <= 0;
|
||||
diff_p6_r1 <= 0;
|
||||
diff_p7_r1 <= 0;
|
||||
|
||||
end
|
||||
else if(en)begin
|
||||
diff_p0_r1 <= din_p0_r0 - din_p7_r1;
|
||||
diff_p1_r1 <= din_p1_r0 - din_p0_r0;
|
||||
diff_p2_r1 <= din_p2_r0 - din_p1_r0;
|
||||
diff_p3_r1 <= din_p3_r0 - din_p2_r0;
|
||||
diff_p4_r1 <= din_p4_r0 - din_p3_r0;
|
||||
diff_p5_r1 <= din_p5_r0 - din_p4_r0;
|
||||
diff_p6_r1 <= din_p6_r0 - din_p5_r0;
|
||||
diff_p7_r1 <= din_p7_r0 - din_p6_r0;
|
||||
end
|
||||
else begin
|
||||
diff_p0_r1 <= diff_p0_r1;
|
||||
diff_p1_r1 <= diff_p1_r1;
|
||||
diff_p2_r1 <= diff_p2_r1;
|
||||
diff_p3_r1 <= diff_p3_r1;
|
||||
diff_p4_r1 <= diff_p4_r1;
|
||||
diff_p5_r1 <= diff_p5_r1;
|
||||
diff_p6_r1 <= diff_p6_r1;
|
||||
diff_p7_r1 <= diff_p7_r1;
|
||||
end
|
||||
end
|
||||
|
||||
wire signed [15:0] diffp_r0 [0:7];
|
||||
generate
|
||||
for (i = 0; i < 8; i = i + 1) begin: diff_assign
|
||||
if (i == 0)
|
||||
assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
|
||||
else
|
||||
assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign dout_p0 = dinp_r1[0];
|
||||
assign dout_p1 = dinp_r1[1];
|
||||
assign dout_p2 = dinp_r1[2];
|
||||
assign dout_p3 = dinp_r1[3];
|
||||
assign dout_p4 = dinp_r1[4];
|
||||
assign dout_p5 = dinp_r1[5];
|
||||
assign dout_p6 = dinp_r1[6];
|
||||
assign dout_p7 = dinp_r1[7];
|
||||
|
||||
reg signed [15:0] diffp_r1 [0:7];
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
diffp_r1[j] <= 0;
|
||||
end
|
||||
end
|
||||
else if (en) begin
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
diffp_r1[j] <= diffp_r0[j];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign diff_p0 = diffp_r1[0];
|
||||
assign diff_p1 = diffp_r1[1];
|
||||
assign diff_p2 = diffp_r1[2];
|
||||
assign diff_p3 = diffp_r1[3];
|
||||
assign diff_p4 = diffp_r1[4];
|
||||
assign diff_p5 = diffp_r1[5];
|
||||
assign diff_p6 = diffp_r1[6];
|
||||
assign diff_p7 = diffp_r1[7];
|
||||
assign diff_p0 = diff_p0_r1;
|
||||
assign diff_p1 = diff_p1_r1;
|
||||
assign diff_p2 = diff_p2_r1;
|
||||
assign diff_p3 = diff_p3_r1;
|
||||
assign diff_p4 = diff_p4_r1;
|
||||
assign diff_p5 = diff_p5_r1;
|
||||
assign diff_p6 = diff_p6_r1;
|
||||
assign diff_p7 = diff_p7_r1;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
|
||||
module rate_adapter
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input vldi
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,input signed [15:0] din4
|
||||
,input signed [15:0] din5
|
||||
,input signed [15:0] din6
|
||||
,input signed [15:0] din7
|
||||
,output signed [15:0] dout0
|
||||
,output signed [15:0] dout1
|
||||
,output signed [15:0] dout2
|
||||
,output signed [15:0] dout3
|
||||
,output vldo
|
||||
);
|
||||
|
||||
|
||||
|
||||
reg signed [15:0] doutf_0;
|
||||
reg signed [15:0] doutf_1;
|
||||
reg signed [15:0] doutf_2;
|
||||
reg signed [15:0] doutf_3;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn) begin
|
||||
doutf_0 <= 0;
|
||||
doutf_1 <= 0;
|
||||
doutf_2 <= 0;
|
||||
doutf_3 <= 0;
|
||||
end
|
||||
else if(!en) begin
|
||||
doutf_0 <= din0;
|
||||
doutf_1 <= din1;
|
||||
doutf_2 <= din2;
|
||||
doutf_3 <= din3;
|
||||
end
|
||||
else begin
|
||||
doutf_0 <= din4;
|
||||
doutf_1 <= din5;
|
||||
doutf_2 <= din6;
|
||||
doutf_3 <= din7;
|
||||
end
|
||||
|
||||
assign dout0 = doutf_0;
|
||||
assign dout1 = doutf_1;
|
||||
assign dout2 = doutf_2;
|
||||
assign dout3 = doutf_3;
|
||||
|
||||
//sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi, vldo ,clk,rstn);
|
||||
assign vldo = vldi;
|
||||
endmodule
|
||||
|
|
@ -8,21 +8,6 @@ module s2p_2 (
|
|||
output vldo
|
||||
);
|
||||
|
||||
reg en_r1;
|
||||
reg en_r2;
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
en_r1 <= 0;
|
||||
en_r2 <= 0;
|
||||
end
|
||||
else begin
|
||||
en_r1 <= en;
|
||||
en_r2 <= en_r1;
|
||||
end
|
||||
end
|
||||
assign vldo = en_r2;
|
||||
|
||||
reg cnt;
|
||||
wire add_cnt;
|
||||
wire end_cnt;
|
||||
|
|
@ -45,7 +30,8 @@ end
|
|||
assign add_cnt = en == 1'b1;
|
||||
assign end_cnt = add_cnt && cnt== 2 - 1 ;
|
||||
|
||||
|
||||
wire en_r1;
|
||||
wire en_r2;
|
||||
reg [ 15: 0] dout0_r0;
|
||||
reg [ 15: 0] dout1_r0;
|
||||
wire dout0_en;
|
||||
|
|
@ -53,66 +39,45 @@ wire dout1_en;
|
|||
wire dout0_hold;
|
||||
wire dout1_hold;
|
||||
|
||||
always @(*)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(!rst_n)begin
|
||||
dout0_r0 <= 16'b0;
|
||||
dout1_r0 <= 16'b0;
|
||||
end
|
||||
else if(dout0_en)begin
|
||||
dout0_r0 = din;
|
||||
dout0_r0 <= din;
|
||||
end
|
||||
else if(dout1_en)begin
|
||||
dout1_r0 = din;
|
||||
end
|
||||
else begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
|
||||
end
|
||||
end
|
||||
assign dout0_en = add_cnt && cnt == 0;
|
||||
assign dout1_en = add_cnt && cnt == 1;
|
||||
|
||||
reg [ 15: 0] dout0_r1;
|
||||
reg [ 15: 0] dout1_r1;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
else if(en)begin
|
||||
dout0_r1 <= dout0_r0;
|
||||
dout1_r1 <= dout1_r0;
|
||||
dout1_r0 <= din;
|
||||
end
|
||||
else if(dout0_hold)begin
|
||||
dout0_r1 <= dout0_r1;
|
||||
dout1_r1 <= 16'd0;
|
||||
dout0_r0 <= dout0_r0;
|
||||
dout1_r0 <= 16'd0;
|
||||
end
|
||||
else if(dout1_hold)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= dout1_r1;
|
||||
dout0_r0 <= 16'd0;
|
||||
dout1_r0 <= dout1_r0;
|
||||
end
|
||||
else begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
dout0_r0 <= 16'd0;
|
||||
dout1_r0 <= 16'd0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign dout0_en = add_cnt && cnt == 0;
|
||||
assign dout1_en = add_cnt && cnt == 1;
|
||||
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
|
||||
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
|
||||
|
||||
reg [ 15: 0] dout0_r2;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r2 <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
dout0_r2 <= dout0_r1;
|
||||
end
|
||||
end
|
||||
sirv_gnrl_dffr #(1) dff_en_1(en , en_r1 ,clk,rst_n);
|
||||
sirv_gnrl_dffr #(1) dff_en_2(en_r1, en_r2 ,clk,rst_n);
|
||||
assign vldo = en_r2;
|
||||
|
||||
assign dout0 = dout0_r2;
|
||||
assign dout1 = dout1_r1;
|
||||
wire [ 15: 0] dout0_r1;
|
||||
sirv_gnrl_dfflr #(16) dff_dout0_1(1'b1,dout0_r0, dout0_r1 ,clk,rst_n);
|
||||
|
||||
assign dout0 = dout0_r1;
|
||||
assign dout1 = dout1_r0;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -0,0 +1,326 @@
|
|||
/*
|
||||
Copyright 2018-2020 Nuclei System Technology, Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//=====================================================================
|
||||
//
|
||||
// Designer : Bob Hu
|
||||
//
|
||||
// Description:
|
||||
// All of the general DFF and Latch modules
|
||||
//
|
||||
// ====================================================================
|
||||
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
`define DISABLE_SV_ASSERTION
|
||||
`define dly #0.2
|
||||
module sirv_gnrl_dfflrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is input
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflrd # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
input [DW-1:0] init,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= init;
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable, no reset
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffl # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : DFFL_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for general latch
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_ltch # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
//input test_mode,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @ *
|
||||
begin : LTCH_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= dnxt;
|
||||
end
|
||||
|
||||
//assign qout = test_mode ? dnxt : qout_r;
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
always_comb
|
||||
begin
|
||||
CHECK_THE_X_VALUE:
|
||||
assert (lden !== 1'bx)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
end
|
||||
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : syncer.v
|
||||
// Department :
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-03-13 PWY AWG dedicated register file
|
||||
// 0.2 2024-05-13 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
module syncer # (
|
||||
parameter width = 1
|
||||
,parameter stage = 2
|
||||
)
|
||||
(
|
||||
input clk_d
|
||||
,input rstn_d
|
||||
,input [width-1:0] data_s
|
||||
,output [width-1:0] data_d
|
||||
);
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
wire [width-1:0] data_temp[stage-1:0];
|
||||
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
|
||||
for(i=1;i<stage;i=i+1) begin: SYNCER
|
||||
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign data_d = data_temp[stage-1];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
|
||||
module z_dsp
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
//,input tc_bypass
|
||||
,input [ 5:0] vldi_coef
|
||||
,input vldi_data
|
||||
//,input [1:0] intp_mode
|
||||
//,input [1:0] dac_mode_sel
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,input signed [31:0] a0_re
|
||||
,input signed [31:0] a0_im
|
||||
,input signed [31:0] b0_re
|
||||
,input signed [31:0] b0_im
|
||||
,input signed [31:0] a1_re
|
||||
,input signed [31:0] a1_im
|
||||
,input signed [31:0] b1_re
|
||||
,input signed [31:0] b1_im
|
||||
,input signed [31:0] a2_re
|
||||
,input signed [31:0] a2_im
|
||||
,input signed [31:0] b2_re
|
||||
,input signed [31:0] b2_im
|
||||
,input signed [31:0] a3_re
|
||||
,input signed [31:0] a3_im
|
||||
,input signed [31:0] b3_re
|
||||
,input signed [31:0] b3_im
|
||||
,input signed [31:0] a4_re
|
||||
,input signed [31:0] a4_im
|
||||
,input signed [31:0] b4_re
|
||||
,input signed [31:0] b4_im
|
||||
,input signed [31:0] a5_re
|
||||
,input signed [31:0] a5_im
|
||||
,input signed [31:0] b5_re
|
||||
,input signed [31:0] b5_im
|
||||
,output signed [15:0] dout0
|
||||
,output signed [15:0] dout1
|
||||
,output signed [15:0] dout2
|
||||
,output signed [15:0] dout3
|
||||
,output vldo
|
||||
);
|
||||
|
||||
|
||||
wire signed [15:0] IIR_out;
|
||||
|
||||
|
||||
wire signed [31:0] ao_re [5:0];
|
||||
wire signed [31:0] ao_im [5:0];
|
||||
wire signed [31:0] ab_re [5:0];
|
||||
wire signed [31:0] ab_im [5:0];
|
||||
wire signed [31:0] abb_re [5:0];
|
||||
wire signed [31:0] abb_im [5:0];
|
||||
wire signed [31:0] ab_pow3_re [5:0];
|
||||
wire signed [31:0] ab_pow3_im [5:0];
|
||||
wire signed [31:0] ab_pow4_re [5:0];
|
||||
wire signed [31:0] ab_pow4_im [5:0];
|
||||
wire signed [31:0] ab_pow5_re [5:0];
|
||||
wire signed [31:0] ab_pow5_im [5:0];
|
||||
wire signed [31:0] ab_pow6_re [5:0];
|
||||
wire signed [31:0] ab_pow6_im [5:0];
|
||||
wire signed [31:0] ab_pow7_re [5:0];
|
||||
wire signed [31:0] ab_pow7_im [5:0];
|
||||
wire signed [31:0] bo_re [5:0];
|
||||
wire signed [31:0] bo_im [5:0];
|
||||
wire signed [31:0] b_pow8_re [5:0];
|
||||
wire signed [31:0] b_pow8_im [5:0];
|
||||
|
||||
CoefGen inst_CoefGen(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.vldi (vldi_coef ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.a_re0 (ao_re[0] ),
|
||||
.a_im0 (ao_im[0] ),
|
||||
.b_re0 (bo_re[0] ),
|
||||
.b_im0 (bo_im[0] ),
|
||||
.ab_re0 (ab_re[0] ),
|
||||
.ab_im0 (ab_im[0] ),
|
||||
.abb_re0 (abb_re[0] ),
|
||||
.abb_im0 (abb_im[0] ),
|
||||
.ab_pow3_re0 (ab_pow3_re[0]),
|
||||
.ab_pow3_im0 (ab_pow3_im[0]),
|
||||
.ab_pow4_re0 (ab_pow4_re[0]),
|
||||
.ab_pow4_im0 (ab_pow4_im[0]),
|
||||
.ab_pow5_re0 (ab_pow5_re[0]),
|
||||
.ab_pow5_im0 (ab_pow5_im[0]),
|
||||
.ab_pow6_re0 (ab_pow6_re[0]),
|
||||
.ab_pow6_im0 (ab_pow6_im[0]),
|
||||
.ab_pow7_re0 (ab_pow7_re[0]),
|
||||
.ab_pow7_im0 (ab_pow7_im[0]),
|
||||
.b_pow8_re0 (b_pow8_re[0] ),
|
||||
.b_pow8_im0 (b_pow8_im[0] ),
|
||||
.a_re1 (ao_re[1] ),
|
||||
.a_im1 (ao_im[1] ),
|
||||
.b_re1 (bo_re[1] ),
|
||||
.b_im1 (bo_im[1] ),
|
||||
.ab_re1 (ab_re[1] ),
|
||||
.ab_im1 (ab_im[1] ),
|
||||
.abb_re1 (abb_re[1] ),
|
||||
.abb_im1 (abb_im[1] ),
|
||||
.ab_pow3_re1 (ab_pow3_re[1]),
|
||||
.ab_pow3_im1 (ab_pow3_im[1]),
|
||||
.ab_pow4_re1 (ab_pow4_re[1]),
|
||||
.ab_pow4_im1 (ab_pow4_im[1]),
|
||||
.ab_pow5_re1 (ab_pow5_re[1]),
|
||||
.ab_pow5_im1 (ab_pow5_im[1]),
|
||||
.ab_pow6_re1 (ab_pow6_re[1]),
|
||||
.ab_pow6_im1 (ab_pow6_im[1]),
|
||||
.ab_pow7_re1 (ab_pow7_re[1]),
|
||||
.ab_pow7_im1 (ab_pow7_im[1]),
|
||||
.b_pow8_re1 (b_pow8_re[1] ),
|
||||
.b_pow8_im1 (b_pow8_im[1] ),
|
||||
.a_re2 (ao_re[2] ),
|
||||
.a_im2 (ao_im[2] ),
|
||||
.b_re2 (bo_re[2] ),
|
||||
.b_im2 (bo_im[2] ),
|
||||
.ab_re2 (ab_re[2] ),
|
||||
.ab_im2 (ab_im[2] ),
|
||||
.abb_re2 (abb_re[2] ),
|
||||
.abb_im2 (abb_im[2] ),
|
||||
.ab_pow3_re2 (ab_pow3_re[2]),
|
||||
.ab_pow3_im2 (ab_pow3_im[2]),
|
||||
.ab_pow4_re2 (ab_pow4_re[2]),
|
||||
.ab_pow4_im2 (ab_pow4_im[2]),
|
||||
.ab_pow5_re2 (ab_pow5_re[2]),
|
||||
.ab_pow5_im2 (ab_pow5_im[2]),
|
||||
.ab_pow6_re2 (ab_pow6_re[2]),
|
||||
.ab_pow6_im2 (ab_pow6_im[2]),
|
||||
.ab_pow7_re2 (ab_pow7_re[2]),
|
||||
.ab_pow7_im2 (ab_pow7_im[2]),
|
||||
.b_pow8_re2 (b_pow8_re[2] ),
|
||||
.b_pow8_im2 (b_pow8_im[2] ),
|
||||
.a_re3 (ao_re[3] ),
|
||||
.a_im3 (ao_im[3] ),
|
||||
.b_re3 (bo_re[3] ),
|
||||
.b_im3 (bo_im[3] ),
|
||||
.ab_re3 (ab_re[3] ),
|
||||
.ab_im3 (ab_im[3] ),
|
||||
.abb_re3 (abb_re[3] ),
|
||||
.abb_im3 (abb_im[3] ),
|
||||
.ab_pow3_re3 (ab_pow3_re[3]),
|
||||
.ab_pow3_im3 (ab_pow3_im[3]),
|
||||
.ab_pow4_re3 (ab_pow4_re[3]),
|
||||
.ab_pow4_im3 (ab_pow4_im[3]),
|
||||
.ab_pow5_re3 (ab_pow5_re[3]),
|
||||
.ab_pow5_im3 (ab_pow5_im[3]),
|
||||
.ab_pow6_re3 (ab_pow6_re[3]),
|
||||
.ab_pow6_im3 (ab_pow6_im[3]),
|
||||
.ab_pow7_re3 (ab_pow7_re[3]),
|
||||
.ab_pow7_im3 (ab_pow7_im[3]),
|
||||
.b_pow8_re3 (b_pow8_re[3] ),
|
||||
.b_pow8_im3 (b_pow8_im[3] ),
|
||||
.a_re4 (ao_re[4] ),
|
||||
.a_im4 (ao_im[4] ),
|
||||
.b_re4 (bo_re[4] ),
|
||||
.b_im4 (bo_im[4] ),
|
||||
.ab_re4 (ab_re[4] ),
|
||||
.ab_im4 (ab_im[4] ),
|
||||
.abb_re4 (abb_re[4] ),
|
||||
.abb_im4 (abb_im[4] ),
|
||||
.ab_pow3_re4 (ab_pow3_re[4]),
|
||||
.ab_pow3_im4 (ab_pow3_im[4]),
|
||||
.ab_pow4_re4 (ab_pow4_re[4]),
|
||||
.ab_pow4_im4 (ab_pow4_im[4]),
|
||||
.ab_pow5_re4 (ab_pow5_re[4]),
|
||||
.ab_pow5_im4 (ab_pow5_im[4]),
|
||||
.ab_pow6_re4 (ab_pow6_re[4]),
|
||||
.ab_pow6_im4 (ab_pow6_im[4]),
|
||||
.ab_pow7_re4 (ab_pow7_re[4]),
|
||||
.ab_pow7_im4 (ab_pow7_im[4]),
|
||||
.b_pow8_re4 (b_pow8_re[4] ),
|
||||
.b_pow8_im4 (b_pow8_im[4] ),
|
||||
.a_re5 (ao_re[5] ),
|
||||
.a_im5 (ao_im[5] ),
|
||||
.b_re5 (bo_re[5] ),
|
||||
.b_im5 (bo_im[5] ),
|
||||
.ab_re5 (ab_re[5] ),
|
||||
.ab_im5 (ab_im[5] ),
|
||||
.abb_re5 (abb_re[5] ),
|
||||
.abb_im5 (abb_im[5] ),
|
||||
.ab_pow3_re5 (ab_pow3_re[5]),
|
||||
.ab_pow3_im5 (ab_pow3_im[5]),
|
||||
.ab_pow4_re5 (ab_pow4_re[5]),
|
||||
.ab_pow4_im5 (ab_pow4_im[5]),
|
||||
.ab_pow5_re5 (ab_pow5_re[5]),
|
||||
.ab_pow5_im5 (ab_pow5_im[5]),
|
||||
.ab_pow6_re5 (ab_pow6_re[5]),
|
||||
.ab_pow6_im5 (ab_pow6_im[5]),
|
||||
.ab_pow7_re5 (ab_pow7_re[5]),
|
||||
.ab_pow7_im5 (ab_pow7_im[5]),
|
||||
.b_pow8_re5 (b_pow8_re[5] ),
|
||||
.b_pow8_im5 (b_pow8_im[5] )
|
||||
);
|
||||
|
||||
wire signed [15:0] dout_0;
|
||||
wire signed [15:0] dout_1;
|
||||
wire signed [15:0] dout_2;
|
||||
wire signed [15:0] dout_3;
|
||||
wire signed [15:0] dout_4;
|
||||
wire signed [15:0] dout_5;
|
||||
wire signed [15:0] dout_6;
|
||||
wire signed [15:0] dout_7;
|
||||
wire vldo_TC;
|
||||
TailCorr_top inst_TailCorr_top
|
||||
(
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
.rstn (rstn ),
|
||||
.vldi (vldi_data ),
|
||||
// .dac_mode_sel (dac_mode_sel ),
|
||||
// .intp_mode (intp_mode ),
|
||||
.din0 (din0 ),
|
||||
.din1 (din1 ),
|
||||
.din2 (din2 ),
|
||||
.din3 (din3 ),
|
||||
.a_re0 (ao_re[0] ),
|
||||
.a_im0 (ao_im[0] ),
|
||||
.b_re0 (bo_re[0] ),
|
||||
.b_im0 (bo_im[0] ),
|
||||
.ab_re0 (ab_re[0] ),
|
||||
.ab_im0 (ab_im[0] ),
|
||||
.abb_re0 (abb_re[0] ),
|
||||
.abb_im0 (abb_im[0] ),
|
||||
.ab_pow3_re0 (ab_pow3_re[0]),
|
||||
.ab_pow3_im0 (ab_pow3_im[0]),
|
||||
.ab_pow4_re0 (ab_pow4_re[0]),
|
||||
.ab_pow4_im0 (ab_pow4_im[0]),
|
||||
.ab_pow5_re0 (ab_pow5_re[0]),
|
||||
.ab_pow5_im0 (ab_pow5_im[0]),
|
||||
.ab_pow6_re0 (ab_pow6_re[0]),
|
||||
.ab_pow6_im0 (ab_pow6_im[0]),
|
||||
.ab_pow7_re0 (ab_pow7_re[0]),
|
||||
.ab_pow7_im0 (ab_pow7_im[0]),
|
||||
.b_pow8_re0 (b_pow8_re[0] ),
|
||||
.b_pow8_im0 (b_pow8_im[0] ),
|
||||
.a_re1 (ao_re[1] ),
|
||||
.a_im1 (ao_im[1] ),
|
||||
.b_re1 (bo_re[1] ),
|
||||
.b_im1 (bo_im[1] ),
|
||||
.ab_re1 (ab_re[1] ),
|
||||
.ab_im1 (ab_im[1] ),
|
||||
.abb_re1 (abb_re[1] ),
|
||||
.abb_im1 (abb_im[1] ),
|
||||
.ab_pow3_re1 (ab_pow3_re[1]),
|
||||
.ab_pow3_im1 (ab_pow3_im[1]),
|
||||
.ab_pow4_re1 (ab_pow4_re[1]),
|
||||
.ab_pow4_im1 (ab_pow4_im[1]),
|
||||
.ab_pow5_re1 (ab_pow5_re[1]),
|
||||
.ab_pow5_im1 (ab_pow5_im[1]),
|
||||
.ab_pow6_re1 (ab_pow6_re[1]),
|
||||
.ab_pow6_im1 (ab_pow6_im[1]),
|
||||
.ab_pow7_re1 (ab_pow7_re[1]),
|
||||
.ab_pow7_im1 (ab_pow7_im[1]),
|
||||
.b_pow8_re1 (b_pow8_re[1] ),
|
||||
.b_pow8_im1 (b_pow8_im[1] ),
|
||||
.a_re2 (ao_re[2] ),
|
||||
.a_im2 (ao_im[2] ),
|
||||
.b_re2 (bo_re[2] ),
|
||||
.b_im2 (bo_im[2] ),
|
||||
.ab_re2 (ab_re[2] ),
|
||||
.ab_im2 (ab_im[2] ),
|
||||
.abb_re2 (abb_re[2] ),
|
||||
.abb_im2 (abb_im[2] ),
|
||||
.ab_pow3_re2 (ab_pow3_re[2]),
|
||||
.ab_pow3_im2 (ab_pow3_im[2]),
|
||||
.ab_pow4_re2 (ab_pow4_re[2]),
|
||||
.ab_pow4_im2 (ab_pow4_im[2]),
|
||||
.ab_pow5_re2 (ab_pow5_re[2]),
|
||||
.ab_pow5_im2 (ab_pow5_im[2]),
|
||||
.ab_pow6_re2 (ab_pow6_re[2]),
|
||||
.ab_pow6_im2 (ab_pow6_im[2]),
|
||||
.ab_pow7_re2 (ab_pow7_re[2]),
|
||||
.ab_pow7_im2 (ab_pow7_im[2]),
|
||||
.b_pow8_re2 (b_pow8_re[2] ),
|
||||
.b_pow8_im2 (b_pow8_im[2] ),
|
||||
.a_re3 (ao_re[3] ),
|
||||
.a_im3 (ao_im[3] ),
|
||||
.b_re3 (bo_re[3] ),
|
||||
.b_im3 (bo_im[3] ),
|
||||
.ab_re3 (ab_re[3] ),
|
||||
.ab_im3 (ab_im[3] ),
|
||||
.abb_re3 (abb_re[3] ),
|
||||
.abb_im3 (abb_im[3] ),
|
||||
.ab_pow3_re3 (ab_pow3_re[3]),
|
||||
.ab_pow3_im3 (ab_pow3_im[3]),
|
||||
.ab_pow4_re3 (ab_pow4_re[3]),
|
||||
.ab_pow4_im3 (ab_pow4_im[3]),
|
||||
.ab_pow5_re3 (ab_pow5_re[3]),
|
||||
.ab_pow5_im3 (ab_pow5_im[3]),
|
||||
.ab_pow6_re3 (ab_pow6_re[3]),
|
||||
.ab_pow6_im3 (ab_pow6_im[3]),
|
||||
.ab_pow7_re3 (ab_pow7_re[3]),
|
||||
.ab_pow7_im3 (ab_pow7_im[3]),
|
||||
.b_pow8_re3 (b_pow8_re[3] ),
|
||||
.b_pow8_im3 (b_pow8_im[3] ),
|
||||
.a_re4 (ao_re[4] ),
|
||||
.a_im4 (ao_im[4] ),
|
||||
.b_re4 (bo_re[4] ),
|
||||
.b_im4 (bo_im[4] ),
|
||||
.ab_re4 (ab_re[4] ),
|
||||
.ab_im4 (ab_im[4] ),
|
||||
.abb_re4 (abb_re[4] ),
|
||||
.abb_im4 (abb_im[4] ),
|
||||
.ab_pow3_re4 (ab_pow3_re[4]),
|
||||
.ab_pow3_im4 (ab_pow3_im[4]),
|
||||
.ab_pow4_re4 (ab_pow4_re[4]),
|
||||
.ab_pow4_im4 (ab_pow4_im[4]),
|
||||
.ab_pow5_re4 (ab_pow5_re[4]),
|
||||
.ab_pow5_im4 (ab_pow5_im[4]),
|
||||
.ab_pow6_re4 (ab_pow6_re[4]),
|
||||
.ab_pow6_im4 (ab_pow6_im[4]),
|
||||
.ab_pow7_re4 (ab_pow7_re[4]),
|
||||
.ab_pow7_im4 (ab_pow7_im[4]),
|
||||
.b_pow8_re4 (b_pow8_re[4] ),
|
||||
.b_pow8_im4 (b_pow8_im[4] ),
|
||||
.a_re5 (ao_re[5] ),
|
||||
.a_im5 (ao_im[5] ),
|
||||
.b_re5 (bo_re[5] ),
|
||||
.b_im5 (bo_im[5] ),
|
||||
.ab_re5 (ab_re[5] ),
|
||||
.ab_im5 (ab_im[5] ),
|
||||
.abb_re5 (abb_re[5] ),
|
||||
.abb_im5 (abb_im[5] ),
|
||||
.ab_pow3_re5 (ab_pow3_re[5]),
|
||||
.ab_pow3_im5 (ab_pow3_im[5]),
|
||||
.ab_pow4_re5 (ab_pow4_re[5]),
|
||||
.ab_pow4_im5 (ab_pow4_im[5]),
|
||||
.ab_pow5_re5 (ab_pow5_re[5]),
|
||||
.ab_pow5_im5 (ab_pow5_im[5]),
|
||||
.ab_pow6_re5 (ab_pow6_re[5]),
|
||||
.ab_pow6_im5 (ab_pow6_im[5]),
|
||||
.ab_pow7_re5 (ab_pow7_re[5]),
|
||||
.ab_pow7_im5 (ab_pow7_im[5]),
|
||||
.b_pow8_re5 (b_pow8_re[5] ),
|
||||
.b_pow8_im5 (b_pow8_im[5] ),
|
||||
.dout_p0 (dout_0 ),
|
||||
.dout_p1 (dout_1 ),
|
||||
.dout_p2 (dout_2 ),
|
||||
.dout_p3 (dout_3 ),
|
||||
.dout_p4 (dout_4 ),
|
||||
.dout_p5 (dout_5 ),
|
||||
.dout_p6 (dout_6 ),
|
||||
.dout_p7 (dout_7 ),
|
||||
.vldo (vldo_TC )
|
||||
|
||||
);
|
||||
|
||||
//assign vldo = vldo_TC;
|
||||
rate_adapter inst_rate_adapter(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
.vldi (vldo_TC ),
|
||||
.din0 (dout_0 ),
|
||||
.din1 (dout_1 ),
|
||||
.din2 (dout_2 ),
|
||||
.din3 (dout_3 ),
|
||||
.din4 (dout_4 ),
|
||||
.din5 (dout_5 ),
|
||||
.din6 (dout_6 ),
|
||||
.din7 (dout_7 ),
|
||||
.dout0 (dout0 ),
|
||||
.dout1 (dout1 ),
|
||||
.dout2 (dout2 ),
|
||||
.dout3 (dout3 ),
|
||||
.vldo (vldo )
|
||||
);
|
||||
|
||||
endmodule
|
||||
565
script_m/z_dsp.m
565
script_m/z_dsp.m
|
|
@ -1,565 +0,0 @@
|
|||
classdef z_dsp < handle
|
||||
properties
|
||||
%input
|
||||
fs_L;
|
||||
fs_H;
|
||||
TargetFrequency;
|
||||
G;
|
||||
simulink_time;
|
||||
intp_mode;
|
||||
dac_mode_sel;
|
||||
route_num;
|
||||
env_num;
|
||||
|
||||
%output
|
||||
Ideal2Low;
|
||||
Ideal2Target;
|
||||
wave_pre;
|
||||
wave_preL;
|
||||
amp_real;
|
||||
amp_imag;
|
||||
time_real;
|
||||
time_imag;
|
||||
name;
|
||||
wave_revised;
|
||||
wave_revisedL;
|
||||
DownsamplingBy12GDataAlign;
|
||||
HardwareMeanIntpDataAlign;
|
||||
Delay;
|
||||
Delay_mode;
|
||||
pause_time;
|
||||
filename;
|
||||
rpt_num;
|
||||
FallingEdge;
|
||||
Amp;
|
||||
itv_time; %信号具有周期性时的间隔
|
||||
end
|
||||
|
||||
methods
|
||||
|
||||
function obj = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel)
|
||||
obj.fs_L = fs_L;
|
||||
obj.fs_H = fs_H;
|
||||
obj.TargetFrequency = TargetFrequency;
|
||||
obj.G = G;
|
||||
obj.simulink_time = simulink_time;
|
||||
obj.intp_mode = intp_mode;
|
||||
obj.dac_mode_sel = dac_mode_sel;
|
||||
obj.Ideal2Low = fs_H/(fs_L/2);
|
||||
obj.Ideal2Target = fs_H/TargetFrequency;
|
||||
obj.name = [
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第一组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第一组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第二组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第二组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第三组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第三组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第四组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第四组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第五组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第五组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第一组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第一组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第二组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第二组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第三组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第三组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第四组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第四组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第五组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第五组S21参数_acz_持续时间50ns_下降沿后";
|
||||
];
|
||||
obj.pause_time = 0.5;
|
||||
obj.Amp = 1.5e4;
|
||||
end
|
||||
|
||||
function env(obj)
|
||||
|
||||
cd("D:\Work\EnvData\acz");
|
||||
obj1 = py.importlib.import_module('acz');
|
||||
py.importlib.reload(obj1);
|
||||
|
||||
%按点数产生理想方波
|
||||
% amp_rect = 1.5e4;
|
||||
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
|
||||
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
|
||||
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
|
||||
%
|
||||
% for i = 1:2
|
||||
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
|
||||
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
|
||||
% end
|
||||
%flattop波
|
||||
A = 1.5e4;
|
||||
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
|
||||
[edge(2), length_flattop(2)] = deal(4,30);
|
||||
[edge(3), length_flattop(3)] = deal(4,50);
|
||||
[edge(4), length_flattop(4)] = deal(4,1000);
|
||||
[edge(5), length_flattop(5)] = deal(100,10000);
|
||||
|
||||
for i = 1:length(length_flattop)
|
||||
[edge_H(i), length_H(i)] = deal(edge(i)*obj.fs_H/1e9,length_flattop(i)*obj.fs_H/1e9);
|
||||
obj.wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
|
||||
end
|
||||
|
||||
%acz波
|
||||
amplitude = 1.5e4;
|
||||
|
||||
carrierFreq = 0.000000;
|
||||
carrierPhase = 0.000000;
|
||||
dragAlpha = 0.000000;
|
||||
thf = 0.864;
|
||||
thi = 0.05;
|
||||
lam2 = -0.18;
|
||||
lam3 = 0.04;
|
||||
|
||||
length_acz(1) = 30;
|
||||
length_acz(2) = 50;
|
||||
|
||||
for i = 1:length(length_acz)
|
||||
length_acz_H(i) = int32(length_acz(i)*obj.fs_H/1e9);
|
||||
obj.wave_pre{i+length(length_flattop)} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
|
||||
end
|
||||
|
||||
obj.env_num = length(length_flattop) + length(length_acz);
|
||||
|
||||
for i = 1:obj.env_num
|
||||
obj.wave_pre{i} = cat(2,repmat(cat(2,obj.wave_pre{i},zeros(1,round(30e-9*obj.fs_H))),1,obj.rpt_num),zeros(1,floor(obj.simulink_time*obj.fs_H))); %校正前的高频信号
|
||||
obj.wave_preL{i} = obj.wave_pre{i}(1:obj.Ideal2Low:end); %校正前的低频信号
|
||||
end
|
||||
|
||||
assignin("base",'wave_preL',obj.wave_preL);
|
||||
obj.FallingEdge = [30e-9,30e-9,50e-9,1000e-9,10000e-9,30e-9,50e-9];
|
||||
|
||||
end
|
||||
|
||||
function route(obj)
|
||||
|
||||
obj.amp_real{1}= [0.025 0.015 0.0002 0.2 0 0];
|
||||
obj.amp_imag{1}= [0 0 0 0 0 0];
|
||||
obj.time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{1} = [0 0 0 0 0 0];
|
||||
|
||||
obj.amp_real{2}= [0.025 0.015 0.0002 0.2 0 0];
|
||||
obj.amp_imag{2}= [0 0 0 0 0 0];
|
||||
obj.time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{2} = [0 -1/300 -1/500 0 0 0];
|
||||
|
||||
obj.amp_real{3}= [0.025 0.009 0.0002 0.2 0 0];
|
||||
obj.amp_imag{3}= [0 0.012 0 0 0 0];
|
||||
obj.time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{3} = [0 -1/300 -1/500 0 0 0];
|
||||
|
||||
obj.amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
|
||||
obj.amp_imag{4}= [0 0 0 0 0 0];
|
||||
obj.time_real{4} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{4} = [0 -1/15 -1/50 0 0 0];
|
||||
|
||||
obj.amp_real{5}= [0.025 0.009 0.0002 0.2 0 0];
|
||||
obj.amp_imag{5}= [0 0.012 0 0 0 0];
|
||||
obj.time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{5} = [0 -1/15 -1/50 0 0 0];
|
||||
|
||||
[m,n] = size(obj.amp_real);
|
||||
obj.route_num = n;
|
||||
end
|
||||
|
||||
function py_cal(obj)
|
||||
|
||||
cd("D:\Work\TailCorr_20241008_NoGit");
|
||||
obj2 = py.importlib.import_module('wave_calculation');
|
||||
py.importlib.reload(obj2);
|
||||
cd("D:\Work\TailCorr");
|
||||
|
||||
convolve_bound = int8(3);
|
||||
calibration_time = int32(20e3);
|
||||
cal_method = int8(1);
|
||||
sampling_rateL = int64(obj.fs_L/2);
|
||||
sampling_rate = int64(obj.fs_H);
|
||||
|
||||
%校正后的高频信号
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:obj.env_num
|
||||
wave_cal = cell(py.wave_calculation.wave_cal(obj.wave_pre{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rate));
|
||||
obj.wave_revised{m,n} = double(wave_cal{1,1});
|
||||
wave_calL = cell(py.wave_calculation.wave_cal(obj.wave_preL{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rateL));
|
||||
obj.wave_revisedL{m,n} = double(wave_calL{1,1});
|
||||
end
|
||||
alpha{m} = double(wave_calL{1,2});
|
||||
beta{m} = double(wave_calL{1,3});
|
||||
end
|
||||
alpha_wideth=32;
|
||||
beta_width=32;
|
||||
%定点化系数
|
||||
for i = 1:obj.route_num
|
||||
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
|
||||
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
|
||||
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
|
||||
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
|
||||
end
|
||||
|
||||
assignin('base', 'alphaFixRe', alphaFixRe);
|
||||
assignin('base', 'alphaFixIm', alphaFixIm);
|
||||
assignin('base', 'betaFixRe' , betaFixRe);
|
||||
assignin('base', 'betaFixIm' , betaFixIm);
|
||||
end
|
||||
|
||||
function FIL(obj)
|
||||
|
||||
for m = 1:obj.route_num
|
||||
assignin('base', 'm', m);
|
||||
for n = 1:obj.env_num
|
||||
assignin('base', 'n', n);
|
||||
optnons=simset('SrcWorkspace','current');
|
||||
sim('z_dsp_FIL',[0,obj.simulink_time]);
|
||||
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
|
||||
dout0{m,n} = sim2m("dout0");
|
||||
dout1{m,n} = sim2m("dout1");
|
||||
dout2{m,n} = sim2m("dout2");
|
||||
dout3{m,n} = sim2m("dout3");
|
||||
|
||||
N = length(dout0{m,n});
|
||||
cs_wave{m,n} = zeros(4*N,1);
|
||||
|
||||
cs_wave{m,n}(1:4:4*N) = dout0{m,n};
|
||||
cs_wave{m,n}(2:4:4*N) = dout1{m,n};
|
||||
cs_wave{m,n}(3:4:4*N) = dout2{m,n};
|
||||
cs_wave{m,n}(4:4:4*N) = dout3{m,n};
|
||||
|
||||
HardwareMeanIntpData{m,n} = cs_wave{m,n};%硬件校正后内插
|
||||
DownsamplingBy12GData{m,n} = obj.wave_revised{m,n}(1:obj.Ideal2Target:end);
|
||||
[obj.DownsamplingBy12GDataAlign{m,n},obj.HardwareMeanIntpDataAlign{m,n},obj.Delay(m,n)] = ...
|
||||
alignsignals(DownsamplingBy12GData{m,n}(1:round(obj.TargetFrequency*20e-6)),HardwareMeanIntpData{m,n}(1:round(obj.TargetFrequency*20e-6)),"Method","xcorr");
|
||||
end
|
||||
end
|
||||
obj.Delay_mode = mode(obj.Delay,'all');
|
||||
fprintf('Delay_mode = %d\n',obj.Delay_mode);
|
||||
end
|
||||
|
||||
function DataShow(obj,save)
|
||||
|
||||
close all;
|
||||
|
||||
fileID = fopen(obj.filename, 'w');
|
||||
if fileID == -1
|
||||
disp('文件打开失败');
|
||||
else
|
||||
disp('文件打开成功');
|
||||
end
|
||||
|
||||
start_time = abs(obj.Delay_mode)/(obj.TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
|
||||
|
||||
if(obj.rpt_num == 1)
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:obj.env_num
|
||||
edge_Align(n) = obj.FallingEdge(n) + start_time;
|
||||
tmp(n) = edge_Align(n) + 10e-9;
|
||||
a{n} = [start_time-5e-9 tmp(n)];%[1/obj.fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
|
||||
b{n} = [tmp(n) 20e-6];
|
||||
|
||||
figure('Units','normalized','Position',[0.0004 0.5174 0.4992 0.4229]);
|
||||
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',a{n},obj.Amp,edge_Align(n),fileID);
|
||||
if(save == "save")
|
||||
savefig(obj.name(m,n));
|
||||
end
|
||||
|
||||
figure('Units','normalized','Position',[0.0004 0.0340 0.4992 0.4229]);
|
||||
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m+5,n),'硬件与脚本的差值',b{n},obj.Amp,edge_Align(n),fileID);
|
||||
if(save == "save")
|
||||
savefig(obj.name(m+5,n));
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:obj.env_num
|
||||
figure('Units','normalized','Position',[0 0.0333 1.0000 0.9125]);
|
||||
title(obj.name(m,n),Interpreter="none");
|
||||
tiledlayout('vertical','TileSpacing','tight')
|
||||
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',obj.FallingEdge(n)+obj.itv_time,obj.Amp,start_time,fileID);
|
||||
if(save == "save")
|
||||
savefig(obj.name(m,n));
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
fclose(fileID);
|
||||
|
||||
end
|
||||
|
||||
function RouteShow(obj,save)
|
||||
|
||||
t = 0:1/(1e2):10000;
|
||||
for i = 1:5
|
||||
amp_routing{i} = obj.amp_real{1,i} + 1j*obj.amp_imag{1,i};
|
||||
time_routing{i} = obj.time_real{1,i} + 1j*obj.time_imag{1,i};
|
||||
tau{i} = -1./time_routing{i};
|
||||
end
|
||||
|
||||
figure()
|
||||
set(gcf,"Position",[1 49 2560 1314])
|
||||
tiledlayout('flow','TileSpacing','tight');
|
||||
title_name = ["第一组S_{21}参数","第二组S_{21}参数","第三组S_{21}参数","第四组S_{21}参数","第五组S_{21}参数"];
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:1:length(amp_routing{1,m})
|
||||
S21_time{m}(:,n) = amp_routing{1,m}(n)*exp(time_routing{1,m}(n)*t);
|
||||
end
|
||||
nexttile
|
||||
plot(t*1e-9,real(sum(S21_time{m},2)));
|
||||
grid on
|
||||
title(title_name(m));
|
||||
end
|
||||
|
||||
if(save == "save")
|
||||
savefig("S21线路参数");
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
function FigDisplay(obj)
|
||||
if(obj.rpt_num == 1)
|
||||
for m = 1:obj.route_num*obj.env_num
|
||||
figure(2*m-1)
|
||||
figure(2*m)
|
||||
pause(obj.pause_time);
|
||||
end
|
||||
|
||||
else
|
||||
for m = 1:obj.route_num*obj.env_num
|
||||
figure(m)
|
||||
pause(obj.pause_time);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
function LoadFigAndDisplay(obj)
|
||||
for n = 1:obj.route_num
|
||||
for m = 1:obj.env_num
|
||||
open(strcat(obj.name(n,m),'.fig'));
|
||||
open(strcat(obj.name(n+5,m),'.fig'));
|
||||
pause(obj.pause_time);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
function ErrAny(obj,save)
|
||||
fid = fopen(obj.filename,'r');
|
||||
if(obj.rpt_num == 1)
|
||||
data = textscan(fid,'Falling edge of 20ns~40ns mean :%s std :%s Falling edge of 1us~1.1us mean :%s std :%s The mean and std stably less than 1e-4 is :%s s');
|
||||
fclose(fid);
|
||||
data{1} = cellfun(@str2num,data{1});
|
||||
data{2} = cellfun(@str2num,data{2});
|
||||
data{3} = cellfun(@str2num,data{3});
|
||||
data{4} = cellfun(@str2num,data{4});
|
||||
data{5} = cellfun(@str2num,data{5});
|
||||
title_name = ["下降沿后20ns~40ns误差的平均值","下降沿后20ns~40ns误差的标准差","下降沿后1us~1.1us误差的平均值","下降沿后1us~1.1us误差的标准差","加窗参数"];
|
||||
err_threshold = [1e-3 1e-3 1e-4 3e-4 5e-6];
|
||||
else
|
||||
data = textscan(fid,'每个周期拖尾误差均值的标准差 = %s s');
|
||||
fclose(fid);
|
||||
data{1} = cellfun(@str2num,data{1});
|
||||
title_name = ["多周期误差平均值的标准差"];
|
||||
err_threshold = [0.5e-3];
|
||||
end
|
||||
[h,v] = size(data);
|
||||
figure()
|
||||
tiledlayout('flow','TileSpacing','tight')
|
||||
colors = lines(obj.route_num);
|
||||
set(gcf,'Position', [1 49 2560 1314]);
|
||||
for m = 1:v
|
||||
nexttile
|
||||
hold on
|
||||
for i = 1:(obj.route_num)
|
||||
idx = (i-1)*(length(data{m})/obj.route_num) + 1 : i*(length(data{m})/obj.route_num);
|
||||
plot(idx,abs(data{m}(idx)),'-o','Color', colors(i, :));
|
||||
end
|
||||
yline(err_threshold(m),'--r');
|
||||
title(title_name(m));
|
||||
set(gca,'YScale','log');
|
||||
legend("第一组线路","第二组线路","第三组线路","第四组线路","第五组线路",'Location','northwest');
|
||||
end
|
||||
if(obj.rpt_num == 1)
|
||||
if(save == "save")
|
||||
savefig("单周期误差分析")
|
||||
end
|
||||
else
|
||||
if(save == "save")
|
||||
savefig("多周期误差分析")
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
%compare FIL with python script
|
||||
function diff_plot_py(obj,fs,iir_out, Script_out,title1,title2,a,amp,edge,fileID)
|
||||
|
||||
%输入数据长度不等时取其公共部分
|
||||
N = min(length(iir_out),length(Script_out));
|
||||
iir_out = iir_out(1:N);
|
||||
Script_out = Script_out(1:N);
|
||||
|
||||
diff = (iir_out - Script_out)/amp;%求差，并归一化
|
||||
|
||||
n = (0:1:N-1)/fs;
|
||||
%找出关心的数据点
|
||||
if(obj.rpt_num == 1)
|
||||
n_edge = find(n>=edge-1e-12);%edge代表下降沿
|
||||
n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
|
||||
n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
|
||||
n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
|
||||
n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
|
||||
|
||||
ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
|
||||
ne(1) = 1;
|
||||
|
||||
window_length = 100e-9*fs;
|
||||
diff_mean_window = movmean(diff,window_length);
|
||||
diff_std_window = movstd(diff,window_length);
|
||||
n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
|
||||
n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
|
||||
n_common = max(n_mean_window(end),n_std_window(end));
|
||||
%原始数据作图
|
||||
tiledlayout(2,1)
|
||||
ax1 = nexttile;
|
||||
plot(n,iir_out,n,Script_out)
|
||||
legend('硬件','软件');
|
||||
xlabel('t/s')
|
||||
xlim(a);
|
||||
title(title1,Interpreter="none");
|
||||
grid on
|
||||
hold on
|
||||
|
||||
%差值做图
|
||||
ax2 = nexttile;
|
||||
plot(n,diff)
|
||||
xlabel('t/s')
|
||||
title('diff')
|
||||
grid on
|
||||
hold on
|
||||
xlim(a)
|
||||
title('硬件与脚本的差值',Interpreter="none");
|
||||
linkaxes([ax1,ax2],'x');
|
||||
|
||||
plot_p = @(x)[
|
||||
plot(n(x),diff(x),'r*');
|
||||
text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
|
||||
];
|
||||
|
||||
ne(1) = 1;
|
||||
|
||||
% [diff_max,R_mpos] = max(abs(diff));%误差最大值
|
||||
% plot_p(R_mpos);
|
||||
|
||||
if a(2) <= 5e-6
|
||||
plot_p(n_edge(1));%下降沿
|
||||
% plot_p(R_mpos);
|
||||
elseif a(2) == 20e-6
|
||||
plot_p(n50(1)); %下降沿20ns
|
||||
plot_p(n1000(1)); %下降沿1us
|
||||
plot_p(ne(end)); %误差小于万分之一
|
||||
fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
|
||||
fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100)));
|
||||
% fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
|
||||
% fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
|
||||
fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
|
||||
end
|
||||
else
|
||||
n_start = find(n>=edge-1e-12);%edge代表下降沿
|
||||
|
||||
% 确定周期长度对应的采样点数量
|
||||
T = a; %在这种情况下，a这个参数用不到了，使用其传递周期，也就是说a这个参数有两种不同的涵义
|
||||
samples_per_period = round(T * fs); % 每个周期采样点数
|
||||
num_periods = obj.rpt_num; % 总周期数
|
||||
period_means = zeros(1, num_periods); % 存储每周期均值
|
||||
|
||||
for i = 1:num_periods
|
||||
% 提取当前周期的起止索引
|
||||
start_idx(i) = n_start(1) + (i - 1) * samples_per_period;
|
||||
end_idx(i) = n_start(1) + i * samples_per_period;
|
||||
|
||||
% 提取当前周期的数据
|
||||
period_data = diff(start_idx(i):end_idx(i));
|
||||
|
||||
% 计算当前周期的均值
|
||||
period_means(i) = mean(period_data);
|
||||
end
|
||||
fprintf(fileID,"每个周期拖尾误差均值的标准差 = %.4e s\n",std(period_means));
|
||||
ax1 = nexttile;
|
||||
plot(n,iir_out,n,Script_out);
|
||||
hold on
|
||||
plot(n(start_idx), Script_out(start_idx), 'r*'); % 标记每个周期的起始点
|
||||
plot(n(end_idx), Script_out(end_idx), 'g*'); % 标记每个周期的起始点
|
||||
legend('硬件','软件');
|
||||
xlabel('t/s');
|
||||
title(title1,Interpreter="none");
|
||||
ax2 = nexttile;
|
||||
hold on
|
||||
plot(n, diff); hold on; % 原始信号
|
||||
plot(n(end_idx), diff(end_idx), 'g*'); % 标记每个周期的起始点
|
||||
xlabel('t/s');
|
||||
ylabel('归一化误差');
|
||||
linkaxes([ax1,ax2],'x');
|
||||
xlim([0,n(end_idx(end)) + 5e-7]);
|
||||
title(title2,Interpreter="none");
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
clc;clear;close all
|
||||
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
|
||||
|
||||
fs_L = 0.75e9; %硬件频率
|
||||
fs_H = 12e9; %以高频近似理想信号
|
||||
TargetFrequency = 3e9;
|
||||
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
|
||||
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
|
||||
route_num = 1; %线路个数
|
||||
env_num = 1; %包络个数
|
||||
alpha_wideth=32; %滤波器系数定点化
|
||||
beta_width=32;
|
||||
G = 1;
|
||||
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
|
||||
|
||||
z_dsp1 = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel);
|
||||
z_dsp1.filename = 'output.txt';
|
||||
z_dsp1.rpt_num = 1;
|
||||
if(z_dsp1.rpt_num > 1)
|
||||
z_dsp1.name = [
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第一组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第一组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第二组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第二组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第三组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第三组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第四组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第四组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第五组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第五组S21参数_acz_持续时间50ns_重复100次";
|
||||
];
|
||||
z_dsp1.FallingEdge = [30e-9 30e-9 50e-9 30e-9 50e-9];
|
||||
z_dsp1.itv_time = 30e-9;
|
||||
end
|
||||
z_dsp1.env(); %产生理想z信号
|
||||
z_dsp1.route(); %配置线路参数
|
||||
% z_dsp1.route_num = 1;
|
||||
% z_dsp1.env_num = 1;
|
||||
z_dsp1.py_cal(); %12G采样率，基于python脚本计算校正后的波形
|
||||
z_dsp1.FIL(); %调用FIL模块计算校正后的波形
|
||||
z_dsp1.DataShow("save"); %计算结束后展示波形，有save时保存图片
|
||||
%%
|
||||
z_dsp1.FigDisplay(); %图片播放
|
||||
%%
|
||||
z_dsp1.RouteShow("save"); %可视化线路参数
|
||||
%%
|
||||
z_dsp1.ErrAny("save") %对关心的指标进行可视化处理
|
||||
%%
|
||||
close all
|
||||
z_dsp1.pause_time = 0.3;
|
||||
z_dsp1.LoadFigAndDisplay()
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
../../rtl/z_dsp/mult_C.v
|
||||
../../rtl/z_dsp/mult_x.v
|
||||
../../rtl/z_dsp/Trunc.v
|
||||
../../rtl/z_dsp/TailCorr_top.v
|
||||
../../rtl/z_dsp/IIR_top.v
|
||||
../../rtl/z_dsp/diff_p.v
|
||||
../../rtl/z_dsp/s2p_2.v
|
||||
../../rtl/z_dsp/IIR_Filter_p8.v
|
||||
../../rtl/z_dsp/IIR_Filter_p1.v
|
||||
../../rtl/z_dsp/sirv_gnrl_dffs.v
|
||||
../../rtl/model/DW02_mult.v
|
||||
|
||||
tb_TailCorr_en.v
|
||||
|
||||
|
|
@ -1,36 +1,4 @@
|
|||
module TB();
|
||||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : tb_TailCorr_en.v
|
||||
// Department : HFNL
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 2025-03-03 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
reg [1 :0] source_mode;
|
||||
|
|
@ -436,7 +404,7 @@ assign dac_mode_sel = 2'b00;
|
|||
|
||||
wire tc_bypass;
|
||||
wire vldo;
|
||||
wire vldo_ref;
|
||||
//wire vldo_ref;
|
||||
|
||||
assign tc_bypass = 1'b0;
|
||||
|
||||
|
|
@ -450,7 +418,6 @@ always @(posedge clk or negedge rstn)begin
|
|||
end
|
||||
end
|
||||
wire signed [15:0] dout_p[7:0];
|
||||
wire signed [15:0] dout_ref_p[7:0];
|
||||
|
||||
|
||||
TailCorr_top inst_TailCorr_top
|
||||
|
|
@ -598,152 +565,6 @@ TailCorr_top inst_TailCorr_top
|
|||
|
||||
);
|
||||
|
||||
TailCorr_top_ref refm_TailCorr_top
|
||||
(
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
.rstn (rstn ),
|
||||
.vldi (vldi_matlab[0] ),
|
||||
// .dac_mode_sel (dac_mode_sel ),
|
||||
// .intp_mode (intp_mode ),
|
||||
.din0 (iir_in[0]),
|
||||
.din1 (iir_in[1]),
|
||||
.din2 (iir_in[2]),
|
||||
.din3 (iir_in[3]),
|
||||
.a_re0 (a_re0),
|
||||
.a_im0 (a_im0),
|
||||
//.b_re0 (b_re0),
|
||||
//.b_im0 (b_im0),
|
||||
.ab_re0 (ab_re0),
|
||||
.ab_im0 (ab_im0),
|
||||
.abb_re0 (abb_re0),
|
||||
.abb_im0 (abb_im0),
|
||||
.ab_pow3_re0 (ab_pow3_re0),
|
||||
.ab_pow3_im0 (ab_pow3_im0),
|
||||
.ab_pow4_re0 (ab_pow4_re0),
|
||||
.ab_pow4_im0 (ab_pow4_im0),
|
||||
.ab_pow5_re0 (ab_pow5_re0),
|
||||
.ab_pow5_im0 (ab_pow5_im0),
|
||||
.ab_pow6_re0 (ab_pow6_re0),
|
||||
.ab_pow6_im0 (ab_pow6_im0),
|
||||
.ab_pow7_re0 (ab_pow7_re0),
|
||||
.ab_pow7_im0 (ab_pow7_im0),
|
||||
.b_pow8_re0 (b_pow8_re0),
|
||||
.b_pow8_im0 (b_pow8_im0),
|
||||
.a_re1 (a_re1),
|
||||
.a_im1 (a_im1),
|
||||
//.b_re1 (b_re1),
|
||||
//.b_im1 (b_im1),
|
||||
.ab_re1 (ab_re1),
|
||||
.ab_im1 (ab_im1),
|
||||
.abb_re1 (abb_re1),
|
||||
.abb_im1 (abb_im1),
|
||||
.ab_pow3_re1 (ab_pow3_re1),
|
||||
.ab_pow3_im1 (ab_pow3_im1),
|
||||
.ab_pow4_re1 (ab_pow4_re1),
|
||||
.ab_pow4_im1 (ab_pow4_im1),
|
||||
.ab_pow5_re1 (ab_pow5_re1),
|
||||
.ab_pow5_im1 (ab_pow5_im1),
|
||||
.ab_pow6_re1 (ab_pow6_re1),
|
||||
.ab_pow6_im1 (ab_pow6_im1),
|
||||
.ab_pow7_re1 (ab_pow7_re1),
|
||||
.ab_pow7_im1 (ab_pow7_im1),
|
||||
.b_pow8_re1 (b_pow8_re1),
|
||||
.b_pow8_im1 (b_pow8_im1),
|
||||
.a_re2 (a_re2),
|
||||
.a_im2 (a_im2),
|
||||
//.b_re2 (b_re2),
|
||||
//.b_im2 (b_im2),
|
||||
.ab_re2 (ab_re2),
|
||||
.ab_im2 (ab_im2),
|
||||
.abb_re2 (abb_re2),
|
||||
.abb_im2 (abb_im2),
|
||||
.ab_pow3_re2 (ab_pow3_re2),
|
||||
.ab_pow3_im2 (ab_pow3_im2),
|
||||
.ab_pow4_re2 (ab_pow4_re2),
|
||||
.ab_pow4_im2 (ab_pow4_im2),
|
||||
.ab_pow5_re2 (ab_pow5_re2),
|
||||
.ab_pow5_im2 (ab_pow5_im2),
|
||||
.ab_pow6_re2 (ab_pow6_re2),
|
||||
.ab_pow6_im2 (ab_pow6_im2),
|
||||
.ab_pow7_re2 (ab_pow7_re2),
|
||||
.ab_pow7_im2 (ab_pow7_im2),
|
||||
.b_pow8_re2 (b_pow8_re2),
|
||||
.b_pow8_im2 (b_pow8_im2),
|
||||
.a_re3 (a_re3),
|
||||
.a_im3 (a_im3),
|
||||
//.b_re3 (b_re3),
|
||||
//.b_im3 (b_im3),
|
||||
.ab_re3 (ab_re3),
|
||||
.ab_im3 (ab_im3),
|
||||
.abb_re3 (abb_re3),
|
||||
.abb_im3 (abb_im3),
|
||||
.ab_pow3_re3 (ab_pow3_re3),
|
||||
.ab_pow3_im3 (ab_pow3_im3),
|
||||
.ab_pow4_re3 (ab_pow4_re3),
|
||||
.ab_pow4_im3 (ab_pow4_im3),
|
||||
.ab_pow5_re3 (ab_pow5_re3),
|
||||
.ab_pow5_im3 (ab_pow5_im3),
|
||||
.ab_pow6_re3 (ab_pow6_re3),
|
||||
.ab_pow6_im3 (ab_pow6_im3),
|
||||
.ab_pow7_re3 (ab_pow7_re3),
|
||||
.ab_pow7_im3 (ab_pow7_im3),
|
||||
.b_pow8_re3 (b_pow8_re3),
|
||||
.b_pow8_im3 (b_pow8_im3),
|
||||
.a_re4 (a_re4),
|
||||
.a_im4 (a_im4),
|
||||
//.b_re4 (b_re4),
|
||||
//.b_im4 (b_im4),
|
||||
.ab_re4 (ab_re4),
|
||||
.ab_im4 (ab_im4),
|
||||
.abb_re4 (abb_re4),
|
||||
.abb_im4 (abb_im4),
|
||||
.ab_pow3_re4 (ab_pow3_re4),
|
||||
.ab_pow3_im4 (ab_pow3_im4),
|
||||
.ab_pow4_re4 (ab_pow4_re4),
|
||||
.ab_pow4_im4 (ab_pow4_im4),
|
||||
.ab_pow5_re4 (ab_pow5_re4),
|
||||
.ab_pow5_im4 (ab_pow5_im4),
|
||||
.ab_pow6_re4 (ab_pow6_re4),
|
||||
.ab_pow6_im4 (ab_pow6_im4),
|
||||
.ab_pow7_re4 (ab_pow7_re4),
|
||||
.ab_pow7_im4 (ab_pow7_im4),
|
||||
.b_pow8_re4 (b_pow8_re4),
|
||||
.b_pow8_im4 (b_pow8_im4),
|
||||
.a_re5 (a_re5),
|
||||
.a_im5 (a_im5),
|
||||
//.b_re5 (b_re5),
|
||||
//.b_im5 (b_im5),
|
||||
.ab_re5 (ab_re5),
|
||||
.ab_im5 (ab_im5),
|
||||
.abb_re5 (abb_re5),
|
||||
.abb_im5 (abb_im5),
|
||||
.ab_pow3_re5 (ab_pow3_re5),
|
||||
.ab_pow3_im5 (ab_pow3_im5),
|
||||
.ab_pow4_re5 (ab_pow4_re5),
|
||||
.ab_pow4_im5 (ab_pow4_im5),
|
||||
.ab_pow5_re5 (ab_pow5_re5),
|
||||
.ab_pow5_im5 (ab_pow5_im5),
|
||||
.ab_pow6_re5 (ab_pow6_re5),
|
||||
.ab_pow6_im5 (ab_pow6_im5),
|
||||
.ab_pow7_re5 (ab_pow7_re5),
|
||||
.ab_pow7_im5 (ab_pow7_im5),
|
||||
.b_pow8_re5 (b_pow8_re5),
|
||||
.b_pow8_im5 (b_pow8_im5),
|
||||
.dout_p0 (dout_ref_p[0] ),
|
||||
.dout_p1 (dout_ref_p[1] ),
|
||||
.dout_p2 (dout_ref_p[2] ),
|
||||
.dout_p3 (dout_ref_p[3] ),
|
||||
.dout_p4 (dout_ref_p[4] ),
|
||||
.dout_p5 (dout_ref_p[5] ),
|
||||
.dout_p6 (dout_ref_p[6] ),
|
||||
.dout_p7 (dout_ref_p[7] ),
|
||||
|
||||
.vldo (vldo_ref )
|
||||
|
||||
);
|
||||
|
||||
|
||||
integer signed In_fid[0:3];
|
||||
integer signed dout_fid[0:7];
|
||||
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
|
||||
|
|
@ -764,9 +585,6 @@ always @(posedge clk) begin
|
|||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
|
||||
end
|
||||
// for (int i = 0; i < 8; i = i + 1) begin
|
||||
// $fclose(In_fid[i]);
|
||||
// end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -775,9 +593,6 @@ always @(posedge clk) begin
|
|||
for (int i = 0; i < 8; i = i + 1) begin
|
||||
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
|
||||
end
|
||||
// for (int i = 0; i < 8; i = i + 1) begin
|
||||
// $fclose(dout_fid[i]);
|
||||
// end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
20
sim/files.f
20
sim/files.f
|
|
@ -1,20 +0,0 @@
|
|||
../rtl/z_dsp/mult_C.v
|
||||
../rtl/z_dsp/mult_x.v
|
||||
../rtl/z_dsp/Trunc.v
|
||||
../rtl/z_dsp/TailCorr_top.v
|
||||
../rtl/z_dsp/IIR_top.v
|
||||
../rtl/z_dsp/diff_p.v
|
||||
../rtl/z_dsp/s2p_2.v
|
||||
../rtl/z_dsp/IIR_Filter_p8.v
|
||||
../rtl/z_dsp/IIR_Filter_p1.v
|
||||
../rtl/ref/mult_C.v
|
||||
../rtl/ref/FixRound.v
|
||||
../rtl/ref/TailCorr_top.v
|
||||
../rtl/ref/IIR_top.v
|
||||
../rtl/ref/diff_p.v
|
||||
../rtl/ref/s2p_2.v
|
||||
../rtl/ref/IIR_Filter_p8.v
|
||||
../rtl/model/DW02_mult.v
|
||||
|
||||
tb_TailCorr_en.v
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
SIMV = ./simv -l sim.log +fsdb+delta
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
|
||||
file:
|
||||
find ../../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
../../rtl/z_dsp/s2p_2.v
|
||||
../../rtl/z_dsp/sirv_gnrl_dffs.v
|
||||
tb_s2p_2.v
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
|
||||
reg clk;
|
||||
reg rst_n;
|
||||
reg [15:0] din;
|
||||
reg enable;
|
||||
reg vldo;
|
||||
reg [21:0] cnt;
|
||||
wire [15:0] dout0;
|
||||
wire [15:0] dout1;
|
||||
|
||||
s2p_2 u_s2p_2(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.din ( din ),
|
||||
.en ( enable ),
|
||||
.dout0 ( dout0 ),
|
||||
.dout1 ( dout1 ),
|
||||
.vldo ( vldo )
|
||||
);
|
||||
|
||||
reg[15:0] din_r1;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
din_r1 <= 0;
|
||||
end
|
||||
else begin
|
||||
din_r1 <= din;
|
||||
end
|
||||
end
|
||||
|
||||
wire signed [15:0] diff;
|
||||
assign diff = din - din_r1;
|
||||
|
||||
reg[15:0] dout1_r1;
|
||||
reg[15:0] dout1_r2;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout1_r1 <= 0;
|
||||
dout1_r2 <= 0;
|
||||
end
|
||||
else begin
|
||||
dout1_r1 <= dout1;
|
||||
dout1_r2 <= dout1_r1;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
wire signed [15:0] diff12;
|
||||
wire signed [15:0] diff23;
|
||||
assign diff12 = dout0 - dout1_r2;
|
||||
assign diff23 = dout1 - dout0;
|
||||
|
||||
initial begin
|
||||
rst_n = 0;
|
||||
enable = 0;
|
||||
clk = 1'b0;
|
||||
din = 16'h0000;
|
||||
|
||||
|
||||
#20;
|
||||
rst_n = 1;
|
||||
|
||||
|
||||
#10;
|
||||
|
||||
end
|
||||
|
||||
|
||||
always #5 clk = ~clk;
|
||||
|
||||
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (rst_n == 1'b0) begin
|
||||
cnt <= 22'd0;
|
||||
end else begin
|
||||
cnt <= cnt + 22'd1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [15:0] enable_cnt;
|
||||
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (rst_n == 1'b0) begin
|
||||
enable <= 0;
|
||||
din <= 16'd0;
|
||||
enable_cnt <= 0;
|
||||
end else begin
|
||||
|
||||
if (cnt < 1000) begin
|
||||
if (enable_cnt == 0) begin
|
||||
if ($urandom % 2 == 0) begin
|
||||
enable <= 1;
|
||||
enable_cnt <= $urandom % 10 + 5;
|
||||
din <= $urandom;
|
||||
end else begin
|
||||
enable <= 0;
|
||||
din <= 16'd0;
|
||||
end
|
||||
end else begin
|
||||
|
||||
enable <= 1;
|
||||
enable_cnt <= enable_cnt - 1;
|
||||
din <= $urandom;
|
||||
end
|
||||
end else begin
|
||||
enable <= 0;
|
||||
din <= 16'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
initial begin
|
||||
wait(cnt[11] == 1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
ifdef seed
|
||||
vcs_run_opts += +ntb_random_seed=${seed}
|
||||
else
|
||||
vcs_run_opts += +ntb_random_seed_automatic
|
||||
endif
|
||||
|
||||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
|
||||
file:
|
||||
find ../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
../../rtl/z_dsp/CoefGen.sv
|
||||
../../rtl/z_dsp/mult_C.v
|
||||
../../rtl/z_dsp/Trunc.v
|
||||
../../rtl/z_dsp/sirv_gnrl_dffs.v
|
||||
../../rtl/model/DW02_mult.v
|
||||
tb_CoefGen.v
|
||||
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
|
||||
`timescale 1 ns/1 ns
|
||||
|
||||
module TB();
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
$fsdbDumpMDA();
|
||||
end
|
||||
|
||||
|
||||
|
||||
reg clk ;
|
||||
reg en;
|
||||
reg [5:0] vldi;
|
||||
reg rst_n;
|
||||
|
||||
|
||||
reg signed [31:0] a_re [5:0];
|
||||
reg signed [31:0] a_im [5:0];
|
||||
reg signed [31:0] b_re [5:0];
|
||||
reg signed [31:0] b_im [5:0];
|
||||
|
||||
|
||||
wire signed [31:0] ao_re [5:0];
|
||||
wire signed [31:0] ao_im [5:0];
|
||||
wire signed [31:0] ab_re [5:0];
|
||||
wire signed [31:0] ab_im [5:0];
|
||||
wire signed [31:0] abb_re [5:0];
|
||||
wire signed [31:0] abb_im [5:0];
|
||||
wire signed [31:0] ab_pow3_re [5:0];
|
||||
wire signed [31:0] ab_pow3_im [5:0];
|
||||
wire signed [31:0] ab_pow4_re [5:0];
|
||||
wire signed [31:0] ab_pow4_im [5:0];
|
||||
wire signed [31:0] ab_pow5_re [5:0];
|
||||
wire signed [31:0] ab_pow5_im [5:0];
|
||||
wire signed [31:0] ab_pow6_re [5:0];
|
||||
wire signed [31:0] ab_pow6_im [5:0];
|
||||
wire signed [31:0] ab_pow7_re [5:0];
|
||||
wire signed [31:0] ab_pow7_im [5:0];
|
||||
wire signed [31:0] bo_re [5:0];
|
||||
wire signed [31:0] bo_im [5:0];
|
||||
wire signed [31:0] b_pow8_re [5:0];
|
||||
wire signed [31:0] b_pow8_im [5:0];
|
||||
|
||||
|
||||
parameter CYCLE = 20;
|
||||
|
||||
|
||||
parameter RST_TIME = 3 ;
|
||||
|
||||
CoefGen inst_CoefGen(
|
||||
.clk (clk ),
|
||||
.rstn (rst_n ),
|
||||
.vldi (vldi ),
|
||||
.a0_re (a_re[0] ),
|
||||
.a0_im (a_im[0] ),
|
||||
.b0_re (b_re[0] ),
|
||||
.b0_im (b_im[0] ),
|
||||
.a1_re (a_re[1] ),
|
||||
.a1_im (a_im[1] ),
|
||||
.b1_re (b_re[1] ),
|
||||
.b1_im (b_im[1] ),
|
||||
.a2_re (a_re[2] ),
|
||||
.a2_im (a_im[2] ),
|
||||
.b2_re (b_re[2] ),
|
||||
.b2_im (b_im[2] ),
|
||||
.a3_re (a_re[3] ),
|
||||
.a3_im (a_im[3] ),
|
||||
.b3_re (b_re[3] ),
|
||||
.b3_im (b_im[3] ),
|
||||
.a4_re (a_re[4] ),
|
||||
.a4_im (a_im[4] ),
|
||||
.b4_re (b_re[4] ),
|
||||
.b4_im (b_im[4] ),
|
||||
.a5_re (a_re[5] ),
|
||||
.a5_im (a_im[5] ),
|
||||
.b5_re (b_re[5] ),
|
||||
.b5_im (b_im[5] ),
|
||||
.a_re0 (ao_re[0] ),
|
||||
.a_im0 (ao_im[0] ),
|
||||
.b_re0 (bo_re[0] ),
|
||||
.b_im0 (bo_im[0] ),
|
||||
.ab_re0 (ab_re[0] ),
|
||||
.ab_im0 (ab_im[0] ),
|
||||
.abb_re0 (abb_re[0] ),
|
||||
.abb_im0 (abb_im[0] ),
|
||||
.ab_pow3_re0 (ab_pow3_re[0]),
|
||||
.ab_pow3_im0 (ab_pow3_im[0]),
|
||||
.ab_pow4_re0 (ab_pow4_re[0]),
|
||||
.ab_pow4_im0 (ab_pow4_im[0]),
|
||||
.ab_pow5_re0 (ab_pow5_re[0]),
|
||||
.ab_pow5_im0 (ab_pow5_im[0]),
|
||||
.ab_pow6_re0 (ab_pow6_re[0]),
|
||||
.ab_pow6_im0 (ab_pow6_im[0]),
|
||||
.ab_pow7_re0 (ab_pow7_re[0]),
|
||||
.ab_pow7_im0 (ab_pow7_im[0]),
|
||||
.b_pow8_re0 (b_pow8_re[0] ),
|
||||
.b_pow8_im0 (b_pow8_im[0] ),
|
||||
.a_re1 (ao_re[1] ),
|
||||
.a_im1 (ao_im[1] ),
|
||||
.b_re1 (bo_re[1] ),
|
||||
.b_im1 (bo_im[1] ),
|
||||
.ab_re1 (ab_re[1] ),
|
||||
.ab_im1 (ab_im[1] ),
|
||||
.abb_re1 (abb_re[1] ),
|
||||
.abb_im1 (abb_im[1] ),
|
||||
.ab_pow3_re1 (ab_pow3_re[1]),
|
||||
.ab_pow3_im1 (ab_pow3_im[1]),
|
||||
.ab_pow4_re1 (ab_pow4_re[1]),
|
||||
.ab_pow4_im1 (ab_pow4_im[1]),
|
||||
.ab_pow5_re1 (ab_pow5_re[1]),
|
||||
.ab_pow5_im1 (ab_pow5_im[1]),
|
||||
.ab_pow6_re1 (ab_pow6_re[1]),
|
||||
.ab_pow6_im1 (ab_pow6_im[1]),
|
||||
.ab_pow7_re1 (ab_pow7_re[1]),
|
||||
.ab_pow7_im1 (ab_pow7_im[1]),
|
||||
.b_pow8_re1 (b_pow8_re[1] ),
|
||||
.b_pow8_im1 (b_pow8_im[1] ),
|
||||
.a_re2 (ao_re[2] ),
|
||||
.a_im2 (ao_im[2] ),
|
||||
.b_re2 (bo_re[2] ),
|
||||
.b_im2 (bo_im[2] ),
|
||||
.ab_re2 (ab_re[2] ),
|
||||
.ab_im2 (ab_im[2] ),
|
||||
.abb_re2 (abb_re[2] ),
|
||||
.abb_im2 (abb_im[2] ),
|
||||
.ab_pow3_re2 (ab_pow3_re[2]),
|
||||
.ab_pow3_im2 (ab_pow3_im[2]),
|
||||
.ab_pow4_re2 (ab_pow4_re[2]),
|
||||
.ab_pow4_im2 (ab_pow4_im[2]),
|
||||
.ab_pow5_re2 (ab_pow5_re[2]),
|
||||
.ab_pow5_im2 (ab_pow5_im[2]),
|
||||
.ab_pow6_re2 (ab_pow6_re[2]),
|
||||
.ab_pow6_im2 (ab_pow6_im[2]),
|
||||
.ab_pow7_re2 (ab_pow7_re[2]),
|
||||
.ab_pow7_im2 (ab_pow7_im[2]),
|
||||
.b_pow8_re2 (b_pow8_re[2] ),
|
||||
.b_pow8_im2 (b_pow8_im[2] ),
|
||||
.a_re3 (ao_re[3] ),
|
||||
.a_im3 (ao_im[3] ),
|
||||
.b_re3 (bo_re[3] ),
|
||||
.b_im3 (bo_im[3] ),
|
||||
.ab_re3 (ab_re[3] ),
|
||||
.ab_im3 (ab_im[3] ),
|
||||
.abb_re3 (abb_re[3] ),
|
||||
.abb_im3 (abb_im[3] ),
|
||||
.ab_pow3_re3 (ab_pow3_re[3]),
|
||||
.ab_pow3_im3 (ab_pow3_im[3]),
|
||||
.ab_pow4_re3 (ab_pow4_re[3]),
|
||||
.ab_pow4_im3 (ab_pow4_im[3]),
|
||||
.ab_pow5_re3 (ab_pow5_re[3]),
|
||||
.ab_pow5_im3 (ab_pow5_im[3]),
|
||||
.ab_pow6_re3 (ab_pow6_re[3]),
|
||||
.ab_pow6_im3 (ab_pow6_im[3]),
|
||||
.ab_pow7_re3 (ab_pow7_re[3]),
|
||||
.ab_pow7_im3 (ab_pow7_im[3]),
|
||||
.b_pow8_re3 (b_pow8_re[3] ),
|
||||
.b_pow8_im3 (b_pow8_im[3] ),
|
||||
.a_re4 (ao_re[4] ),
|
||||
.a_im4 (ao_im[4] ),
|
||||
.b_re4 (bo_re[4] ),
|
||||
.b_im4 (bo_im[4] ),
|
||||
.ab_re4 (ab_re[4] ),
|
||||
.ab_im4 (ab_im[4] ),
|
||||
.abb_re4 (abb_re[4] ),
|
||||
.abb_im4 (abb_im[4] ),
|
||||
.ab_pow3_re4 (ab_pow3_re[4]),
|
||||
.ab_pow3_im4 (ab_pow3_im[4]),
|
||||
.ab_pow4_re4 (ab_pow4_re[4]),
|
||||
.ab_pow4_im4 (ab_pow4_im[4]),
|
||||
.ab_pow5_re4 (ab_pow5_re[4]),
|
||||
.ab_pow5_im4 (ab_pow5_im[4]),
|
||||
.ab_pow6_re4 (ab_pow6_re[4]),
|
||||
.ab_pow6_im4 (ab_pow6_im[4]),
|
||||
.ab_pow7_re4 (ab_pow7_re[4]),
|
||||
.ab_pow7_im4 (ab_pow7_im[4]),
|
||||
.b_pow8_re4 (b_pow8_re[4] ),
|
||||
.b_pow8_im4 (b_pow8_im[4] ),
|
||||
.a_re5 (ao_re[5] ),
|
||||
.a_im5 (ao_im[5] ),
|
||||
.b_re5 (bo_re[5] ),
|
||||
.b_im5 (bo_im[5] ),
|
||||
.ab_re5 (ab_re[5] ),
|
||||
.ab_im5 (ab_im[5] ),
|
||||
.abb_re5 (abb_re[5] ),
|
||||
.abb_im5 (abb_im[5] ),
|
||||
.ab_pow3_re5 (ab_pow3_re[5]),
|
||||
.ab_pow3_im5 (ab_pow3_im[5]),
|
||||
.ab_pow4_re5 (ab_pow4_re[5]),
|
||||
.ab_pow4_im5 (ab_pow4_im[5]),
|
||||
.ab_pow5_re5 (ab_pow5_re[5]),
|
||||
.ab_pow5_im5 (ab_pow5_im[5]),
|
||||
.ab_pow6_re5 (ab_pow6_re[5]),
|
||||
.ab_pow6_im5 (ab_pow6_im[5]),
|
||||
.ab_pow7_re5 (ab_pow7_re[5]),
|
||||
.ab_pow7_im5 (ab_pow7_im[5]),
|
||||
.b_pow8_re5 (b_pow8_re[5] ),
|
||||
.b_pow8_im5 (b_pow8_im[5] )
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever
|
||||
#(CYCLE/2)
|
||||
clk=~clk;
|
||||
end
|
||||
reg [15:0] st1;
|
||||
reg [15:0] st2;
|
||||
reg [15:0] st3;
|
||||
reg [15:0] st4;
|
||||
|
||||
initial begin
|
||||
rst_n = 0;
|
||||
vldi <= 0;
|
||||
st1 = 100;
|
||||
st2 = 101;
|
||||
st3 = 110;
|
||||
st4 = 111;
|
||||
repeat(3) @(posedge clk);
|
||||
vldi[0] <= 1;
|
||||
rst_n = 1;
|
||||
a_re[0] <= 55007237;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 2143083068;
|
||||
b_im[0] <= 0;
|
||||
@(posedge clk);
|
||||
vldi[0] <= 0;
|
||||
a_re[0] <= 0;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 0;
|
||||
b_im[0] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi[1] <= 1;
|
||||
rst_n = 1;
|
||||
a_re[1] <= 32690030;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 2145807236;
|
||||
b_im[1] <= 0;
|
||||
@(posedge clk);
|
||||
vldi[1] <= 0;
|
||||
a_re[1] <= 0;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 0;
|
||||
b_im[1] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi[2] <= 1;
|
||||
rst_n = 1;
|
||||
a_re[2] <= 429516;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 2146812530;
|
||||
b_im[2] <= 0;
|
||||
@(posedge clk);
|
||||
vldi[2] <= 0;
|
||||
a_re[2] <= 0;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 0;
|
||||
b_im[2] <= 0;
|
||||
|
||||
end
|
||||
|
||||
|
||||
reg [21:0] cnt;
|
||||
always@(posedge clk or negedge rst_n)
|
||||
if(!rst_n) begin
|
||||
cnt <= 22'd0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 22'd1;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
ifdef seed
|
||||
vcs_run_opts += +ntb_random_seed=${seed}
|
||||
else
|
||||
vcs_run_opts += +ntb_random_seed_automatic
|
||||
endif
|
||||
|
||||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
|
||||
file:
|
||||
find ../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
../../rtl/z_dsp/z_dsp.v
|
||||
../../rtl/z_dsp/TailCorr_top.v
|
||||
../../rtl/z_dsp/rate_adapter.v
|
||||
../../rtl/z_dsp/IIR_top.v
|
||||
../../rtl/z_dsp/IIR_Filter_p1.v
|
||||
../../rtl/z_dsp/IIR_Filter_p8.v
|
||||
../../rtl/z_dsp/CoefGen.sv
|
||||
../../rtl/z_dsp/diff_p.v
|
||||
../../rtl/z_dsp/s2p_2.v
|
||||
../../rtl/z_dsp/Trunc.v
|
||||
../../rtl/z_dsp/mult_C.v
|
||||
../../rtl/z_dsp/mult_x.v
|
||||
../../rtl/z_dsp/syncer.v
|
||||
../../rtl/z_dsp/sirv_gnrl_dffs.v
|
||||
../../rtl/model/DW02_mult.v
|
||||
tb_z_dsp.v
|
||||
|
||||
|
|
@ -0,0 +1,312 @@
|
|||
`timescale 1 ns/1 ns
|
||||
module TB();
|
||||
|
||||
|
||||
reg [1 :0] source_mode;
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
$fsdbDumpMDA();
|
||||
// $srandom(417492050);
|
||||
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
|
||||
end
|
||||
|
||||
reg rstn;
|
||||
|
||||
reg [15:0] din_rect;
|
||||
reg [ 5:0] vldi_coef;
|
||||
reg vldi_data;
|
||||
|
||||
parameter CYCLE = 20;
|
||||
|
||||
reg clk;
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever
|
||||
#(CYCLE/2)
|
||||
clk=~clk;
|
||||
end
|
||||
|
||||
|
||||
reg signed [31:0] a_re [5:0];
|
||||
reg signed [31:0] a_im [5:0];
|
||||
reg signed [31:0] b_re [5:0];
|
||||
reg signed [31:0] b_im [5:0];
|
||||
|
||||
initial begin
|
||||
rstn = 0;
|
||||
vldi_data <= 0;
|
||||
vldi_coef <= 0;
|
||||
din_rect = 16'd0;
|
||||
a_re[3] <= 0;
|
||||
a_im[3] <= 0;
|
||||
b_re[3] <= 0;
|
||||
b_im[3] <= 0;
|
||||
a_re[4] <= 0;
|
||||
a_im[4] <= 0;
|
||||
b_re[4] <= 0;
|
||||
b_im[4] <= 0;
|
||||
a_re[5] <= 0;
|
||||
a_im[5] <= 0;
|
||||
b_re[5] <= 0;
|
||||
b_im[5] <= 0;
|
||||
repeat(3) @(posedge clk);
|
||||
vldi_coef[0] <= 1;
|
||||
rstn = 1;
|
||||
a_re[0] <= 55007237;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 2143083068;
|
||||
b_im[0] <= 0;
|
||||
@(posedge clk);
|
||||
vldi_coef[0] <= 0;
|
||||
a_re[0] <= 0;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 0;
|
||||
b_im[0] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi_coef[1] <= 1;
|
||||
rstn = 1;
|
||||
a_re[1] <= 32690030;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 2145807236;
|
||||
b_im[1] <= 0;
|
||||
@(posedge clk);
|
||||
vldi_coef[1] <= 0;
|
||||
a_re[1] <= 0;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 0;
|
||||
b_im[1] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi_coef[2] <= 1;
|
||||
rstn = 1;
|
||||
a_re[2] <= 429516;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 2146812530;
|
||||
b_im[2] <= 0;
|
||||
@(posedge clk);
|
||||
vldi_coef[2] <= 0;
|
||||
a_re[2] <= 0;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 0;
|
||||
b_im[2] <= 0;
|
||||
repeat(108) @(posedge clk);
|
||||
vldi_data <= 1;
|
||||
// repeat(10000) @(posedge clk);
|
||||
// vldi_data <= 0;
|
||||
|
||||
end
|
||||
|
||||
|
||||
reg [21:0] cnt;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
reg vldi_data_r1;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
vldi_data_r1 <= 1'b0;
|
||||
else
|
||||
begin
|
||||
vldi_data_r1 <= vldi_data;
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
din_rect <= 22'd0;
|
||||
else if(vldi_data)
|
||||
begin
|
||||
din_rect <= 16'd30000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_rect <= 16'd0;
|
||||
end
|
||||
|
||||
reg signed [15:0] random_in [0:3];
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= 16'd0;
|
||||
end
|
||||
end
|
||||
else if (vldi_data) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= $urandom % 30000;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= 16'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
integer file[3:0];
|
||||
reg [15:0] data[3:0];
|
||||
integer status[3:0];
|
||||
reg [15:0] reg_array[3:0];
|
||||
|
||||
initial begin
|
||||
if(source_mode == 3) begin
|
||||
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
file[i] = $fopen(filenames[i], "r");
|
||||
if (file[i] == 0) begin
|
||||
$display("Failed to open file: %s", filenames[i]);
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
reg_array[i] <= 16'd0;
|
||||
end
|
||||
end else if(vldi_data && source_mode == 3) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
status[i] = $fscanf(file[i], "%d\n", data[i]);
|
||||
if (status[i] == 1 ) begin
|
||||
reg_array[i] <= data[i];
|
||||
end
|
||||
else begin
|
||||
reg_array[i] <= 16'd0;
|
||||
vldi_data <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg signed [15:0] iir_in[3:0];
|
||||
|
||||
always @(*)
|
||||
case(source_mode)
|
||||
2'b01 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = din_rect;
|
||||
end
|
||||
end
|
||||
2'b10 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = random_in[i];
|
||||
end
|
||||
end
|
||||
2'b11 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = reg_array[i];
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
assign intp_mode = 2'b10;
|
||||
|
||||
wire [1:0] dac_mode_sel;
|
||||
assign dac_mode_sel = 2'b00;
|
||||
|
||||
wire tc_bypass;
|
||||
wire vldo;
|
||||
|
||||
assign tc_bypass = 1'b0;
|
||||
|
||||
reg en;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
en <= 1;
|
||||
end
|
||||
else begin
|
||||
en <= ~en;
|
||||
end
|
||||
end
|
||||
wire signed [15:0] dout_p[7:0];
|
||||
|
||||
z_dsp inst_z_dsp(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
// .tc_bypass (tc_bypass ),
|
||||
.vldi_coef (vldi_coef ),
|
||||
.vldi_data (vldi_data_r1 ),
|
||||
// .intp_mode (intp_mode ),
|
||||
// .dac_mode_sel (dac_mode_sel ),
|
||||
.din0 (iir_in[0] ),
|
||||
.din1 (iir_in[1] ),
|
||||
.din2 (iir_in[2] ),
|
||||
.din3 (iir_in[3] ),
|
||||
.a0_re (a_re[0] ),
|
||||
.a0_im (a_im[0] ),
|
||||
.b0_re (b_re[0] ),
|
||||
.b0_im (b_im[0] ),
|
||||
.a1_re (a_re[1] ),
|
||||
.a1_im (a_im[1] ),
|
||||
.b1_re (b_re[1] ),
|
||||
.b1_im (b_im[1] ),
|
||||
.a2_re (a_re[2] ),
|
||||
.a2_im (a_im[2] ),
|
||||
.b2_re (b_re[2] ),
|
||||
.b2_im (b_im[2] ),
|
||||
.a3_re (a_re[3] ),
|
||||
.a3_im (a_im[3] ),
|
||||
.b3_re (b_re[3] ),
|
||||
.b3_im (b_im[3] ),
|
||||
.a4_re (a_re[4] ),
|
||||
.a4_im (a_im[4] ),
|
||||
.b4_re (b_re[4] ),
|
||||
.b4_im (b_im[4] ),
|
||||
.a5_re (a_re[5] ),
|
||||
.a5_im (a_im[5] ),
|
||||
.b5_re (b_re[5] ),
|
||||
.b5_im (b_im[5] ),
|
||||
.dout0 (dout_p[0] ),
|
||||
.dout1 (dout_p[1] ),
|
||||
.dout2 (dout_p[2] ),
|
||||
.dout3 (dout_p[3] ),
|
||||
.vldo ( vldo )
|
||||
);
|
||||
|
||||
|
||||
integer signed In_fid[0:3];
|
||||
integer signed dout_fid[0:7];
|
||||
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
|
||||
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
In_fid[i] = $fopen(filenames_in[i]);
|
||||
end
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
dout_fid[i] = $fopen(filenames_dout[i]);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (vldi_data_r1) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (vldo) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue