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Author SHA1 Message Date
dada eba7fac84d merge 2025-03-14 17:07:07 +08:00
dada e14d9494b0 merge 2025-03-14 16:49:03 +08:00
dada 487aa20517 parameterize modules 2025-03-13 11:31:31 +08:00
dada 4a451196fd promote precision to about half LSB 2025-03-13 11:16:26 +08:00
dada 69b80e4575 data width of multiplier ports has been modified in order to reduce ovreheads 2025-03-12 22:30:22 +08:00
dada 3e00afece0 data width of multiplier ports has been modified in order to reduce ovreheads 2025-03-12 22:01:27 +08:00
dada 5fbf171cbe 八路并行的IIR滤波器，只有一路超前计算，其余支路进位链 
2st
 2025-03-12 14:54:27 +08:00
dada dea52768ee 2st 2025-03-12 14:39:35 +08:00
dada 832408d29b 1st 2025-03-12 14:36:22 +08:00
5 changed files with 88 additions and 357 deletions
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1
rtl/z_dsp/IIR_Filter_p8.v
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@ -71,7 +71,6 @@ assign ab_pow_im[2] = abb_im;
assign ab_pow_im[1] = ab_im; assign ab_pow_im[1] = ab_im;
assign ab_pow_im[0] = a_im; assign ab_pow_im[0] = a_im;
wire signed [temp_var_width-1 :0] x_re [0:7]; wire signed [temp_var_width-1 :0] x_re [0:7];
wire signed [temp_var_width-1 :0] x_im [0:7]; wire signed [temp_var_width-1 :0] x_im [0:7];

1
rtl/z_dsp/IIR_top.v
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@ -1,4 +1,5 @@
module IIR_top #( module IIR_top #(
parameter data_out_width = 23 parameter data_out_width = 23
,parameter temp_var_width = data_out_width + 14 ,parameter temp_var_width = data_out_width + 14

4
rtl/z_dsp/TailCorr_top.v
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@ -1,4 +1,5 @@
module TailCorr_top #( module TailCorr_top #(
parameter temp_var_width = 22 parameter temp_var_width = 22
) )
@ -175,6 +176,7 @@ wire signed [temp_var_width+2:0] sum_IIRout_p4;
wire signed [temp_var_width+2:0] sum_IIRout_p5; wire signed [temp_var_width+2:0] sum_IIRout_p5;
wire signed [temp_var_width+2:0] sum_IIRout_p6; wire signed [temp_var_width+2:0] sum_IIRout_p6;
wire signed [temp_var_width+2:0] sum_IIRout_p7; wire signed [temp_var_width+2:0] sum_IIRout_p7;
reg signed [15:0] din_p0_r [16:0]; reg signed [15:0] din_p0_r [16:0];
reg signed [15:0] din_p1_r [16:0]; reg signed [15:0] din_p1_r [16:0];
reg signed [15:0] din_p2_r [16:0]; reg signed [15:0] din_p2_r [16:0];
@ -183,6 +185,7 @@ reg signed [15:0] din_p4_r [16:0];
reg signed [15:0] din_p5_r [16:0]; reg signed [15:0] din_p5_r [16:0];
reg signed [15:0] din_p6_r [16:0]; reg signed [15:0] din_p6_r [16:0];
reg signed [15:0] din_p7_r [16:0]; reg signed [15:0] din_p7_r [16:0];
reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7) reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7)
reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22) reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22)
reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37) reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37)
@ -270,6 +273,7 @@ always @(posedge clk or negedge rstn) begin
end end
end end
end end
/* /*
wire signed [15:0] din_p0_r1; wire signed [15:0] din_p0_r1;
wire signed [15:0] din_p1_r1; wire signed [15:0] din_p1_r1;

113
rtl/z_dsp/diff_p.v
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@ -1,4 +1,5 @@
module diff_p module diff_p
( (
@ -122,38 +123,90 @@ if(rstn==1'b0)begin
diff_p5_r1 <= 0; diff_p5_r1 <= 0;
diff_p6_r1 <= 0; diff_p6_r1 <= 0;
diff_p7_r1 <= 0; diff_p7_r1 <= 0;
end
else if(en)begin
diff_p0_r1 <= din_p0_r0 - din_p7_r1;
diff_p1_r1 <= din_p1_r0 - din_p0_r0;
diff_p2_r1 <= din_p2_r0 - din_p1_r0;
diff_p3_r1 <= din_p3_r0 - din_p2_r0;
diff_p4_r1 <= din_p4_r0 - din_p3_r0;
diff_p5_r1 <= din_p5_r0 - din_p4_r0;
diff_p6_r1 <= din_p6_r0 - din_p5_r0;
diff_p7_r1 <= din_p7_r0 - din_p6_r0;
end
else begin
diff_p0_r1 <= diff_p0_r1;
diff_p1_r1 <= diff_p1_r1;
diff_p2_r1 <= diff_p2_r1;
diff_p3_r1 <= diff_p3_r1;
diff_p4_r1 <= diff_p4_r1;
diff_p5_r1 <= diff_p5_r1;
diff_p6_r1 <= diff_p6_r1;
diff_p7_r1 <= diff_p7_r1;
end
end end
assign diff_p0 = diff_p0_r1; wire [15:0] din_wire [0:3];
assign diff_p1 = diff_p1_r1;
assign diff_p2 = diff_p2_r1; assign din_wire[0] = din0;
assign diff_p3 = diff_p3_r1; assign din_wire[1] = din1;
assign diff_p4 = diff_p4_r1; assign din_wire[2] = din2;
assign diff_p5 = diff_p5_r1; assign din_wire[3] = din3;
assign diff_p6 = diff_p6_r1;
assign diff_p7 = diff_p7_r1;
wire [3:0] vldo_temp;
wire signed [15:0] dinp_r0 [7:0];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin: s2p_inst
s2p_2 inst_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din_wire[i]),
.en (vldi),
.dout0 (dinp_r0[i]),
.dout1 (dinp_r0[i+4]),
.vldo (vldo_temp[i])
);
end
endgenerate
assign vldo = vldo_temp[0];
reg signed [15:0] dinp_r1 [0:7];
integer j;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (j = 0; j < 8; j = j + 1) begin
dinp_r1[j] <= 'h0;
end
end
else if (en) begin
for (j = 0; j < 8; j = j + 1) begin
dinp_r1[j] <= dinp_r0[j];
end
end
end
wire signed [15:0] diffp_r0 [0:7];
generate
for (i = 0; i < 8; i = i + 1) begin: diff_assign
if (i == 0)
assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
else
assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
end
endgenerate
assign dout_p0 = dinp_r1[0];
assign dout_p1 = dinp_r1[1];
assign dout_p2 = dinp_r1[2];
assign dout_p3 = dinp_r1[3];
assign dout_p4 = dinp_r1[4];
assign dout_p5 = dinp_r1[5];
assign dout_p6 = dinp_r1[6];
assign dout_p7 = dinp_r1[7];
reg signed [15:0] diffp_r1 [0:7];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (j = 0; j < 8; j = j + 1) begin
diffp_r1[j] <= 0;
end
end
else if (en) begin
for (j = 0; j < 8; j = j + 1) begin
diffp_r1[j] <= diffp_r0[j];
end
end
end
assign diff_p0 = diffp_r1[0];
assign diff_p1 = diffp_r1[1];
assign diff_p2 = diffp_r1[2];
assign diff_p3 = diffp_r1[3];
assign diff_p4 = diffp_r1[4];
assign diff_p5 = diffp_r1[5];
assign diff_p6 = diffp_r1[6];
assign diff_p7 = diffp_r1[7];
endmodule endmodule

326
rtl/z_dsp/sirv_gnrl_dffs.v
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@ -1,326 +0,0 @@
/*
Copyright 2018-2020 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// All of the general DFF and Latch modules
//
// ====================================================================
//
//
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1
//
// ===========================================================================
`define DISABLE_SV_ASSERTION
`define dly #0.2
module sirv_gnrl_dfflrs # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dfflr # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is input
//
// ===========================================================================
module sirv_gnrl_dfflrd # (
parameter DW = 32
) (
input [DW-1:0] init,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= init;
else if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset
//
// ===========================================================================
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;
always @(posedge clk)
begin : DFFL_PROC
if (lden == 1'b1)
qout_r <= `dly dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else
qout_r <= `dly dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else
qout_r <= `dly dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module for general latch
//
// ===========================================================================
module sirv_gnrl_ltch # (
parameter DW = 32
) (
//input test_mode,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout
);
reg [DW-1:0] qout_r;
always @ *
begin : LTCH_PROC
if (lden == 1'b1)
qout_r <= dnxt;
end
//assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
always_comb
begin
CHECK_THE_X_VALUE:
assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end
//synopsys translate_on
`endif//}
`endif//}
endmodule