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Author SHA1 Message Date
futh0403 4e0f4a2d31 合并main分支的部分修改 
-尽量避免使用for循环
 2025-03-14 09:32:00 +08:00
dada ec72ff7551 parameterize modules 2025-03-14 09:32:00 +08:00
dada 6215a3516d promote precision to about half LSB 2025-03-14 09:32:00 +08:00
dada 092100d6ad data width of multiplier ports has been modified in order to reduce ovreheads 2025-03-14 09:32:00 +08:00
dada e98731cdd1 八路并行，一路超前计算，七路进位链 2025-03-14 09:31:51 +08:00
26 changed files with 2341 additions and 2057 deletions
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37
rtl/ref/FixRound.v Normal file
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module FixRound #(
parameter integer Data_width = 8
,parameter integer Fix_frac_coef_width = 31//division
)
(
input clk
,input rstn
,input en
,input signed [Data_width-1:0] din
,output signed [Data_width-1:0] dout
);
reg signed [Data_width-1:0] din_round;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_round <= 'h0;
end
else if(en) begin
if(din[Data_width-1] == 1'b0)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
end
else if (din[Data_width-1] == 1'b1)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
end
end
else begin
din_round <= din_round;
end
assign dout = din_round;
endmodule

345
rtl/ref/IIR_Filter_p8.v Normal file
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p8_ref #(
parameter data_in_width = 16
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1:0] dinp0
,input signed [data_in_width-1:0] dinp1
,input signed [data_in_width-1:0] dinp2
,input signed [data_in_width-1:0] dinp3
,input signed [data_in_width-1:0] dinp4
,input signed [data_in_width-1:0] dinp5
,input signed [data_in_width-1:0] dinp6
,input signed [data_in_width-1:0] dinp7
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] abb_im
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow3_im
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow4_im
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow5_im
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow6_im
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow7_im
,input signed [coef_width-1 :0] b_pow8_re
,input signed [coef_width-1 :0] b_pow8_im
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width+frac_data_out_width:0] x1_re;
wire signed [data_in_width+frac_data_out_width:0] x1_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp0 ),
.b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x*dinp0
.Im (x1_im )
);
wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp1 ),
.b (16'd0 ),
.c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*dinp1
.Im (x2_im )
);
wire signed [data_in_width+frac_data_out_width:0] x3_re;
wire signed [data_in_width+frac_data_out_width:0] x3_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp2 ),
.b (16'd0 ),
.c ({abb_re,{frac_data_out_width{1'b0}}} ),
.d ({abb_im,{frac_data_out_width{1'b0}}} ),
.Re (x3_re ),//a*b*b*dinp2
.Im (x3_im )
);
wire signed [data_in_width+frac_data_out_width:0] x4_re;
wire signed [data_in_width+frac_data_out_width:0] x4_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp3 ),
.b (16'd0 ),
.c ({ab_pow3_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow3_im,{frac_data_out_width{1'b0}}} ),
.Re (x4_re ),//a*b^3*dinp3
.Im (x4_im )
);
wire signed [data_in_width+frac_data_out_width:0] x5_re;
wire signed [data_in_width+frac_data_out_width:0] x5_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp4 ),
.b (16'd0 ),
.c ({ab_pow4_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow4_im,{frac_data_out_width{1'b0}}} ),
.Re (x5_re ),//a*b^4*dinp4
.Im (x5_im )
);
wire signed [data_in_width+frac_data_out_width:0] x6_re;
wire signed [data_in_width+frac_data_out_width:0] x6_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp5 ),
.b (16'd0 ),
.c ({ab_pow5_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow5_im,{frac_data_out_width{1'b0}}} ),
.Re (x6_re ),//a*b^5*dinp5
.Im (x6_im )
);
wire signed [data_in_width+frac_data_out_width:0] x7_re;
wire signed [data_in_width+frac_data_out_width:0] x7_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp6 ),
.b (16'd0 ),
.c ({ab_pow6_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow6_im,{frac_data_out_width{1'b0}}} ),
.Re (x7_re ),//a*b^6*dinp6
.Im (x7_im )
);
wire signed [data_in_width+frac_data_out_width:0] x8_re;
wire signed [data_in_width+frac_data_out_width:0] x8_im;
mult_C_ref
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c8 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp7 ),
.b (16'd0 ),
.c ({ab_pow7_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow7_im,{frac_data_out_width{1'b0}}} ),
.Re (x8_re ),//a*b^7*dinp7
.Im (x8_im )
);
wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im;
assign v_re = x1_re + x2_re + x3_re + x4_re + x5_re + x6_re + x7_re + x8_re;
assign v_im = x1_im + x2_im + x3_im + x4_im + x5_im + x6_im + x7_im + x8_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re;
reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im;
reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
reg signed [data_in_width-1:0] dout_re;
mult_C_ref
#(
.A_width(data_in_width+frac_data_out_width+2)
,.B_width(data_in_width+frac_data_out_width+2)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c9 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),
.b (y_im ),
.c (b_pow8_re ),
.d (b_pow8_im ),
.Re (y1_re ),//b^8*y(n-1)
.Im (y1_im )
);
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule

379
rtl/ref/IIR_top.v Normal file
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_top_ref
(
input rstn
,input clk
,input en
,input signed [15:0] IIRin_p0
,input signed [15:0] IIRin_p1
,input signed [15:0] IIRin_p2
,input signed [15:0] IIRin_p3
,input signed [15:0] IIRin_p4
,input signed [15:0] IIRin_p5
,input signed [15:0] IIRin_p6
,input signed [15:0] IIRin_p7
,input signed [31 :0] a_re
,input signed [31 :0] a_im
,input signed [31 :0] ab_re
,input signed [31 :0] ab_im
,input signed [31 :0] abb_re
,input signed [31 :0] abb_im
,input signed [31 :0] ab_pow3_re
,input signed [31 :0] ab_pow3_im
,input signed [31 :0] ab_pow4_re
,input signed [31 :0] ab_pow4_im
,input signed [31 :0] ab_pow5_re
,input signed [31 :0] ab_pow5_im
,input signed [31 :0] ab_pow6_re
,input signed [31 :0] ab_pow6_im
,input signed [31 :0] ab_pow7_re
,input signed [31 :0] ab_pow7_im
,input signed [31 :0] b_pow8_re
,input signed [31 :0] b_pow8_im
,output signed [15:0] IIRout_p0
,output signed [15:0] IIRout_p1
,output signed [15:0] IIRout_p2
,output signed [15:0] IIRout_p3
,output signed [15:0] IIRout_p4
,output signed [15:0] IIRout_p5
,output signed [15:0] IIRout_p6
,output signed [15:0] IIRout_p7
);
reg signed [15:0] IIRin_p0_r1;
reg signed [15:0] IIRin_p1_r1;
reg signed [15:0] IIRin_p2_r1;
reg signed [15:0] IIRin_p3_r1;
reg signed [15:0] IIRin_p4_r1;
reg signed [15:0] IIRin_p5_r1;
reg signed [15:0] IIRin_p6_r1;
reg signed [15:0] IIRin_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
IIRin_p0_r1 <= 'h0;
IIRin_p1_r1 <= 'h0;
IIRin_p2_r1 <= 'h0;
IIRin_p3_r1 <= 'h0;
IIRin_p4_r1 <= 'h0;
IIRin_p5_r1 <= 'h0;
IIRin_p6_r1 <= 'h0;
IIRin_p7_r1 <= 'h0;
end
else if(en)
begin
IIRin_p0_r1 <= IIRin_p0;
IIRin_p1_r1 <= IIRin_p1;
IIRin_p2_r1 <= IIRin_p2;
IIRin_p3_r1 <= IIRin_p3;
IIRin_p4_r1 <= IIRin_p4;
IIRin_p5_r1 <= IIRin_p5;
IIRin_p6_r1 <= IIRin_p6;
IIRin_p7_r1 <= IIRin_p7;
end
else
begin
IIRin_p0_r1 <= IIRin_p0_r1;
IIRin_p1_r1 <= IIRin_p1_r1;
IIRin_p2_r1 <= IIRin_p2_r1;
IIRin_p3_r1 <= IIRin_p3_r1;
IIRin_p4_r1 <= IIRin_p4_r1;
IIRin_p5_r1 <= IIRin_p5_r1;
IIRin_p6_r1 <= IIRin_p6_r1;
IIRin_p7_r1 <= IIRin_p7_r1;
end
IIR_Filter_p8_ref inst_iir_0_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p0 ),
.dinp1 (IIRin_p7_r1 ),
.dinp2 (IIRin_p6_r1 ),
.dinp3 (IIRin_p5_r1 ),
.dinp4 (IIRin_p4_r1 ),
.dinp5 (IIRin_p3_r1 ),
.dinp6 (IIRin_p2_r1 ),
.dinp7 (IIRin_p1_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p0 )
);
IIR_Filter_p8_ref inst_iir_o_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p1 ),
.dinp1 (IIRin_p0 ),
.dinp2 (IIRin_p7_r1 ),
.dinp3 (IIRin_p6_r1 ),
.dinp4 (IIRin_p5_r1 ),
.dinp5 (IIRin_p4_r1 ),
.dinp6 (IIRin_p3_r1 ),
.dinp7 (IIRin_p2_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p1 )
);
IIR_Filter_p8_ref inst_iir_0_p2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p2 ),
.dinp1 (IIRin_p1 ),
.dinp2 (IIRin_p0 ),
.dinp3 (IIRin_p7_r1 ),
.dinp4 (IIRin_p6_r1 ),
.dinp5 (IIRin_p5_r1 ),
.dinp6 (IIRin_p4_r1 ),
.dinp7 (IIRin_p3_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p2 )
);
IIR_Filter_p8_ref inst_iir_0_p3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p3 ),
.dinp1 (IIRin_p2 ),
.dinp2 (IIRin_p1 ),
.dinp3 (IIRin_p0 ),
.dinp4 (IIRin_p7_r1 ),
.dinp5 (IIRin_p6_r1 ),
.dinp6 (IIRin_p5_r1 ),
.dinp7 (IIRin_p4_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p3 )
);
IIR_Filter_p8_ref inst_iir_0_p4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p4 ),
.dinp1 (IIRin_p3 ),
.dinp2 (IIRin_p2 ),
.dinp3 (IIRin_p1 ),
.dinp4 (IIRin_p0 ),
.dinp5 (IIRin_p7_r1 ),
.dinp6 (IIRin_p6_r1 ),
.dinp7 (IIRin_p5_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p4 )
);
IIR_Filter_p8_ref inst_iir_0_p5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p5 ),
.dinp1 (IIRin_p4 ),
.dinp2 (IIRin_p3 ),
.dinp3 (IIRin_p2 ),
.dinp4 (IIRin_p1 ),
.dinp5 (IIRin_p0 ),
.dinp6 (IIRin_p7_r1 ),
.dinp7 (IIRin_p6_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p5 )
);
IIR_Filter_p8_ref inst_iir_0_p6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p6 ),
.dinp1 (IIRin_p5 ),
.dinp2 (IIRin_p4 ),
.dinp3 (IIRin_p3 ),
.dinp4 (IIRin_p2 ),
.dinp5 (IIRin_p1 ),
.dinp6 (IIRin_p0 ),
.dinp7 (IIRin_p7_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p6 )
);
IIR_Filter_p8_ref inst_iir_0_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p7 ),
.dinp1 (IIRin_p6 ),
.dinp2 (IIRin_p5 ),
.dinp3 (IIRin_p4 ),
.dinp4 (IIRin_p3 ),
.dinp5 (IIRin_p2 ),
.dinp6 (IIRin_p1 ),
.dinp7 (IIRin_p0 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p7 )
);
endmodule

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rtl/ref/TailCorr_top.v Normal file
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@ -0,0 +1,900 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2025-02-28 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module TailCorr_top_ref
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [31:0] a_re0
,input signed [31:0] a_im0
,input signed [31:0] ab_re0
,input signed [31:0] ab_im0
,input signed [31:0] abb_re0
,input signed [31:0] abb_im0
,input signed [31:0] ab_pow3_re0
,input signed [31:0] ab_pow3_im0
,input signed [31:0] ab_pow4_re0
,input signed [31:0] ab_pow4_im0
,input signed [31:0] ab_pow5_re0
,input signed [31:0] ab_pow5_im0
,input signed [31:0] ab_pow6_re0
,input signed [31:0] ab_pow6_im0
,input signed [31:0] ab_pow7_re0
,input signed [31:0] ab_pow7_im0
,input signed [31:0] b_pow8_re0
,input signed [31:0] b_pow8_im0
,input signed [31:0] a_re1
,input signed [31:0] a_im1
,input signed [31:0] ab_re1
,input signed [31:0] ab_im1
,input signed [31:0] abb_re1
,input signed [31:0] abb_im1
,input signed [31:0] ab_pow3_re1
,input signed [31:0] ab_pow3_im1
,input signed [31:0] ab_pow4_re1
,input signed [31:0] ab_pow4_im1
,input signed [31:0] ab_pow5_re1
,input signed [31:0] ab_pow5_im1
,input signed [31:0] ab_pow6_re1
,input signed [31:0] ab_pow6_im1
,input signed [31:0] ab_pow7_re1
,input signed [31:0] ab_pow7_im1
,input signed [31:0] b_pow8_re1
,input signed [31:0] b_pow8_im1
,input signed [31:0] a_re2
,input signed [31:0] a_im2
,input signed [31:0] ab_re2
,input signed [31:0] ab_im2
,input signed [31:0] abb_re2
,input signed [31:0] abb_im2
,input signed [31:0] ab_pow3_re2
,input signed [31:0] ab_pow3_im2
,input signed [31:0] ab_pow4_re2
,input signed [31:0] ab_pow4_im2
,input signed [31:0] ab_pow5_re2
,input signed [31:0] ab_pow5_im2
,input signed [31:0] ab_pow6_re2
,input signed [31:0] ab_pow6_im2
,input signed [31:0] ab_pow7_re2
,input signed [31:0] ab_pow7_im2
,input signed [31:0] b_pow8_re2
,input signed [31:0] b_pow8_im2
,input signed [31:0] a_re3
,input signed [31:0] a_im3
,input signed [31:0] ab_re3
,input signed [31:0] ab_im3
,input signed [31:0] abb_re3
,input signed [31:0] abb_im3
,input signed [31:0] ab_pow3_re3
,input signed [31:0] ab_pow3_im3
,input signed [31:0] ab_pow4_re3
,input signed [31:0] ab_pow4_im3
,input signed [31:0] ab_pow5_re3
,input signed [31:0] ab_pow5_im3
,input signed [31:0] ab_pow6_re3
,input signed [31:0] ab_pow6_im3
,input signed [31:0] ab_pow7_re3
,input signed [31:0] ab_pow7_im3
,input signed [31:0] b_pow8_re3
,input signed [31:0] b_pow8_im3
,input signed [31:0] a_re4
,input signed [31:0] a_im4
,input signed [31:0] ab_re4
,input signed [31:0] ab_im4
,input signed [31:0] abb_re4
,input signed [31:0] abb_im4
,input signed [31:0] ab_pow3_re4
,input signed [31:0] ab_pow3_im4
,input signed [31:0] ab_pow4_re4
,input signed [31:0] ab_pow4_im4
,input signed [31:0] ab_pow5_re4
,input signed [31:0] ab_pow5_im4
,input signed [31:0] ab_pow6_re4
,input signed [31:0] ab_pow6_im4
,input signed [31:0] ab_pow7_re4
,input signed [31:0] ab_pow7_im4
,input signed [31:0] b_pow8_re4
,input signed [31:0] b_pow8_im4
,input signed [31:0] a_re5
,input signed [31:0] a_im5
,input signed [31:0] ab_re5
,input signed [31:0] ab_im5
,input signed [31:0] abb_re5
,input signed [31:0] abb_im5
,input signed [31:0] ab_pow3_re5
,input signed [31:0] ab_pow3_im5
,input signed [31:0] ab_pow4_re5
,input signed [31:0] ab_pow4_im5
,input signed [31:0] ab_pow5_re5
,input signed [31:0] ab_pow5_im5
,input signed [31:0] ab_pow6_re5
,input signed [31:0] ab_pow6_im5
,input signed [31:0] ab_pow7_re5
,input signed [31:0] ab_pow7_im5
,input signed [31:0] b_pow8_re5
,input signed [31:0] b_pow8_im5
,output signed [15:0] dout_p0
,output signed [15:0] dout_p1
,output signed [15:0] dout_p2
,output signed [15:0] dout_p3
,output signed [15:0] dout_p4
,output signed [15:0] dout_p5
,output signed [15:0] dout_p6
,output signed [15:0] dout_p7
,output vldo
);
wire signed [15:0] din_p0;
wire signed [15:0] din_p1;
wire signed [15:0] din_p2;
wire signed [15:0] din_p3;
wire signed [15:0] din_p4;
wire signed [15:0] din_p5;
wire signed [15:0] din_p6;
wire signed [15:0] din_p7;
wire signed [15:0] IIRin_p0;
wire signed [15:0] IIRin_p1;
wire signed [15:0] IIRin_p2;
wire signed [15:0] IIRin_p3;
wire signed [15:0] IIRin_p4;
wire signed [15:0] IIRin_p5;
wire signed [15:0] IIRin_p6;
wire signed [15:0] IIRin_p7;
wire vldo_diff;
diff_p_ref inst_diff_p_ref (
.rstn (rstn),
.clk (clk ),
.en (en ),
.vldi (vldi),
.din0 (din0),
.din1 (din1),
.din2 (din2),
.din3 (din3),
.vldo (vldo_diff),
.dout_p0 (din_p0),
.dout_p1 (din_p1),
.dout_p2 (din_p2),
.dout_p3 (din_p3),
.dout_p4 (din_p4),
.dout_p5 (din_p5),
.dout_p6 (din_p6),
.dout_p7 (din_p7),
.diff_p0 (IIRin_p0),
.diff_p1 (IIRin_p1),
.diff_p2 (IIRin_p2),
.diff_p3 (IIRin_p3),
.diff_p4 (IIRin_p4),
.diff_p5 (IIRin_p5),
.diff_p6 (IIRin_p6),
.diff_p7 (IIRin_p7)
);
reg signed [15:0] din_p0_r1;
reg signed [15:0] din_p0_r2;
reg signed [15:0] din_p0_r3;
reg signed [15:0] din_p0_r4;
reg signed [15:0] din_p0_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p0_r1 <= 'h0;
din_p0_r2 <= 'h0;
din_p0_r3 <= 'h0;
din_p0_r4 <= 'h0;
din_p0_r5 <= 'h0;
end
else if(en)
begin
din_p0_r1 <= din_p0;
din_p0_r2 <= din_p0_r1;
din_p0_r3 <= din_p0_r2;
din_p0_r4 <= din_p0_r3;
din_p0_r5 <= din_p0_r4;
end
else
begin
din_p0_r1 <= din_p0_r1;
din_p0_r2 <= din_p0_r2;
din_p0_r3 <= din_p0_r3;
din_p0_r4 <= din_p0_r4;
din_p0_r5 <= din_p0_r5;
end
reg signed [15:0] din_p1_r1;
reg signed [15:0] din_p1_r2;
reg signed [15:0] din_p1_r3;
reg signed [15:0] din_p1_r4;
reg signed [15:0] din_p1_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p1_r1 <= 'h0;
din_p1_r2 <= 'h0;
din_p1_r3 <= 'h0;
din_p1_r4 <= 'h0;
din_p1_r5 <= 'h0;
end
else if(en)
begin
din_p1_r1 <= din_p1;
din_p1_r2 <= din_p1_r1;
din_p1_r3 <= din_p1_r2;
din_p1_r4 <= din_p1_r3;
din_p1_r5 <= din_p1_r4;
end
else
begin
din_p1_r1 <= din_p1_r1;
din_p1_r2 <= din_p1_r2;
din_p1_r3 <= din_p1_r3;
din_p1_r4 <= din_p1_r4;
din_p1_r5 <= din_p1_r5;
end
reg signed [15:0] din_p2_r1;
reg signed [15:0] din_p2_r2;
reg signed [15:0] din_p2_r3;
reg signed [15:0] din_p2_r4;
reg signed [15:0] din_p2_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p2_r1 <= 'h0;
din_p2_r2 <= 'h0;
din_p2_r3 <= 'h0;
din_p2_r4 <= 'h0;
din_p2_r5 <= 'h0;
end
else if(en)
begin
din_p2_r1 <= din_p2;
din_p2_r2 <= din_p2_r1;
din_p2_r3 <= din_p2_r2;
din_p2_r4 <= din_p2_r3;
din_p2_r5 <= din_p2_r4;
end
else
begin
din_p2_r1 <= din_p2_r1;
din_p2_r2 <= din_p2_r2;
din_p2_r3 <= din_p2_r3;
din_p2_r4 <= din_p2_r4;
din_p2_r5 <= din_p2_r5;
end
reg signed [15:0] din_p3_r1;
reg signed [15:0] din_p3_r2;
reg signed [15:0] din_p3_r3;
reg signed [15:0] din_p3_r4;
reg signed [15:0] din_p3_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p3_r1 <= 'h0;
din_p3_r2 <= 'h0;
din_p3_r3 <= 'h0;
din_p3_r4 <= 'h0;
din_p3_r5 <= 'h0;
end
else if(en)
begin
din_p3_r1 <= din_p3;
din_p3_r2 <= din_p3_r1;
din_p3_r3 <= din_p3_r2;
din_p3_r4 <= din_p3_r3;
din_p3_r5 <= din_p3_r4;
end
else
begin
din_p3_r1 <= din_p3_r1;
din_p3_r2 <= din_p3_r2;
din_p3_r3 <= din_p3_r3;
din_p3_r4 <= din_p3_r4;
din_p3_r5 <= din_p3_r5;
end
reg signed [15:0] din_p4_r1;
reg signed [15:0] din_p4_r2;
reg signed [15:0] din_p4_r3;
reg signed [15:0] din_p4_r4;
reg signed [15:0] din_p4_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p4_r1 <= 'h0;
din_p4_r2 <= 'h0;
din_p4_r3 <= 'h0;
din_p4_r4 <= 'h0;
din_p4_r5 <= 'h0;
end
else if(en)
begin
din_p4_r1 <= din_p4;
din_p4_r2 <= din_p4_r1;
din_p4_r3 <= din_p4_r2;
din_p4_r4 <= din_p4_r3;
din_p4_r5 <= din_p4_r4;
end
else
begin
din_p4_r1 <= din_p4_r1;
din_p4_r2 <= din_p4_r2;
din_p4_r3 <= din_p4_r3;
din_p4_r4 <= din_p4_r4;
din_p4_r5 <= din_p4_r5;
end
reg signed [15:0] din_p5_r1;
reg signed [15:0] din_p5_r2;
reg signed [15:0] din_p5_r3;
reg signed [15:0] din_p5_r4;
reg signed [15:0] din_p5_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p5_r1 <= 'h0;
din_p5_r2 <= 'h0;
din_p5_r3 <= 'h0;
din_p5_r4 <= 'h0;
din_p5_r5 <= 'h0;
end
else if(en)
begin
din_p5_r1 <= din_p5;
din_p5_r2 <= din_p5_r1;
din_p5_r3 <= din_p5_r2;
din_p5_r4 <= din_p5_r3;
din_p5_r5 <= din_p5_r4;
end
else
begin
din_p5_r1 <= din_p5_r1;
din_p5_r2 <= din_p5_r2;
din_p5_r3 <= din_p5_r3;
din_p5_r4 <= din_p5_r4;
din_p5_r5 <= din_p5_r5;
end
reg signed [15:0] din_p6_r1;
reg signed [15:0] din_p6_r2;
reg signed [15:0] din_p6_r3;
reg signed [15:0] din_p6_r4;
reg signed [15:0] din_p6_r5;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p6_r1 <= 'h0;
din_p6_r2 <= 'h0;
din_p6_r3 <= 'h0;
din_p6_r4 <= 'h0;
din_p6_r5 <= 'h0;
end
else if(en)
begin
din_p6_r1 <= din_p6;
din_p6_r2 <= din_p6_r1;
din_p6_r3 <= din_p6_r2;
din_p6_r4 <= din_p6_r3;
din_p6_r5 <= din_p6_r4;
end
else
begin
din_p6_r1 <= din_p6_r1;
din_p6_r2 <= din_p6_r2;
din_p6_r3 <= din_p6_r3;
din_p6_r4 <= din_p6_r4;
din_p6_r5 <= din_p6_r5;
end
reg signed [15:0] din_p7_r1;
reg signed [15:0] din_p7_r2;
reg signed [15:0] din_p7_r3;
reg signed [15:0] din_p7_r4;
reg signed [15:0] din_p7_r5;
reg signed [15:0] din_p7_r6;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p7_r1 <= 'h0;
din_p7_r2 <= 'h0;
din_p7_r3 <= 'h0;
din_p7_r4 <= 'h0;
din_p7_r5 <= 'h0;
end
else if(en)
begin
din_p7_r1 <= din_p7;
din_p7_r2 <= din_p7_r1;
din_p7_r3 <= din_p7_r2;
din_p7_r4 <= din_p7_r3;
din_p7_r5 <= din_p7_r4;
end
else
begin
din_p7_r1 <= din_p7_r1;
din_p7_r2 <= din_p7_r2;
din_p7_r3 <= din_p7_r3;
din_p7_r4 <= din_p7_r4;
din_p7_r5 <= din_p7_r5;
end
wire signed [15:0] IIRout0_p0;
wire signed [15:0] IIRout0_p1;
wire signed [15:0] IIRout0_p2;
wire signed [15:0] IIRout0_p3;
wire signed [15:0] IIRout0_p4;
wire signed [15:0] IIRout0_p5;
wire signed [15:0] IIRout0_p6;
wire signed [15:0] IIRout0_p7;
IIR_top_ref inst_IIR_top_ref_0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re0 ),
.a_im (a_im0 ),
.ab_re (ab_re0 ),
.ab_im (ab_im0 ),
.abb_re (abb_re0 ),
.abb_im (abb_im0 ),
.ab_pow3_re (ab_pow3_re0 ),
.ab_pow3_im (ab_pow3_im0 ),
.ab_pow4_re (ab_pow4_re0 ),
.ab_pow4_im (ab_pow4_im0 ),
.ab_pow5_re (ab_pow5_re0 ),
.ab_pow5_im (ab_pow5_im0 ),
.ab_pow6_re (ab_pow6_re0 ),
.ab_pow6_im (ab_pow6_im0 ),
.ab_pow7_re (ab_pow7_re0 ),
.ab_pow7_im (ab_pow7_im0 ),
.b_pow8_re (b_pow8_re0 ),
.b_pow8_im (b_pow8_im0 ),
.IIRout_p0 (IIRout0_p0 ),
.IIRout_p1 (IIRout0_p1 ),
.IIRout_p2 (IIRout0_p2 ),
.IIRout_p3 (IIRout0_p3 ),
.IIRout_p4 (IIRout0_p4 ),
.IIRout_p5 (IIRout0_p5 ),
.IIRout_p6 (IIRout0_p6 ),
.IIRout_p7 (IIRout0_p7 )
);
wire signed [15:0] IIRout1_p0;
wire signed [15:0] IIRout1_p1;
wire signed [15:0] IIRout1_p2;
wire signed [15:0] IIRout1_p3;
wire signed [15:0] IIRout1_p4;
wire signed [15:0] IIRout1_p5;
wire signed [15:0] IIRout1_p6;
wire signed [15:0] IIRout1_p7;
IIR_top_ref inst_IIR_top_ref_1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re1 ),
.a_im (a_im1 ),
.ab_re (ab_re1 ),
.ab_im (ab_im1 ),
.abb_re (abb_re1 ),
.abb_im (abb_im1 ),
.ab_pow3_re (ab_pow3_re1 ),
.ab_pow3_im (ab_pow3_im1 ),
.ab_pow4_re (ab_pow4_re1 ),
.ab_pow4_im (ab_pow4_im1 ),
.ab_pow5_re (ab_pow5_re1 ),
.ab_pow5_im (ab_pow5_im1 ),
.ab_pow6_re (ab_pow6_re1 ),
.ab_pow6_im (ab_pow6_im1 ),
.ab_pow7_re (ab_pow7_re1 ),
.ab_pow7_im (ab_pow7_im1 ),
.b_pow8_re (b_pow8_re1 ),
.b_pow8_im (b_pow8_im1 ),
.IIRout_p0 (IIRout1_p0 ),
.IIRout_p1 (IIRout1_p1 ),
.IIRout_p2 (IIRout1_p2 ),
.IIRout_p3 (IIRout1_p3 ),
.IIRout_p4 (IIRout1_p4 ),
.IIRout_p5 (IIRout1_p5 ),
.IIRout_p6 (IIRout1_p6 ),
.IIRout_p7 (IIRout1_p7 )
);
wire signed [15:0] IIRout2_p0;
wire signed [15:0] IIRout2_p1;
wire signed [15:0] IIRout2_p2;
wire signed [15:0] IIRout2_p3;
wire signed [15:0] IIRout2_p4;
wire signed [15:0] IIRout2_p5;
wire signed [15:0] IIRout2_p6;
wire signed [15:0] IIRout2_p7;
IIR_top_ref inst_IIR_top_ref_2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re2 ),
.a_im (a_im2 ),
.ab_re (ab_re2 ),
.ab_im (ab_im2 ),
.abb_re (abb_re2 ),
.abb_im (abb_im2 ),
.ab_pow3_re (ab_pow3_re2 ),
.ab_pow3_im (ab_pow3_im2 ),
.ab_pow4_re (ab_pow4_re2 ),
.ab_pow4_im (ab_pow4_im2 ),
.ab_pow5_re (ab_pow5_re2 ),
.ab_pow5_im (ab_pow5_im2 ),
.ab_pow6_re (ab_pow6_re2 ),
.ab_pow6_im (ab_pow6_im2 ),
.ab_pow7_re (ab_pow7_re2 ),
.ab_pow7_im (ab_pow7_im2 ),
.b_pow8_re (b_pow8_re2 ),
.b_pow8_im (b_pow8_im2 ),
.IIRout_p0 (IIRout2_p0 ),
.IIRout_p1 (IIRout2_p1 ),
.IIRout_p2 (IIRout2_p2 ),
.IIRout_p3 (IIRout2_p3 ),
.IIRout_p4 (IIRout2_p4 ),
.IIRout_p5 (IIRout2_p5 ),
.IIRout_p6 (IIRout2_p6 ),
.IIRout_p7 (IIRout2_p7 )
);
wire signed [15:0] IIRout3_p0;
wire signed [15:0] IIRout3_p1;
wire signed [15:0] IIRout3_p2;
wire signed [15:0] IIRout3_p3;
wire signed [15:0] IIRout3_p4;
wire signed [15:0] IIRout3_p5;
wire signed [15:0] IIRout3_p6;
wire signed [15:0] IIRout3_p7;
IIR_top_ref inst_IIR_top_ref_3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re3 ),
.a_im (a_im3 ),
.ab_re (ab_re3 ),
.ab_im (ab_im3 ),
.abb_re (abb_re3 ),
.abb_im (abb_im3 ),
.ab_pow3_re (ab_pow3_re3 ),
.ab_pow3_im (ab_pow3_im3 ),
.ab_pow4_re (ab_pow4_re3 ),
.ab_pow4_im (ab_pow4_im3 ),
.ab_pow5_re (ab_pow5_re3 ),
.ab_pow5_im (ab_pow5_im3 ),
.ab_pow6_re (ab_pow6_re3 ),
.ab_pow6_im (ab_pow6_im3 ),
.ab_pow7_re (ab_pow7_re3 ),
.ab_pow7_im (ab_pow7_im3 ),
.b_pow8_re (b_pow8_re3 ),
.b_pow8_im (b_pow8_im3 ),
.IIRout_p0 (IIRout3_p0 ),
.IIRout_p1 (IIRout3_p1 ),
.IIRout_p2 (IIRout3_p2 ),
.IIRout_p3 (IIRout3_p3 ),
.IIRout_p4 (IIRout3_p4 ),
.IIRout_p5 (IIRout3_p5 ),
.IIRout_p6 (IIRout3_p6 ),
.IIRout_p7 (IIRout3_p7 )
);
wire signed [15:0] IIRout4_p0;
wire signed [15:0] IIRout4_p1;
wire signed [15:0] IIRout4_p2;
wire signed [15:0] IIRout4_p3;
wire signed [15:0] IIRout4_p4;
wire signed [15:0] IIRout4_p5;
wire signed [15:0] IIRout4_p6;
wire signed [15:0] IIRout4_p7;
IIR_top_ref inst_IIR_top_ref_4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re4 ),
.a_im (a_im4 ),
.ab_re (ab_re4 ),
.ab_im (ab_im4 ),
.abb_re (abb_re4 ),
.abb_im (abb_im4 ),
.ab_pow3_re (ab_pow3_re4 ),
.ab_pow3_im (ab_pow3_im4 ),
.ab_pow4_re (ab_pow4_re4 ),
.ab_pow4_im (ab_pow4_im4 ),
.ab_pow5_re (ab_pow5_re4 ),
.ab_pow5_im (ab_pow5_im4 ),
.ab_pow6_re (ab_pow6_re4 ),
.ab_pow6_im (ab_pow6_im4 ),
.ab_pow7_re (ab_pow7_re4 ),
.ab_pow7_im (ab_pow7_im4 ),
.b_pow8_re (b_pow8_re4 ),
.b_pow8_im (b_pow8_im4 ),
.IIRout_p0 (IIRout4_p0 ),
.IIRout_p1 (IIRout4_p1 ),
.IIRout_p2 (IIRout4_p2 ),
.IIRout_p3 (IIRout4_p3 ),
.IIRout_p4 (IIRout4_p4 ),
.IIRout_p5 (IIRout4_p5 ),
.IIRout_p6 (IIRout4_p6 ),
.IIRout_p7 (IIRout4_p7 )
);
wire signed [15:0] IIRout5_p0;
wire signed [15:0] IIRout5_p1;
wire signed [15:0] IIRout5_p2;
wire signed [15:0] IIRout5_p3;
wire signed [15:0] IIRout5_p4;
wire signed [15:0] IIRout5_p5;
wire signed [15:0] IIRout5_p6;
wire signed [15:0] IIRout5_p7;
IIR_top_ref inst_IIR_top_ref_5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.IIRin_p0 (IIRin_p0 ),
.IIRin_p1 (IIRin_p1 ),
.IIRin_p2 (IIRin_p2 ),
.IIRin_p3 (IIRin_p3 ),
.IIRin_p4 (IIRin_p4 ),
.IIRin_p5 (IIRin_p5 ),
.IIRin_p6 (IIRin_p6 ),
.IIRin_p7 (IIRin_p7 ),
.a_re (a_re5 ),
.a_im (a_im5 ),
.ab_re (ab_re5 ),
.ab_im (ab_im5 ),
.abb_re (abb_re5 ),
.abb_im (abb_im5 ),
.ab_pow3_re (ab_pow3_re5 ),
.ab_pow3_im (ab_pow3_im5 ),
.ab_pow4_re (ab_pow4_re5 ),
.ab_pow4_im (ab_pow4_im5 ),
.ab_pow5_re (ab_pow5_re5 ),
.ab_pow5_im (ab_pow5_im5 ),
.ab_pow6_re (ab_pow6_re5 ),
.ab_pow6_im (ab_pow6_im5 ),
.ab_pow7_re (ab_pow7_re5 ),
.ab_pow7_im (ab_pow7_im5 ),
.b_pow8_re (b_pow8_re5 ),
.b_pow8_im (b_pow8_im5 ),
.IIRout_p0 (IIRout5_p0 ),
.IIRout_p1 (IIRout5_p1 ),
.IIRout_p2 (IIRout5_p2 ),
.IIRout_p3 (IIRout5_p3 ),
.IIRout_p4 (IIRout5_p4 ),
.IIRout_p5 (IIRout5_p5 ),
.IIRout_p6 (IIRout5_p6 ),
.IIRout_p7 (IIRout5_p7 )
);
wire signed [18:0] dout_p0_r0;
wire signed [18:0] dout_p1_r0;
wire signed [18:0] dout_p2_r0;
wire signed [18:0] dout_p3_r0;
wire signed [18:0] dout_p4_r0;
wire signed [18:0] dout_p5_r0;
wire signed [18:0] dout_p6_r0;
wire signed [18:0] dout_p7_r0;
assign dout_p0_r0 = din_p0_r5 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0;
assign dout_p1_r0 = din_p1_r5 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1;
assign dout_p2_r0 = din_p2_r5 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2;
assign dout_p3_r0 = din_p3_r5 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3;
assign dout_p4_r0 = din_p4_r5 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4;
assign dout_p5_r0 = din_p5_r5 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5;
assign dout_p6_r0 = din_p6_r5 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6;
assign dout_p7_r0 = din_p7_r5 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7;
reg signed [18:0] dout_p0_r1;
reg signed [15:0] dout_p [7:0];
wire signed [18:0] dout_p_r0 [0:7];
assign dout_p_r0[0] = dout_p0_r0;
assign dout_p_r0[1] = dout_p1_r0;
assign dout_p_r0[2] = dout_p2_r0;
assign dout_p_r0[3] = dout_p3_r0;
assign dout_p_r0[4] = dout_p4_r0;
assign dout_p_r0[5] = dout_p5_r0;
assign dout_p_r0[6] = dout_p6_r0;
assign dout_p_r0[7] = dout_p7_r0;
integer i;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (i = 0; i < 8; i = i + 1) begin
dout_p[i] <= 'h0;
end
end
else if (en) begin
for (i = 0; i < 8; i = i + 1) begin
if (dout_p_r0[i][16:15] == 2'b01)
dout_p[i] <= 16'd32767;
else if (dout_p_r0[i][16:15] == 2'b10)
dout_p[i] <= -16'd32768;
else
dout_p[i] <= dout_p_r0[i][15:0];
end
end
end
assign dout_p0 = dout_p[0];
assign dout_p1 = dout_p[1];
assign dout_p2 = dout_p[2];
assign dout_p3 = dout_p[3];
assign dout_p4 = dout_p[4];
assign dout_p5 = dout_p[5];
assign dout_p6 = dout_p[6];
assign dout_p7 = dout_p[7];
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_p0_r1 <= 16'd0;
end
else if(en)
begin
dout_p0_r1 <= dout_p0_r0;
end
else
begin
dout_p0_r1 <= dout_p0_r1;
end
reg signed [18:0] dout_p0_r2;
reg signed [18:0] dout_p0_r3;
reg signed [18:0] dout_p0_r4;
reg signed [18:0] dout_p0_r5;
reg signed [18:0] dout_p0_r6;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_p0_r2 <= 16'd0;
dout_p0_r3 <= 16'd0;
dout_p0_r4 <= 16'd0;
dout_p0_r5 <= 16'd0;
dout_p0_r6 <= 16'd0;
end
else if(en)
begin
dout_p0_r2 <= dout_p0_r1;
dout_p0_r3 <= dout_p0_r2;
dout_p0_r4 <= dout_p0_r3;
dout_p0_r5 <= dout_p0_r4;
dout_p0_r6 <= dout_p0_r5;
end
else
begin
dout_p0_r2 <= dout_p0_r2;
dout_p0_r3 <= dout_p0_r3;
dout_p0_r4 <= dout_p0_r4;
dout_p0_r5 <= dout_p0_r5;
dout_p0_r6 <= dout_p0_r6;
end
reg vldo_diff_r1;
reg vldo_diff_r2;
reg vldo_diff_r3;
reg vldo_diff_r4;
reg vldo_diff_r5;
reg vldo_diff_r6;
reg vldo_diff_r7;
reg vldo_diff_r8;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
vldo_diff_r1 <= 16'd0;
vldo_diff_r2 <= 16'd0;
vldo_diff_r3 <= 16'd0;
vldo_diff_r4 <= 16'd0;
vldo_diff_r5 <= 16'd0;
vldo_diff_r6 <= 16'd0;
vldo_diff_r7 <= 16'd0;
vldo_diff_r8 <= 16'd0;
end
else if(en) begin
vldo_diff_r1 <= vldo_diff;
vldo_diff_r2 <= vldo_diff_r1;
vldo_diff_r3 <= vldo_diff_r2;
vldo_diff_r4 <= vldo_diff_r3;
vldo_diff_r5 <= vldo_diff_r4;
vldo_diff_r6 <= vldo_diff_r5;
vldo_diff_r7 <= vldo_diff_r6;
vldo_diff_r8 <= vldo_diff_r7;
end
else begin
vldo_diff_r1 <= vldo_diff_r1;
vldo_diff_r2 <= vldo_diff_r2;
vldo_diff_r3 <= vldo_diff_r3;
vldo_diff_r4 <= vldo_diff_r4;
vldo_diff_r5 <= vldo_diff_r5;
vldo_diff_r6 <= vldo_diff_r6;
vldo_diff_r7 <= vldo_diff_r7;
vldo_diff_r8 <= vldo_diff_r8;
end
end
wire vldo_r0_h;
wire vldo_r0_l;
reg vldo_r0;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
vldo_r0 <= 0;
end
else if(vldo_r0_h)begin
vldo_r0 <= 1;
end
else if(vldo_r0_l)begin
vldo_r0 <= 0;
end
end
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ;
assign vldo = vldo_r0;
endmodule

236
rtl/ref/diff_p.v Normal file
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@ -0,0 +1,236 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module diff_p_ref
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,output vldo
,output signed [15:0] dout_p0
,output signed [15:0] dout_p1
,output signed [15:0] dout_p2
,output signed [15:0] dout_p3
,output signed [15:0] dout_p4
,output signed [15:0] dout_p5
,output signed [15:0] dout_p6
,output signed [15:0] dout_p7
,output signed [15:0] diff_p0
,output signed [15:0] diff_p1
,output signed [15:0] diff_p2
,output signed [15:0] diff_p3
,output signed [15:0] diff_p4
,output signed [15:0] diff_p5
,output signed [15:0] diff_p6
,output signed [15:0] diff_p7
);
wire signed [15:0] din_p0_r0;
wire signed [15:0] din_p1_r0;
wire signed [15:0] din_p2_r0;
wire signed [15:0] din_p3_r0;
wire signed [15:0] din_p4_r0;
wire signed [15:0] din_p5_r0;
wire signed [15:0] din_p6_r0;
wire signed [15:0] din_p7_r0;
s2p_2_ref inst1_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din0),
.en (vldi),
.dout0 (din_p0_r0),
.dout1 (din_p4_r0)
,.vldo( vldo)
);
s2p_2_ref inst2_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din1),
.en (vldi),
.dout0 (din_p1_r0),
.dout1 (din_p5_r0)
,.vldo( )
);
s2p_2_ref inst3_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din2),
.en (vldi),
.dout0 (din_p2_r0),
.dout1 (din_p6_r0)
,.vldo( )
);
s2p_2_ref inst4_s2p_2_ref (
.clk (clk),
.rst_n (rstn),
.din (din3),
.en (vldi),
.dout0 (din_p3_r0),
.dout1 (din_p7_r0)
,.vldo( )
);
reg signed [15:0] din_p0_r1;
reg signed [15:0] din_p1_r1;
reg signed [15:0] din_p2_r1;
reg signed [15:0] din_p3_r1;
reg signed [15:0] din_p4_r1;
reg signed [15:0] din_p5_r1;
reg signed [15:0] din_p6_r1;
reg signed [15:0] din_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p0_r1 <= 'h0;
din_p1_r1 <= 'h0;
din_p2_r1 <= 'h0;
din_p3_r1 <= 'h0;
din_p4_r1 <= 'h0;
din_p5_r1 <= 'h0;
din_p6_r1 <= 'h0;
din_p7_r1 <= 'h0;
end
else if(en)
begin
din_p0_r1 <= din_p0_r0;
din_p1_r1 <= din_p1_r0;
din_p2_r1 <= din_p2_r0;
din_p3_r1 <= din_p3_r0;
din_p4_r1 <= din_p4_r0;
din_p5_r1 <= din_p5_r0;
din_p6_r1 <= din_p6_r0;
din_p7_r1 <= din_p7_r0;
end
else
begin
din_p0_r1 <= din_p0_r1;
din_p1_r1 <= din_p1_r1;
din_p2_r1 <= din_p2_r1;
din_p3_r1 <= din_p3_r1;
din_p4_r1 <= din_p4_r1;
din_p5_r1 <= din_p5_r1;
din_p6_r1 <= din_p6_r1;
din_p7_r1 <= din_p7_r1;
end
assign dout_p0 = din_p0_r1;
assign dout_p1 = din_p1_r1;
assign dout_p2 = din_p2_r1;
assign dout_p3 = din_p3_r1;
assign dout_p4 = din_p4_r1;
assign dout_p5 = din_p5_r1;
assign dout_p6 = din_p6_r1;
assign dout_p7 = din_p7_r1;
wire signed [15:0] diff_p0_r0;
wire signed [15:0] diff_p1_r0;
wire signed [15:0] diff_p2_r0;
wire signed [15:0] diff_p3_r0;
wire signed [15:0] diff_p4_r0;
wire signed [15:0] diff_p5_r0;
wire signed [15:0] diff_p6_r0;
wire signed [15:0] diff_p7_r0;
assign diff_p0_r0 = din_p0_r0 - din_p7_r1;
assign diff_p1_r0 = din_p1_r0 - din_p0_r0;
assign diff_p2_r0 = din_p2_r0 - din_p1_r0;
assign diff_p3_r0 = din_p3_r0 - din_p2_r0;
assign diff_p4_r0 = din_p4_r0 - din_p3_r0;
assign diff_p5_r0 = din_p5_r0 - din_p4_r0;
assign diff_p6_r0 = din_p6_r0 - din_p5_r0;
assign diff_p7_r0 = din_p7_r0 - din_p6_r0;
reg signed [15:0] diff_p0_r1;
reg signed [15:0] diff_p1_r1;
reg signed [15:0] diff_p2_r1;
reg signed [15:0] diff_p3_r1;
reg signed [15:0] diff_p4_r1;
reg signed [15:0] diff_p5_r1;
reg signed [15:0] diff_p6_r1;
reg signed [15:0] diff_p7_r1;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
diff_p0_r1 <= 0;
diff_p1_r1 <= 0;
diff_p2_r1 <= 0;
diff_p3_r1 <= 0;
diff_p4_r1 <= 0;
diff_p5_r1 <= 0;
diff_p6_r1 <= 0;
diff_p7_r1 <= 0;
end
else if(en)begin
diff_p0_r1 <= diff_p0_r0;
diff_p1_r1 <= diff_p1_r0;
diff_p2_r1 <= diff_p2_r0;
diff_p3_r1 <= diff_p3_r0;
diff_p4_r1 <= diff_p4_r0;
diff_p5_r1 <= diff_p5_r0;
diff_p6_r1 <= diff_p6_r0;
diff_p7_r1 <= diff_p7_r0;
end
else begin
diff_p0_r1 <= diff_p0_r1;
diff_p1_r1 <= diff_p1_r1;
diff_p2_r1 <= diff_p2_r1;
diff_p3_r1 <= diff_p3_r1;
diff_p4_r1 <= diff_p4_r1;
diff_p5_r1 <= diff_p5_r1;
diff_p6_r1 <= diff_p6_r1;
diff_p7_r1 <= diff_p7_r1;
end
end
assign diff_p0 = diff_p0_r1;
assign diff_p1 = diff_p1_r1;
assign diff_p2 = diff_p2_r1;
assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
assign diff_p5 = diff_p5_r1;
assign diff_p6 = diff_p6_r1;
assign diff_p7 = diff_p7_r1;
endmodule

110
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@ -0,0 +1,110 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C_ref #(
parameter integer A_width = 8
,parameter integer B_width = 8
,parameter integer C_width = 8
,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division
)
(
clk,
rstn,
en,
a,
b,
c,
d,
Re,
Im
);
input rstn;
input clk;
input en;
input signed [A_width-1:0] a;
input signed [B_width-1:0] b;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-frac_coef_width-1:0] Re;
output signed [A_width+D_width-frac_coef_width-1:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc;
wire signed [A_width+C_width:0] Re_round;
wire signed [A_width+D_width:0] Im_round;
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
assign Re = Re_round[A_width+D_width-1:frac_coef_width];
assign Im = Im_round[A_width+D_width-1:frac_coef_width];
endmodule

121
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module s2p_2_ref (
input clk,
input rst_n,
input [15:0] din,
input en,
output [15:0] dout0,
output [15:0] dout1,
output vldo
);
reg en_r1;
reg en_r2;
reg en_r3;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
en_r1 <= 0;
en_r2 <= 0;
en_r3 <= 0;
end
else begin
en_r1 <= en;
en_r2 <= en_r1;
end
end
assign vldo = en_r2;
reg cnt;
wire add_cnt;
wire end_cnt;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
cnt <= 0;
end
else if(add_cnt)begin
if(end_cnt)
cnt <= 0;
else
cnt <= cnt + 1;
end
else begin
cnt <= 0;
end
end
assign add_cnt = en == 1'b1;
assign end_cnt = add_cnt && cnt== 2 - 1 ;
reg [ 15: 0] dout0_r0;
reg [ 15: 0] dout1_r0;
wire dout0_en;
wire dout1_en;
wire dout0_hold;
wire dout1_hold;
always @(*)begin
if(rst_n==1'b0)begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
else if(dout0_en)begin
dout0_r0 = din;
end
else if(dout1_en)begin
dout1_r0 = din;
end
else begin
dout0_r0 = 16'd0;
dout1_r0 = 16'd0;
end
end
assign dout0_en = add_cnt && cnt == 0;
assign dout1_en = add_cnt && cnt == 1;
reg [ 15: 0] dout0_r1;
reg [ 15: 0] dout1_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
else if(en)begin
dout0_r1 <= dout0_r0;
dout1_r1 <= dout1_r0;
end
else if(dout0_hold)begin
dout0_r1 <= dout0_r1;
dout1_r1 <= 16'd0;
end
else if(dout1_hold)begin
dout0_r1 <= 16'd0;
dout1_r1 <= dout1_r1;
end
else begin
dout0_r1 <= 16'd0;
dout1_r1 <= 16'd0;
end
end
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
reg [ 15: 0] dout0_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout0_r2 <= 16'd0;
end
else begin
dout0_r2 <= dout0_r1;
end
end
assign dout0 = dout0_r2;
assign dout1 = dout1_r1;
endmodule

704
rtl/z_dsp/CoefGen.sv
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@ -1,704 +0,0 @@
module CoefGen #(
parameter data_in_width = 32
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input [5:0] vldi
,input signed [31:0] a0_re
,input signed [31:0] a0_im
,input signed [31:0] b0_re
,input signed [31:0] b0_im
,input signed [31:0] a1_re
,input signed [31:0] a1_im
,input signed [31:0] b1_re
,input signed [31:0] b1_im
,input signed [31:0] a2_re
,input signed [31:0] a2_im
,input signed [31:0] b2_re
,input signed [31:0] b2_im
,input signed [31:0] a3_re
,input signed [31:0] a3_im
,input signed [31:0] b3_re
,input signed [31:0] b3_im
,input signed [31:0] a4_re
,input signed [31:0] a4_im
,input signed [31:0] b4_re
,input signed [31:0] b4_im
,input signed [31:0] a5_re
,input signed [31:0] a5_im
,input signed [31:0] b5_re
,input signed [31:0] b5_im
,output reg signed [31:0] a_re0
,output reg signed [31:0] a_im0
,output reg signed [31:0] b_re0
,output reg signed [31:0] b_im0
,output reg signed [31:0] ab_re0
,output reg signed [31:0] ab_im0
,output reg signed [31:0] abb_re0
,output reg signed [31:0] abb_im0
,output reg signed [31:0] ab_pow3_re0
,output reg signed [31:0] ab_pow3_im0
,output reg signed [31:0] ab_pow4_re0
,output reg signed [31:0] ab_pow4_im0
,output reg signed [31:0] ab_pow5_re0
,output reg signed [31:0] ab_pow5_im0
,output reg signed [31:0] ab_pow6_re0
,output reg signed [31:0] ab_pow6_im0
,output reg signed [31:0] ab_pow7_re0
,output reg signed [31:0] ab_pow7_im0
,output reg signed [31:0] b_pow8_re0
,output reg signed [31:0] b_pow8_im0
,output reg signed [31:0] a_re1
,output reg signed [31:0] a_im1
,output reg signed [31:0] b_re1
,output reg signed [31:0] b_im1
,output reg signed [31:0] ab_re1
,output reg signed [31:0] ab_im1
,output reg signed [31:0] abb_re1
,output reg signed [31:0] abb_im1
,output reg signed [31:0] ab_pow3_re1
,output reg signed [31:0] ab_pow3_im1
,output reg signed [31:0] ab_pow4_re1
,output reg signed [31:0] ab_pow4_im1
,output reg signed [31:0] ab_pow5_re1
,output reg signed [31:0] ab_pow5_im1
,output reg signed [31:0] ab_pow6_re1
,output reg signed [31:0] ab_pow6_im1
,output reg signed [31:0] ab_pow7_re1
,output reg signed [31:0] ab_pow7_im1
,output reg signed [31:0] b_pow8_re1
,output reg signed [31:0] b_pow8_im1
,output reg signed [31:0] a_re2
,output reg signed [31:0] a_im2
,output reg signed [31:0] b_re2
,output reg signed [31:0] b_im2
,output reg signed [31:0] ab_re2
,output reg signed [31:0] ab_im2
,output reg signed [31:0] abb_re2
,output reg signed [31:0] abb_im2
,output reg signed [31:0] ab_pow3_re2
,output reg signed [31:0] ab_pow3_im2
,output reg signed [31:0] ab_pow4_re2
,output reg signed [31:0] ab_pow4_im2
,output reg signed [31:0] ab_pow5_re2
,output reg signed [31:0] ab_pow5_im2
,output reg signed [31:0] ab_pow6_re2
,output reg signed [31:0] ab_pow6_im2
,output reg signed [31:0] ab_pow7_re2
,output reg signed [31:0] ab_pow7_im2
,output reg signed [31:0] b_pow8_re2
,output reg signed [31:0] b_pow8_im2
,output reg signed [31:0] a_re3
,output reg signed [31:0] a_im3
,output reg signed [31:0] b_re3
,output reg signed [31:0] b_im3
,output reg signed [31:0] ab_re3
,output reg signed [31:0] ab_im3
,output reg signed [31:0] abb_re3
,output reg signed [31:0] abb_im3
,output reg signed [31:0] ab_pow3_re3
,output reg signed [31:0] ab_pow3_im3
,output reg signed [31:0] ab_pow4_re3
,output reg signed [31:0] ab_pow4_im3
,output reg signed [31:0] ab_pow5_re3
,output reg signed [31:0] ab_pow5_im3
,output reg signed [31:0] ab_pow6_re3
,output reg signed [31:0] ab_pow6_im3
,output reg signed [31:0] ab_pow7_re3
,output reg signed [31:0] ab_pow7_im3
,output reg signed [31:0] b_pow8_re3
,output reg signed [31:0] b_pow8_im3
,output reg signed [31:0] a_re4
,output reg signed [31:0] a_im4
,output reg signed [31:0] b_re4
,output reg signed [31:0] b_im4
,output reg signed [31:0] ab_re4
,output reg signed [31:0] ab_im4
,output reg signed [31:0] abb_re4
,output reg signed [31:0] abb_im4
,output reg signed [31:0] ab_pow3_re4
,output reg signed [31:0] ab_pow3_im4
,output reg signed [31:0] ab_pow4_re4
,output reg signed [31:0] ab_pow4_im4
,output reg signed [31:0] ab_pow5_re4
,output reg signed [31:0] ab_pow5_im4
,output reg signed [31:0] ab_pow6_re4
,output reg signed [31:0] ab_pow6_im4
,output reg signed [31:0] ab_pow7_re4
,output reg signed [31:0] ab_pow7_im4
,output reg signed [31:0] b_pow8_re4
,output reg signed [31:0] b_pow8_im4
,output reg signed [31:0] a_re5
,output reg signed [31:0] a_im5
,output reg signed [31:0] b_re5
,output reg signed [31:0] b_im5
,output reg signed [31:0] ab_re5
,output reg signed [31:0] ab_im5
,output reg signed [31:0] abb_re5
,output reg signed [31:0] abb_im5
,output reg signed [31:0] ab_pow3_re5
,output reg signed [31:0] ab_pow3_im5
,output reg signed [31:0] ab_pow4_re5
,output reg signed [31:0] ab_pow4_im5
,output reg signed [31:0] ab_pow5_re5
,output reg signed [31:0] ab_pow5_im5
,output reg signed [31:0] ab_pow6_re5
,output reg signed [31:0] ab_pow6_im5
,output reg signed [31:0] ab_pow7_re5
,output reg signed [31:0] ab_pow7_im5
,output reg signed [31:0] b_pow8_re5
,output reg signed [31:0] b_pow8_im5
);
reg vldi_or_r1;
wire vldi_or = | vldi;
sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn);
reg signed [data_in_width-1:0] a_re_r1;
reg signed [data_in_width-1:0] a_im_r1;
reg signed [data_in_width-1:0] b_re_r1;
reg signed [data_in_width-1:0] b_im_r1;
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
a_re_r1 <= 'h0;
a_im_r1 <= 'h0;
b_re_r1 <= 'h0;
b_im_r1 <= 'h0;
end
else if(|vldi) begin
case(1'b1)
vldi[0]: begin
a_re_r1 <= a0_re;
a_im_r1 <= a0_im;
b_re_r1 <= b0_re;
b_im_r1 <= b0_im;
end
vldi[1]: begin
a_re_r1 <= a1_re;
a_im_r1 <= a1_im;
b_re_r1 <= b1_re;
b_im_r1 <= b1_im;
end
vldi[2]: begin
a_re_r1 <= a2_re;
a_im_r1 <= a2_im;
b_re_r1 <= b2_re;
b_im_r1 <= b2_im;
end
vldi[3]: begin
a_re_r1 <= a3_re;
a_im_r1 <= a3_im;
b_re_r1 <= b3_re;
b_im_r1 <= b3_im;
end
vldi[4]: begin
a_re_r1 <= a4_re;
a_im_r1 <= a4_im;
b_re_r1 <= b4_re;
b_im_r1 <= b4_im;
end
vldi[5]: begin
a_re_r1 <= a5_re;
a_im_r1 <= a5_im;
b_re_r1 <= b5_re;
b_im_r1 <= b5_im;
end
// default: begin
// a_re_r1 <= a_re[0];
// a_im_r1 <= a_im[0];
// b_re_r1 <= b_re[0];
// b_im_r1 <= b_im[0];
// end
endcase
end
end
reg en;
reg en_r1;
sirv_gnrl_dffr #(1) dff_en_1(en, en_r1 ,clk,rstn);
reg [3:0] cnt0;
wire add_cnt0;
wire end_cnt0;
always @(posedge clk or negedge rstn)begin
if(!rstn)begin
cnt0 <= 0;
end
else if(add_cnt0)begin
if(end_cnt0)
cnt0 <= 0;
else
cnt0 <= cnt0 + 1;
end
end
assign add_cnt0 = en;
assign end_cnt0 = add_cnt0 && cnt0== 8-1;
wire en_l;
wire en_h;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 0;
end
else if(en_h)begin
en <= 1;
end
else if(en_l)begin
en <= 0;
end
end
assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
assign en_l = end_cnt0;
reg signed [data_in_width-1:0] bin_re;
reg signed [data_in_width-1:0] bin_im;
wire signed [data_in_width-1:0] bout_re;
wire signed [data_in_width-1:0] bout_im;
always @(*)begin
if(en_r1) begin
bin_re <= bout_re;
bin_im <= bout_im;
end
else begin
bin_re <= 32'd2147483647;
bin_im <= 0;
end
end
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.o_width(data_in_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (b_re_r1 ),
.d (b_im_r1 ),
.Re (bout_re ),
.Im (bout_im )
);
wire signed [data_in_width-1:0] abo_re;
wire signed [data_in_width-1:0] abo_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width)
,.D_width(coef_width)
,.o_width(data_in_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (bin_re ),
.b (bin_im ),
.c (a_re_r1 ),
.d (a_im_r1 ),
.Re (abo_re ),
.Im (abo_im )
);
reg signed [coef_width-1 :0] ao_re_r1 ;
reg signed [coef_width-1 :0] ao_im_r1 ;
reg signed [coef_width-1 :0] ab_re_r1 ;
reg signed [coef_width-1 :0] ab_im_r1 ;
reg signed [coef_width-1 :0] abb_re_r1 ;
reg signed [coef_width-1 :0] abb_im_r1 ;
reg signed [coef_width-1 :0] ab_pow3_re_r1 ;
reg signed [coef_width-1 :0] ab_pow3_im_r1 ;
reg signed [coef_width-1 :0] ab_pow4_re_r1 ;
reg signed [coef_width-1 :0] ab_pow4_im_r1 ;
reg signed [coef_width-1 :0] ab_pow5_re_r1 ;
reg signed [coef_width-1 :0] ab_pow5_im_r1 ;
reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
reg signed [coef_width-1 :0] ab_pow6_im_r1 ;
reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
reg signed [coef_width-1 :0] ab_pow7_im_r1 ;
reg signed [coef_width-1 :0] bo_re_r1 ;
reg signed [coef_width-1 :0] bo_im_r1 ;
reg signed [coef_width-1 :0] b_pow8_re_r1 ;
reg signed [coef_width-1 :0] b_pow8_im_r1 ;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
ao_re_r1 <= 0;
ao_im_r1 <= 0;
ab_re_r1 <= 0;
ab_im_r1 <= 0;
abb_re_r1 <= 0;
abb_im_r1 <= 0;
ab_pow3_re_r1 <= 0;
ab_pow3_im_r1 <= 0;
ab_pow4_re_r1 <= 0;
ab_pow4_im_r1 <= 0;
ab_pow5_re_r1 <= 0;
ab_pow5_im_r1 <= 0;
ab_pow6_re_r1 <= 0;
ab_pow6_im_r1 <= 0;
ab_pow7_re_r1 <= 0;
ab_pow7_im_r1 <= 0;
b_pow8_re_r1 <= 0;
b_pow8_im_r1 <= 0;
end
else if(add_cnt0 && cnt0 == 1 && en_r1)begin
ao_re_r1 <= abo_re;
ao_im_r1 <= abo_im;
bo_re_r1 <= bin_re;
bo_im_r1 <= bin_im;
end
else if(add_cnt0 && cnt0 == 2 && en_r1)begin
ab_re_r1 <= abo_re;
ab_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 3 && en_r1)begin
abb_re_r1 <= abo_re;
abb_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 4 && en_r1)begin
ab_pow3_re_r1 <= abo_re;
ab_pow3_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 5 && en_r1)begin
ab_pow4_re_r1 <= abo_re;
ab_pow4_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 6 && en_r1)begin
ab_pow5_re_r1 <= abo_re;
ab_pow5_im_r1 <= abo_im;
end
else if(add_cnt0 && cnt0 == 7 && en_r1)begin
ab_pow6_re_r1 <= abo_re;
ab_pow6_im_r1 <= abo_im;
end
else if(cnt0 == 0 && en_r1)begin
ab_pow7_re_r1 <= abo_re;
ab_pow7_im_r1 <= abo_im;
b_pow8_re_r1 <= bin_re;
b_pow8_im_r1 <= bin_im;
end
// else begin
// end
end
reg [5:0] vldi_r1;
reg [5:0] vldi_r2;
reg [5:0] vldi_r3;
reg [5:0] vldi_r4;
reg [5:0] vldi_r5;
reg [5:0] vldi_r6;
reg [5:0] vldi_r7;
reg [5:0] vldi_r8;
reg [5:0] vldi_r9;
reg [5:0] vldi_r10;
//syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);
sirv_gnrl_dffr #(6) dff_vldi_1(vldi,vldi_r1,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn);
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
a_re0 <= 0;
a_im0 <= 0;
b_re0 <= 0;
b_im0 <= 0;
ab_re0 <= 0;
ab_im0 <= 0;
abb_re0 <= 0;
abb_im0 <= 0;
ab_pow3_re0 <= 0;
ab_pow3_im0 <= 0;
ab_pow4_re0 <= 0;
ab_pow4_im0 <= 0;
ab_pow5_re0 <= 0;
ab_pow5_im0 <= 0;
ab_pow6_re0 <= 0;
ab_pow6_im0 <= 0;
ab_pow7_re0 <= 0;
ab_pow7_im0 <= 0;
b_pow8_re0 <= 0;
b_pow8_im0 <= 0;
a_re1 <= 0;
a_im1 <= 0;
b_re1 <= 0;
b_im1 <= 0;
ab_re1 <= 0;
ab_im1 <= 0;
abb_re1 <= 0;
abb_im1 <= 0;
ab_pow3_re1 <= 0;
ab_pow3_im1 <= 0;
ab_pow4_re1 <= 0;
ab_pow4_im1 <= 0;
ab_pow5_re1 <= 0;
ab_pow5_im1 <= 0;
ab_pow6_re1 <= 0;
ab_pow6_im1 <= 0;
ab_pow7_re1 <= 0;
ab_pow7_im1 <= 0;
b_pow8_re1 <= 0;
b_pow8_im1 <= 0;
a_re2 <= 0;
a_im2 <= 0;
b_re2 <= 0;
b_im2 <= 0;
ab_re2 <= 0;
ab_im2 <= 0;
abb_re2 <= 0;
abb_im2 <= 0;
ab_pow3_re2 <= 0;
ab_pow3_im2 <= 0;
ab_pow4_re2 <= 0;
ab_pow4_im2 <= 0;
ab_pow5_re2 <= 0;
ab_pow5_im2 <= 0;
ab_pow6_re2 <= 0;
ab_pow6_im2 <= 0;
ab_pow7_re2 <= 0;
ab_pow7_im2 <= 0;
b_pow8_re2 <= 0;
b_pow8_im2 <= 0;
a_re3 <= 0;
a_im3 <= 0;
b_re3 <= 0;
b_im3 <= 0;
ab_re3 <= 0;
ab_im3 <= 0;
abb_re3 <= 0;
abb_im3 <= 0;
ab_pow3_re3 <= 0;
ab_pow3_im3 <= 0;
ab_pow4_re3 <= 0;
ab_pow4_im3 <= 0;
ab_pow5_re3 <= 0;
ab_pow5_im3 <= 0;
ab_pow6_re3 <= 0;
ab_pow6_im3 <= 0;
ab_pow7_re3 <= 0;
ab_pow7_im3 <= 0;
b_pow8_re3 <= 0;
b_pow8_im3 <= 0;
a_re4 <= 0;
a_im4 <= 0;
b_re4 <= 0;
b_im4 <= 0;
ab_re4 <= 0;
ab_im4 <= 0;
abb_re4 <= 0;
abb_im4 <= 0;
ab_pow3_re4 <= 0;
ab_pow3_im4 <= 0;
ab_pow4_re4 <= 0;
ab_pow4_im4 <= 0;
ab_pow5_re4 <= 0;
ab_pow5_im4 <= 0;
ab_pow6_re4 <= 0;
ab_pow6_im4 <= 0;
ab_pow7_re4 <= 0;
ab_pow7_im4 <= 0;
b_pow8_re4 <= 0;
b_pow8_im4 <= 0;
a_re5 <= 0;
a_im5 <= 0;
b_re5 <= 0;
b_im5 <= 0;
ab_re5 <= 0;
ab_im5 <= 0;
abb_re5 <= 0;
abb_im5 <= 0;
ab_pow3_re5 <= 0;
ab_pow3_im5 <= 0;
ab_pow4_re5 <= 0;
ab_pow4_im5 <= 0;
ab_pow5_re5 <= 0;
ab_pow5_im5 <= 0;
ab_pow6_re5 <= 0;
ab_pow6_im5 <= 0;
ab_pow7_re5 <= 0;
ab_pow7_im5 <= 0;
b_pow8_re5 <= 0;
b_pow8_im5 <= 0;
end
else if(|vldi_r10) begin
case(1'b1)
vldi_r10[0]: begin
a_re0 <= ao_re_r1 ;
a_im0 <= ao_im_r1 ;
b_re0 <= bo_re_r1 ;
b_im0 <= bo_im_r1 ;
ab_re0 <= ab_re_r1 ;
ab_im0 <= ab_im_r1 ;
abb_re0 <= abb_re_r1 ;
abb_im0 <= abb_im_r1 ;
ab_pow3_re0 <= ab_pow3_re_r1;
ab_pow3_im0 <= ab_pow3_im_r1;
ab_pow4_re0 <= ab_pow4_re_r1;
ab_pow4_im0 <= ab_pow4_im_r1;
ab_pow5_re0 <= ab_pow5_re_r1;
ab_pow5_im0 <= ab_pow5_im_r1;
ab_pow6_re0 <= ab_pow6_re_r1;
ab_pow6_im0 <= ab_pow6_im_r1;
ab_pow7_re0 <= ab_pow7_re_r1;
ab_pow7_im0 <= ab_pow7_im_r1;
b_pow8_re0 <= b_pow8_re_r1 ;
b_pow8_im0 <= b_pow8_im_r1 ;
end
vldi_r10[1]: begin
a_re1 <= ao_re_r1 ;
a_im1 <= ao_im_r1 ;
b_re1 <= bo_re_r1 ;
b_im1 <= bo_im_r1 ;
ab_re1 <= ab_re_r1 ;
ab_im1 <= ab_im_r1 ;
abb_re1 <= abb_re_r1 ;
abb_im1 <= abb_im_r1 ;
ab_pow3_re1 <= ab_pow3_re_r1;
ab_pow3_im1 <= ab_pow3_im_r1;
ab_pow4_re1 <= ab_pow4_re_r1;
ab_pow4_im1 <= ab_pow4_im_r1;
ab_pow5_re1 <= ab_pow5_re_r1;
ab_pow5_im1 <= ab_pow5_im_r1;
ab_pow6_re1 <= ab_pow6_re_r1;
ab_pow6_im1 <= ab_pow6_im_r1;
ab_pow7_re1 <= ab_pow7_re_r1;
ab_pow7_im1 <= ab_pow7_im_r1;
b_pow8_re1 <= b_pow8_re_r1 ;
b_pow8_im1 <= b_pow8_im_r1 ;
end
vldi_r10[2]: begin
a_re2 <= ao_re_r1 ;
a_im2 <= ao_im_r1 ;
b_re2 <= bo_re_r1 ;
b_im2 <= bo_im_r1 ;
ab_re2 <= ab_re_r1 ;
ab_im2 <= ab_im_r1 ;
abb_re2 <= abb_re_r1 ;
abb_im2 <= abb_im_r1 ;
ab_pow3_re2 <= ab_pow3_re_r1;
ab_pow3_im2 <= ab_pow3_im_r1;
ab_pow4_re2 <= ab_pow4_re_r1;
ab_pow4_im2 <= ab_pow4_im_r1;
ab_pow5_re2 <= ab_pow5_re_r1;
ab_pow5_im2 <= ab_pow5_im_r1;
ab_pow6_re2 <= ab_pow6_re_r1;
ab_pow6_im2 <= ab_pow6_im_r1;
ab_pow7_re2 <= ab_pow7_re_r1;
ab_pow7_im2 <= ab_pow7_im_r1;
b_pow8_re2 <= b_pow8_re_r1 ;
b_pow8_im2 <= b_pow8_im_r1 ;
end
vldi_r10[3]: begin
a_re3 <= ao_re_r1 ;
a_im3 <= ao_im_r1 ;
b_re3 <= bo_re_r1 ;
b_im3 <= bo_im_r1 ;
ab_re3 <= ab_re_r1 ;
ab_im3 <= ab_im_r1 ;
abb_re3 <= abb_re_r1 ;
abb_im3 <= abb_im_r1 ;
ab_pow3_re3 <= ab_pow3_re_r1;
ab_pow3_im3 <= ab_pow3_im_r1;
ab_pow4_re3 <= ab_pow4_re_r1;
ab_pow4_im3 <= ab_pow4_im_r1;
ab_pow5_re3 <= ab_pow5_re_r1;
ab_pow5_im3 <= ab_pow5_im_r1;
ab_pow6_re3 <= ab_pow6_re_r1;
ab_pow6_im3 <= ab_pow6_im_r1;
ab_pow7_re3 <= ab_pow7_re_r1;
ab_pow7_im3 <= ab_pow7_im_r1;
b_pow8_re3 <= b_pow8_re_r1 ;
b_pow8_im3 <= b_pow8_im_r1 ;
end
vldi_r10[4]: begin
a_re4 <= ao_re_r1 ;
a_im4 <= ao_im_r1 ;
b_re4 <= bo_re_r1 ;
b_im4 <= bo_im_r1 ;
ab_re4 <= ab_re_r1 ;
ab_im4 <= ab_im_r1 ;
abb_re4 <= abb_re_r1 ;
abb_im4 <= abb_im_r1 ;
ab_pow3_re4 <= ab_pow3_re_r1;
ab_pow3_im4 <= ab_pow3_im_r1;
ab_pow4_re4 <= ab_pow4_re_r1;
ab_pow4_im4 <= ab_pow4_im_r1;
ab_pow5_re4 <= ab_pow5_re_r1;
ab_pow5_im4 <= ab_pow5_im_r1;
ab_pow6_re4 <= ab_pow6_re_r1;
ab_pow6_im4 <= ab_pow6_im_r1;
ab_pow7_re4 <= ab_pow7_re_r1;
ab_pow7_im4 <= ab_pow7_im_r1;
b_pow8_re4 <= b_pow8_re_r1 ;
b_pow8_im4 <= b_pow8_im_r1 ;
end
vldi_r10[5]: begin
a_re5 <= ao_re_r1 ;
a_re5 <= ao_re_r1 ;
b_im5 <= bo_im_r1 ;
b_im5 <= bo_im_r1 ;
ab_re5 <= ab_re_r1 ;
ab_im5 <= ab_im_r1 ;
abb_re5 <= abb_re_r1 ;
abb_im5 <= abb_im_r1 ;
ab_pow3_re5 <= ab_pow3_re_r1;
ab_pow3_im5 <= ab_pow3_im_r1;
ab_pow4_re5 <= ab_pow4_re_r1;
ab_pow4_im5 <= ab_pow4_im_r1;
ab_pow5_re5 <= ab_pow5_re_r1;
ab_pow5_im5 <= ab_pow5_im_r1;
ab_pow6_re5 <= ab_pow6_re_r1;
ab_pow6_im5 <= ab_pow6_im_r1;
ab_pow7_re5 <= ab_pow7_re_r1;
ab_pow7_im5 <= ab_pow7_im_r1;
b_pow8_re5 <= b_pow8_re_r1 ;
b_pow8_im5 <= b_pow8_im_r1 ;
end
// default: begin
// ao_re[0] <= 'h0;
// ao_im[0] <= 'h0;
// ab_re[0] <= 'h0;
// ab_im[0] <= 'h0;
// abb_re[0] <= 'h0;
// abb_im[0] <= 'h0;
// ab_pow3_re[0] <= 'h0;
// ab_pow3_im[0] <= 'h0;
// ab_pow4_re[0] <= 'h0;
// ab_pow4_im[0] <= 'h0;
// ab_pow5_re[0] <= 'h0;
// ab_pow5_im[0] <= 'h0;
// ab_pow6_re[0] <= 'h0;
// ab_pow6_im[0] <= 'h0;
// ab_pow7_re[0] <= 'h0;
// ab_pow7_im[0] <= 'h0;
// b_pow8_re[0] <= 'h0;
// b_pow8_im[0] <= 'h0;
// end
endcase
end
end
endmodule

2
rtl/z_dsp/TailCorr_top.v
View File

@ -910,7 +910,7 @@ always @(posedge clk or negedge rstn)begin
end
end
assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
assign vldo_r0_h = vldo_diff_r[17] == 0 && vldo_diff_r[16] == 1 ;
assign vldo_r0_h = vldo_diff_r[16] == 0 && vldo_diff_r[15] == 1 ;
assign vldo = vldo_r0;
endmodule

57
rtl/z_dsp/rate_adapter.v
View File

@ -1,57 +0,0 @@
module rate_adapter
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [15:0] din4
,input signed [15:0] din5
,input signed [15:0] din6
,input signed [15:0] din7
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
);
reg signed [15:0] doutf_0;
reg signed [15:0] doutf_1;
reg signed [15:0] doutf_2;
reg signed [15:0] doutf_3;
always@(posedge clk or negedge rstn)
if(!rstn) begin
doutf_0 <= 0;
doutf_1 <= 0;
doutf_2 <= 0;
doutf_3 <= 0;
end
else if(!en) begin
doutf_0 <= din0;
doutf_1 <= din1;
doutf_2 <= din2;
doutf_3 <= din3;
end
else begin
doutf_0 <= din4;
doutf_1 <= din5;
doutf_2 <= din6;
doutf_3 <= din7;
end
assign dout0 = doutf_0;
assign dout1 = doutf_1;
assign dout2 = doutf_2;
assign dout3 = doutf_3;
//sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi, vldo ,clk,rstn);
assign vldo = vldi;
endmodule

58
rtl/z_dsp/syncer.v
View File

@ -1,58 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : syncer.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-03-13 PWY AWG dedicated register file
// 0.2 2024-05-13 PWY
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module syncer # (
parameter width = 1
,parameter stage = 2
)
(
input clk_d
,input rstn_d
,input [width-1:0] data_s
,output [width-1:0] data_d
);
generate
genvar i;
wire [width-1:0] data_temp[stage-1:0];
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
for(i=1;i<stage;i=i+1) begin: SYNCER
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
end
endgenerate
assign data_d = data_temp[stage-1];
endmodule

396
rtl/z_dsp/z_dsp.sv
View File

@ -1,396 +0,0 @@
module z_dsp
(
input rstn
,input clk
,input en
//,input tc_bypass
,input [ 5:0] vldi_coef
,input vldi_data
//,input [1:0] intp_mode
//,input [1:0] dac_mode_sel
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,input signed [31:0] a0_re
,input signed [31:0] a0_im
,input signed [31:0] b0_re
,input signed [31:0] b0_im
,input signed [31:0] a1_re
,input signed [31:0] a1_im
,input signed [31:0] b1_re
,input signed [31:0] b1_im
,input signed [31:0] a2_re
,input signed [31:0] a2_im
,input signed [31:0] b2_re
,input signed [31:0] b2_im
,input signed [31:0] a3_re
,input signed [31:0] a3_im
,input signed [31:0] b3_re
,input signed [31:0] b3_im
,input signed [31:0] a4_re
,input signed [31:0] a4_im
,input signed [31:0] b4_re
,input signed [31:0] b4_im
,input signed [31:0] a5_re
,input signed [31:0] a5_im
,input signed [31:0] b5_re
,input signed [31:0] b5_im
,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output vldo
);
wire signed [15:0] IIR_out;
reg signed [31:0] ao_re [5:0];
reg signed [31:0] ao_im [5:0];
reg signed [31:0] ab_re [5:0];
reg signed [31:0] ab_im [5:0];
reg signed [31:0] abb_re [5:0];
reg signed [31:0] abb_im [5:0];
reg signed [31:0] ab_pow3_re [5:0];
reg signed [31:0] ab_pow3_im [5:0];
reg signed [31:0] ab_pow4_re [5:0];
reg signed [31:0] ab_pow4_im [5:0];
reg signed [31:0] ab_pow5_re [5:0];
reg signed [31:0] ab_pow5_im [5:0];
reg signed [31:0] ab_pow6_re [5:0];
reg signed [31:0] ab_pow6_im [5:0];
reg signed [31:0] ab_pow7_re [5:0];
reg signed [31:0] ab_pow7_im [5:0];
reg signed [31:0] bo_re [5:0];
reg signed [31:0] bo_im [5:0];
reg signed [31:0] b_pow8_re [5:0];
reg signed [31:0] b_pow8_im [5:0];
CoefGen inst_CoefGen(
.clk (clk ),
.rstn (rstn ),
.vldi (vldi_coef ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] )
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
reg vldo_TC;
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.vldi (vldi_data ),
// .dac_mode_sel (dac_mode_sel ),
// .intp_mode (intp_mode ),
.din0 (din0 ),
.din1 (din1 ),
.din2 (din2 ),
.din3 (din3 ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] ),
.dout_p0 (dout_0 ),
.dout_p1 (dout_1 ),
.dout_p2 (dout_2 ),
.dout_p3 (dout_3 ),
.dout_p4 (dout_4 ),
.dout_p5 (dout_5 ),
.dout_p6 (dout_6 ),
.dout_p7 (dout_7 ),
.vldo (vldo_TC )
);
//assign vldo = vldo_TC;
rate_adapter inst_rate_adapter(
.rstn (rstn ),
.clk (clk ),
.en (en ),
.vldi (vldo_TC ),
.din0 (dout_0 ),
.din1 (dout_1 ),
.din2 (dout_2 ),
.din3 (dout_3 ),
.din4 (dout_4 ),
.din5 (dout_5 ),
.din6 (dout_6 ),
.din7 (dout_7 ),
.dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.vldo (vldo )
);
endmodule

10
script_m/TailCorr_Test_Verdi.m
View File

@ -2,11 +2,11 @@
clc;clear;close all
% addpath("/data/work/thfu/TailCorr/script_m");
data_source = 'matlab';
file_path = "/home/thfu/work/TailCorr/sim/z_dsp/";
file_path = "/home/thfu/work/TailCorr/sim/";
rng('shuffle');
if strcmp(data_source, 'matlab')
in = floor(cat(1,0,3000*randn(4*2579+4,1)));
in = floor(cat(1,0,30000*ones(4*2579+4,1)));
for i = 0:3
filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
subset = in(i+1:4:end);
@ -33,14 +33,14 @@ end
cs_wave = [];
for i = 0:3
for i = 0:7
filename = strcat(file_path, "dout", num2str(i), ".dat");
dout_data = importdata(filename);
if isempty(cs_wave)
N = length(dout_data);
cs_wave = zeros(4*N, 1);
cs_wave = zeros(8*N, 1);
end
cs_wave(i+1:4:end) = dout_data;
cs_wave(i+1:8:end) = dout_data;
end
A = [0.025 0.015*1 0.0002*1 0];

0
sim/TailCorr_en/Makefile → sim/Makefile
View File

14
sim/TailCorr_en/files.f
View File

@ -1,14 +0,0 @@
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_TailCorr_en.v

21
sim/files.f Normal file
View File

@ -0,0 +1,21 @@
../rtl/z_dsp/mult_C.v
../rtl/z_dsp/mult_x.v
../rtl/z_dsp/Trunc.v
../rtl/z_dsp/TailCorr_top.v
../rtl/z_dsp/IIR_top.v
../rtl/z_dsp/diff_p.v
../rtl/z_dsp/s2p_2.v
../rtl/z_dsp/IIR_Filter_p8.v
../rtl/z_dsp/IIR_Filter_p1.v
../rtl/z_dsp/sirv_gnrl_dffs.v
../rtl/ref/mult_C.v
../rtl/ref/FixRound.v
../rtl/ref/TailCorr_top.v
../rtl/ref/IIR_top.v
../rtl/ref/diff_p.v
../rtl/ref/s2p_2.v
../rtl/ref/IIR_Filter_p8.v
../rtl/model/DW02_mult.v
tb_TailCorr_en.v

17
sim/s2p_2/Makefile
View File

@ -1,17 +0,0 @@
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

3
sim/s2p_2/files.f
View File

@ -1,3 +0,0 @@
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
tb_s2p_2.v

131
sim/s2p_2/tb_s2p_2.v
View File

@ -1,131 +0,0 @@
`timescale 1ns/1ps
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rst_n;
reg [15:0] din;
reg enable;
reg vldo;
reg [21:0] cnt;
wire [15:0] dout0;
wire [15:0] dout1;
s2p_2 u_s2p_2(
.clk ( clk ),
.rst_n ( rst_n ),
.din ( din ),
.en ( enable ),
.dout0 ( dout0 ),
.dout1 ( dout1 ),
.vldo ( vldo )
);
reg[15:0] din_r1;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
din_r1 <= 0;
end
else begin
din_r1 <= din;
end
end
wire signed [15:0] diff;
assign diff = din - din_r1;
reg[15:0] dout1_r1;
reg[15:0] dout1_r2;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
dout1_r1 <= 0;
dout1_r2 <= 0;
end
else begin
dout1_r1 <= dout1;
dout1_r2 <= dout1_r1;
end
end
wire signed [15:0] diff12;
wire signed [15:0] diff23;
assign diff12 = dout0 - dout1_r2;
assign diff23 = dout1 - dout0;
initial begin
rst_n = 0;
enable = 0;
clk = 1'b0;
din = 16'h0000;
#20;
rst_n = 1;
#10;
end
always #5 clk = ~clk;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
cnt <= 22'd0;
end else begin
cnt <= cnt + 22'd1;
end
end
reg [15:0] enable_cnt;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
enable <= 0;
din <= 16'd0;
enable_cnt <= 0;
end else begin
if (cnt < 1000) begin
if (enable_cnt == 0) begin
if ($urandom % 2 == 0) begin
enable <= 1;
enable_cnt <= $urandom % 10 + 5;
din <= $urandom;
end else begin
enable <= 0;
din <= 16'd0;
end
end else begin
enable <= 1;
enable_cnt <= enable_cnt - 1;
din <= $urandom;
end
end else begin
enable <= 0;
din <= 16'd0;
end
end
end
initial begin
wait(cnt[11] == 1);
$finish;
end
endmodule

24
sim/tb_CoefGen/Makefile
View File

@ -1,24 +0,0 @@
ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

7
sim/tb_CoefGen/files.f
View File

@ -1,7 +0,0 @@
../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_CoefGen.v

286
sim/tb_CoefGen/tb_CoefGen.v
View File

@ -1,286 +0,0 @@
`timescale 1 ns/1 ns
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
end
reg clk ;
reg en;
reg [5:0] vldi;
reg rst_n;
reg signed [31:0] a_re [5:0];
reg signed [31:0] a_im [5:0];
reg signed [31:0] b_re [5:0];
reg signed [31:0] b_im [5:0];
wire signed [31:0] ao_re [5:0];
wire signed [31:0] ao_im [5:0];
wire signed [31:0] ab_re [5:0];
wire signed [31:0] ab_im [5:0];
wire signed [31:0] abb_re [5:0];
wire signed [31:0] abb_im [5:0];
wire signed [31:0] ab_pow3_re [5:0];
wire signed [31:0] ab_pow3_im [5:0];
wire signed [31:0] ab_pow4_re [5:0];
wire signed [31:0] ab_pow4_im [5:0];
wire signed [31:0] ab_pow5_re [5:0];
wire signed [31:0] ab_pow5_im [5:0];
wire signed [31:0] ab_pow6_re [5:0];
wire signed [31:0] ab_pow6_im [5:0];
wire signed [31:0] ab_pow7_re [5:0];
wire signed [31:0] ab_pow7_im [5:0];
wire signed [31:0] bo_re [5:0];
wire signed [31:0] bo_im [5:0];
wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0];
parameter CYCLE = 20;
parameter RST_TIME = 3 ;
CoefGen inst_CoefGen(
.clk (clk ),
.rstn (rst_n ),
.vldi (vldi ),
.a0_re (a_re[0] ),
.a0_im (a_im[0] ),
.b0_re (b_re[0] ),
.b0_im (b_im[0] ),
.a1_re (a_re[1] ),
.a1_im (a_im[1] ),
.b1_re (b_re[1] ),
.b1_im (b_im[1] ),
.a2_re (a_re[2] ),
.a2_im (a_im[2] ),
.b2_re (b_re[2] ),
.b2_im (b_im[2] ),
.a3_re (a_re[3] ),
.a3_im (a_im[3] ),
.b3_re (b_re[3] ),
.b3_im (b_im[3] ),
.a4_re (a_re[4] ),
.a4_im (a_im[4] ),
.b4_re (b_re[4] ),
.b4_im (b_im[4] ),
.a5_re (a_re[5] ),
.a5_im (a_im[5] ),
.b5_re (b_re[5] ),
.b5_im (b_im[5] ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] )
);
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg [15:0] st1;
reg [15:0] st2;
reg [15:0] st3;
reg [15:0] st4;
initial begin
rst_n = 0;
vldi <= 0;
st1 = 100;
st2 = 101;
st3 = 110;
st4 = 111;
repeat(3) @(posedge clk);
vldi[0] <= 1;
rst_n = 1;
a_re[0] <= 55007237;
a_im[0] <= 0;
b_re[0] <= 2143083068;
b_im[0] <= 0;
@(posedge clk);
vldi[0] <= 0;
a_re[0] <= 0;
a_im[0] <= 0;
b_re[0] <= 0;
b_im[0] <= 0;
repeat(8) @(posedge clk);
vldi[1] <= 1;
rst_n = 1;
a_re[1] <= 32690030;
a_im[1] <= 0;
b_re[1] <= 2145807236;
b_im[1] <= 0;
@(posedge clk);
vldi[1] <= 0;
a_re[1] <= 0;
a_im[1] <= 0;
b_re[1] <= 0;
b_im[1] <= 0;
repeat(8) @(posedge clk);
vldi[2] <= 1;
rst_n = 1;
a_re[2] <= 429516;
a_im[2] <= 0;
b_re[2] <= 2146812530;
b_im[2] <= 0;
@(posedge clk);
vldi[2] <= 0;
a_re[2] <= 0;
a_im[2] <= 0;
b_re[2] <= 0;
b_im[2] <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rst_n)
if(!rst_n) begin
cnt <= 22'd0;
end
else begin
cnt <= cnt + 22'd1;
end
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
endmodule

187
sim/TailCorr_en/tb_TailCorr_en.v → sim/tb_TailCorr_en.v
View File

@ -1,4 +1,36 @@
module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode;
@ -404,7 +436,7 @@ assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
//wire vldo_ref;
wire vldo_ref;
assign tc_bypass = 1'b0;
@ -418,6 +450,7 @@ always @(posedge clk or negedge rstn)begin
end
end
wire signed [15:0] dout_p[7:0];
wire signed [15:0] dout_ref_p[7:0];
TailCorr_top inst_TailCorr_top
@ -565,6 +598,152 @@ TailCorr_top inst_TailCorr_top
);
TailCorr_top_ref refm_TailCorr_top
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.vldi (vldi_matlab[0] ),
// .dac_mode_sel (dac_mode_sel ),
// .intp_mode (intp_mode ),
.din0 (iir_in[0]),
.din1 (iir_in[1]),
.din2 (iir_in[2]),
.din3 (iir_in[3]),
.a_re0 (a_re0),
.a_im0 (a_im0),
//.b_re0 (b_re0),
//.b_im0 (b_im0),
.ab_re0 (ab_re0),
.ab_im0 (ab_im0),
.abb_re0 (abb_re0),
.abb_im0 (abb_im0),
.ab_pow3_re0 (ab_pow3_re0),
.ab_pow3_im0 (ab_pow3_im0),
.ab_pow4_re0 (ab_pow4_re0),
.ab_pow4_im0 (ab_pow4_im0),
.ab_pow5_re0 (ab_pow5_re0),
.ab_pow5_im0 (ab_pow5_im0),
.ab_pow6_re0 (ab_pow6_re0),
.ab_pow6_im0 (ab_pow6_im0),
.ab_pow7_re0 (ab_pow7_re0),
.ab_pow7_im0 (ab_pow7_im0),
.b_pow8_re0 (b_pow8_re0),
.b_pow8_im0 (b_pow8_im0),
.a_re1 (a_re1),
.a_im1 (a_im1),
//.b_re1 (b_re1),
//.b_im1 (b_im1),
.ab_re1 (ab_re1),
.ab_im1 (ab_im1),
.abb_re1 (abb_re1),
.abb_im1 (abb_im1),
.ab_pow3_re1 (ab_pow3_re1),
.ab_pow3_im1 (ab_pow3_im1),
.ab_pow4_re1 (ab_pow4_re1),
.ab_pow4_im1 (ab_pow4_im1),
.ab_pow5_re1 (ab_pow5_re1),
.ab_pow5_im1 (ab_pow5_im1),
.ab_pow6_re1 (ab_pow6_re1),
.ab_pow6_im1 (ab_pow6_im1),
.ab_pow7_re1 (ab_pow7_re1),
.ab_pow7_im1 (ab_pow7_im1),
.b_pow8_re1 (b_pow8_re1),
.b_pow8_im1 (b_pow8_im1),
.a_re2 (a_re2),
.a_im2 (a_im2),
//.b_re2 (b_re2),
//.b_im2 (b_im2),
.ab_re2 (ab_re2),
.ab_im2 (ab_im2),
.abb_re2 (abb_re2),
.abb_im2 (abb_im2),
.ab_pow3_re2 (ab_pow3_re2),
.ab_pow3_im2 (ab_pow3_im2),
.ab_pow4_re2 (ab_pow4_re2),
.ab_pow4_im2 (ab_pow4_im2),
.ab_pow5_re2 (ab_pow5_re2),
.ab_pow5_im2 (ab_pow5_im2),
.ab_pow6_re2 (ab_pow6_re2),
.ab_pow6_im2 (ab_pow6_im2),
.ab_pow7_re2 (ab_pow7_re2),
.ab_pow7_im2 (ab_pow7_im2),
.b_pow8_re2 (b_pow8_re2),
.b_pow8_im2 (b_pow8_im2),
.a_re3 (a_re3),
.a_im3 (a_im3),
//.b_re3 (b_re3),
//.b_im3 (b_im3),
.ab_re3 (ab_re3),
.ab_im3 (ab_im3),
.abb_re3 (abb_re3),
.abb_im3 (abb_im3),
.ab_pow3_re3 (ab_pow3_re3),
.ab_pow3_im3 (ab_pow3_im3),
.ab_pow4_re3 (ab_pow4_re3),
.ab_pow4_im3 (ab_pow4_im3),
.ab_pow5_re3 (ab_pow5_re3),
.ab_pow5_im3 (ab_pow5_im3),
.ab_pow6_re3 (ab_pow6_re3),
.ab_pow6_im3 (ab_pow6_im3),
.ab_pow7_re3 (ab_pow7_re3),
.ab_pow7_im3 (ab_pow7_im3),
.b_pow8_re3 (b_pow8_re3),
.b_pow8_im3 (b_pow8_im3),
.a_re4 (a_re4),
.a_im4 (a_im4),
//.b_re4 (b_re4),
//.b_im4 (b_im4),
.ab_re4 (ab_re4),
.ab_im4 (ab_im4),
.abb_re4 (abb_re4),
.abb_im4 (abb_im4),
.ab_pow3_re4 (ab_pow3_re4),
.ab_pow3_im4 (ab_pow3_im4),
.ab_pow4_re4 (ab_pow4_re4),
.ab_pow4_im4 (ab_pow4_im4),
.ab_pow5_re4 (ab_pow5_re4),
.ab_pow5_im4 (ab_pow5_im4),
.ab_pow6_re4 (ab_pow6_re4),
.ab_pow6_im4 (ab_pow6_im4),
.ab_pow7_re4 (ab_pow7_re4),
.ab_pow7_im4 (ab_pow7_im4),
.b_pow8_re4 (b_pow8_re4),
.b_pow8_im4 (b_pow8_im4),
.a_re5 (a_re5),
.a_im5 (a_im5),
//.b_re5 (b_re5),
//.b_im5 (b_im5),
.ab_re5 (ab_re5),
.ab_im5 (ab_im5),
.abb_re5 (abb_re5),
.abb_im5 (abb_im5),
.ab_pow3_re5 (ab_pow3_re5),
.ab_pow3_im5 (ab_pow3_im5),
.ab_pow4_re5 (ab_pow4_re5),
.ab_pow4_im5 (ab_pow4_im5),
.ab_pow5_re5 (ab_pow5_re5),
.ab_pow5_im5 (ab_pow5_im5),
.ab_pow6_re5 (ab_pow6_re5),
.ab_pow6_im5 (ab_pow6_im5),
.ab_pow7_re5 (ab_pow7_re5),
.ab_pow7_im5 (ab_pow7_im5),
.b_pow8_re5 (b_pow8_re5),
.b_pow8_im5 (b_pow8_im5),
.dout_p0 (dout_ref_p[0] ),
.dout_p1 (dout_ref_p[1] ),
.dout_p2 (dout_ref_p[2] ),
.dout_p3 (dout_ref_p[3] ),
.dout_p4 (dout_ref_p[4] ),
.dout_p5 (dout_ref_p[5] ),
.dout_p6 (dout_ref_p[6] ),
.dout_p7 (dout_ref_p[7] ),
.vldo (vldo_ref )
);
integer signed In_fid[0:3];
integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
@ -585,6 +764,9 @@ always @(posedge clk) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(In_fid[i]);
// end
end
end
@ -593,6 +775,9 @@ always @(posedge clk) begin
for (int i = 0; i < 8; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(dout_fid[i]);
// end
end
end
endmodule

24
sim/z_dsp/Makefile
View File

@ -1,24 +0,0 @@
ifdef seed
vcs_run_opts += +ntb_random_seed=${seed}
else
vcs_run_opts += +ntb_random_seed_automatic
endif
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

17
sim/z_dsp/files.f
View File

@ -1,17 +0,0 @@
../../rtl/z_dsp/z_dsp.sv
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/rate_adapter.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/syncer.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v
tb_z_dsp.v

312
sim/z_dsp/tb_z_dsp.v
View File

@ -1,312 +0,0 @@
`timescale 1 ns/1 ns
module TB();
reg [1 :0] source_mode;
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
$fsdbDumpMDA();
// $srandom(417492050);
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
end
reg rstn;
reg [15:0] din_rect;
reg [ 5:0] vldi_coef;
reg vldi_data;
parameter CYCLE = 20;
reg clk;
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
reg signed [31:0] a_re [5:0];
reg signed [31:0] a_im [5:0];
reg signed [31:0] b_re [5:0];
reg signed [31:0] b_im [5:0];
initial begin
rstn = 0;
vldi_data <= 0;
vldi_coef <= 0;
din_rect = 16'd0;
a_re[3] <= 0;
a_im[3] <= 0;
b_re[3] <= 0;
b_im[3] <= 0;
a_re[4] <= 0;
a_im[4] <= 0;
b_re[4] <= 0;
b_im[4] <= 0;
a_re[5] <= 0;
a_im[5] <= 0;
b_re[5] <= 0;
b_im[5] <= 0;
repeat(3) @(posedge clk);
vldi_coef[0] <= 1;
rstn = 1;
a_re[0] <= 55007237;
a_im[0] <= 0;
b_re[0] <= 2143083068;
b_im[0] <= 0;
@(posedge clk);
vldi_coef[0] <= 0;
a_re[0] <= 0;
a_im[0] <= 0;
b_re[0] <= 0;
b_im[0] <= 0;
repeat(8) @(posedge clk);
vldi_coef[1] <= 1;
rstn = 1;
a_re[1] <= 32690030;
a_im[1] <= 0;
b_re[1] <= 2145807236;
b_im[1] <= 0;
@(posedge clk);
vldi_coef[1] <= 0;
a_re[1] <= 0;
a_im[1] <= 0;
b_re[1] <= 0;
b_im[1] <= 0;
repeat(8) @(posedge clk);
vldi_coef[2] <= 1;
rstn = 1;
a_re[2] <= 429516;
a_im[2] <= 0;
b_re[2] <= 2146812530;
b_im[2] <= 0;
@(posedge clk);
vldi_coef[2] <= 0;
a_re[2] <= 0;
a_im[2] <= 0;
b_re[2] <= 0;
b_im[2] <= 0;
repeat(108) @(posedge clk);
vldi_data <= 1;
// repeat(10000) @(posedge clk);
// vldi_data <= 0;
end
reg [21:0] cnt;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
reg vldi_data_r1;
always@(posedge clk or negedge rstn)
if(!rstn)
vldi_data_r1 <= 1'b0;
else
begin
vldi_data_r1 <= vldi_data;
end
always@(posedge clk or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(vldi_data)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
reg signed [15:0] random_in [0:3];
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
else if (vldi_data) begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= $urandom % 30000;
end
end
else begin
for (int i = 0; i < 4; i = i + 1) begin
random_in[i] <= 16'd0;
end
end
end
integer file[3:0];
reg [15:0] data[3:0];
integer status[3:0];
reg [15:0] reg_array[3:0];
initial begin
if(source_mode == 3) begin
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
for (int i = 0; i < 4; i = i + 1) begin
file[i] = $fopen(filenames[i], "r");
if (file[i] == 0) begin
$display("Failed to open file: %s", filenames[i]);
$finish;
end
end
end
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 4; i = i + 1) begin
reg_array[i] <= 16'd0;
end
end else if(vldi_data && source_mode == 3) begin
for (int i = 0; i < 4; i = i + 1) begin
status[i] = $fscanf(file[i], "%d\n", data[i]);
if (status[i] == 1 ) begin
reg_array[i] <= data[i];
end
else begin
reg_array[i] <= 16'd0;
vldi_data <= 0;
end
end
end
end
reg signed [15:0] iir_in[3:0];
always @(*)
case(source_mode)
2'b01 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = din_rect;
end
end
2'b10 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = random_in[i];
end
end
2'b11 : begin
for (int i = 0; i < 4; i = i + 1) begin
iir_in[i] = reg_array[i];
end
end
endcase
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
wire vldo;
assign tc_bypass = 1'b0;
reg en;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
en <= 1;
end
else begin
en <= ~en;
end
end
wire signed [15:0] dout_p[7:0];
z_dsp inst_z_dsp(
.rstn (rstn ),
.clk (clk ),
.en (en ),
// .tc_bypass (tc_bypass ),
.vldi_coef (vldi_coef ),
.vldi_data (vldi_data_r1 ),
// .intp_mode (intp_mode ),
// .dac_mode_sel (dac_mode_sel ),
.din0 (iir_in[0] ),
.din1 (iir_in[1] ),
.din2 (iir_in[2] ),
.din3 (iir_in[3] ),
.a0_re (a_re[0] ),
.a0_im (a_im[0] ),
.b0_re (b_re[0] ),
.b0_im (b_im[0] ),
.a1_re (a_re[1] ),
.a1_im (a_im[1] ),
.b1_re (b_re[1] ),
.b1_im (b_im[1] ),
.a2_re (a_re[2] ),
.a2_im (a_im[2] ),
.b2_re (b_re[2] ),
.b2_im (b_im[2] ),
.a3_re (a_re[3] ),
.a3_im (a_im[3] ),
.b3_re (b_re[3] ),
.b3_im (b_im[3] ),
.a4_re (a_re[4] ),
.a4_im (a_im[4] ),
.b4_re (b_re[4] ),
.b4_im (b_im[4] ),
.a5_re (a_re[5] ),
.a5_im (a_im[5] ),
.b5_re (b_re[5] ),
.b5_im (b_im[5] ),
.dout0 (dout_p[0] ),
.dout1 (dout_p[1] ),
.dout2 (dout_p[2] ),
.dout3 (dout_p[3] ),
.vldo ( vldo )
);
integer signed In_fid[0:3];
integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
initial begin
#0;
for (int i = 0; i < 4; i = i + 1) begin
In_fid[i] = $fopen(filenames_in[i]);
end
for (int i = 0; i < 4; i = i + 1) begin
dout_fid[i] = $fopen(filenames_dout[i]);
end
end
always @(posedge clk) begin
if (vldi_data_r1) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end
end
end
always @(posedge clk) begin
if (vldo) begin
for (int i = 0; i < 4; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end
end
end
endmodule