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thfu:EZQ2p5
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12 Commits
52efa3a769 ... cdea3f4d6a

Author SHA1 Message Date
thfu cdea3f4d6a 后端报warning，修改了parameter的位置； 
整理了文件夹；
修改z_dsp.m用于扫描线路和波形

删除了Z芯片的SRAM文件夹；
修改z_dsp.m用于扫描线路和波形，diff_plot_py.m配合做出修改.
 2025-03-11 19:54:48 +08:00
thfu 270d149d1f v04-using DW_iir_dc_m.v;TB don't use ca_wave 2025-03-11 19:54:48 +08:00
thfu 79a0eae046 四路输出，删除原八路输出； 
v04-MeanIntp_8 with FixRound;Modify the directory structure
 2025-03-11 19:52:54 +08:00
thfu 22ceafb511 z芯片在环验证 
v04-delete unnecessary .m files

v04-spi ram delete unnecessary ports and add related .m

v04-z_chip_top modify and DataShow.m comparing case
 2025-03-11 19:51:46 +08:00
thfu 5433610d48 输出8路转4路后和原来的8路进行比较； 
.m输出二进制数，方便配寄存器；
将z_dsp综合成网表用于z芯片的在环验证

v04-script add hex output

v04-z_dsp's netlist used to  z_chip_top
 2025-03-11 19:48:56 +08:00
thfu 596b32273b 八倍内插模块的使能改为时钟二分频； 
八路输出转为四路输出；
.m文件计算输入加滤波结果

v04-add valid output port and convert from 8 to 4

Modify the directory structure

Modify the directory structure 2th

v04-din+IIR_out to compare with verdi

v04-add valid output port and convert from 8 to 4 on FPGA
 2025-03-11 19:44:53 +08:00
thfu 7057a430d1 基于IP核的滤波器，使能二分频 
v04-z_dsp on FPGA
 2025-03-11 19:42:44 +08:00
thfu 9c0a3a7acf 运算结束后进行四舍五入 
v04-round edf
 2025-03-11 19:41:25 +08:00
thfu 685e094c03 v04-synthesis z_dsp 2025-03-11 19:41:24 +08:00
thfu 84f84448df IIR滤波器使用IP核； 
v04-eliminate warning
 2025-03-11 19:40:19 +08:00
thfu e058191d12 Modify enable signal as clk divided by 2 
使能口连时钟二分频；
diff_plot.m使用最短的进行对比

Fit modification of enable signal as clk divided by 2

choose the min length to compare

Enable of clk_div2 tested on FPGA
 2025-03-11 19:38:34 +08:00
unknown 08484e4771 增加了八倍内插模块； 
删除了上传的临时文件，整理了文件结构；
增加了matlab代码与仿真结果对比

delete repeated .v file

delete sim file,there is too many temporary file

only add makefile and filelist in sim

add verification code of matlab

modify relevant .v file and .m file to verify the accuracy of rtl code
 2025-03-11 19:36:24 +08:00
10 changed files with 377 additions and 2002 deletions
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72
script_m/diff_plot_py.m Normal file
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%compare FIL with python script
function diff_plot_py(fs,iir_out, Script_out,title1,title2,a,amp,edge,fileID)
%输入数据长度不等时取其公共部分
N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N);
Script_out = Script_out(1:N);
diff = (iir_out - Script_out)/amp;%求差，并归一化
n = (0:1:N-1)/fs;
%找出关心的数据点
n_edge = find(n>=edge-1e-12);%edge代表下降沿
n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
ne(1) = 1;
window_length = 100e-9*fs;
diff_mean_window = movmean(diff,window_length);
diff_std_window = movstd(diff,window_length);
n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
n_common = max(n_mean_window(end),n_std_window(end));
%原始数据作图
tiledlayout(2,1)
ax1 = nexttile;
plot(n,iir_out,n,Script_out)
legend(title1,title2)
xlabel('t/s')
xlim(a)
grid on
hold on
%差值做图
ax2 = nexttile;
plot(n,diff)
xlabel('t/s')
title('diff')
grid on
hold on
xlim(a)
linkaxes([ax1,ax2],'x');
plot_p = @(x)[
plot(n(x),diff(x),'r*');
text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
];
ne(1) = 1;
% [diff_max,R_mpos] = max(abs(diff));%误差最大值
% plot_p(R_mpos);
if a(2) <= 5e-6
plot_p(n_edge(1));%下降沿
% plot_p(R_mpos);
elseif a(2) == 20e-6
plot_p(n50(1)); %下降沿20ns
plot_p(n1000(1)); %下降沿1us
plot_p(ne(end)); %误差小于万分之一
fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100)));
% fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
% fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
end

305
script_m/z_dsp.m Normal file
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clc;clear;close all
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
%%配置参数
fs_L = 0.75e9; %硬件频率
fs_H = 12e9; %以高频近似理想信号
TargetFrequency = 3e9;
G = 1;
DownSample = 2;
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
route_num = 5;
env_num = 7;
Ideal2Low = fs_H/(fs_L/2);
Ideal2Target = fs_H/TargetFrequency;
%% 添加路径、产生包络、配置S21参数、使用脚本计算
%%添加路径
% addpath(genpath('D:\Work\EnvData'));
% addpath(genpath('D:\Work\EnvData\data-v2'));
% addpath(genpath('D:\Work\TailCorr_20241008_NoGit'));
% addpath('D:\Work\TailCorr\script_m');
cd("D:\Work\EnvData\acz");
obj1 = py.importlib.import_module('acz');
py.importlib.reload(obj1);
cd("D:\Work\TailCorr_20241008_NoGit");
obj2 = py.importlib.import_module('wave_calculation');
py.importlib.reload(obj2);
cd("D:\Work\TailCorr");
%%产生包络
%按点数产生理想方波
% amp_rect = 1.5e4;
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
%
% for i = 1:2
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
% end
%flattop波
A = 1.5e4;
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
[edge(2), length_flattop(2)] = deal(4,30);
[edge(3), length_flattop(3)] = deal(4,50);
[edge(4), length_flattop(4)] = deal(4,1000);
[edge(5), length_flattop(5)] = deal(100,10000);
for i = 1:5
[edge_H(i), length_H(i)] = deal(edge(i)*fs_H/1e9,length_flattop(i)*fs_H/1e9);
wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
end
%acz波
amplitude = 1.5e4;
carrierFreq = 0.000000;
carrierPhase = 0.000000;
dragAlpha = 0.000000;
thf = 0.864;
thi = 0.05;
lam2 = -0.18;
lam3 = 0.04;
length_acz(1) = 30;
length_acz(2) = 50;
for i = 1:2
length_acz_H(i) = int32(length_acz(i)*fs_H/1e9);
wave_pre{i+5} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
end
for i = 1:7
wave_pre{i} = cat(2,wave_pre{i},zeros(1,floor(simulink_time*fs_H))); %校正前的高频信号
wave_preL{i} = wave_pre{i}(1:Ideal2Low:end); %校正前的低频信号
end
%%S21参数
amp_real{1} = [0.025 0.015 0.0002 0.2 0 0];
amp_imag{1} = [0 0 0 0 0 0];
time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
time_imag{1} = [0 -1/300 -1/500 0 0 0];
amp_real{2} = [0.025 0.015 0.0002 0.2 0 0];
amp_imag{2} = [0 0 0 0 0 0];
time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
time_imag{2} = [0 -1/300 -1/500 0 0 0];
amp_real{3} = [0.025 0.009 0.0002 0.2 0 0];
amp_imag{3} = [0 0.012 0 0 0 0];
time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
time_imag{3} = [0 -1/300 -1/500 0 0 0];
amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
amp_imag{4}= [0 0 0 0 0 0];
time_real{4}= [-1/250, -1/2000, -1/1600 -1/20 0 0];
time_imag{4}= [0 -1/15 -1/50 0 0 0];
amp_real{5} = [0.025 0.009 0.0002 0.2 0 0];
amp_imag{5} = [0 0.012 0 0 0 0];
time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
time_imag{5} = [0 -1/15 -1/50 0 0 0];
for i = 1:5
amp_routing{i} = amp_real{1,i} + 1j*amp_imag{1,i};
time_routing{i} = time_real{1,i} + 1j*time_imag{1,i};
tau{i} = -1./time_routing{i};
end
%%python脚本校正结果
convolve_bound = int8(3);
calibration_time = int32(20e3);
cal_method = int8(1);
sampling_rateL = int64(fs_L/2);
sampling_rate = int64(fs_H);
%校正后的高频信号
for j = 1:route_num
for i = 1:env_num
wave_cal = cell(py.wave_calculation.wave_cal(wave_pre{1,i}, amp_real{1,j}, amp_imag{1,j}, time_real{1,j}, time_imag{1,j}, convolve_bound, calibration_time, cal_method, sampling_rate));
wave_revised{j,i} = double(wave_cal{1,1});
wave_calL = cell(py.wave_calculation.wave_cal(wave_preL{1,i}, amp_real{1,j}, amp_imag{1,j}, time_real{1,j}, time_imag{1,j}, convolve_bound, calibration_time, cal_method, sampling_rateL));
wave_revisedL{j,i} = double(wave_calL{1,1});
end
alpha{j} = double(wave_calL{1,2});
beta{j} = double(wave_calL{1,3});
end
% signalAnalyzer(wave_pre{1,1},'SampleRate',fs_H);
%校正后的低频信号
alpha_wideth=32;
beta_width=32;
%定点化系数
for i = 1:route_num
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
end
%% 仿真
for j = 1:route_num
for i = 1:env_num
options=simset('SrcWorkspace','current');
sim('z_dsp',[0,simulink_time]);
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
dout0{j,i} = sim2m("dout0");
dout1{j,i} = sim2m("dout1");
dout2{j,i} = sim2m("dout2");
dout3{j,i} = sim2m("dout3");
N = length(dout0{j,i});
cs_wave{j,i} = zeros(4*N,1);
cs_wave{j,i}(1:4:4*N) = dout0{j,i};
cs_wave{j,i}(2:4:4*N) = dout1{j,i};
cs_wave{j,i}(3:4:4*N) = dout2{j,i};
cs_wave{j,i}(4:4:4*N) = dout3{j,i};
HardwareMeanIntpData{j,i} = cs_wave{j,i};%硬件校正后内插
DownsamplingBy12GData{j,i} = wave_revised{j,i}(1:Ideal2Target:end);
[DownsamplingBy12GDataAlign{j,i},HardwareMeanIntpDataAlign{j,i},Delay(j,i)] = ...
alignsignals(DownsamplingBy12GData{j,i}(1:round(TargetFrequency*20e-6)),HardwareMeanIntpData{j,i}(1:round(TargetFrequency*20e-6)),"Method","xcorr");
end
end
% signalAnalyzer(DownsamplingBy12GDataAlign{1},HardwareMeanIntpDataAlign{1},'SampleRate',3e9);
%% 绘图并保存
close all;
Amp = 1.5e4;
FallingEdge = [
% 150e-9,4050e-9,...%矩形波
30e-9,30e-9,50e-9,1000e-9,10000e-9,...%flattop
30e-9,50e-9%acz
];
name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第一组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第一组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第二组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第二组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第三组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第三组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第四组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第四组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
"第五组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
"第五组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第一组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第一组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第二组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第二组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第三组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第三组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第四组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第四组S21参数_acz_持续时间50ns_下降沿后1us.fig";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
"第五组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
"第五组S21参数_acz_持续时间50ns_下降沿后1us.fig";
];
Delay_mode = mode(Delay,'all');
fileID = fopen('20241223_output.txt', 'w');
if fileID == -1
disp('文件打开失败');
else
end
for j = 1:route_num
for i = 1:env_num
start_time(i) = abs(Delay_mode)/(TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
edge_Align(i) = FallingEdge(i) + start_time(i);
tmp(i) = edge_Align(i) + 10e-9;
a{i} = [start_time(i)-5e-9 tmp(i)];%[1/fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
b{i} = [tmp(i) 20e-6];
fig1 = figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',a{i},Amp,edge_Align(i),fileID);
title(name(i,1),Interpreter="none");
savefig(name(j,i));
fig2 = figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]);
diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',b{i},Amp,edge_Align(i),fileID);
title(name(i,2),Interpreter="none");
savefig(name(j+5,i));
end
end
fclose(fileID);
%% 可视化S21参数
t = 0:1/(1e2):10000;
for i = 1:1:length(amp_routing)
S21_time(:,i) = amp_routing(i)*exp(time_routing(i)*t);
end
figure
plot(t*1e-9,real(sum(S21_time,2)));
grid on
title("s(t)");
% savefig("S21参数");
% signalAnalyzer(real(sum(S21_time,2)),'SampleRate',1e11);%时间是1ns，还得加上采样率
% rmpath(genpath('D:\Work\EnvData'));
% rmpath(genpath('D:\Work\EnvData\data-v2'));
% rmpath(genpath('D:\Work\TailCorr_20241008_NoGit'));
%% 图像可视化
cd("D:\Work\TailCorr\仿真结果\20241101_125M八倍内插至1G_第1组S21参数")
for i = 1:8
close all
open(name(i,1));
open(name(i,2));
pause()
end

172
spi_tx_rx/rx/rx_sram.v
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@ -1,172 +0,0 @@
// Relese History
// Version Date Author Description
// 0.2 2024-06-14 ZYZ
//-----------------------------------------------------------------------------------------------------------------
// Keywords : receive data from spi_master,sent data to PC
// set reset to output Rdata_PC
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module rx_sram(
input clk,
input rstn,
(* mark_debug="true" *) input [31:0] din ,
(* mark_debug="true" *) input din_vld ,
(* mark_debug="true" *) input data_rden_rx,
(* mark_debug="true" *) output [31:0] Rdata_PC
);
parameter width = 32 ;
parameter depth = 65536 ;
//=================================================
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
//=================================================
localparam aw = clog2(depth-1);
//=================================================
//wr&rd address
(* mark_debug="true" *) reg [aw-1:0] cnta ;
(* mark_debug="true" *) reg [aw-1:0] cntb ;
(* mark_debug="true" *) reg ena ;
(* mark_debug="true" *) reg enb ;
(* mark_debug="true" *) wire [31:0] doutb ;
(* mark_debug="true" *) reg [31:0] din_reg;
always @(posedge clk or negedge rstn)
begin
if(!rstn ) begin
din_reg <= 1'b0;
end
else begin
din_reg <= din;
end
end
(* mark_debug="true" *) reg data_rden_rx_reg;
always @(posedge clk or negedge rstn)
begin
if(!rstn) begin
data_rden_rx_reg <= 1'b0 ;
end
else begin
data_rden_rx_reg <= data_rden_rx ;
end
end
//addra addrb
always @(posedge clk or negedge rstn)
begin
if(!rstn) begin
cnta <= 'h0 ;
end
else if(ena) begin
cnta <= cnta + 'b1;
end
else
cnta <= cnta ;
end
always @(posedge clk or negedge rstn)
begin
if(!rstn ) begin
cntb <= 'h0;
end
else if(enb) begin
cntb <= cntb + 'b1;
end
else begin
cntb <= cntb;
end
end
//enable
always @(posedge clk or negedge rstn)
begin
if(!rstn ) begin
ena <= 1'b0;
end
else begin
ena <= din_vld;
end
end
always @(posedge clk or negedge rstn)
begin
if(!rstn) begin
enb <= 1'b0 ;
end
else if(data_rden_rx_reg & (cntb <= cnta - 1'b1))begin
enb <= 1'b1 ;
end
else begin
enb <= 1'b0 ;
end
end
reg [31:0] Rdata_PC_reg;
always @(posedge clk or negedge rstn)
begin
if(!rstn ) begin
Rdata_PC_reg <= 32'b0;
end
else begin
Rdata_PC_reg <= doutb;
end
end
assign Rdata_PC = Rdata_PC_reg;
/*
blk_mem_gen_0 blk_mem_gen_0_inst(
.clka(clk),
.ena(1'b1),
.wea(ena),
.dina(Rdata_reg),
.addra(cnta),
.clkb(clk),
.enb(enb),
.doutb(doutb),
.addrb(cntb)
);
*/
spram_model #(
.width(width),
.depth(depth)
)spram_inst(
.clka(clk),
.ena(~ena),
.dina(din_reg),
.addra(cnta),
.clkb(clk),
.enb(~enb),
.doutb(doutb),
.addrb(cntb)
);
endmodule

219
spi_tx_rx/spi_master/AxiSpi.v
View File

@ -1,219 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/04/03 15:36:03
// Design Name:
// Module Name: AxiSpi
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AxiSpi(
input clk,
input reset,
input WR, // write en
input RD, // read en
//input [7 : 0] Wlength, // д³¤È
//input [7 : 0] Rlength, // Á³¤È
input [31 : 0] WADDR, // дµØÖ·
input [31 : 0] RADDR, // ÁµØÖ·
(* KEEP="TRUE"*) input [31 : 0] DIN,
input WVALID, // дÊý¾ÝµÄvalid
input cmd_s, // Ö¡¸ñʽ¿ØÖÆ×Ö
input [4 : 0] chirpID,
input [31 : 0] Nlen,
(* KEEP="TRUE"*) output WREADY, // ¿ÉÒÔдÊý
(* KEEP="TRUE"*) output RREADY, // ¿ÉÒÔÁÊý
// read data from spi slave, need to send to axi
(* KEEP="TRUE"*) output RVALID,
(* KEEP="TRUE"*) output [31 : 0] RDATA,
// interface to spi slave
input spi_slave_bit,
(* KEEP="TRUE"*) output ss,
(* KEEP="TRUE"*) output spi_clk,
(* KEEP="TRUE"*) output spi_master_bit
);
// ÎÞÂÛÁд¼ÒªÍ¨¹ýдspi slave µÄ·½Ê½£¬Ö»ÊÇдµÄÖ¸Áͬ
//axi_slave_mem axi_slave_mem_u(
// .clk1(sys_clk), // write clk
// .reset(!sys_rst_n),
// .WR(WR1),
// .RD(1'b0),
// .ADDR_WR(ADDR_WR),
// .ADDR_RD(ADDR_RD),
// .DIN(DIN),
// .cmd_s(1'b0),
// .DVALID(DVALID1),
// .DOUT(DOUT1),
// .ValidRange(ValidRange1)
// );
//axi_slave_mem axi_slave_mem_u2( // Á
// .clk1(sys_clk), // write clk
// // .clk2(sys_clk), // read clk
// .reset(!sys_rst_n),
// .WR(WR2),
// .RD(1'b1),
// .ADDR_WR(ADDR_WR2),
// .ADDR_RD(ADDR_WR2),
// .DIN(DIN2),
// .cmd_s(1'b0),
// .DVALID(DVALID2),
// .DOUT(DOUT2),
// .ValidRange(ValidRange2)
//);
reg WR_c; // Á»¹ÊÇдµÄÑ¡Ôñ
always@(posedge clk)
begin
if(reset)
begin
WR_c <= 1'b0;
end
else if(WR_c == 1'b0) // д״̬ÏÂÖ±µ½ÁÖ¸Áîµ½À´ÔÙ·´×ª
begin
if(RD)
WR_c <= 1'b1;
end
else // Á״̬ÏÂÖ±µ½Ð´Ö¸Áîµ½À´ÔÙ·´×ª
begin
if(WR)
WR_c <= 1'b0;
end
end
// ÓÉÓÚWR_cµÄÔ­Òò£¬ËùÓÐÊäÈë¼ÒªºóÑÓÒ»¸öclk²ÅÄܺÍWR_cÔÆë
reg WR_r;
reg RD_r;
reg [31 : 0] WADDR_r;
reg [31 : 0] RADDR_r;
reg [31 : 0] DIN_r;
reg cmd_sr;
always@(posedge clk)
begin
if(reset)
begin
WADDR_r <= 32'b0;
RADDR_r <= 32'b0;
DIN_r <= 32'b0;
cmd_sr <= 1'b0;
WR_r <= 1'b0;
RD_r <= 1'b0;
end
else
begin
WADDR_r <= WADDR;
RADDR_r <= RADDR;
DIN_r <= DIN ;
cmd_sr <= cmd_s;
WR_r <= WR;
RD_r <= RD;
end
end
wire DVALID;
wire [7 : 0] DOUT;
wire ValidRange;
wire [31 : 0] data_spi_32;
wire WR_mem;
assign WR_mem = WR_r || RD_r; // ÎÞÂÛÁ»¹ÊÇд£¬¼ÐèÒªÁд
axi_slave_mem axi_slave_mem_u( // µØÖ·Ö»»á¸øÊ×µØÖ·£¬ºóÃæÐèÒª×Ô¼º²¹ÉÏ£¬»òÕßÏÈ°´Ã¿´ÎÖ»·¢Ò»Ö¡Ð´
.clk1(clk), // write clk
.reset(reset),
.WR(WR_mem), //WR_r
.RD(WR_c),
.ADDR_WR(WADDR_r),
.ADDR_RD(RADDR_r),
.DIN(DIN_r),
.cmd_s(cmd_sr),
.chirpID(chirpID),
.Nlen(Nlen),
.DVALID(DVALID),
.DOUT(DOUT),
.ValidRange(ValidRange),
.data_spi_32(data_spi_32)
);
wire [7 : 0] spi_master_byte;
wire spi_master_valid;
//wire miso;
spi_master spi_master_u(
// control signal
.clk(clk),
.reset(reset),
//// TX(MOSI) signal
.Rx_ready(~ValidRange), // ÐèÒªÁдspiʱÖÃ1
.axi_byte(DOUT),
.axi_valid(DVALID),
.ss(ss), // ƬѡÐźÅ
.spi_master_bit(spi_master_bit),
.spi_clk(spi_clk),
// RX(MISO) signal
.spi_slave_bit(spi_slave_bit),
.spi_master_byte(spi_master_byte),
.spi_master_valid(spi_master_valid)
// SPI Interface
);
spi_master_mem spi_master_mem_u( // ¼ÓÒ»¸öreadyÐźţ¬±íʾ¿ÉÒÔÁд£¨spi´«Êýʱ²»ÄÜÁд£©
.clk(clk),
.reset(reset),
.RD(WR_c), // axi
.ADDR_RD(RADDR_r), // axi
.DIN(spi_master_byte), // spi
.DVALID(spi_master_valid), // spi
.cmd_s(cmd_s),
.chirpID(chirpID),
.Nlen(Nlen),
.data_spi_32(data_spi_32),
.DREADY(~ss),
.DOUT(RDATA),
.DVALID_o(RVALID)
);
reg ss_r1;
reg ss_r2;
always@(negedge clk)
begin
if(reset)
begin
ss_r1 <= 1'b0;
ss_r2 <= 1'b0;
end
else
begin
ss_r1 <= ss;
ss_r2 <= ss_r1;
end
end
assign WREADY = ss_r2 && ss_r1 && ss;
assign RREADY = ~(ss_r2 && ss_r1 && ss);
endmodule

371
spi_tx_rx/spi_master/axi_slave_mem.v
View File

@ -1,371 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/03/25 16:00:22
// Design Name:
// Module Name: axi_slave_mem
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axi_slave_mem(
clk1, // write clk
// clk2, // read clk
reset,
WR,
RD,
ADDR_WR,
ADDR_RD,
DIN,
cmd_s,
chirpID,
Nlen, // ÿһ֡Êý¾ÝµÄ³¤È
DVALID,
DOUT,
ValidRange,
data_spi_32
);
parameter MEM_WORDS = 10000;
input clk1;
input reset;
input WR;
input RD;
input [31:0] ADDR_WR;
input [31:0] ADDR_RD;
input [31:0] DIN;
input cmd_s;
input [4 :0] chirpID;
input [31:0] Nlen;
output DVALID;
output [7:0] DOUT;
output ValidRange;
output [31 : 0] data_spi_32;
reg [32-1:0] Mem_data [MEM_WORDS-1:0];
reg [32-1:0] Mem_addr [MEM_WORDS-1:0];
reg WR_r;
wire WR_begin;
wire WR_end;
reg [32-1:0] addr_cnt;
reg [32-1:0] DIN_r;
reg [32-1:0] ADDR_WR_r;
always @(posedge clk1)
begin
if (reset)
begin
WR_r <= 1'b0;
DIN_r <= 1'b0;
ADDR_WR_r <= 1'b0;
end
else if(RD == 1'b0) // write
begin
WR_r <= WR;
DIN_r <= DIN; // when need to write, just write the data_in in to memory
ADDR_WR_r <= ADDR_WR;
end
else // read
begin
WR_r <= WR;
DIN_r <= DIN; // when need to write, just write the data_in in to memory
ADDR_WR_r <= ADDR_RD;
end
end
assign WR_begin = WR & (~WR_r);
assign WR_end = (~WR) & (WR_r);
always @(posedge clk1)
begin
if (WR_begin)
begin
addr_cnt <= 32'b0;
end
else if(WR_r) // ´æ´¢Êý¾ÝºÍµØÖ·
begin
addr_cnt <= addr_cnt + 1'b1;
Mem_data[addr_cnt] <= DIN_r; // when need to write, just write the data_in in to memory
Mem_addr[addr_cnt] <= ADDR_WR_r;
end
end
wire [31 : 0] Length; //È·¨Ö¡³¤È
//assign Length = (cmd_s == 1'b0) ? 5'd2 : 5'd17;
assign Length = Nlen + 1'b1;
reg [6 : 0] data32_cnt; // 32bit data counter [5 : 0]--> 2·ÖƵ£»[6 : 0]--> 4·ÖƵ
reg [31 : 0] length_cnt; // 32bit data counter
always@(posedge clk1)
begin
if(reset || WR_end)
begin
data32_cnt <= 5'b0;
end
else if(length_cnt == Length)
begin
data32_cnt <= 5'b0;
end
else
begin
data32_cnt <= data32_cnt + 1'b1;
end
end
always@(posedge clk1)
begin
if(reset || WR_end)
begin
length_cnt <= 32'b0;
end
else if(data32_cnt == 7'd127) // 63--> 2·ÖƵ£»127--> 4·ÖƵ
begin
length_cnt <= length_cnt + 1'b1;
end
else if((length_cnt == Length) && (data32_cnt == 5'd0))
begin
length_cnt <= 32'b0;
end
end
reg [31 : 0] length_cnt_r;
always@(posedge clk1)
begin
if(reset || WR_end)
begin
length_cnt_r <= 32'b0;
end
else
begin
length_cnt_r <= length_cnt;
end
end
reg valid_32; // ÿ32bitÔÓ¦Ò»¸övalid
reg valid_32r;
always@(posedge clk1)
begin
if(reset || WR_end || (length_cnt == Length))
begin
valid_32 <= 1'b0;
valid_32r <= 1'b0;
end
else if(data32_cnt == 5'd1)
begin
valid_32 <= 1'b1;
valid_32r <= valid_32;
end
else
begin
valid_32 <= 1'b0;
valid_32r <= valid_32;
end
end
reg [31 : 0] data_spi_32;
reg [31 : 0] data_addr_cnt;
reg [31 : 0] data_addr;
reg [31 : 0] data_mem;
always@(posedge clk1)
begin
if(reset || WR_end || WR_begin)
begin
data_addr_cnt <= 32'b0;
data_spi_32 <= 32'b0;
data_addr <= 32'b0;
data_mem <= 32'b0;
end
else if(RD == 1'b0)
begin
if (data_addr_cnt <= addr_cnt)
begin
if((data32_cnt == 5'd0) && (length_cnt != 1'b1) && (length_cnt != Length))
begin
data_addr_cnt <= data_addr_cnt + 32'b1;
data_addr <= Mem_addr[data_addr_cnt];
data_mem <= Mem_data[data_addr_cnt];
end
if((data32_cnt == 5'd1) && (length_cnt == 1'b0)) // zhentou
begin
// data_spi_32 <= {1'b0, cmd_s,data_addr[24 : 0], 5'b0 };
data_spi_32 <= {1'b0,data_addr[24 : 0], chirpID, 1'b0 };
end
else if((data32_cnt == 5'd1)) // && (length_cnt == Length - 1)
begin
data_spi_32 <= data_mem;
end
end
else
begin
data_addr <= 32'hffff;
data_spi_32 <= 32'hffff;
end
end
else if(RD == 1'b1)
begin
if (data_addr_cnt <= addr_cnt)
begin
if((data32_cnt == 5'd0) && (length_cnt != 1'b1) && (length_cnt != Length))
begin
data_addr_cnt <= data_addr_cnt + 32'b1;
data_addr <= Mem_addr[data_addr_cnt];
end
if((data32_cnt == 5'd1) && (length_cnt == 1'b0)) // zhentou
begin
// data_spi_32 <= {1'b1, cmd_s,data_addr[24 : 0], 5'b0 };
data_spi_32 <= {1'b1,data_addr[24 : 0], chirpID, 1'b0 };
end
else if((data32_cnt == 5'd1)) // && (length_cnt == Length - 1)
begin
data_spi_32 <= 32'b0;
end
end
else
begin
data_addr <= 32'hffff;
data_spi_32 <= 32'hffff;
end
end
end
reg ss_wr;
always@(posedge clk1)
begin
if(reset || WR_begin || (data_addr_cnt > addr_cnt)) // ÔÚдʱ²»ÔÊÐí´«Êý
begin
ss_wr <= 1'b1;
end
else if ((WR_end))
begin
ss_wr <= 1'b0;
end
end
reg ss_dr;
always@(posedge clk1)
begin
if(length_cnt_r == Length) // ÿ´«ÍêÒ»Ö¡£¬ssÀ­µÍÒ»¸öclk
begin
ss_dr <= 1'b1;
end
else
begin
ss_dr <= 1'b0;
end
end
reg ss_wr1;
reg ss_wr2;
always@(posedge clk1)
begin
if(reset || (data_addr_cnt > addr_cnt))
begin
ss_wr1 <= 1'b1;
ss_wr2 <= 1'b1;
end
else
begin
ss_wr1 <= ss_wr;
ss_wr2 <= ss_wr1;
end
end
wire ss_r;
assign ss_r = ss_wr || ss_dr;
wire ValidRange_r;
assign ValidRange_r = ss_wr2 || ss_dr;
reg ss_r1;
reg ss_r2;
always@(posedge clk1)
begin
if(reset)
begin
ss_r1 <= 1'b1;
ss_r2 <= 1'b1;
end
else
begin
ss_r1 <= ValidRange_r;
ss_r2 <= ss_r1;
end
end
reg [7 : 0] data_spi; // spi data input
reg [6 : 0] data_spi_cnt; // [5 : 0]->2, [6 : 0] ->4
always @(posedge clk1)
if (ValidRange_r | reset)
begin
data_spi_cnt <= 5'b0;
end
else
begin
data_spi_cnt <= data_spi_cnt + 1'b1;
end
reg valid_spi;
always @(posedge clk1)
if (reset)
begin
data_spi <= 8'b0;
// data_spi_cnt <= 4'b0; //mutl_driven
// data_addr_cnt <= 32'b0;
valid_spi <= 1'b0;
end
else if (~ValidRange_r)
begin
if(data_spi_cnt == 4'b1)
begin
valid_spi <= 1'b1;
data_spi <= data_spi_32[31 : 24]; // ´Ó¸ßµ½µÍ·¢ËÍ
end
else if(data_spi_cnt == 7'd33)
begin
valid_spi <= 1'b1;
data_spi <= data_spi_32[23 : 16];
end
else if(data_spi_cnt == 7'd65)
begin
valid_spi <= 1'b1;
data_spi <= data_spi_32[15 : 8];
end
else if(data_spi_cnt == 7'd97)
begin
valid_spi <= 1'b1;
data_spi <= data_spi_32[7 : 0];
end
else
begin
valid_spi <= 1'b0;
end
end
else
begin
valid_spi <= 1'b0;
end
wire valid_spi_o;
assign valid_spi_o = valid_spi && (~ss_r);
assign DVALID = valid_spi_o;
assign DOUT = data_spi ;
assign ValidRange = ss_r2;
endmodule

213
spi_tx_rx/spi_master/spi_master.v
View File

@ -1,213 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/06/24
// Design Name:
// Module Name: spi_master
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies: V0.2 Corresponding to the code of June 19, the spi slave side of the three-state port output
// Fixed a bug where high resistance z was sampled during the first falling edge sampling
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_master
#(parameter SPI_MODE = 3)
(
// control signal
input clk,
input reset,
//// TX(MOSI) signal
input Rx_ready, // ÐèÒªÁдspiʱÖÃ1
input [7 : 0] axi_byte,
input axi_valid,
output ss, // ƬѡÐźÅ
output spi_master_bit,
output spi_clk,
// RX(MISO) signal
// output [7 : 0] RX_byte,
// output RX_valid,
input spi_slave_bit,
output [7 : 0] spi_master_byte,
output spi_master_valid
// SPI Interface
);
wire w_CPOL; // Clock polarity
wire w_CPHA; // Clock phase
assign w_CPOL = (SPI_MODE == 2) | (SPI_MODE == 3);
assign w_CPHA = (SPI_MODE == 1) | (SPI_MODE == 3);
reg Rx_ready_r1;
reg Rx_ready_r2;
always@(posedge clk)
begin
if(reset)
begin
Rx_ready_r1 <= 1'b0;
Rx_ready_r2 <= 1'b0;
end
else
begin
Rx_ready_r1 <= Rx_ready;
Rx_ready_r2 <= Rx_ready_r1;
end
end
reg spi_clk_r;
reg spi_clk_rr;
always@(posedge clk)
begin
if(reset)
begin
spi_clk_r <= 1'b1;
//spi_clk_rr <= 1'b1;
end
else
begin
if(Rx_ready)
begin
spi_clk_r <= spi_clk_r + 1'b1;
end
//spi_clk_rr <= spi_clk_r; // 2·ÖƵ
end
end
always@(posedge clk)
begin
if(reset)
begin
spi_clk_rr <= 1'b1;
end
else
begin
if(spi_clk_r == 1'b0)
spi_clk_rr <= ~spi_clk_rr; //4·ÖƵ
end
end
reg ss_r;
reg ss_rr;
wire rx_edge;
always@(negedge clk) // only ss need to read negedge of clk
begin
if(reset)
begin
ss_r <= 1'b1;
ss_rr <= ss_r;
// rx_edge_r <= 1'b0;
end
else
begin
ss_r <= ~Rx_ready;
ss_rr <= ss_r;
// rx_edge_r <= rx_edge;
end
end
wire tx_edge;
assign rx_edge = (spi_clk_r) & (~spi_clk_rr); // mode 3
assign tx_edge = (~spi_clk_r) & (spi_clk_rr);
reg rx_edge_r;
reg rx_edge_r2;
reg rx_edge_r3;
always@(posedge clk)
begin
if(reset)
begin
rx_edge_r <= 1'b0;
rx_edge_r2 <= 1'b0;
rx_edge_r3 <= 1'b0;
end
else
begin
rx_edge_r <= rx_edge;
rx_edge_r2 <= rx_edge_r;
rx_edge_r3 <= rx_edge_r2;
end
end
reg spi_master_bit_r;
//reg spi_master_bit_rr;
reg [7 : 0] spi_master_byte_r;
reg [2 : 0] bit_cnt1; // 0~7
reg [2 : 0] bit_cnt2; // 0~7
always@(posedge clk)
begin
// if(reset || (~Rx_ready))
// begin
// spi_master_bit_r <= 1'b0;
// spi_master_bit_rr <= 1'b0;
// spi_master_byte_r <= 8'b0;
// bit_cnt1 <= 3'd7;
// bit_cnt2 <= 3'd7;
// end
if(reset)
begin
spi_master_bit_r <= 1'b0;
//spi_master_bit_rr <= 1'b0;
spi_master_byte_r <= 8'b0;
bit_cnt1 <= 3'd7;
bit_cnt2 <= 3'd7;
end
else if (~Rx_ready_r1)
begin
bit_cnt1 <= 3'd7;
bit_cnt2 <= 3'd7;
end
else
begin
if(tx_edge)
begin
spi_master_bit_r <= axi_byte[bit_cnt1]; // spi_master_bit_r Ó¦¸Ã°´spi clk ø²»ÊÇ clk ±ä»¯
bit_cnt1 <= bit_cnt1 - 1'b1;
//spi_master_bit_rr <= spi_master_bit_r;
end
else if(rx_edge_r2)
begin
spi_master_byte_r[bit_cnt2] <= spi_slave_bit;
bit_cnt2 <= bit_cnt2 - 1'b1;
end
end
end
assign spi_clk = spi_clk_rr;
assign ss = ss_rr;
assign spi_master_bit = spi_master_bit_r;
assign spi_master_byte = spi_master_byte_r;
assign spi_master_valid = ((bit_cnt2 == 3'd7) && (rx_edge_r3 == 1'b1)) ? 1'b1 : 1'b0;
/*
reg spi_master_valid_reg;
always@(posedge clk)
begin
if(reset)begin
spi_master_valid_reg <= 1'b0;
end else if(spi_master_valid & Rx_ready)begin
spi_master_valid_reg <= 1'b1;
end else if(~Rx_ready)begin
spi_master_valid_reg <= 1'b0;
end
end
assign miso_valid = spi_master_valid & spi_master_valid_reg;
*/
endmodule

221
spi_tx_rx/spi_master/spi_master_mem.v
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@ -1,221 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2024/03/26 15:21:07
// Design Name:
// Module Name: spi_master_mem
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_master_mem(
clk,
reset,
RD, // axi
ADDR_RD, // axi
DIN, // spi
DVALID, // spi
cmd_s,
chirpID,
Nlen,
data_spi_32,
DREADY,
DOUT,
DVALID_o
);
parameter MEM_WORDS = 1000;
input clk;
input reset;
input RD;
input [31:0] ADDR_RD;
input [7:0] DIN;
input DVALID;
input cmd_s; // Ö¡¸ñʽ¿ØÖÆ×Ö
input [4 :0] chirpID;
input [31:0] Nlen;
input [31 :0] data_spi_32; // ×ÖÍ·
input DREADY;
output [31:0] DOUT;
output DVALID_o;
reg DREADY_r;
always @(posedge clk)
begin
if(reset)
DREADY_r <= 1'b0;
else
DREADY_r <= DREADY;
end
reg [1 : 0] valid_cnt; // valid count,ÒÔ4ΪÖÜÆÚ
reg [5 : 0] valid_cnt16; // valid count, ÒÔ16*4ΪÖÜÆÚ
reg [31 : 0] head_cnt; // Ö¡¼ÆÊý
wire [31 : 0] Length; // Ö¡³¤È
//assign Length = (cmd_s == 1'b0) ? 8'd7 : 8'd67; // 7 = 2*4 -1; 67 = 17 * 4 -1
assign Length = (Nlen + 1) * 4 - 1;
reg [31 : 0] data_32;
always @(posedge clk)
begin
if (reset || (~RD) || (~DREADY_r))
begin
valid_cnt <= 2'b0;
valid_cnt16 <= 4'b0;
data_32 <= 32'b0;
end
else if(RD && DREADY_r && DVALID)
begin
begin
valid_cnt <= valid_cnt + 1'b1;
valid_cnt16 <= valid_cnt16 + 1'b1;
end
if(valid_cnt == 2'b0)
begin
data_32 <= {DIN, data_32[23 : 0]}; // MSB
end
else if(valid_cnt == 2'd1)
begin
data_32 <= {data_32[31 : 24], DIN, data_32[15 : 0]};
end
else if(valid_cnt == 2'd2)
begin
data_32 <= {data_32[31 : 16], DIN, data_32[7 : 0]};
end
else if(valid_cnt == 2'd3)
begin
data_32 <= {data_32[31 : 8], DIN};
end
end
end
always @(posedge clk)
begin
if (reset || (~RD) || (~DREADY_r))
begin
head_cnt <= 32'b0;
end
else if(RD && DREADY_r && DVALID)
begin
if(head_cnt < Length)
begin
head_cnt <= head_cnt + 1'b1;
end
else
begin
head_cnt <= 32'b0;
end
end
end
reg DVALID_r;
always@(posedge clk)
begin
if(reset)
begin
DVALID_r <= 1'b0;
end
else
begin
DVALID_r <= DVALID;
end
end
reg [31 : 0] data_o;
reg valid_o;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// ÓÉÓÚspi masterÄ£¿éµÄ´¦Àí£¬ÕâÀïµÄÊý¾Ý±Èaxi_slave_mem ·¢³öµÄÊý¾ÝÒªÍíһЩ£¬ÐèÒªÑÓʱÒÔÔÆë
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [31 : 0] data_spi_32_r1;
reg [31 : 0] data_spi_32_r2;
reg [31 : 0] data_spi_32_r3;
reg [31 : 0] data_spi_32_r4;
reg [31 : 0] data_spi_32_r5;
reg [31 : 0] data_spi_32_r6;
reg [31 : 0] data_spi_32_r7;
reg [31 : 0] data_spi_32_r8;
always@(posedge clk)
begin
if(reset)
begin
data_spi_32_r1 <= 32'b0;
data_spi_32_r2 <= 32'b0;
data_spi_32_r3 <= 32'b0;
data_spi_32_r4 <= 32'b0;
data_spi_32_r5 <= 32'b0;
data_spi_32_r6 <= 32'b0;
data_spi_32_r7 <= 32'b0;
data_spi_32_r8 <= 32'b0;
end
else
begin
data_spi_32_r1 <= data_spi_32;
data_spi_32_r2 <= data_spi_32_r1;
data_spi_32_r3 <= data_spi_32_r2;
data_spi_32_r4 <= data_spi_32_r3;
data_spi_32_r5 <= data_spi_32_r4;
data_spi_32_r6 <= data_spi_32_r5;
data_spi_32_r7 <= data_spi_32_r6;
data_spi_32_r8 <= data_spi_32_r7;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// spi slave ·µ»ØÊý¾ÝÔÚÖ¡Í·´¦·µ»ØÈ«Á㣬²»ÐèÑÓºóÊý¾Ý£¬ÔÚÈ«Áã´¦²ðÈëÖ¡Í·¼´¿É
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk)
begin
if(reset || (~RD) || (~DREADY_r))
begin
data_o <= 32'b0;
valid_o <= 1'b0;
end
begin
if(DVALID_r && (valid_cnt == 2'd0) && (RD) ) //&& DREADY
begin
if(head_cnt == 32'd4) // ÿ֡ǰ4¸ö×Ö½ÚÊÇÖ¡Í·
begin
data_o <= data_spi_32_r8;
valid_o <= 1'b1;
end
else
begin
data_o <= data_32;
valid_o <= 1'b1;
end
end
else
begin
valid_o <= 1'b0;
end
end
end
assign DOUT = data_o;
assign DVALID_o = valid_o;
endmodule

69
spi_tx_rx/spram_model_0.v
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@ -1,69 +0,0 @@
module spram_model #(
parameter width = 32
,parameter depth = 256
)(
clka,
ena,
dina,
addra,
clkb,
enb,
doutb,
addrb
);
//=================================================
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
//=================================================
localparam aw = clog2(depth-1);
//=================================================
input clka;
input ena;
input [width-1:0] dina;
input [aw-1:0] addra;
input clkb;
input enb;
output [width-1:0] doutb;
input [aw-1:0] addrb;
//================================================
wire clka;
wire ena;
wire [width-1:0] dina;
wire [aw-1:0] addra;
wire clkb;
wire enb;
reg [width-1:0] doutb;
wire [aw-1:0] addrb;
//================================================
reg [width-1:0] mem[0:depth-1];
always@(posedge clka)begin
if(!ena)begin
mem[addra] <=dina;
end
end
always@(posedge clkb)begin
if(!enb)begin
doutb <=mem[addrb];
end
else begin
doutb <=0;
end
end
endmodule

486
spi_tx_rx/top/sram_z_top.v
View File

@ -1,486 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : spi_to_sram_v1.2.v
// Department :
// Author : ZYZ
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-30 ZYZ
//-----------------------------------------------------------------------------------------------------------------
// Keywords : (1) connect rx_sram , tx_sram , spi-master ,digital_top successfully,the
// verilog files of the digital_top is marked 2024.5.17
// (2) when reading data,tx_sram still need to complete the data
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
`include "../../rtl/define/chip_define.v"
module sram_z_top(
input clk
,input por_rstn
,input async_rstn // hardware Reset, active low
//sync
,input sync_in // Chip synchronization signal input, high pulse valid
,output sync_out // Chip synchronization signal output, high pulse valid
,input [1 :0] ch0_feedback // Ch0 Feedback signals from the readout chip
`ifdef CHANNEL_IS_FOUR
,input [1 :0] ch1_feedback // Ch1 Feedback signals from the readout chip
,input [1 :0] ch2_feedback // Ch2 Feedback signals from the readout chip
,input [1 :0] ch3_feedback // Ch3 Feedback signals from the readout chip
`endif
,input [4 :0] cfgid // During power-on initialization, the IO configuration
// values are read as the chip ID number
//irq
,output irq
//tx_sram port
,input [31 :0] din
,input [15 :0] data_length
,output data_done_all
,output data_out_per
,input ch0_dac_Cal_end
,input ch0_dc_Cal_end
//digital_top port
,output oen
//rx_sram port
,input data_rden_rx
,output [31:0] Rdata_PC
//------------------------------Ch0 DSP data out----------------------------------------------------
,output [15 :0] ch0_z_dsp_dout0
,output [15 :0] ch0_z_dsp_dout1
,output [15 :0] ch0_z_dsp_dout2
,output [15 :0] ch0_z_dsp_dout3
,output ch0_z_DEM_MSB_vld
);
//tx_sram signal
wire [31:0] Nlen;
wire [4 :0] chip_ID;
wire [24:0] address;
wire [31:0] data_out_rx;
wire wr_en;
wire rd_en;
wire RREADY;
wire WREADY;
//axi-spi signal
wire spi_master_bit;
wire spi_clk;
wire ss;
wire spi_slave_bit;
//rx_sram signal
wire [31:0] RDATA;
wire RVALID;
wire [14 :0] ch0_z_DEM_MSB_OUT0;
wire [14 :0] ch0_z_DEM_MSB_OUT1;
wire [14 :0] ch0_z_DEM_MSB_OUT2;
wire [14 :0] ch0_z_DEM_MSB_OUT3;
wire [6 :0] ch0_z_DEM_ISB_OUT0;
wire [6 :0] ch0_z_DEM_ISB_OUT1;
wire [6 :0] ch0_z_DEM_ISB_OUT2;
wire [6 :0] ch0_z_DEM_ISB_OUT3;
wire [8 :0] ch0_z_DEM_LSB_OUT0;
wire [8 :0] ch0_z_DEM_LSB_OUT1;
wire [8 :0] ch0_z_DEM_LSB_OUT2;
wire [8 :0] ch0_z_DEM_LSB_OUT3;
tx_sram inst_tx_sram(
.clk(clk),
.rstn(por_rstn),
//input
.dina(din),
.data_length (data_length),
.WREADY (WREADY),
.RREADY (RREADY),
//output
.Nlen (Nlen),
.chip_ID (chip_ID),
.address (address),
.data_out (data_out_rx),
.wr_en (wr_en),
.rd_en (rd_en),
.data_done_all (data_done_all),
.data_out_per (data_out_per)
);
AxiSpi inst_AxiSpi(
.clk (clk ),
.reset (!por_rstn ),
.WR (wr_en ),
.RD (rd_en ),
//input
.WADDR ({7'b0,address}),
.RADDR ({7'b0,address}),
.DIN (data_out_rx ),
.WVALID ( ),
.cmd_s ( ),
.chirpID (chip_ID ),
.Nlen (Nlen ),
//output
.WREADY (WREADY ),
.RREADY (RREADY ),
// read data from spi slave, need to send to axi
.RVALID (RVALID ),
.RDATA (RDATA ),
// interface to spi slave
.spi_slave_bit (spi_slave_bit ), //miso
.ss (ss ), //ss
.spi_clk (spi_clk ), //2 or 4
.spi_master_bit (spi_master_bit) //mosi
);
rx_sram inst_rx_sram(
.clk (clk),
.rstn (por_rstn),
.din (RDATA),
.din_vld (RVALID),
.data_rden_rx (data_rden_rx),
.Rdata_PC (Rdata_PC)
);
z_chip_top inst_chip_top (
//+++++++++++++++++++++++++++++++++++++++++++++//
// PAD Strat //
//+++++++++++++++++++++++++++++++++++++++++++++//
.PI_async_rstn (async_rstn )// hardware Reset, active low
//sync
,.PI_sync_in (sync_in ) // Chip synchronization signal input, high pulse valid
,.PO_sync_out (sync_out ) // Chip synchronization signal output, high pulse valid
//Feedback signal
,.PI_ch0_feedback (ch0_feedback)// Ch0 Feedback signals from the readout chip
`ifdef CHANNEL_IS_FOUR
,.PI_ch1_feedback (ch1_feedback) // Ch1 Feedback signals from the readout chip
,.PI_ch2_feedback (ch2_feedback) // Ch2 Feedback signals from the readout chip
,.PI_ch3_feedback (ch3_feedback) // Ch3 Feedback signals from the readout chip
`endif
//config chip id
,.PI_cfgid (cfgid)// During power-on initialization, the IO configuration
// values are read as the chip ID number
//spi port
,.PI_sclk (spi_clk ) // Spi Clock
,.PI_csn (ss ) // Spi Chip Select active low
,.PI_mosi (spi_master_bit) // Spi Mosi
,.PO_miso (spi_slave_bit ) // Spi Miso
//irq
,.PO_irq (irq )// Interrupt signal in the chip, high level active
//Attenuator Control Bit\u200c
,.PO_ch0_att ( ) // CH0 Attenuator Control Bit
`ifdef CHANNEL_IS_FOUR
,.PO_ch1_att ( ) // CH1 Attenuator Control Bit
,.PO_ch2_att ( ) // CH2 Attenuator Control Bit
,.PO_ch3_att ( ) // CH3 Attenuator Control Bit
`endif
//+++++++++++++++++++++++++++++++++++++++++++++//
// PAD End //
//+++++++++++++++++++++++++++++++++++++++++++++//
//+++++++++++++++++++++++++++++++++++++++++++++//
// PIN Strat //
//+++++++++++++++++++++++++++++++++++++++++++++//
//-------------------------clcok pin from pll-------------------------------------------------
,.clk (clk )// System Main Clock
//-------------------------Power on reset pin from por----------------------------------------
,.por_rstn (por_rstn )// Power on reset, active low
//------------------------------digital IO----------------------------------------------------
//------------------------------PLL cfg pin----------------------------------------------------
,.ref_sel ( )// Clock source selection for a frequency divider;
// 1'b0:External clock source
// 1'b1:internal phase-locked loop clock source
,.ref_en ( )// Input reference clock enable
// 1'b0:enable,1'b1:disable
,.ref_s2d_en ( )// Referenced clock differential to single-ended conversion enable
// 1'b0:enable,1'b1:disable
,.p_cnt ( ) // P counter
,.pfd_delay ( ) // PFD Dead Zone
,.pfd_dff_Set ( ) // Setting the PFD register,active high
,.pfd_dff_4and ( ) // PFD output polarity
,.spd_div ( ) // SPD Frequency Divider
,.spd_pulse_width ( ) // Pulse Width of SPD
,.spd_pulse_sw ( ) // Pulse sw of SPD
,.cpc_sel ( ) // current source selection
,.swcp_i ( ) // PTAT current switch
,.sw_ptat_r ( ) // PTAT current adjustment
//,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current
//,output sw_fll_delay // PLL Dead Zone
,.pfd_sel ( ) // PFD Loop selection
,.spd_sel ( ) // SPD Loop selection
,.dtd_en ( ) //
//,output fll_sel // FLL Loop selection
,.vco_tc ( ) // VCO temperature compensation
,.vco_tcr ( ) // VCO temperature compensation resistor
,.vco_gain_adj ( ) // VCO gain adjustment
,.vco_gain_adj_r ( ) // VCO gain adjustment resistor
,.vco_cur_adj ( ) // VCO current adjustment
,.vco_buff_en ( ) // VCO buff enable,active high
,.vco_en ( ) // VCO enable,active high
,.vco_fb_adj ( ) // VCO frequency band adjustment
// ,.pll_dpwr_adj ( ) // PLL frequency division output power adjustment
// ,output [7 :0] vco_fb_adj // VCO frequency band adjustment
,.tc_sel ( ) // Temperature compensation options
,.pata_res_en ( ) // PATAMOS resistance enable
,.pata_s_dc_sel ( ) // PATA slope DC selection
,.pata_res_vdc300 ( ) // PATAMOS resistance bias
,.pata_res_vdc500 ( ) // PATAMOS resistance bias
,.pata_res_vdc800 ( ) // PATAMOS resistance bias
,.sw_var_temp_en ( ) // Temperature-compensated automatic switch
,.sw_var_temp ( ) // Temperature-compensated manual switch
,.afc_en ( ) // AFC enable
,.afc_shutdown ( ) // AFC module shutdown signal
,.afc_reset ( ) // AFC reset
//,output [0 :0] afc_det_speed // AFC detection speed
//,output [0 :0] flag_out_sel // Read and choose the signs
,.afc_clk_sel ( ) // AFC clock frequency choose
,.afc_pres ( ) // AFC comparator accuracy adjustment
,.afc_fb_cnt ( ) // AFC frequency band adjustment function counter
,.afc_fb_target ( ) // AFC frequency band adjustment function target number of cycles
,.afc_ld_cnt ( ) // Adjust the counting time of the AFC lock detection // feature counter
,.afc_ld_target ( )// AFC Lock Detection Function Target Cycle Count
,.div_rstn_sel ( ) // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
,.test_clk_sel ( ) // test clk select, 4'b0001:DIV1 clk, 4'b0010:DIV2 clk, 4'b0100:DIV4 clk, 4'b1000:DIV8 clk
,.test_clk_oen ( ) // test clk output enable, 1'b0:disenable, 1'b1:enable
,.dig_clk_sel ( ) // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
,.clkrx_pdn ( ) // CLock Rx Power Down
,.sync_clr ( ) // PLL div sync clr,low active
,.pll_rstn ( ) // PLL reset,active low
,.pll_lock ( ) // PLL LOCK
,.afc_end_flag ( )
,.clk_resv ( )
//------------------------------Ch0 DAC cfg pin----------------------------------------------------
,.ch0_dac_addr ()
,.ch0_dac_dw ()
,.ch0_dac_ref ()
,.ch0_dac_Prbs_rst0 ()
,.ch0_dac_Prbs_set0 ()
,.ch0_dac_Prbs_rst1 ()
,.ch0_dac_Prbs_set1 ()
,.ch0_dac_Cal_sig ()
,.ch0_dac_Cal_rstn ()
,.ch0_dac_Cal_div_rstn()
,.ch0_dac_Cal_end (ch0_dac_Cal_end)
,.ch0_dac_Ctrlp ()
,.ch0_dac_Ctrln ()
//------------------------------Ch0 DC Bias cfg pin----------------------------------------------------
,.ch0_dc_addr ()
,.ch0_dc_dw ()
,.ch0_dc_ref ()
,.ch0_dc_Cal_sig ()
,.ch0_dc_Cal_rstn ()
,.ch0_dc_Cal_div_rstn ()
,.ch0_dc_Cal_end (ch0_dc_Cal_end)
,.ch0_dc_clkout ()
`ifdef CHANNEL_IS_FOUR
//------------------------------Ch1 DAC cfg pin----------------------------------------------------
,.ch1_dac_addr ()
,.ch1_dac_dw ()
,.ch1_dac_ref ()
,.ch1_dac_Prbs_rst0 ()
,.ch1_dac_Prbs_set0 ()
,.ch1_dac_Prbs_rst1 ()
,.ch1_dac_Prbs_set1 ()
,.ch1_dac_Cal_sig ()
,.ch1_dac_Cal_rstn ()
,.ch1_dac_Cal_div_rstn()
,.ch1_dac_Cal_end ()
,.ch1_dac_Ctrlp ()
,.ch1_dac_Ctrln ()
//------------------------------Ch1 DC Bias cfg pin----------------------------------------------------
,.ch1_dc_addr ()
,.ch1_dc_dw ()
,.ch1_dc_ref ()
,.ch1_dc_Cal_sig ()
,.ch1_dc_Cal_rstn ()
,.ch1_dc_Cal_div_rstn ()
,.ch1_dc_Cal_end ()
,.ch1_dc_clkout ()
//------------------------------Ch2 DAC cfg pin----------------------------------------------------
,.ch2_dac_addr ()
,.ch2_dac_dw ()
,.ch2_dac_ref ()
,.ch2_dac_Prbs_rst0 ()
,.ch2_dac_Prbs_set0 ()
,.ch2_dac_Prbs_rst1 ()
,.ch2_dac_Prbs_set1 ()
,.ch2_dac_Cal_sig ()
,.ch2_dac_Cal_rstn ()
,.ch2_dac_Cal_div_rstn()
,.ch2_dac_Cal_end ()
,.ch2_dac_Ctrlp ()
,.ch2_dac_Ctrln ()
//------------------------------Ch2 DC Bias cfg pin----------------------------------------------------
,.ch2_dc_addr ()
,.ch2_dc_dw ()
,.ch2_dc_ref ()
,.ch2_dc_Cal_sig ()
,.ch2_dc_Cal_rstn ()
,.ch2_dc_Cal_div_rstn ()
,.ch2_dc_Cal_end ()
,.ch2_dc_clkout ()
//------------------------------Ch3 DAC cfg pin----------------------------------------------------
,.ch3_dac_addr ()
,.ch3_dac_dw ()
,.ch3_dac_ref ()
,.ch3_dac_Prbs_rst0 ()
,.ch3_dac_Prbs_set0 ()
,.ch3_dac_Prbs_rst1 ()
,.ch3_dac_Prbs_set1 ()
,.ch3_dac_Cal_sig ()
,.ch3_dac_Cal_rstn ()
,.ch3_dac_Cal_div_rstn()
,.ch3_dac_Cal_end ()
,.ch3_dac_Ctrlp ()
,.ch3_dac_Ctrln ()
//------------------------------Ch3 DC Bias cfg pin----------------------------------------------------
,.ch3_dc_addr ()
,.ch3_dc_dw ()
,.ch3_dc_ref ()
,.ch3_dc_Cal_sig ()
,.ch3_dc_Cal_rstn ()
,.ch3_dc_Cal_div_rstn ()
,.ch3_dc_Cal_end ()
,.ch3_dc_clkout ()
`endif
`ifdef CHANNEL_Z_ON
//------------------------------Ch0 DSP data out----------------------------------------------------
,.ch0_z_DEM_MSB_OUT0 (ch0_z_DEM_MSB_OUT0)
,.ch0_z_DEM_MSB_OUT1 (ch0_z_DEM_MSB_OUT1)
,.ch0_z_DEM_MSB_OUT2 (ch0_z_DEM_MSB_OUT2)
,.ch0_z_DEM_MSB_OUT3 (ch0_z_DEM_MSB_OUT3)
,.ch0_z_DEM_ISB_OUT0 (ch0_z_DEM_ISB_OUT0)
,.ch0_z_DEM_ISB_OUT1 (ch0_z_DEM_ISB_OUT1)
,.ch0_z_DEM_ISB_OUT2 (ch0_z_DEM_ISB_OUT2)
,.ch0_z_DEM_ISB_OUT3 (ch0_z_DEM_ISB_OUT3)
,.ch0_z_DEM_LSB_OUT0 (ch0_z_DEM_LSB_OUT0)
,.ch0_z_DEM_LSB_OUT1 (ch0_z_DEM_LSB_OUT1)
,.ch0_z_DEM_LSB_OUT2 (ch0_z_DEM_LSB_OUT2)
,.ch0_z_DEM_LSB_OUT3 (ch0_z_DEM_LSB_OUT3)
,.ch0_z_DEM_MSB_vld (ch0_z_DEM_MSB_vld )
,.ch0_dc_bias_o ( )
,.ch0_dc_bias_latch ( )
`endif
`ifdef CHANNEL_IS_FOUR
//------------------------------Ch1 DSP data out----------------------------------------------------
`ifdef CHANNEL_Z_ON
,.ch1_z_DEM_MSB_OUT0 ( )
,.ch1_z_DEM_MSB_OUT1 ( )
,.ch1_z_DEM_MSB_OUT2 ( )
,.ch1_z_DEM_MSB_OUT3 ( )
,.ch1_z_DEM_ISB_OUT0 ( )
,.ch1_z_DEM_ISB_OUT1 ( )
,.ch1_z_DEM_ISB_OUT2 ( )
,.ch1_z_DEM_ISB_OUT3 ( )
,.ch1_z_DEM_LSB_OUT0 ( )
,.ch1_z_DEM_LSB_OUT1 ( )
,.ch1_z_DEM_LSB_OUT2 ( )
,.ch1_z_DEM_LSB_OUT3 ( )
,.ch1_z_DEM_MSB_vld ( )
,.ch1_dc_bias_o ( )
,.ch1_dc_bias_latch ( )
`endif
//------------------------------Ch2 DSP data out----------------------------------------------------
`ifdef CHANNEL_Z_ON
,.ch2_z_DEM_MSB_OUT0 ( )
,.ch2_z_DEM_MSB_OUT1 ( )
,.ch2_z_DEM_MSB_OUT2 ( )
,.ch2_z_DEM_MSB_OUT3 ( )
,.ch2_z_DEM_ISB_OUT0 ( )
,.ch2_z_DEM_ISB_OUT1 ( )
,.ch2_z_DEM_ISB_OUT2 ( )
,.ch2_z_DEM_ISB_OUT3 ( )
,.ch2_z_DEM_LSB_OUT0 ( )
,.ch2_z_DEM_LSB_OUT1 ( )
,.ch2_z_DEM_LSB_OUT2 ( )
,.ch2_z_DEM_LSB_OUT3 ( )
,.ch2_z_DEM_MSB_vld ( )
,.ch2_dc_bias_o ( )
,.ch2_dc_bias_latch ( )
`endif
//------------------------------Ch3 DSP data out----------------------------------------------------
`ifdef CHANNEL_Z_ON
,.ch3_z_DEM_MSB_OUT0 ( )
,.ch3_z_DEM_MSB_OUT1 ( )
,.ch3_z_DEM_MSB_OUT2 ( )
,.ch3_z_DEM_MSB_OUT3 ( )
,.ch3_z_DEM_ISB_OUT0 ( )
,.ch3_z_DEM_ISB_OUT1 ( )
,.ch3_z_DEM_ISB_OUT2 ( )
,.ch3_z_DEM_ISB_OUT3 ( )
,.ch3_z_DEM_LSB_OUT0 ( )
,.ch3_z_DEM_LSB_OUT1 ( )
,.ch3_z_DEM_LSB_OUT2 ( )
,.ch3_z_DEM_LSB_OUT3 ( )
,.ch3_z_DEM_MSB_vld ( )
,.ch3_dc_bias_o ( )
,.ch3_dc_bias_latch ( )
`endif
`endif
//+++++++++++++++++++++++++++++++++++++++++++++//
// PIN END //
//+++++++++++++++++++++++++++++++++++++++++++++//
);
thermo2binary_top Ch0_0_thermo2binary_top (
.clk ( clk )
,.DEM_MSB_IN ( ch0_z_DEM_MSB_OUT0 )
,.DEM_ISB_IN ( ch0_z_DEM_ISB_OUT0 )
,.DEM_LSB_IN ( ch0_z_DEM_LSB_OUT0 )
,.DOUT ( ch0_z_dsp_dout0 )
);
thermo2binary_top Ch0_1_thermo2binary_top (
.clk ( clk )
,.DEM_MSB_IN ( ch0_z_DEM_MSB_OUT1 )
,.DEM_ISB_IN ( ch0_z_DEM_ISB_OUT1 )
,.DEM_LSB_IN ( ch0_z_DEM_LSB_OUT1 )
,.DOUT ( ch0_z_dsp_dout1 )
);
thermo2binary_top Ch0_2_thermo2binary_top (
.clk ( clk )
,.DEM_MSB_IN ( ch0_z_DEM_MSB_OUT2 )
,.DEM_ISB_IN ( ch0_z_DEM_ISB_OUT2 )
,.DEM_LSB_IN ( ch0_z_DEM_LSB_OUT2 )
,.DOUT ( ch0_z_dsp_dout2 )
);
thermo2binary_top Ch0_3_thermo2binary_top (
.clk ( clk )
,.DEM_MSB_IN ( ch0_z_DEM_MSB_OUT3 )
,.DEM_ISB_IN ( ch0_z_DEM_ISB_OUT3 )
,.DEM_LSB_IN ( ch0_z_DEM_LSB_OUT3 )
,.DOUT ( ch0_z_dsp_dout3 )
);
endmodule

251
spi_tx_rx/tx/tx_sram.v
View File

@ -1,251 +0,0 @@
// Relese History
// Version Date Author Description
// 0.3 2024-05-29 ZYZ
//-----------------------------------------------------------------------------------------------------------------
// Keywords : connect spi-master
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter :
// cmd[31:0] form:
// form-v0.2 {WR ,RSV ,ID ,ADDR}
// [31] [30] [29:25] [24:0]
//
// form-v0.3 {WR ,ADDR ,ID ,RSV}
// [31] [30:6] [5:1] [0]
//
// form-v0.2 is defined by design , it has len[31:0];
// form-v0.3 is produced by spi interface ,it doesn't have len[31:0];
//
// size : 256K
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module tx_sram(
input clk,
input rstn,
(* mark_debug="true" *)input [31:0] dina,
(* mark_debug="true" *)input [15:0] data_length,
output [31:0] Nlen,
output [4 :0] chip_ID,
output [24:0] address,
output [31:0] data_out,
(* mark_debug="true" *)output wr_en,
(* mark_debug="true" *)output rd_en,
(* mark_debug="true" *)input WREADY,
(* mark_debug="true" *)input RREADY,
output data_done_all,
output data_out_per
);
parameter width = 32 ;
parameter depth = 65536 ;
//=================================================
function integer clog2(input integer depth);
begin
for(clog2=0;depth>0;clog2=clog2+1)
depth =depth>>1;
end
endfunction
//=================================================
localparam aw = clog2(depth-1);
//=================================================
//wr&rd address
(* mark_debug="true" *) reg [aw-1:0]cnta ;
(* mark_debug="true" *) reg [aw-1:0]cntb ;
(* mark_debug="true" *) wire ena ;
(* mark_debug="true" *) wire enb ;
(* mark_debug="true" *) wire full ;
(* mark_debug="true" *) wire [31:0] doutb;
//current len of data ,initial value is 0
(* mark_debug="true" *) reg [31:0]len_current ;
//cmd
(* mark_debug="true" *) reg cmd_s ;
(* mark_debug="true" *) reg [4:0] chip_ID_reg ;
(* mark_debug="true" *)reg [24:0]address_reg ;
always@(posedge clk or negedge rstn)begin
if(!rstn)begin
cmd_s <= 1'b0;
chip_ID_reg <= 5'b0;
address_reg <= 25'b0;
end
else if(cntb == len_current + 2'd1)begin
cmd_s <= doutb[31];
chip_ID_reg <= doutb[5:1];
address_reg <= doutb[30:6];
end
else begin
cmd_s <= cmd_s;
chip_ID_reg <= chip_ID_reg;
address_reg <= address_reg;
end
end
assign chip_ID = chip_ID_reg;
assign address = address_reg;
//len of data_out
(* mark_debug="true" *) reg [31:0]len_reg ;
always@(posedge clk or negedge rstn)begin
if(!rstn)begin
len_reg <= 32'b0;
end
else if(cntb == len_current + 2'd2)begin
len_reg <= doutb ;
end
else begin
len_reg <= len_reg;
end
end
assign Nlen = len_reg;
//data_out
(* mark_debug="true" *) reg [31:0]data_out_reg ;
(* mark_debug="true" *) wire data_out_en ;
always@(posedge clk or negedge rstn)begin
if(!rstn)begin
data_out_reg <= 32'b0;
end
else if(data_out_en)begin
data_out_reg <= doutb ;
end
else begin
data_out_reg <= 32'b0;
end
end
reg data_out_en_r1;
always@(posedge clk or negedge rstn)begin
if(!rstn)begin
data_out_en_r1 <= 1'b0;
end
else begin
data_out_en_r1 <= data_out_en;
end
end
assign data_out = data_out_reg;
assign data_out_en = (cntb >= len_current + 2'd3) & (cntb <= len_current + len_reg + 2'd2);
//signal send to spi_master
assign wr_en = !cmd_s & data_out_en_r1;
assign rd_en = cmd_s & data_out_en_r1;
//signal send to PC
assign data_out_per = (cntb == len_current + 3'd3 ) ? 1'b1 : 1'b0;
assign data_done_all = (cntb == data_length-1'b1 | cnta == data_length - 1'b1) ? 1'b1 : 1'b0;
//the time ready for writing data and updata len_current
reg [2:0] wready_reg;
always @(posedge clk or negedge rstn)
begin
if(!rstn ) begin
wready_reg <= 3'b0;
end
else begin
wready_reg <= {wready_reg[1:0],WREADY};
end
end
assign wready_posedge = wready_reg[1:0] == 2'b01 ? 1'b1 : 1'b0;
//updata len_current and cntb
always@(posedge clk or negedge rstn)begin
if(!rstn)begin
len_current <= 32'b0;
end
else if( wready_posedge & len_reg != 0)begin
len_current <= len_current + len_reg + 2'd2 ;
end
else begin
len_current <= len_current;
end
end
//write address: addra
//read address: addrb
always @(posedge clk or negedge rstn)
begin
if(!rstn) begin
cnta <= 'hffff;
end
else if(ena) begin
cnta <= cnta + 1'b1;
end
else
cnta <= cnta ;
end
always @(posedge clk or negedge rstn)
begin
if(!rstn ) begin
cntb <= 'h0 ;
end
else if(enb) begin
cntb <= cntb + 1'b1;
end
else if(wready_posedge & len_reg != 0) begin
cntb <= cntb - 1'b1 ; // better solution?
end
else begin
cntb <= cntb;
end
end
assign full = (cnta+1'b1 <= data_length )? 1'b0 : 1'b1 ;
assign ena = !full;
assign enb = full & (cntb <= data_length ) & WREADY & (cntb <= len_current + len_reg + 2'd2);
/*
blk_mem_gen_0 blk_mem_gen_0_inst(
.clka(clk),
.ena(1'b1),
.wea(ena),
.dina(dina),
.addra(cnta),
.clkb(clk),
.enb(enb),
.doutb(doutb),
.addrb(cntb)
);
*/
spram_model #(
.width(width),
.depth(depth)
)spram_inst(
.clka(clk),
.ena(~ena),
.dina(dina),
.addra(cnta),
.clkb(clk),
.enb(~enb),
.doutb(doutb),
.addrb(cntb)
);
endmodule