Commit Graph

23 Commits

Author SHA1 Message Date
dada eba7fac84d merge 2025-03-14 17:07:07 +08:00
dada e14d9494b0 merge 2025-03-14 16:49:03 +08:00
futh0403 6e386a2743 合并main分支的部分修改
-尽量避免使用for循环
2025-03-13 22:39:05 +08:00
dada 601600c760 parameterize modules 2025-03-13 18:51:53 +08:00
dada 928978f034 promote precision to about half LSB 2025-03-13 18:51:31 +08:00
dada 73bc72cfc8 data width of multiplier ports has been modified in order to reduce ovreheads 2025-03-13 18:49:19 +08:00
dada 30cc4e3d35 八路并行,一路超前计算,七路进位链
2st
2025-03-13 18:48:39 +08:00
dada 487aa20517 parameterize modules 2025-03-13 11:31:31 +08:00
dada 4a451196fd promote precision to about half LSB 2025-03-13 11:16:26 +08:00
dada 69b80e4575 data width of multiplier ports has been modified in order to reduce ovreheads 2025-03-12 22:30:22 +08:00
dada 3e00afece0 data width of multiplier ports has been modified in order to reduce ovreheads 2025-03-12 22:01:27 +08:00
dada 5fbf171cbe 八路并行的IIR滤波器,只有一路超前计算,其余支路进位链
2st
2025-03-12 14:54:27 +08:00
dada 832408d29b 1st 2025-03-12 14:36:22 +08:00
futh0403 9c8cd6cdfc 与基于IP核的分支合并,保留全八路并行的IIR滤波器;
diff_p.v中的循环展开;
使用syncer.v同步,提高代码可读性
2025-03-12 13:23:25 +08:00
thfu cdea3f4d6a 后端报warning,修改了parameter的位置;
整理了文件夹;
修改z_dsp.m用于扫描线路和波形

删除了Z芯片的SRAM文件夹;
修改z_dsp.m用于扫描线路和波形,diff_plot_py.m配合做出修改.
2025-03-11 19:54:48 +08:00
thfu 270d149d1f v04-using DW_iir_dc_m.v;TB don't use ca_wave 2025-03-11 19:54:48 +08:00
thfu 79a0eae046 四路输出,删除原八路输出;
v04-MeanIntp_8 with FixRound;Modify the directory structure
2025-03-11 19:52:54 +08:00
thfu d126901a8a 将二维数组展开 2025-03-11 17:35:58 +08:00
thfu ad5c6434e2 片上实时产生系数;
增加了z_dsp.sv;
删除了过去插值的相关文件,整理文件夹的结构;
FPGA消耗资源过多,端口使用二维数组;
提高了IIR_Filter_p8.v的可读性,未来需要进一步提高IIR_top.v的可读性,信号的互联是个问题;
2025-03-11 17:31:24 +08:00
thfu 8c6c5bb906 八路并行的IIR滤波器;
未来需要在片上实时生成系数;
需要提高代码可读性
2025-03-11 16:28:33 +08:00
thfu 98f6a41ec9 实现了两路并行的IIR滤波器;增加了将输入分为奇偶两路的模块 2025-03-11 16:28:32 +08:00
unknown bc06605912 .m增加了寻找误差和均方误差均小于万分之一的功能
修改了z_dsp.m的路径
2025-03-11 16:28:32 +08:00
thfu 8fe84d2a79 增加了四舍五入的模块,用于复数乘法器,八倍线性插值模块;
修改了文件夹的结构;
增加了z_dsp.m add和diff_plot_py.m;

对valid信号进行修改;增加了z_dsp.m add和diff_plot_py.m
2025-03-11 16:28:23 +08:00