5 Commits

Author	SHA1	Message	Date
unknown	e757bd72c6	Enable of clk_div2 tested on FPGA	2024-11-07 10:57:58 +08:00
thfu	2fdaaa3611	Fit modification of enable signal as clk divided by 2	2024-11-04 19:07:35 +08:00
thfu	da3157a7d8	Modify enable signal as clk divided by 2	2024-11-04 19:03:02 +08:00
thfu	85b2d97c02	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
unknown	c6ff7dc280	add 8 interpolation	2024-10-08 11:24:32 +08:00