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Author	SHA1	Message	Date
thfu	e058191d12	Modify enable signal as clk divided by 2 ... 使能口连时钟二分频； diff_plot.m使用最短的进行对比 Fit modification of enable signal as clk divided by 2 choose the min length to compare Enable of clk_div2 tested on FPGA	2025-03-11 19:38:34 +08:00
unknown	08484e4771	增加了八倍内插模块； ... 删除了上传的临时文件，整理了文件结构； 增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code	2025-03-11 19:36:24 +08:00
unknown	dcd8166010	init	2024-04-16 10:14:19 +08:00