八路输出转为四路输出；
.m文件计算输入加滤波结果
v04-add valid output port and convert from 8 to 4
Modify the directory structure
Modify the directory structure 2th
v04-din+IIR_out to compare with verdi
v04-add valid output port and convert from 8 to 4 on FPGA
使能口连时钟二分频；
diff_plot.m使用最短的进行对比
Fit modification of enable signal as clk divided by 2
choose the min length to compare
Enable of clk_div2 tested on FPGA
删除了上传的临时文件，整理了文件结构；
增加了matlab代码与仿真结果对比
delete repeated .v file
delete sim file,there is too many temporary file
only add makefile and filelist in sim
add verification code of matlab
modify relevant .v file and .m file to verify the accuracy of rtl code
thfu