 thfu
|
cbf8ab957e
|
v04-using DW_iir_dc_m.v;TB don't use ca_wave
|
2024-11-27 16:35:27 +08:00 |
|
thfu
|
7a9171d964
|
v04-MeanIntp_8 with FixRound;Modify the directory structure
|
2024-11-27 10:06:26 +08:00 |
|
thfu
|
334a19edec
|
v04-z_dsp 4 ports output
|
2024-11-26 20:59:57 +08:00 |
|
thfu
|
cdfd6d716d
|
v04-z_dsp's netlist used to z_chip_top
|
2024-11-23 21:58:54 +08:00 |
|
thfu
|
bcfd586b53
|
v04-Test enable for 8pin and 4pin together
|
2024-11-21 14:50:01 +08:00 |
|
thfu
|
fda936e228
|
Modify the directory structure 2th
|
2024-11-20 20:24:08 +08:00 |
|
thfu
|
b95b0ba2d2
|
Modify the directory structure
|
2024-11-20 20:19:36 +08:00 |
|
thfu
|
038ab149bc
|
v04-add valid output port and convert from 8 to 4
|
2024-11-14 20:35:56 +08:00 |
|
thfu
|
01db8232c2
|
v04-MeanIntp_8.v work with enable
|
2024-11-14 20:32:29 +08:00 |
|
thfu
|
a86850e439
|
v04-z_dsp on FPGA
|
2024-11-12 20:03:17 +08:00 |
|
thfu
|
d6eb195dde
|
v04-enable of clk_div2
|
2024-11-12 17:35:22 +08:00 |
|
thfu
|
e9dbf0564e
|
v04-round edf
|
2024-11-11 17:26:22 +08:00 |
|
thfu
|
8d46d2bbd3
|
v04-round
|
2024-11-11 17:17:15 +08:00 |
|
thfu
|
e2c8c38898
|
v04-synthesis z_dsp
|
2024-11-10 11:14:47 +08:00 |
|
thfu
|
993ed34ee4
|
v04-eliminate warning
|
2024-11-09 17:51:37 +08:00 |
|
thfu
|
8fa46ded3a
|
v04-IIR based on IP core
|
2024-11-09 17:13:18 +08:00 |
|
unknown
|
e757bd72c6
|
Enable of clk_div2 tested on FPGA
|
2024-11-07 10:57:58 +08:00 |
|
thfu
|
2fdaaa3611
|
Fit modification of enable signal as clk divided by 2
|
2024-11-04 19:07:35 +08:00 |
|
thfu
|
da3157a7d8
|
Modify enable signal as clk divided by 2
|
2024-11-04 19:03:02 +08:00 |
|
thfu
|
85b2d97c02
|
modify relevant .v file and .m file to verify the accuracy of rtl code
|
2024-10-17 17:29:11 +08:00 |
|
unknown
|
c6ff7dc280
|
add 8 interpolation
|
2024-10-08 11:24:32 +08:00 |