 thfu
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a86850e439
|
v04-z_dsp on FPGA
|
2024-11-12 20:03:17 +08:00 |
|
thfu
|
d6eb195dde
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v04-enable of clk_div2
|
2024-11-12 17:35:22 +08:00 |
|
thfu
|
e9dbf0564e
|
v04-round edf
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2024-11-11 17:26:22 +08:00 |
|
thfu
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8d46d2bbd3
|
v04-round
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2024-11-11 17:17:15 +08:00 |
|
thfu
|
e2c8c38898
|
v04-synthesis z_dsp
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2024-11-10 11:14:47 +08:00 |
|
thfu
|
993ed34ee4
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v04-eliminate warning
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2024-11-09 17:51:37 +08:00 |
|
thfu
|
8fa46ded3a
|
v04-IIR based on IP core
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2024-11-09 17:13:18 +08:00 |
|
unknown
|
e757bd72c6
|
Enable of clk_div2 tested on FPGA
|
2024-11-07 10:57:58 +08:00 |
|
thfu
|
2fdaaa3611
|
Fit modification of enable signal as clk divided by 2
|
2024-11-04 19:07:35 +08:00 |
|
thfu
|
da3157a7d8
|
Modify enable signal as clk divided by 2
|
2024-11-04 19:03:02 +08:00 |
|
thfu
|
85b2d97c02
|
modify relevant .v file and .m file to verify the accuracy of rtl code
|
2024-10-17 17:29:11 +08:00 |
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unknown
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c6ff7dc280
|
add 8 interpolation
|
2024-10-08 11:24:32 +08:00 |