 unknown
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9dcfcd4028
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v01-.v files convert reg to wire;.m files include diff and sqt both less than 1e-4
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2024-11-26 20:38:29 +08:00 |
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unknown
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456a9fb479
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v01-z_dsp delay width debug;add z_dsp.m add diff_plot_py.m
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2024-11-26 17:57:19 +08:00 |
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thfu
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5cd9b46a21
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v01-add round module;intp8 and mult_C using round;Modify the directory structure
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2024-11-26 13:34:17 +08:00 |
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thfu
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6908587dae
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v01-enable of clk_div2;8pin to 4pin;valid I/O
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2024-11-25 23:05:43 +08:00 |
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thfu
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34cf630d95
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v01-coef both with 32bit;width parameterized
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2024-11-25 20:26:22 +08:00 |
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unknown
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e757bd72c6
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Enable of clk_div2 tested on FPGA
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2024-11-07 10:57:58 +08:00 |
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thfu
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2fdaaa3611
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Fit modification of enable signal as clk divided by 2
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2024-11-04 19:07:35 +08:00 |
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thfu
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da3157a7d8
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Modify enable signal as clk divided by 2
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2024-11-04 19:03:02 +08:00 |
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thfu
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85b2d97c02
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modify relevant .v file and .m file to verify the accuracy of rtl code
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2024-10-17 17:29:11 +08:00 |
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unknown
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c6ff7dc280
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add 8 interpolation
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2024-10-08 11:24:32 +08:00 |