 thfu
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cbf8ab957e
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v04-using DW_iir_dc_m.v;TB don't use ca_wave
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2024-11-27 16:35:27 +08:00 |
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thfu
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bcfd586b53
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v04-Test enable for 8pin and 4pin together
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2024-11-21 14:50:01 +08:00 |
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thfu
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038ab149bc
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v04-add valid output port and convert from 8 to 4
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2024-11-14 20:35:56 +08:00 |
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thfu
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d6eb195dde
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v04-enable of clk_div2
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2024-11-12 17:35:22 +08:00 |
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thfu
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8d46d2bbd3
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v04-round
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2024-11-11 17:17:15 +08:00 |
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thfu
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993ed34ee4
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v04-eliminate warning
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2024-11-09 17:51:37 +08:00 |
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thfu
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8fa46ded3a
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v04-IIR based on IP core
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2024-11-09 17:13:18 +08:00 |
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thfu
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2fdaaa3611
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Fit modification of enable signal as clk divided by 2
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2024-11-04 19:07:35 +08:00 |
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thfu
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da3157a7d8
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Modify enable signal as clk divided by 2
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2024-11-04 19:03:02 +08:00 |
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thfu
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85b2d97c02
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modify relevant .v file and .m file to verify the accuracy of rtl code
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2024-10-17 17:29:11 +08:00 |
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unknown
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c6ff7dc280
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add 8 interpolation
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2024-10-08 11:24:32 +08:00 |