 thfu
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a0f18c5a21
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add coefficient generation module and z_dsp; remove interpolation module and other files; suggest further simplification of RTL code using for-loops
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2025-03-08 16:33:58 +08:00 |
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thfu
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e42378b1ab
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An eight-channel parallel IIR filter, with the on-chip coefficient generation module yet to be developed, and no for loops used.
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2025-03-03 18:10:00 +08:00 |
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unknown
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f547d17650
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原脚本太长，将其划分为不同功能模块并进行封装管理
目前已完成功能设计，但通过全局变量传参，后期需要维护
包络的产生还不够灵活
这里只是扫描线路参数和波形，但还没有支持对不同的采样率进行扫描
Signed-off-by: thfu
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2025-02-26 15:59:43 +08:00 |
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unknown
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6e1218e622
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修改z_dsp.m相关函数以批量扫描线路参数和波形
修改TailCorr_Test的名字便于区分Verdi平台用的脚本和Windows平台
Signed-off-by: unknown <2779155576@qq.com>
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2025-02-26 15:59:43 +08:00 |
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thfu
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2861f02533
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Á½Â·²¢ÐеÄIIRÂ˲¨Æ÷£¬ÏÂÒ»²½¸ÄÖÁ°Ë·²¢ÐÐ
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2025-02-26 15:50:49 +08:00 |
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unknown
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a7b7faf8df
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v01-modiy absolute path in z_dsp.m
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2024-11-26 22:57:15 +08:00 |
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unknown
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9dcfcd4028
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v01-.v files convert reg to wire;.m files include diff and sqt both less than 1e-4
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2024-11-26 20:38:29 +08:00 |
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unknown
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456a9fb479
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v01-z_dsp delay width debug;add z_dsp.m add diff_plot_py.m
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2024-11-26 17:57:19 +08:00 |
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thfu
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5cd9b46a21
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v01-add round module;intp8 and mult_C using round;Modify the directory structure
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2024-11-26 13:34:17 +08:00 |
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thfu
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6908587dae
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v01-enable of clk_div2;8pin to 4pin;valid I/O
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2024-11-25 23:05:43 +08:00 |
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thfu
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34cf630d95
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v01-coef both with 32bit;width parameterized
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2024-11-25 20:26:22 +08:00 |
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unknown
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e757bd72c6
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Enable of clk_div2 tested on FPGA
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2024-11-07 10:57:58 +08:00 |
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thfu
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b00693ce73
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choose the min length to compare
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2024-11-04 19:09:41 +08:00 |
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thfu
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2fdaaa3611
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Fit modification of enable signal as clk divided by 2
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2024-11-04 19:07:35 +08:00 |
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thfu
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da3157a7d8
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Modify enable signal as clk divided by 2
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2024-11-04 19:03:02 +08:00 |
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thfu
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85b2d97c02
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modify relevant .v file and .m file to verify the accuracy of rtl code
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2024-10-17 17:29:11 +08:00 |
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thfu
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7a1c7f3523
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add verification code of matlab
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2024-10-08 17:58:26 +08:00 |
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unknown
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df1da34c44
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only add makefile and filelist in sim
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2024-10-08 11:43:02 +08:00 |
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unknown
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fa9fc93456
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delete sim file,there is too many temporary file
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2024-10-08 11:38:13 +08:00 |
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unknown
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1dcfdbd76a
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delete repeated .v file
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2024-10-08 11:34:25 +08:00 |
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unknown
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c6ff7dc280
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add 8 interpolation
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2024-10-08 11:24:32 +08:00 |
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unknown
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dcd8166010
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init
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2024-04-16 10:14:19 +08:00 |