 thfu
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9f61ed8b68
|
v04-din+IIR_out to compare with verdi
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2024-11-20 20:27:50 +08:00 |
|
thfu
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fda936e228
|
Modify the directory structure 2th
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2024-11-20 20:24:08 +08:00 |
|
thfu
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b95b0ba2d2
|
Modify the directory structure
|
2024-11-20 20:19:36 +08:00 |
|
thfu
|
038ab149bc
|
v04-add valid output port and convert from 8 to 4
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2024-11-14 20:35:56 +08:00 |
|
thfu
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01db8232c2
|
v04-MeanIntp_8.v work with enable
|
2024-11-14 20:32:29 +08:00 |
|
thfu
|
a86850e439
|
v04-z_dsp on FPGA
|
2024-11-12 20:03:17 +08:00 |
|
thfu
|
d6eb195dde
|
v04-enable of clk_div2
|
2024-11-12 17:35:22 +08:00 |
|
thfu
|
e9dbf0564e
|
v04-round edf
|
2024-11-11 17:26:22 +08:00 |
|
thfu
|
8d46d2bbd3
|
v04-round
|
2024-11-11 17:17:15 +08:00 |
|
thfu
|
e2c8c38898
|
v04-synthesis z_dsp
|
2024-11-10 11:14:47 +08:00 |
|
thfu
|
993ed34ee4
|
v04-eliminate warning
|
2024-11-09 17:51:37 +08:00 |
|
thfu
|
8fa46ded3a
|
v04-IIR based on IP core
|
2024-11-09 17:13:18 +08:00 |
|
unknown
|
e757bd72c6
|
Enable of clk_div2 tested on FPGA
|
2024-11-07 10:57:58 +08:00 |
|
thfu
|
b00693ce73
|
choose the min length to compare
|
2024-11-04 19:09:41 +08:00 |
|
thfu
|
2fdaaa3611
|
Fit modification of enable signal as clk divided by 2
|
2024-11-04 19:07:35 +08:00 |
|
thfu
|
da3157a7d8
|
Modify enable signal as clk divided by 2
|
2024-11-04 19:03:02 +08:00 |
|
thfu
|
85b2d97c02
|
modify relevant .v file and .m file to verify the accuracy of rtl code
|
2024-10-17 17:29:11 +08:00 |
|
thfu
|
7a1c7f3523
|
add verification code of matlab
|
2024-10-08 17:58:26 +08:00 |
|
unknown
|
df1da34c44
|
only add makefile and filelist in sim
|
2024-10-08 11:43:02 +08:00 |
|
unknown
|
fa9fc93456
|
delete sim file,there is too many temporary file
|
2024-10-08 11:38:13 +08:00 |
|
unknown
|
1dcfdbd76a
|
delete repeated .v file
|
2024-10-08 11:34:25 +08:00 |
|
unknown
|
c6ff7dc280
|
add 8 interpolation
|
2024-10-08 11:24:32 +08:00 |
|
unknown
|
dcd8166010
|
init
|
2024-04-16 10:14:19 +08:00 |