2 Commits

Author	SHA1	Message	Date
unknown	9dcfcd4028	v01-.v files convert reg to wire;.m files include diff and sqt both less than 1e-4	2024-11-26 20:38:29 +08:00
unknown	456a9fb479	v01-z_dsp delay width debug;add z_dsp.m add diff_plot_py.m	2024-11-26 17:57:19 +08:00