TailCorr

Commit Graph

Author	SHA1	Message	Date
thfu	596b32273b	八倍内插模块的使能改为时钟二分频；八路输出转为四路输出； .m文件计算输入加滤波结果 v04-add valid output port and convert from 8 to 4 Modify the directory structure Modify the directory structure 2th v04-din+IIR_out to compare with verdi v04-add valid output port and convert from 8 to 4 on FPGA	2025-03-11 19:44:53 +08:00
unknown	08484e4771	增加了八倍内插模块；删除了上传的临时文件，整理了文件结构；增加了matlab代码与仿真结果对比 delete repeated .v file delete sim file,there is too many temporary file only add makefile and filelist in sim add verification code of matlab modify relevant .v file and .m file to verify the accuracy of rtl code	2025-03-11 19:36:24 +08:00

Author

SHA1

Message

Date

thfu

596b32273b

八倍内插模块的使能改为时钟二分频；

八路输出转为四路输出；
.m文件计算输入加滤波结果

v04-add valid output port and convert from 8 to 4

Modify the directory structure

Modify the directory structure 2th

v04-din+IIR_out to compare with verdi

v04-add valid output port and convert from 8 to 4 on FPGA

2025-03-11 19:44:53 +08:00

unknown

08484e4771

增加了八倍内插模块；

删除了上传的临时文件，整理了文件结构；
增加了matlab代码与仿真结果对比

delete repeated .v file

delete sim file,there is too many temporary file

only add makefile and filelist in sim

add verification code of matlab

modify relevant .v file and .m file to verify the accuracy of rtl code

2025-03-11 19:36:24 +08:00

2 Commits