6 Commits

Author	SHA1	Message	Date
thfu	334a19edec	v04-z_dsp 4 ports output	2024-11-26 20:59:57 +08:00
thfu	bcfd586b53	v04-Test enable for 8pin and 4pin together	2024-11-21 14:50:01 +08:00
thfu	038ab149bc	v04-add valid output port and convert from 8 to 4	2024-11-14 20:35:56 +08:00
thfu	d6eb195dde	v04-enable of clk_div2	2024-11-12 17:35:22 +08:00
unknown	e757bd72c6	Enable of clk_div2 tested on FPGA	2024-11-07 10:57:58 +08:00
thfu	da3157a7d8	Modify enable signal as clk divided by 2	2024-11-04 19:03:02 +08:00