TailCorr

Commit Graph

Author	SHA1	Message	Date
thfu	270d149d1f	v04-using DW_iir_dc_m.v;TB don't use ca_wave	2025-03-11 19:54:48 +08:00
thfu	596b32273b	八倍内插模块的使能改为时钟二分频；八路输出转为四路输出； .m文件计算输入加滤波结果 v04-add valid output port and convert from 8 to 4 Modify the directory structure Modify the directory structure 2th v04-din+IIR_out to compare with verdi v04-add valid output port and convert from 8 to 4 on FPGA	2025-03-11 19:44:53 +08:00
thfu	e058191d12	Modify enable signal as clk divided by 2 使能口连时钟二分频； diff_plot.m使用最短的进行对比 Fit modification of enable signal as clk divided by 2 choose the min length to compare Enable of clk_div2 tested on FPGA	2025-03-11 19:38:34 +08:00

Author

SHA1

Message

Date

thfu

270d149d1f

v04-using DW_iir_dc_m.v;TB don't use ca_wave

2025-03-11 19:54:48 +08:00

thfu

596b32273b

八倍内插模块的使能改为时钟二分频；

八路输出转为四路输出；
.m文件计算输入加滤波结果

v04-add valid output port and convert from 8 to 4

Modify the directory structure

Modify the directory structure 2th

v04-din+IIR_out to compare with verdi

v04-add valid output port and convert from 8 to 4 on FPGA

2025-03-11 19:44:53 +08:00

thfu

e058191d12

Modify enable signal as clk divided by 2

使能口连时钟二分频；
diff_plot.m使用最短的进行对比

Fit modification of enable signal as clk divided by 2

choose the min length to compare

Enable of clk_div2 tested on FPGA

2025-03-11 19:38:34 +08:00

3 Commits