thfu
/
TailCorr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
10 Commits 4 Branches 0 Tags 22 MiB
Commit Graph

10 Commits

Author SHA1 Message Date
thfu 22ceafb511 z芯片在环验证 
v04-delete unnecessary .m files

v04-spi ram delete unnecessary ports and add related .m

v04-z_chip_top modify and DataShow.m comparing case
 2025-03-11 19:51:46 +08:00
thfu 5433610d48 输出8路转4路后和原来的8路进行比较； 
.m输出二进制数，方便配寄存器；
将z_dsp综合成网表用于z芯片的在环验证

v04-script add hex output

v04-z_dsp's netlist used to  z_chip_top
 2025-03-11 19:48:56 +08:00
thfu 596b32273b 八倍内插模块的使能改为时钟二分频； 
八路输出转为四路输出；
.m文件计算输入加滤波结果

v04-add valid output port and convert from 8 to 4

Modify the directory structure

Modify the directory structure 2th

v04-din+IIR_out to compare with verdi

v04-add valid output port and convert from 8 to 4 on FPGA
 2025-03-11 19:44:53 +08:00
thfu 7057a430d1 基于IP核的滤波器，使能二分频 
v04-z_dsp on FPGA
 2025-03-11 19:42:44 +08:00
thfu 9c0a3a7acf 运算结束后进行四舍五入 
v04-round edf
 2025-03-11 19:41:25 +08:00
thfu 685e094c03 v04-synthesis z_dsp 2025-03-11 19:41:24 +08:00
thfu 84f84448df IIR滤波器使用IP核； 
v04-eliminate warning
 2025-03-11 19:40:19 +08:00
thfu e058191d12 Modify enable signal as clk divided by 2 
使能口连时钟二分频；
diff_plot.m使用最短的进行对比

Fit modification of enable signal as clk divided by 2

choose the min length to compare

Enable of clk_div2 tested on FPGA
 2025-03-11 19:38:34 +08:00
unknown 08484e4771 增加了八倍内插模块； 
删除了上传的临时文件，整理了文件结构；
增加了matlab代码与仿真结果对比

delete repeated .v file

delete sim file,there is too many temporary file

only add makefile and filelist in sim

add verification code of matlab

modify relevant .v file and .m file to verify the accuracy of rtl code
 2025-03-11 19:36:24 +08:00
unknown dcd8166010 init 2024-04-16 10:14:19 +08:00