 thfu
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038ab149bc
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v04-add valid output port and convert from 8 to 4
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2024-11-14 20:35:56 +08:00 |
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thfu
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01db8232c2
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v04-MeanIntp_8.v work with enable
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2024-11-14 20:32:29 +08:00 |
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thfu
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a86850e439
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v04-z_dsp on FPGA
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2024-11-12 20:03:17 +08:00 |
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thfu
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d6eb195dde
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v04-enable of clk_div2
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2024-11-12 17:35:22 +08:00 |
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thfu
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e9dbf0564e
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v04-round edf
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2024-11-11 17:26:22 +08:00 |
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thfu
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8d46d2bbd3
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v04-round
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2024-11-11 17:17:15 +08:00 |
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thfu
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e2c8c38898
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v04-synthesis z_dsp
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2024-11-10 11:14:47 +08:00 |
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thfu
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993ed34ee4
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v04-eliminate warning
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2024-11-09 17:51:37 +08:00 |
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thfu
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8fa46ded3a
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v04-IIR based on IP core
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2024-11-09 17:13:18 +08:00 |
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unknown
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e757bd72c6
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Enable of clk_div2 tested on FPGA
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2024-11-07 10:57:58 +08:00 |
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thfu
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b00693ce73
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choose the min length to compare
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2024-11-04 19:09:41 +08:00 |
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thfu
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2fdaaa3611
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Fit modification of enable signal as clk divided by 2
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2024-11-04 19:07:35 +08:00 |
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thfu
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da3157a7d8
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Modify enable signal as clk divided by 2
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2024-11-04 19:03:02 +08:00 |
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thfu
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85b2d97c02
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modify relevant .v file and .m file to verify the accuracy of rtl code
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2024-10-17 17:29:11 +08:00 |
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thfu
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7a1c7f3523
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add verification code of matlab
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2024-10-08 17:58:26 +08:00 |
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unknown
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df1da34c44
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only add makefile and filelist in sim
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2024-10-08 11:43:02 +08:00 |
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unknown
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fa9fc93456
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delete sim file,there is too many temporary file
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2024-10-08 11:38:13 +08:00 |
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unknown
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1dcfdbd76a
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delete repeated .v file
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2024-10-08 11:34:25 +08:00 |
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unknown
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c6ff7dc280
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add 8 interpolation
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2024-10-08 11:24:32 +08:00 |
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unknown
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dcd8166010
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init
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2024-04-16 10:14:19 +08:00 |