thfu
/
TailCorr
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

增加了八倍内插模块； 

删除了一些重复的.v文件和临时文件，使文件夹更简洁，sim文件夹中只保留了makefile和filelist；
增加了matlab的验证代码，比较rtl代码和matlab代码的结果；

删除了一些重复的.v文件，使文件夹更简洁

删除了无用的临时文件

sim文件夹中只保留了makefile和filelist

增加了matlab的验证代码，比较rtl代码和matlab代码的结果
This commit is contained in:
unknown 2024-10-08 11:23:42 +08:00 committed by futh0403
parent dcd8166010
commit f67df5f554
33 changed files with 3533 additions and 232 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

103
IIR_Filter.v
View File

@ -1,103 +0,0 @@
module IIR_Filter (
clk,
rstn,
din_re,
din_im,
a_re,
a_im,
b_re,
b_im,
dout
);
input rstn;
input clk;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [31:0] a_re;
input signed [31:0] a_im;
input signed [31:0] b_re;
input signed [31:0] b_im;
output signed [15:0] dout;
wire signed [48:0] mult_x_re;
wire signed [48:0] mult_x_im;
wire signed [54:0] mult_y_re;
wire signed [54:0] mult_y_im;
wire signed [15:0] dout_t;
wire signed [50:0] Ysum_re;
wire signed [50:0] Ysum_im;
reg signed [15:0] dout_r1;
reg signed [50:0] YsumR_re;
reg signed [50:0] YsumR_im;
reg signed [50:0] YsumR1_re;
reg signed [50:0] YsumR1_im;
mult_C #(16,16,32,32) inst_c1 ( .a (din_re ),
.b (din_im ),
.c (a_re ),
.d (a_im ),
.Re (mult_x_re ),
.Im (mult_x_im )
);
mult_C #(32,32,32,32) inst_c2 ( .a (YsumR_re ),
.b (YsumR_im ),
.c (b_re ),
.d (b_im ),
.Re (mult_y_re ),
.Im (mult_y_im )
);
assign Ysum_re = mult_x_re - mult_y_re;
assign Ysum_im = mult_x_im - mult_y_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
YsumR_re <= 'h0;
YsumR_im <= 'h0;
end
else
begin
YsumR_re <= {{20{Ysum_re[50]}},Ysum_re[50:20]} + Ysum_re[50];
YsumR_im <= {{20{Ysum_im[50]}},Ysum_im[50:20]} + Ysum_im[50];
end
always @(posedge clk or negedge rstn)
if (!rstn)
begin
YsumR1_re <= 'h0;
end
else
begin
YsumR1_re <= {{16{YsumR_re[50]}},YsumR_re[50:16]};
end
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_r1 <= 'h0;
end
else
begin
if(YsumR1_re[16:15]==2'b01)
dout_r1 <= 16'd32767;
else if(YsumR1_re[16:15]==2'b10)
dout_r1 <= -16'd32768;
else
dout_r1 <= YsumR1_re[15:0];
end
assign dout = dout_r1;
endmodule

37
diff.v
View File

@ -1,37 +0,0 @@
module diff(
clk,
rstn,
din,
dout
);
input rstn;
input clk;
input signed [15:0] din;
output signed [15:0] dout;
reg [15:0] din_r;
reg [15:0] din_r1;
reg [15:0] out_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_r <= 16'd0;
din_r1 <= 16'd0;
out_r <= 16'd0;
end
else
begin
din_r <= din;
din_r1 <= din_r;
out_r <= din_r - din_r1;
end
assign dout = out_r;
endmodule

53
mulc_C.v
View File

@ -1,53 +0,0 @@
module mult_C(
a,
b,
c,
d,
Re,
Im
);
parameter integer A_width = 8;
parameter integer B_width = 8;
parameter integer C_width = 8;
parameter integer D_width = 8;
input signed [A_width-1:0] a;
input signed [B_width-1:0] b;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width:0] Re;
output signed [A_width+D_width:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
assign Re = ac - bd;
assign Im = ad + bc;
endmodule

0
DW02_mult.v → rtl/DW02_mult.v
View File

357
rtl/DW_mult_pipe.v Normal file
View File

@ -0,0 +1,357 @@
////////////////////////////////////////////////////////////////////////////////
//
// This confidential and proprietary software may be used only
// as authorized by a licensing agreement from Synopsys Inc.
// In the event of publication, the following notice is applicable:
//
// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC.
// ALL RIGHTS RESERVED
//
// The entire notice above must be reproduced on all authorized
// copies.
//
// AUTHOR: Rajeev Huralikoppi Feb 15, 2002
//
// VERSION: Verilog Simulation Architecture
//
// DesignWare_version: 4e25d03d
// DesignWare_release: O-2018.06-DWBB_201806.3
//
////////////////////////////////////////////////////////////////////////////////
//-----------------------------------------------------------------------------
// ABSTRACT: An n stage pipelined multipler simulation model
//
// Parameters Valid Values Description
// ========== ========= ===========
// a_width >= 1 default: none
// Word length of a
//
// b_width >= 1 default: none
// Word length of b
//
// num_stages >= 2 default: 2
// Number of pipelined stages
//
// stall_mode 0 or 1 default: 1
// Stall mode
// 0 => non-stallable
// 1 => stallable
//
// rst_mode 0 to 2 default: 1
// Reset mode
// 0 => no reset
// 1 => asynchronous reset
// 2 => synchronous reset
//
// op_iso_mode 0 to 4 default: 0
// Type of operand isolation
// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied
// 0 => Follow intent defined by Power Compiler user setting
// 1 => no operand isolation
// 2 => 'and' gate operand isolaton
// 3 => 'or' gate operand isolation
// 4 => preferred isolation style: 'and'
//
//
// Input Ports Size Description
// =========== ==== ============
// clk 1 Clock
// rst_n 1 Reset, active low
// en 1 Register enable, active high
// tc 1 2's complement control
// a a_width Multiplier
// b b_width Multiplicand
//
// product a_width+b_width Product (a*b)
//
// MODIFIED:
// RJK 05/14/15 Updated model to work with less propagated 'X's
// so as to be more friendly with VCS-NLP
//
// RJK 05/28/13 Updated documentation in comments to properly
// describe the "en" input (STAR 9000627580)
//
// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter
// and related code.
//
// DLL 11/14/05 Changed legality checking of 'num_stages'
// parameter along with its abstract "Valid Values"
//
//
//-----------------------------------------------------------------------------
module DW_mult_pipe (clk,rst_n,en,tc,a,b,product);
parameter integer a_width = 2;
parameter integer b_width = 2;
parameter integer num_stages = 2;
parameter integer stall_mode = 1;
parameter integer rst_mode = 1;
parameter integer op_iso_mode = 0;
input clk;
input rst_n;
input [a_width-1 : 0] a;
input [b_width-1 : 0] b;
input tc;
input en;
output [a_width+b_width-1: 0] product;
reg [a_width-1 : 0] a_reg [0 : num_stages-2];
reg [b_width-1 : 0] b_reg [0 : num_stages-2];
reg tc_reg [0 : num_stages-2];
// synopsys translate_off
//---------------------------------------------------------------------------
// Behavioral model
//---------------------------------------------------------------------------
generate
if (rst_mode == 0) begin : GEN_RSM_EQ_0
if (stall_mode == 0) begin : GEN_RM0_SM0
always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC
integer i;
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end // block: rm0_pipe_reg_PROC
end else begin : GEN_RM0_SM1
always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC
integer i;
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end
end
end
end else if (rst_mode == 1) begin : GEN_RM_EQ_1
if (stall_mode == 0) begin : GEN_RM1_SM0
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm1_pipe_reg_PROC
end else begin : GEN_RM1_SM1
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm1_pipe_reg_PROC
end
end else begin : GEN_RM_GT_1
if (stall_mode == 0) begin : GEN_RM2_SM0
always @(posedge clk) begin: rm2_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= a;
b_reg[0] <= b;
tc_reg[0] <= tc;
end else begin
a_reg[i] <= a_reg[i-1];
b_reg[i] <= b_reg[i-1];
tc_reg[i] <= tc_reg[i-1];
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm2_pipe_reg_PROC
end else begin : GEN_RM2_SM1
always @(posedge clk) begin: rm2_pipe_reg_PROC
integer i;
if (rst_n == 1'b0) begin
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'b0}};
b_reg[i] <= {b_width{1'b0}};
tc_reg[i] <= 1'b0;
end // for (i= 0; i < num_stages-1; i++)
end else if (rst_n == 1'b1) begin
for(i= 0; i < num_stages-1; i=i+1) begin
if (i == 0) begin
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
end else begin
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
end
end // for (i= 0; i < num_stages-1; i++)
end else begin // rst_n not 1'b0 and not 1'b1
for (i= 0; i < num_stages-1; i=i+1) begin
a_reg[i] <= {a_width{1'bx}};
b_reg[i] <= {b_width{1'bx}};
tc_reg[i] <= 1'bx;
end // for (i= 0; i < num_stages-1; i++)
end
end // block: rm2_pipe_reg_PROC
end
end
endgenerate
DW02_mult #(a_width, b_width)
U1 (.A(a_reg[num_stages-2]),
.B(b_reg[num_stages-2]),
.TC(tc_reg[num_stages-2]),
.PRODUCT(product));
//---------------------------------------------------------------------------
// Parameter legality check and initializations
//---------------------------------------------------------------------------
initial begin : parameter_check
integer param_err_flg;
param_err_flg = 0;
if (a_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)",
a_width );
end
if (b_width < 1) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)",
b_width );
end
if (num_stages < 2) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)",
num_stages );
end
if ( (stall_mode < 0) || (stall_mode > 1) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)",
stall_mode );
end
if ( (rst_mode < 0) || (rst_mode > 2) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)",
rst_mode );
end
if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin
param_err_flg = 1;
$display(
"ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)",
op_iso_mode );
end
if ( param_err_flg == 1) begin
$display(
"%m :\n Simulation aborted due to invalid parameter value(s)");
$finish;
end
end // parameter_check
//---------------------------------------------------------------------------
// Report unknown clock inputs
//---------------------------------------------------------------------------
always @ (clk) begin : clk_monitor
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
$time, clk );
end // clk_monitor
// synopsys translate_on
endmodule //

184
rtl/IIR_Filter.v Normal file
View File

@ -0,0 +1,184 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter (
rstn,
en,
clk,
din_re,
din_im,
a_re,
a_im,
b_re,
b_im,
dout
);
input rstn;
input clk;
input en;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [36:0] a_re;
input signed [36:0] a_im;
input signed [20:0] b_re;
input signed [20:0] b_im;
output signed [15:0] dout;
wire signed [31:0] x1_re;
wire signed [31:0] x1_im;
wire signed [31:0] x2_re;
wire signed [31:0] x2_im;
wire signed [31:0] v_re;
wire signed [31:0] v_im;
reg signed [31:0] v1_re;
reg signed [31:0] v1_im;
wire signed [31:0] y_re;
wire signed [31:0] y_im;
wire signed [31:0] y1_re;
wire signed [31:0] y1_im;
wire signed [31:0] y2_re;
wire signed [31:0] y2_im;
reg signed [15:0] dout_re;
mult_C #(16,16,37,37) inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din_re ),
.b (din_im ),
.c (a_re ),
.d (a_im ),
.Re (x1_re ),
.Im (x1_im )
);
mult_C #(32,32,21,21) inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (x1_re ),
.b (x1_im ),
.c (b_re ),
.d (b_im ),
.Re (x2_re ),
.Im (x2_im )
);
assign v_re = x1_re - x2_re;
assign v_im = x1_im - x2_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
mult_C #(32,32,21,21) inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),
.b (y_im ),
.c (b_re ),
.d (b_im ),
.Re (y1_re ),
.Im (y1_im )
);
mult_C #(32,32,21,21) inst_c4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y1_re ),
.b (y1_im ),
.c (b_re ),
.d (b_im ),
.Re (y2_re ),
.Im (y2_im )
);
assign y_re = v1_re + y2_re;
assign y_im = v1_im + y2_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= y_re[31:16];
end
else
begin
dout_re <= dout_re;
end
/*
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_r1 <= 'h0;
end
else if(en)
begin
if(YsumR1_re[16:15]==2'b01)
dout_r1 <= 16'd32767;
else if(YsumR1_re[16:15]==2'b10)
dout_r1 <= -16'd32768;
else
dout_r1 <= YsumR1_re[15:0];
end
else
begin
dout_r1 <= dout_r1;
end
*/
assign dout = dout_re;
endmodule

144
rtl/MeanIntp_8.v Normal file
View File

@ -0,0 +1,144 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : MeanIntp_8.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-09-27 thfu top module of 8 mean interpolation
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module MeanIntp_8(
clk,
rstn,
en,
din, //input
dout_0,//output
dout_1,
dout_2,
dout_3,
dout_4,
dout_5,
dout_6,
dout_7
);
input rstn;
input clk;
input en;
input signed [15:0] din;
output signed [15:0] dout_0;
output signed [15:0] dout_1;
output signed [15:0] dout_2;
output signed [15:0] dout_3;
output signed [15:0] dout_4;
output signed [15:0] dout_5;
output signed [15:0] dout_6;
output signed [15:0] dout_7;
reg [15:0] din_r1;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_r1 <= 'h0;
end
else if(en)
begin
din_r1 <= din;
end
else
begin
din_r1 <= din_r1;
end
wire [16:0] sum_0_1;
assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
wire signed [16:0] diff_1_2;//(din-din_r1)/2
wire signed [16:0] diff_1_4;//(din-din_r1)/4
wire signed [16:0] diff_1_8;//(din-din_r1)/8
assign diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]};
assign diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]};
assign diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]};
reg signed [16:0] dout_r0;
reg signed [16:0] dout_r1;
reg signed [16:0] dout_r2;
reg signed [16:0] dout_r3;
reg signed [16:0] dout_r4;
reg signed [16:0] dout_r5;
reg signed [16:0] dout_r6;
reg signed [16:0] dout_r7;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
dout_r0 <= 'h0;
dout_r1 <= 'h0;
dout_r2 <= 'h0;
dout_r3 <= 'h0;
dout_r4 <= 'h0;
dout_r5 <= 'h0;
dout_r6 <= 'h0;
dout_r7 <= 'h0;
end
else if(en)
begin
dout_r0 <= din_r1;
dout_r1 <= din_r1 + diff_1_8;
dout_r2 <= din_r1 + diff_1_4;
dout_r3 <= din_r1 + diff_1_4 + diff_1_8;
dout_r4 <= din_r1 + diff_1_2;
dout_r5 <= din_r1 + diff_1_2 + diff_1_8;
dout_r6 <= din_r1 + diff_1_2 + diff_1_4;
dout_r7 <= din_r1 + diff_1_2 + diff_1_4 + diff_1_8;
end
else
begin
dout_r0 <= dout_r0;
dout_r1 <= dout_r1;
dout_r2 <= dout_r2;
dout_r3 <= dout_r3;
dout_r4 <= dout_r4;
dout_r5 <= dout_r5;
dout_r6 <= dout_r6;
dout_r7 <= dout_r7;
end
assign dout_0 = dout_r0[15:0];
assign dout_1 = dout_r1[15:0];
assign dout_2 = dout_r2[15:0];
assign dout_3 = dout_r3[15:0];
assign dout_4 = dout_r4[15:0];
assign dout_5 = dout_r5[15:0];
assign dout_6 = dout_r6[15:0];
assign dout_7 = dout_r7[15:0];
endmodule

117
TailCorr_top.v → rtl/TailCorr_top.v
View File

@ -1,8 +1,43 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module TailCorr_top module TailCorr_top
( (
clk, clk,
rstn, rstn,
en,
tc_bypass,
din_re, din_re,
din_im, din_im,
a0_re, a0_re,
@ -34,32 +69,34 @@ module TailCorr_top
input rstn; input rstn;
input clk; input clk;
input en;
input tc_bypass;
input signed [15:0] din_re; input signed [15:0] din_re;
input signed [15:0] din_im; input signed [15:0] din_im;
input signed [31:0] a0_re; input signed [36:0] a0_re;
input signed [31:0] a0_im; input signed [36:0] a0_im;
input signed [31:0] b0_re; input signed [20:0] b0_re;
input signed [31:0] b0_im; input signed [20:0] b0_im;
input signed [31:0] a1_re; input signed [36:0] a1_re;
input signed [31:0] a1_im; input signed [36:0] a1_im;
input signed [31:0] b1_re; input signed [20:0] b1_re;
input signed [31:0] b1_im; input signed [20:0] b1_im;
input signed [31:0] a2_re; input signed [36:0] a2_re;
input signed [31:0] a2_im; input signed [36:0] a2_im;
input signed [31:0] b2_re; input signed [20:0] b2_re;
input signed [31:0] b2_im; input signed [20:0] b2_im;
input signed [31:0] a3_re; input signed [36:0] a3_re;
input signed [31:0] a3_im; input signed [36:0] a3_im;
input signed [31:0] b3_re; input signed [20:0] b3_re;
input signed [31:0] b3_im; input signed [20:0] b3_im;
input signed [31:0] a4_re; input signed [36:0] a4_re;
input signed [31:0] a4_im; input signed [36:0] a4_im;
input signed [31:0] b4_re; input signed [20:0] b4_re;
input signed [31:0] b4_im; input signed [20:0] b4_im;
input signed [31:0] a5_re; input signed [36:0] a5_re;
input signed [31:0] a5_im; input signed [36:0] a5_im;
input signed [31:0] b5_re; input signed [20:0] b5_re;
input signed [31:0] b5_im; input signed [20:0] b5_im;
output signed [15:0] dout; output signed [15:0] dout;
@ -85,6 +122,7 @@ diff inst_diffRe
( (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din (din_re ), .din (din_re ),
.dout (IIRin_re ) .dout (IIRin_re )
); );
@ -93,6 +131,7 @@ diff inst_diffIm
( (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din (din_im ), .din (din_im ),
.dout (IIRin_im ) .dout (IIRin_im )
); );
@ -100,6 +139,7 @@ diff inst_diffIm
IIR_Filter inst_iir_0 ( IIR_Filter inst_iir_0 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din_re (IIRin_re ), .din_re (IIRin_re ),
.din_im (IIRin_im ), .din_im (IIRin_im ),
.a_re (a0_re ), .a_re (a0_re ),
@ -112,6 +152,7 @@ IIR_Filter inst_iir_0 (
IIR_Filter inst_iir_1 ( IIR_Filter inst_iir_1 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din_re (IIRin_re ), .din_re (IIRin_re ),
.din_im (IIRin_im ), .din_im (IIRin_im ),
.a_re (a1_re ), .a_re (a1_re ),
@ -124,6 +165,7 @@ IIR_Filter inst_iir_1 (
IIR_Filter inst_iir_2 ( IIR_Filter inst_iir_2 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din_re (IIRin_re ), .din_re (IIRin_re ),
.din_im (IIRin_im ), .din_im (IIRin_im ),
.a_re (a2_re ), .a_re (a2_re ),
@ -136,6 +178,7 @@ IIR_Filter inst_iir_2 (
IIR_Filter inst_iir_3 ( IIR_Filter inst_iir_3 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din_re (IIRin_re ), .din_re (IIRin_re ),
.din_im (IIRin_im ), .din_im (IIRin_im ),
.a_re (a3_re ), .a_re (a3_re ),
@ -148,6 +191,7 @@ IIR_Filter inst_iir_3 (
IIR_Filter inst_iir_4 ( IIR_Filter inst_iir_4 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din_re (IIRin_re ), .din_re (IIRin_re ),
.din_im (IIRin_im ), .din_im (IIRin_im ),
.a_re (a4_re ), .a_re (a4_re ),
@ -160,6 +204,7 @@ IIR_Filter inst_iir_4 (
IIR_Filter inst_iir_5 ( IIR_Filter inst_iir_5 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.din_re (IIRin_re ), .din_re (IIRin_re ),
.din_im (IIRin_im ), .din_im (IIRin_im ),
.a_re (a5_re ), .a_re (a5_re ),
@ -179,7 +224,7 @@ always @(posedge clk or negedge rstn)
din_r3 <= 'h0; din_r3 <= 'h0;
din_r4 <= 'h0; din_r4 <= 'h0;
end end
else else if(en)
begin begin
din_r0 <= din_re; din_r0 <= din_re;
din_r1 <= din_r0; din_r1 <= din_r0;
@ -187,16 +232,26 @@ always @(posedge clk or negedge rstn)
din_r3 <= din_r2; din_r3 <= din_r2;
din_r4 <= din_r3; din_r4 <= din_r3;
end end
else
begin
din_r0 <= din_r0;
din_r1 <= din_r1;
din_r2 <= din_r2;
din_r3 <= din_r3;
din_r4 <= din_r4;
end
assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4; assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if (!rstn) if (!rstn)begin
begin
dout_r <= 'h0; dout_r <= 'h0;
end end
else else if(tc_bypass)begin
begin dout_r <= din_re;
end
else begin
if(en)begin
if(Ysum[16:15]==2'b01) if(Ysum[16:15]==2'b01)
dout_r <= 16'd32767; dout_r <= 16'd32767;
else if(Ysum[16:15]==2'b10) else if(Ysum[16:15]==2'b10)
@ -204,6 +259,10 @@ always@(posedge clk or negedge rstn)
else else
dout_r <= Ysum[15:0]; dout_r <= Ysum[15:0];
end end
else begin
dout_r <= dout_r;
end
end
assign dout = dout_r; assign dout = dout_r;
endmodule endmodule

75
rtl/diff.v Normal file
View File

@ -0,0 +1,75 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : diff.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-11 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module diff(
clk,
rstn,
en,
din,
dout
);
input rstn;
input clk;
input en;
input signed [15:0] din;
output signed [15:0] dout;
reg [15:0] din_r;
reg [15:0] din_r1;
reg [15:0] out_r;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_r <= 16'd0;
din_r1 <= 16'd0;
out_r <= 16'd0;
end
else if(en)
begin
din_r <= din;
din_r1 <= din_r;
out_r <= din_r - din_r1;
end
else
begin
din_r <= din_r;
din_r1 <= din_r1;
out_r <= out_r;
end
assign dout = out_r;
endmodule

139
rtl/lsdacif.v Normal file
View File

@ -0,0 +1,139 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : dacif.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-11 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module lsdacif (
input clk
,input rstn
//DAC mode select
,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
,input [1 :0] intp_mode //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
//mixer data input
,input [15:0] din0
,input [15:0] din1
,input [15:0] din2
,input [15:0] din3
//data output
,output [15:0] dout0
,output [15:0] dout1
,output [15:0] dout2
,output [15:0] dout3
);
////////////////////////////////////////////////////
// regs
////////////////////////////////////////////////////
reg [15:0] dout0_r ;
reg [15:0] dout1_r ;
reg [15:0] dout2_r ;
reg [15:0] dout3_r ;
////////////////////////////////////////////////////
// intp mode select
////////////////////////////////////////////////////
/*
always@(posedge clk) begin
case(intp_mode)
2'b00 : begin
mux_p_0 <= {~din0[15],din0[14:0]};
mux_p_1 <= 16'h0;
mux_p_2 <= 16'h0;
mux_p_3 <= 16'h0;
end
2'b01 : begin
mux_p_0 <= {~din0[15],din0[14:0]};
mux_p_1 <= {~din1[15],din1[14:0]};
mux_p_2 <= 16'h0 ;
mux_p_3 <= 16'h0 ;
end
2'b10 : begin
mux_p_0 <= {~din0[15],din0[14:0]} ;
mux_p_1 <= {~din1[15],din1[14:0]} ;
mux_p_2 <= {~din2[15],din2[14:0]} ;
mux_p_3 <= {~din3[15],din3[14:0]};
end
default : begin
mux_p_0 <= {~din0[15],din0[14:0]} ;
mux_p_1 <= {~din1[15],din1[14:0]} ;
mux_p_2 <= {~din2[15],din2[14:0]} ;
mux_p_3 <= {~din3[15],din3[14:0]} ;
end
endcase
end
*/
////////////////////////////////////////////////////
// mode select
////////////////////////////////////////////////////
always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin
dout0_r <= 16'h0;
dout1_r <= 16'h0;
dout2_r <= 16'h0;
dout3_r <= 16'h0;
end
else begin
case(dac_mode_sel)
2'b00 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din1[15],din1[14:0]};
dout2_r <= {~din2[15],din2[14:0]};
dout3_r <= {~din3[15],din3[14:0]};
end
2'b01 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din0[15],din0[14:0]};
dout2_r <= {~din1[15],din1[14:0]};
dout3_r <= {~din1[15],din1[14:0]};
end
2'b10 : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din0[15],din0[14:0]};
dout2_r <= {~din0[15],din0[14:0]};
dout3_r <= {~din0[15],din0[14:0]};
end
default : begin
dout0_r <= {~din0[15],din0[14:0]};
dout1_r <= {~din1[15],din1[14:0]};
dout2_r <= {~din2[15],din2[14:0]};
dout3_r <= {~din3[15],din3[14:0]};
end
endcase
end
end
assign dout0 = dout0_r ;
assign dout1 = dout1_r ;
assign dout2 = dout2_r ;
assign dout3 = dout3_r ;
endmodule

113
rtl/mult_C.v Normal file
View File

@ -0,0 +1,113 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C(
clk,
rstn,
en,
a,
b,
c,
d,
Re,
Im
);
parameter integer A_width = 8;
parameter integer B_width = 8;
parameter integer C_width = 8;
parameter integer D_width = 8;
input rstn;
input clk;
input en;
input signed [A_width-1:0] a;
input signed [B_width-1:0] b;
input signed [C_width-1:0] c;
input signed [D_width-1:0] d;
output signed [A_width+C_width-22:0] Re;
output signed [A_width+D_width-22:0] Im;
wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc;
reg signed [A_width+C_width:0] Re_tmp;
reg signed [A_width+D_width:0] Im_tmp;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (bd )
);
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ),
.TC (1'b1 ),
.PRODUCT (ad )
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
always@(posedge clk or negedge rstn)
if(!rstn)
begin
Re_tmp <= 'h0;
Im_tmp <= 'h0;
end
else if(en)
begin
Re_tmp <= ac - bd;
Im_tmp <= ad + bc;
end
else
begin
Re_tmp <= Re_tmp;
Im_tmp <= Im_tmp;
end
assign Re = Re_tmp[A_width+D_width-1:20];
assign Im = Im_tmp[A_width+D_width-1:20];
endmodule

73
rtl/z_data_mux.v Normal file
View File

@ -0,0 +1,73 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : z_data_mux.v
// Department :
// Author : PWY
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-13 PWY debug top-level
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_data_mux (
//system port
input clk // System Main Clock
,input rst_n // Spi Reset active low
//---------------from ctrl regfile------------------------------------
,input sel // 1'b0 --> mod modem data; 1'b1 --> mod nco data
//Z dsp data
,input [15:0] z_dsp_data0
,input [15:0] z_dsp_data1
,input [15:0] z_dsp_data2
,input [15:0] z_dsp_data3
//XY dsp data
,input [15:0] xy_dsp_data0
,input [15:0] xy_dsp_data1
,input [15:0] xy_dsp_data2
,input [15:0] xy_dsp_data3
//mux out data
,output [15:0] mux_data_0
,output [15:0] mux_data_1
,output [15:0] mux_data_2
,output [15:0] mux_data_3
);
wire [15:0] mux_data_0_w = sel ? xy_dsp_data0 : z_dsp_data0;
wire [15:0] mux_data_1_w = sel ? xy_dsp_data1 : z_dsp_data1;
wire [15:0] mux_data_2_w = sel ? xy_dsp_data2 : z_dsp_data2;
wire [15:0] mux_data_3_w = sel ? xy_dsp_data3 : z_dsp_data3;
x-special/nautilus-clipboard
copy
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_dffs.v
file:///tmp/VMwareDnD/x9misj/sirv_gnrl_xchecker.v
sirv_gnrl_dffr #(16) mux_data_0_dffr (mux_data_0_w , mux_data_0 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_1_dffr (mux_data_1_w , mux_data_1 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_2_dffr (mux_data_2_w , mux_data_2 , clk, rst_n);
sirv_gnrl_dffr #(16) mux_data_3_dffr (mux_data_3_w , mux_data_3 , clk, rst_n);
endmodule

184
rtl/z_dsp.v Normal file
View File

@ -0,0 +1,184 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : Z_dsp.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp
(
clk,
rstn,
en, //enable
dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve;
tc_bypass,
intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
din_re,
din_im,
a0_re, //a0's real part
a0_im, //a0's image part
b0_re,
b0_im,
a1_re,
a1_im,
b1_re,
b1_im,
a2_re,
a2_im,
b2_re,
b2_im,
a3_re,
a3_im,
b3_re,
b3_im,
a4_re,
a4_im,
b4_re,
b4_im,
a5_re,
a5_im,
b5_re,
b5_im,
dout0,
dout1,
dout2,
dout3
);
input rstn;
input clk;
input en;
input tc_bypass;
input [1:0] intp_mode;
input [1:0] dac_mode_sel;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [36:0] a0_re;
input signed [36:0] a0_im;
input signed [20:0] b0_re;
input signed [20:0] b0_im;
input signed [36:0] a1_re;
input signed [36:0] a1_im;
input signed [20:0] b1_re;
input signed [20:0] b1_im;
input signed [36:0] a2_re;
input signed [36:0] a2_im;
input signed [20:0] b2_re;
input signed [20:0] b2_im;
input signed [36:0] a3_re;
input signed [36:0] a3_im;
input signed [20:0] b3_re;
input signed [20:0] b3_im;
input signed [36:0] a4_re;
input signed [36:0] a4_im;
input signed [20:0] b4_re;
input signed [20:0] b4_im;
input signed [36:0] a5_re;
input signed [36:0] a5_im;
input signed [20:0] b5_re;
input signed [20:0] b5_im;
output signed [15:0] dout0;
output signed [15:0] dout1;
output signed [15:0] dout2;
output signed [15:0] dout3;
wire signed [15:0] IIR_out;
TailCorr_top inst_TailCorr_top
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.din_re (din_re ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout (IIR_out )
);
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
MeanIntp4_top inst_MeanIntp4
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (IIR_out ),
.dout_0 (dout_0 ),
.dout_1 (dout_1 ),
.dout_2 (dout_2 ),
.dout_3 (dout_3 )
);
lsdacif inst_lsdacif
(
.clk (clk ),
.rstn (rstn ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din0 (dout_0 ),
.din1 (dout_1 ),
.din2 (dout_2 ),
.din3 (dout_3 ),
.dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 )
);
endmodule

6
script_m/MeanIntp.m Executable file
View File

@ -0,0 +1,6 @@
%%% so means original, s_mean means mean value
function [s,s_mean] = MeanIntp(s,s_r1)
s_mean = (s+s_r1)/2;
end

35
script_m/MyIIR.m Executable file
View File

@ -0,0 +1,35 @@
function out = MyIIR(a,b,x,YStartState,sel_double)
len = length(x);
switch sel_double
case 0
x = int64(x);
a = int64(a);
b = int64(b);
y(1) = int64(YStartState);
case 1
x = double(x);
a = double(a);
b = double(b);
y(1) = double(YStartState);
end
switch sel_double
case 0
for i = 1:len-1
y_tmp(i+1) = a*x(i+1) - b*y(i)';
y(i+1) = bitsra(y_tmp(i+1),20) + bitget(y_tmp(i+1),64);
end
out = bitsra(y,16);
case 1
for i = 1:len-1
y_tmp(i+1) = floor(a*x(i+1) - b*y(i)');
y(i+1) = floor(y_tmp(i+1)/2^20) + bitget(int64(y_tmp(i+1)),64);
end
out = floor(y/2^16);
end

30
script_m/MyIIR_test.m Executable file
View File

@ -0,0 +1,30 @@
clc;clear;close all
cd('/data/work/thfu/TailCorr/script_m');
a = 13740916;
b = -1047703;
y(1) = 0;
sel_double = 0;
switch sel_double
case 0
iir_in = int64(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
iir_out = int64(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
case 1
iir_in = double(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
iir_out = double(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
end
Script_out = MyIIR(a,b,iir_in,y(1),sel_double)';
y_revised = iir_in + Script_out;
tau = finddelay(y_revised,iir_out);
Script_outPhi = cat(1,zeros(1,tau)',Script_out(1:end-tau,1));
n = 1:length(iir_in);
diff = iir_out(n)-Script_outPhi(n);
diff_plot(iir_out, Script_outPhi)
tau

44
script_m/PolyMean_Test.m Executable file
View File

@ -0,0 +1,44 @@
clc;clear all;close all
fs = 1e8;
t = (0:1:1e2)'/fs;
% f = 20e6;
% s = sin(2*pi*f*t);
s = triang(1e2-1);
s = [zeros(1,10) s' zeros(1,10)]';
N = length(s);
ts = (0:1:N-1)'/fs;
%%%
s_r1 = [0 s(1:end-1,1)']';
[s2,s2_mean] = MeanIntp(s,s_r1);
s_intp2 = zeros(2*N,1);
s_intp2(1:2:2*N) = s2_mean;
s_intp2(2:2:2*N) = s2;
t_intp2 = (0:1:2*N-1)'/fs/2;
%%%
s2_r1 = [0 s2(1:end-1,1)']';
[s4_4,s4_3] = MeanIntp(s2,s2_mean);
[s4_2,s4_1] = MeanIntp(s2_mean,s2_r1);
s_intp4 = zeros(4*N,1);
s_intp4(1:4:4*N) = s4_1;
s_intp4(2:4:4*N) = s4_2;
s_intp4(3:4:4*N) = s4_3;
s_intp4(4:4:4*N) = s4_4;
t_intp4 = (0:1:4*N-1)'/fs/4;
figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
plot(ts,s,t_intp2,s_intp2)
grid on
% xlim([0.58 0.62]*1e-6)
%
%
figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]);
plot(t_intp4,s_intp4)
grid on
% xlim([0.58 0.62]*1e-6)

27
script_m/TailCorr.m Executable file
View File

@ -0,0 +1,27 @@
function out = TailCorr(alpha,beta,iir_in,YStartState,sel_double)
len = length(iir_in);
N = length(alpha);
iir_inR1 = cat(1,0,iir_in(1:end-1,1));
diff = iir_in - iir_inR1;
Ystart = YStartState;
for i = 1:1:N
y(1:len,i) = MyIIR(alpha(i),beta(i),diff,Ystart,sel_double);
y = floor(y);
end
switch sel_double
case 0
y_sum = int64(sum(y,2));
case 1
y_sum = double(sum(y,2));
end
out = iir_in+y_sum;

27
script_m/TailCorr_test.m Executable file
View File

@ -0,0 +1,27 @@
clc;clear;close all
cd('/data/work/thfu/TailCorr/script_m');
sel_double = 1;
switch sel_double
case 0
iir_in = int64(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
iir_out = int64(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
case 1
iir_in = double(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
iir_out = double(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
end
alpha = [1757225200, 1045400392, 13740916];
beta = -[1042856 1046395 1047703];
Ystart = 0;
y_revised = TailCorr(alpha,beta,iir_in,Ystart,sel_double);
tau = finddelay(y_revised,iir_out);
y_revisedPhi = cat(1,zeros(1,tau)',y_revised(1:end-tau,1));
diff_plot(iir_out, y_revisedPhi,'verdi','matlab',[0 1e4])

72
script_m/TailCorr_test_P.m Executable file
View File

@ -0,0 +1,72 @@
clc;clear;close all
cd('/data/work/thfu/TailCorr/script_m');
sel_double = 1;
switch sel_double
case 0
iir_in = int64(importdata("/home/thfu/work/TailCorr/Test/sim/in") -32768);
iir_out_x1 = int64(importdata("/home/thfu/work/TailCorr/Test/sim/X1_data.dat") -32768);
iir_out_x2 = int64(importdata("/home/thfu/work/TailCorr/Test/sim/X2_data.dat") -32768);
iir_out_x4 = int64(importdata("/home/thfu/work/TailCorr/Test/sim/X4_data.dat") -32768);
case 1
iir_in = double(importdata("/home/thfu/work/TailCorr/Test/sim/in") + 0);
iir_out_x1 = double(importdata("/home/thfu/work/TailCorr/Test/sim/X1_data.dat") - 32768);
iir_out_x2 = double(importdata("/home/thfu/work/TailCorr/Test/sim/X2_data.dat") - 32768);
iir_out_x4 = double(importdata("/home/thfu/work/TailCorr/Test/sim/X4_data.dat") - 32768);
end
% iir_out_x1 = [iir_out_x1' zeros(1,2)]';
% iir_out_x2 = [iir_out_x2' zeros(1,3)]';
% iir_out_x4 = [iir_out_x4' zeros(1,6)]';
alpha = [1757225200, 1045400392, 13740916];
beta = -[1042856 1046395 1047703];
Ystart = 0;
y_revised = TailCorr(alpha,beta,iir_in,Ystart,sel_double);
s = round(y_revised);
N = length(s);
s_r1 = [0 s(1:end-1,1)']';
[s2,s2_mean] = MeanIntp(s,s_r1);
s2 = floor(s2);
s2_mean = floor(s2_mean);
s2_r1 = [0 s2(1:end-1,1)']';
[s4_4,s4_3] = MeanIntp(s2,s2_mean);
[s4_2,s4_1] = MeanIntp(s2_mean,s2_r1);
s4_1 = floor(s4_1);
s4_2 = floor(s4_2);
s4_3 = floor(s4_3);
s4_4 = floor(s4_4);
s_intp2 = zeros(2*N,1);
s_intp2(1:2:2*N) = s2_mean;
s_intp2(2:2:2*N) = s2;
s_intp4 = zeros(4*N,1);
s_intp4(1:4:4*N) = s4_1;
s_intp4(2:4:4*N) = s4_2;
s_intp4(3:4:4*N) = s4_3;
s_intp4(4:4:4*N) = s4_4;
%%%
tau1 = finddelay(y_revised,iir_out_x1);
y_revisedPhi1 = cat(1,zeros(1,tau1)',y_revised(1:end-tau1,1));
figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
diff_plot(iir_out_x1, y_revisedPhi1,'verdi','matlab',[0 2e4])
tau2 = finddelay(s_intp2,iir_out_x2);
y_revisedPhi2 = cat(1,zeros(1,tau2)',s_intp2(1:end-tau2,1));
figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]);
diff_plot(iir_out_x2, y_revisedPhi2,'verdi','matlab',[0 4e4])
tau4 = finddelay(s_intp4,iir_out_x4);
y_revisedPhi4 = cat(1,zeros(1,tau4)',s_intp4(1:end-tau4,1));
figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]);
diff_plot(iir_out_x4, y_revisedPhi4,'verdi','matlab',[0 8e4])

26
script_m/diff_plot.m Executable file
View File

@ -0,0 +1,26 @@
function diff_plot(iir_out, Script_out,leg1,leg2,a)
N = length(iir_out);
n = 0:1:N-1;
diff = iir_out-Script_out;
subplot(211)
plot(n,iir_out,n,Script_out)
xlabel('n')
legend(leg1,leg2)
xlim(a)
title('time domain')
grid on
subplot(212)
plot(n,diff)
xlabel('n')
title('diff')
grid on
hold on
xlim(a)
[diff_max,R_mpos] = max(abs(diff));
plot(n(R_mpos),diff(R_mpos),'r*')
text(n(R_mpos), diff(R_mpos), ['(',num2str(n(R_mpos)),',',num2str(diff(R_mpos)),')'],'color','k');
% max(abs(diff))

19
sim/Makefile Normal file
View File

@ -0,0 +1,19 @@
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
SIMV = ./simv -l sim.log
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -f files.f -top TB -nologo &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~

22
sim/files.f Normal file
View File

@ -0,0 +1,22 @@
../rtl/Tail/diff.v
../rtl/Tail/DW02_mult.v
../rtl/Tail/IIR_Filter.v
../rtl/Tail/lsdacif.v
../rtl/Tail/MeanIntp_8.v
../rtl/Tail/mult_C.v
../rtl/Tail/TailCorr_top.v
//../rtl/Tail/z_dsp.v
../rtl/Tail/sirv_gnrl_dffs.v
../rtl/Tail/sirv_gnrl_xchecker.v
../rtl/nco/coef_s.v
../rtl/nco/nco.v
../rtl/nco/coef_c.v
../rtl/nco/ph2amp.v
../rtl/nco/sin_op.v
../rtl/nco/p_nco.v
../rtl/nco/pipe_add_48bit.v
../rtl/nco/cos_op.v
../rtl/nco/pipe_acc_48bit.v
../rtl/nco/DW_mult_pipe.v
../tb/tb_mean8_top.v
../tb/clk_gen.v

141
tb/clk_gen.v Normal file
View File

@ -0,0 +1,141 @@
module clk_gen(
input rstn,
input clk,
output clk_div16_0,
output clk_div16_1,
output clk_div16_2,
output clk_div16_3,
output clk_div16_4,
output clk_div16_5,
output clk_div16_6,
output clk_div16_7,
output clk_div16_8,
output clk_div16_9,
output clk_div16_a,
output clk_div16_b,
output clk_div16_c,
output clk_div16_d,
output clk_div16_e,
output clk_div16_f,
output clk_h,
output clk_l
);
reg [3:0] cnt_ini;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt_ini <= 4'd0;
else if(cnt_ini <= 4'd7)
cnt_ini <= cnt_ini + 4'd1;
else
cnt_ini <= cnt_ini;
wire div_en;
assign div_en = (cnt_ini ==4'd8)? 1'b1:1'b0;
reg [3:0] cnt_0;
reg [3:0] cnt_1;
reg [3:0] cnt_2;
reg [3:0] cnt_3;
reg [3:0] cnt_4;
reg [3:0] cnt_5;
reg [3:0] cnt_6;
reg [3:0] cnt_7;
reg [3:0] cnt_8;
reg [3:0] cnt_9;
reg [3:0] cnt_a;
reg [3:0] cnt_b;
reg [3:0] cnt_c;
reg [3:0] cnt_d;
reg [3:0] cnt_e;
reg [3:0] cnt_f;
always@(posedge clk or negedge rstn)
if(!rstn) begin
cnt_0 <= 4'h0;
cnt_1 <= 4'h1;
cnt_2 <= 4'h2;
cnt_3 <= 4'h3;
cnt_4 <= 4'h4;
cnt_5 <= 4'h5;
cnt_6 <= 4'h6;
cnt_7 <= 4'h7;
cnt_8 <= 4'h8;
cnt_9 <= 4'h9;
cnt_a <= 4'ha;
cnt_b <= 4'hb;
cnt_c <= 4'hc;
cnt_d <= 4'hd;
cnt_e <= 4'he;
cnt_f <= 4'hf;
end
else if(div_en) begin
cnt_0 <= cnt_0 + 4'd1;
cnt_1 <= cnt_1 + 4'd1;
cnt_2 <= cnt_2 + 4'd1;
cnt_3 <= cnt_3 + 4'd1;
cnt_4 <= cnt_4 + 4'd1;
cnt_5 <= cnt_5 + 4'd1;
cnt_6 <= cnt_6 + 4'd1;
cnt_7 <= cnt_7 + 4'd1;
cnt_8 <= cnt_8 + 4'd1;
cnt_9 <= cnt_9 + 4'd1;
cnt_a <= cnt_a + 4'd1;
cnt_b <= cnt_b + 4'd1;
cnt_c <= cnt_c + 4'd1;
cnt_d <= cnt_d + 4'd1;
cnt_e <= cnt_e + 4'd1;
cnt_f <= cnt_f + 4'd1;
end
else begin
cnt_0 <= cnt_0;
cnt_1 <= cnt_1;
cnt_2 <= cnt_2;
cnt_3 <= cnt_3;
cnt_4 <= cnt_4;
cnt_5 <= cnt_5;
cnt_6 <= cnt_6;
cnt_7 <= cnt_7;
cnt_8 <= cnt_8;
cnt_9 <= cnt_9;
cnt_a <= cnt_a;
cnt_b <= cnt_b;
cnt_c <= cnt_c;
cnt_d <= cnt_d;
cnt_e <= cnt_e;
cnt_f <= cnt_f;
end
assign clk_div16_0 = cnt_0[3];
assign clk_div16_1 = cnt_1[3];
assign clk_div16_2 = cnt_2[3];
assign clk_div16_3 = cnt_3[3];
assign clk_div16_4 = cnt_4[3];
assign clk_div16_5 = cnt_5[3];
assign clk_div16_6 = cnt_6[3];
assign clk_div16_7 = cnt_7[3];
assign clk_div16_8 = cnt_8[3];
assign clk_div16_9 = cnt_9[3];
assign clk_div16_a = cnt_a[3];
assign clk_div16_b = cnt_b[3];
assign clk_div16_c = cnt_c[3];
assign clk_div16_d = cnt_d[3];
assign clk_div16_e = cnt_e[3];
assign clk_div16_f = cnt_f[3];
reg [3:0] cnt_div16;
always@(posedge clk_div16_0 or negedge rstn)
if(!rstn)
cnt_div16 <= 4'd0;
else if(div_en)
cnt_div16 <= cnt_div16 + 4'd1;
else
cnt_div16 <= cnt_div16;
assign clk_h = clk_div16_0;
assign clk_l = cnt_div16[0];
endmodule

61
tb/tb_diff.v Normal file
View File

@ -0,0 +1,61 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_in;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_in = 1'b0;
#3400;
rstn = 1'b1;
din_in = 1'b1;
#6400;
rstn = 1'b1;
din_in = 1'b0;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[16]==1'b1)
$finish(0);
end
reg [47:0] fcw;
diff inst_diff
(
.clk (clk ),
.rstn (rstn ),
.din (din_in ),
.dout (dout_p0 )
);
endmodule

154
tb/tb_iir.v Normal file
View File

@ -0,0 +1,154 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_im;
reg [36:0] a;
reg [36:0] b;
reg [20:0] c;
reg [20:0] d;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] diff_in;
reg en;
wire [1 :0] source_mode;
wire [15 :0] iir_in;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_im = 16'd0;
a = 37'd1757225200;
b = 37'd0;
c = -21'd1042856;
d = 21'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#3600;
en = 1'b1;
#3800;
rstn = 1'b1;
din_imp = 16'd32767;
din_rect = 16'd30000;
#400;
din_imp = 16'd0;
#12000;
din_rect = 16'd0;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
diff_in <= 16'd0;
end
else
din_cos <= cos;
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : diff_in = din_imp;
2'b01 : diff_in = din_rect;
2'b10 : diff_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
diff inst_diff
(
.clk (clk ),
.en (en ),
.rstn (rstn ),
.din (diff_in ),
.dout (iir_in )
);
IIR_Filter inst1_IIR_Filter
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din_re (iir_in ),
.din_im (din_im ),
.a_re (a ),
.a_im (b ),
.b_re (c ),
.b_im (d ),
.dout (dout_p0 )
);
integer signed In_fid;
integer signed Out_fid;
initial begin
#0;
In_fid = $fopen("./in");
Out_fid = $fopen("./out");
end
always@(posedge clk)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk)
$fwrite(Out_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
endmodule

152
tb/tb_iir.v.bak Normal file
View File

@ -0,0 +1,152 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_im;
reg [31:0] a;
reg [31:0] b;
reg [31:0] c;
reg [31:0] d;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg en;
reg [15 :0] diff_in;
wire [1 :0] source_mode;
wire [15 :0] iir_in;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_im = 16'd0;
a = 32'd13740916;
b = 32'd0;
c = -32'd1047703;
d = 32'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#3600;
en = 16'd0;
#3800;
rstn = 1'b1;
din_imp = 16'd32767;
din_rect = 16'd32767;
#400;
din_imp = 16'd0;
#12000;
din_rect = 16'd0;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
diff_in <= 16'd0;
end
else
din_cos <= cos;
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : diff_in = din_imp;
2'b01 : diff_in = din_rect;
2'b10 : diff_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
diff inst_diff
(
.clk (clk ),
.rstn (rstn ),
.din (diff_in ),
.dout (iir_in )
);
IIR_Filter inst1_IIR_Filter
(
.clk (clk ),
.rstn (rstn ),
.din_re (iir_in ),
.din_im (din_im ),
.a_re (a ),
.a_im (b ),
.b_re (c ),
.b_im (d ),
.dout (dout_p0 )
);
integer signed In_fid;
integer signed Out_fid;
initial begin
#0;
In_fid = $fopen("./in");
Out_fid = $fopen("./out");
end
always@(posedge clk)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk)
$fwrite(Out_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
endmodule

98
tb/tb_mean2.v Normal file
View File

@ -0,0 +1,98 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [15:0] din_in;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
din_in = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
always@(posedge clk or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
MeanIntp2 inst_MeanIntp2
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.din (cos & {16{en}} ),
.dout_m (dout_p0 ),
.dout_o (dout_p1 )
);
reg [15:0] cs_wave;
always@(posedge clk) cs_wave = dout_p1;
always@(negedge clk) cs_wave = dout_p0;
endmodule

142
tb/tb_mean4.v Normal file
View File

@ -0,0 +1,142 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
MeanIntp4 inst_MeanIntp4
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.din (cos & {16{en}} ),
.dout4_0 (dout_p0 ),
.dout4_1 (dout_p1 ),
.dout4_2 (dout_p2 ),
.dout4_3 (dout_p3 )
);
reg [15:0] cs_wave;
always@(posedge clk_div16_e) cs_wave = dout_p0;
always@(posedge clk_div16_a) cs_wave = dout_p1;
always@(posedge clk_div16_6) cs_wave = dout_p2;
always@(posedge clk_div16_2) cs_wave = dout_p3;
endmodule

164
tb/tb_mean4_top.v Normal file
View File

@ -0,0 +1,164 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
MeanIntp4_top inst_MeanIntp4
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (cos & {16{en}} ),
.dout_0 (dout_p0 ),
.dout_1 (dout_p1 ),
.dout_2 (dout_p2 ),
.dout_3 (dout_p3 )
);
reg [15:0] cs_wave;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
endcase
join
endmodule

164
tb/tb_mean8_top.v Normal file
View File

@ -0,0 +1,164 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg en;
reg [21:0] cnt;
initial begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
#300;
rstn = 1'b1;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial begin
wait(cnt[17]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
begin
if(cnt >= 2047 )
begin
en <= 1'b1;
end
else
begin
en <= 1'b0;
end
end
reg [47:0] fcw;
initial begin
fcw = 48'h0840_0000_0000;
end
wire [15:0] cos;
wire [15:0] sin;
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [15:0] dout_p4;
wire [15:0] dout_p5;
wire [15:0] dout_p6;
wire [15:0] dout_p7;
assign intp_mode = 2'b10;
MeanIntp_8 inst_MeanIntp8
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.din (cos & {16{en}} ),
.dout_0 (dout_p0 ),
.dout_1 (dout_p1 ),
.dout_2 (dout_p2 ),
.dout_3 (dout_p3 ),
.dout_4 (dout_p4 ),
.dout_5 (dout_p5 ),
.dout_6 (dout_p6 ),
.dout_7 (dout_p7 )
);
reg [15:0] cs_wave;
always@(*)
fork
// begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_c) cs_wave = dout_p1;
@(posedge clk_div16_a) cs_wave = dout_p2;
@(posedge clk_div16_8) cs_wave = dout_p3;
@(posedge clk_div16_6) cs_wave = dout_p4;
@(posedge clk_div16_4) cs_wave = dout_p5;
@(posedge clk_div16_2) cs_wave = dout_p6;
@(posedge clk_div16_0) cs_wave = dout_p7;
// end
join
endmodule

391
tb/tb_top.v Normal file
View File

@ -0,0 +1,391 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_im;
reg [31:0] a0_re;
reg [31:0] a0_im;
reg [31:0] b0_re;
reg [31:0] b0_im;
reg [31:0] a1_re;
reg [31:0] a1_im;
reg [31:0] b1_re;
reg [31:0] b1_im;
reg [31:0] a2_re;
reg [31:0] a2_im;
reg [31:0] b2_re;
reg [31:0] b2_im;
reg [31:0] a3_re;
reg [31:0] a3_im;
reg [31:0] b3_re;
reg [31:0] b3_im;
reg [31:0] a4_re;
reg [31:0] a4_im;
reg [31:0] b4_re;
reg [31:0] b4_im;
reg [31:0] a5_re;
reg [31:0] a5_im;
reg [31:0] b5_re;
reg [31:0] b5_im;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] iir_in;
wire [1 :0] source_mode;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
reg en;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
din_im = 16'd0;
a0_re = 32'd1757225200;
a0_im = 32'd0;
b0_re = -32'd1042856;
b0_im = 32'd0;
a1_re = 32'd1045400392;
a1_im = 32'd0;
b1_re = -32'd1046395;
b1_im = 32'd0;
a2_re = 32'd13740916;
a2_im = 32'd0;
b2_re = -32'd1047703;
b2_im = 32'd0;
a3_re = 32'd0;
a3_im = 32'd0;
b3_re = -32'd0;
b3_im = 32'd0;
a4_re = 32'd0;
a4_im = 32'd0;
b4_re = -32'd0;
b4_im = 32'd0;
a5_re = 32'd0;
a5_im = 32'd0;
b5_re = -32'd0;
b5_im = 32'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#300;
rstn = 1'b1;
#16600300;
// din_imp = 16'd30000;
// din_rect = 16'd30000;
// en = 1'b1;
#6400;
// din_imp = 16'd0;
#64000;
// din_rect = 16'd0;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
din_imp <= 22'd0;
else if(cnt == 100)
begin
din_imp <= 16'd32767;
//en <= 1'b1;
end
else
din_imp <= 'h0;
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
en <= 22'd0;
else if(cnt >= 100 )
begin
en <= 1'b1;
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
iir_in <= 16'd0;
end
else
din_cos <= cos;
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : iir_in = din_imp;
2'b01 : iir_in = din_rect;
2'b10 : iir_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
z_dsp inst_Z_dsp
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_p0 ),
.dout1 (dout_p1 ),
.dout2 (dout_p2 ),
.dout3 (dout_p3 )
);
reg [15:0] cs_wave = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
endcase
join
integer signed In_fid;
integer X1_fid;
integer X2_fid;
integer X4_fid;
initial begin
#0;
In_fid = $fopen("./in");
case (intp_mode)
2'b00 : X1_fid = $fopen("./X1_data.dat");
2'b01 : X2_fid = $fopen("./X2_data.dat");
2'b10 : X4_fid = $fopen("./X4_data.dat");
endcase
end
always@(posedge clk_div16_f)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{{iir_in[15]}},iir_in[14:0]});
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
end
2'b01 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
end
2'b10 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
end
endcase
join
/*
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
always@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
always@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
*/
endmodule

391
tb/tb_top.v.bak Normal file
View File

@ -0,0 +1,391 @@
module TB();
initial
begin
$fsdbDumpfile("TB.fsdb");
$fsdbDumpvars(0, TB);
end
reg clk;
reg rstn;
reg [15:0] din_im;
reg [31:0] a0_re;
reg [31:0] a0_im;
reg [31:0] b0_re;
reg [31:0] b0_im;
reg [31:0] a1_re;
reg [31:0] a1_im;
reg [31:0] b1_re;
reg [31:0] b1_im;
reg [31:0] a2_re;
reg [31:0] a2_im;
reg [31:0] b2_re;
reg [31:0] b2_im;
reg [31:0] a3_re;
reg [31:0] a3_im;
reg [31:0] b3_re;
reg [31:0] b3_im;
reg [31:0] a4_re;
reg [31:0] a4_im;
reg [31:0] b4_re;
reg [31:0] b4_im;
reg [31:0] a5_re;
reg [31:0] a5_im;
reg [31:0] b5_re;
reg [31:0] b5_im;
reg [47:0] fcw;
reg [21:0] cnt;
reg [15:0] din_imp;
reg [15:0] din_rect;
reg [15:0] din_cos;
reg [15:0] iir_in;
wire [1 :0] source_mode;
wire [15:0] cos;
wire [15:0] sin;
wire [15:0] dout_p0;
reg en;
initial
begin
#0;
rstn = 1'b0;
clk = 1'b0;
en = 1'b0;
din_im = 16'd0;
a0_re = 32'd1757225200;
a0_im = 32'd0;
b0_re = -32'd1042856;
b0_im = 32'd0;
a1_re = 32'd1045400392;
a1_im = 32'd0;
b1_re = -32'd1046395;
b1_im = 32'd0;
a2_re = 32'd13740916;
a2_im = 32'd0;
b2_re = -32'd1047703;
b2_im = 32'd0;
a3_re = 32'd0;
a3_im = 32'd0;
b3_re = -32'd0;
b3_im = 32'd0;
a4_re = 32'd0;
a4_im = 32'd0;
b4_re = -32'd0;
b4_im = 32'd0;
a5_re = 32'd0;
a5_im = 32'd0;
b5_re = -32'd0;
b5_im = 32'd0;
fcw = 48'h0840_0000_0000;
din_imp = 16'd0;
din_rect = 16'd0;
din_cos = 16'd0;
#300;
rstn = 1'b1;
#16600300;
// din_imp = 16'd30000;
// din_rect = 16'd30000;
// en = 1'b1;
#6400;
// din_imp = 16'd0;
#64000;
// din_rect = 16'd0;
end
always #200 clk = ~clk;
wire clk_div16_0;
wire clk_div16_1;
wire clk_div16_2;
wire clk_div16_3;
wire clk_div16_4;
wire clk_div16_5;
wire clk_div16_6;
wire clk_div16_7;
wire clk_div16_8;
wire clk_div16_9;
wire clk_div16_a;
wire clk_div16_b;
wire clk_div16_c;
wire clk_div16_d;
wire clk_div16_e;
wire clk_div16_f;
clk_gen inst_clk_gen(
.rstn (rstn ),
.clk (clk ),
.clk_div16_0 (clk_div16_0 ),
.clk_div16_1 (clk_div16_1 ),
.clk_div16_2 (clk_div16_2 ),
.clk_div16_3 (clk_div16_3 ),
.clk_div16_4 (clk_div16_4 ),
.clk_div16_5 (clk_div16_5 ),
.clk_div16_6 (clk_div16_6 ),
.clk_div16_7 (clk_div16_7 ),
.clk_div16_8 (clk_div16_8 ),
.clk_div16_9 (clk_div16_9 ),
.clk_div16_a (clk_div16_a ),
.clk_div16_b (clk_div16_b ),
.clk_div16_c (clk_div16_c ),
.clk_div16_d (clk_div16_d ),
.clk_div16_e (clk_div16_e ),
.clk_div16_f (clk_div16_f ),
.clk_h (clk_h ),
.clk_l (clk_l )
);
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
cnt <= 22'd0;
else
cnt <= cnt + 22'd1;
initial
begin
wait(cnt[16]==1'b1)
$finish(0);
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
din_imp <= 22'd0;
else if(cnt == 100)
begin
din_imp <= 16'd32767;
//en <= 1'b1;
end
else
din_imp <= 'h0;
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
din_rect <= 22'd0;
else if(cnt >= 100 && cnt <=10100)
begin
din_rect <= 16'd30000;
end
else
begin
din_rect <= 16'd0;
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
en <= 22'd0;
else if(cnt >= 100 )
begin
en <= 1'b1;
end
always@(posedge clk_div16_f or negedge rstn)
if(!rstn)
begin
din_cos <= 16'd0;
iir_in <= 16'd0;
end
else
din_cos <= cos;
assign source_mode = 2'b01;
always @(*)
case(source_mode)
2'b00 : iir_in = din_imp;
2'b01 : iir_in = din_rect;
2'b10 : iir_in = din_cos;
endcase
NCO inst_nco_0(
.clk (clk_div16_f ),
.rstn (rstn ),
.phase_manual_clr (1'b0 ),
.phase_auto_clr (1'b0 ),
.fcw (fcw ),
.pha (16'd0 ),
.cos (cos ),
.sin (sin )
);
wire [15:0] dout_p0;
wire [15:0] dout_p1;
wire [15:0] dout_p2;
wire [15:0] dout_p3;
wire [1:0] intp_mode;
assign intp_mode = 2'b10;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
z_dsp inst_Z_dsp
(
.clk (clk_div16_f ),
.rstn (rstn ),
.en (en ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in & {16{en}} ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_p0 ),
.dout1 (dout_p1 ),
.dout2 (dout_p2 ),
.dout3 (dout_p3 )
);
reg [15:0] cs_wave = 0;
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
end
2'b01 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_6) cs_wave = dout_p1;
end
2'b10 :
begin
@(posedge clk_div16_e) cs_wave = dout_p0;
@(posedge clk_div16_a) cs_wave = dout_p1;
@(posedge clk_div16_6) cs_wave = dout_p2;
@(posedge clk_div16_2) cs_wave = dout_p3;
end
endcase
join
integer signed In_fid;
integer X1_fid;
integer X2_fid;
integer X4_fid;
initial begin
#0;
In_fid = $fopen("./in");
case (intp_mode)
2'b00 : X1_fid = $fopen("./X1_data.dat");
2'b01 : X2_fid = $fopen("./X2_data.dat");
2'b10 : X4_fid = $fopen("./X4_data.dat");
endcase
end
always@(posedge clk_div16_f)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{{iir_in[15]}},iir_in[14:0]});
always@(*)
fork
case (intp_mode)
2'b00 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
end
2'b01 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
end
2'b10 :
begin
@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
end
endcase
join
/*
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
always@(posedge clk_div16_e)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
always@(posedge clk_div16_a)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
always@(posedge clk_div16_6)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
always@(posedge clk_div16_2)
if(cnt >= 90)
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
*/
endmodule