v04-spi ram delete unnecessary ports and add related .m
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9068d5393d
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ef140f0245
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@ -0,0 +1,45 @@
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clc;clear
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%conver case from bin2dec
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data_bin = textread("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/case/TC_SingleWaveCombine_bin.txt",'%s');
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data_dec = bin2dec(data_bin);
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data_hex = string(dec2hex(data_dec,8));
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%%
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%read data
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clc;clear;close all
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dout0 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout0.dat")-32768;
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dout1 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout1.dat")-32768;
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dout2 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout2.dat")-32768;
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dout3 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout3.dat")-32768;
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en = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/en.dat" ) ;
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N_all = length(dout0);
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cs_wave_all(1:4:4*N_all) = dout0;
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cs_wave_all(2:4:4*N_all) = dout1;
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cs_wave_all(3:4:4*N_all) = dout2;
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cs_wave_all(4:4:4*N_all) = dout3;
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start_indices = find(en(1:end-1) == 0 & en(2:end) == 1) + 1; %point from 0 to 1
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end_indices = find(en(1:end-1) == 1 & en(2:end) == 0);
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figure()
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for i = 1:length(start_indices)
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N = end_indices(i) - start_indices(i) + 1;
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cs_wave{i}(1:4:4*N) = dout0(start_indices(i):end_indices(i));
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cs_wave{i}(2:4:4*N) = dout1(start_indices(i):end_indices(i));
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cs_wave{i}(3:4:4*N) = dout2(start_indices(i):end_indices(i));
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cs_wave{i}(4:4:4*N) = dout3(start_indices(i):end_indices(i));
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subplot(20,5,i);
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plot(cs_wave{i});
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end
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% signalAnalyzer(cs_wave_all,'SampleRate',1);
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%%
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N = 31; % length of data
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fs = 1;
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fe = 0.3; % center frequency
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D = 1;
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nfft = 32;
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[y,freq]=exzfft_ma(cs_wave_split{1},fe,fs,nfft,D);
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figure(1)
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plot(freq,abs(y))
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@ -0,0 +1,24 @@
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function [y,freq,c]=exzfft_ma(x,fe,fs,nfft,D)
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nt=length(x); % ¼ÆËã¶ÁÈëÊý¾Ý³¤¶È
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fi=fe-fs/D/2; % ¼ÆËãϸ»¯½ØֹƵÂÊÏÂÏÞ
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fa=fi+fs/D; % ¼ÆËãϸ»¯½ØֹƵÂÊÉÏÏÞ
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na=round(0.5 * nt/D+1); % È·¶¨µÍͨÂ˲¨Æ÷½ØֹƵÂʶÔÓ¦µÄÆ×ÏßÌõÊý
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% ƵÒÆ
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n=0: nt-1; % ÐòÁÐË÷ÒýºÅ
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b=n*pi* (fi+fa)/fs; % ÉèÖõ¥Î»ÐýתÒò×Ó
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y=x.*exp(-1i*b); % ½øÐÐƵÒÆ
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b= fft(y, nt); % FFT
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% µÍͨÂ˲¨ºÍϲÉÑù
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a(1: na) =b(1: na); % È¡ÕýƵÂʲ¿·ÖµÄµÍƵ³É·Ö
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a(nt-na+2 : nt) =b(nt-na+2 : nt); % È¡¸ºÆµÂʲ¿·ÖµÄµÍƵ³É·Ö
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b=ifft(a, nt); % IFFT
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c=b(1 : D: nt); % ϲÉÑù
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% Çóϸ»¯ÆµÆ×
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y=fft(c, nfft) * 2/nfft;% ÔÙÒ»´ÎFFT
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y=fftshift(y); % ÖØÐÂÅÅÁÐ
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freq=fi+(0:nfft-1)*fs/D/nfft; % ƵÂÊÉèÖÃ
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figure
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plot(freq,20*log10(y))
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grid on
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@ -54,48 +54,24 @@ module sram_z_top(
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// values are read as the chip ID number
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// values are read as the chip ID number
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//irq
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//irq
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,output irq
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,output irq
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,output [5 :0] PO_ch0_att // CH0 Attenuator Control Bit
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//tx_sram port
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//tx_sram port
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,input [31 :0] din
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,input [31 :0] din
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,input [15 :0] data_length
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,input [15 :0] data_length
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,output data_done_all
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,output data_done_all
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,output data_out_per
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,output data_out_per
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,input ch0_dac_Cal_end
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,input ch0_dc_Cal_end
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//digital_top port
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//digital_top port
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,output oen
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,output oen
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//rx_sram port
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//rx_sram port
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,input data_rden_rx
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,input data_rden_rx
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,output [31:0] Rdata_PC
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,output [31:0] Rdata_PC
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// PLL LOCK
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//------------------------------Ch0 DAC cfg pin----------------------------------------------------
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,output [2 :0] ch0_dac_addr
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,output [2 :0] ch0_dac_dw
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,output [8 :0] ch0_dac_ref
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,output [16 :0] ch0_dac_Prbs_rst0
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,output [16 :0] ch0_dac_Prbs_set0
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,output [16 :0] ch0_dac_Prbs_rst1
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,output [16 :0] ch0_dac_Prbs_set1
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,output ch0_dac_Cal_sig
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,output ch0_dac_Cal_rstn
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,output ch0_dac_Cal_div_rstn
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,input ch0_dac_Cal_end
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,output [2 :0] ch0_dac_Ctrlp
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,output [2 :0] ch0_dac_Ctrln
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//------------------------------Ch0 DC Bias cfg pin----------------------------------------------------
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,output [2 :0] ch0_dc_addr
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,output [2 :0] ch0_dc_dw
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,output [8 :0] ch0_dc_ref
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,output ch0_dc_Cal_sig
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,output ch0_dc_Cal_rstn
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,output ch0_dc_Cal_div_rstn
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,input ch0_dc_Cal_end
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//------------------------------Ch0 DSP data out----------------------------------------------------
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//------------------------------Ch0 DSP data out----------------------------------------------------
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,output [15 :0] ch0_z_dsp_dout0
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,output [15 :0] ch0_z_dsp_dout0
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,output [15 :0] ch0_z_dsp_dout1
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,output [15 :0] ch0_z_dsp_dout1
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,output [15 :0] ch0_z_dsp_dout2
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,output [15 :0] ch0_z_dsp_dout2
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,output [15 :0] ch0_z_dsp_dout3
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,output [15 :0] ch0_z_dsp_dout3
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,output [15 :0] ch0_dc_bias_o
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,output ch0_z_DEM_MSB_vld
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,output ch0_dc_bias_latch
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);
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);
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//tx_sram signal
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//tx_sram signal
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@ -218,7 +194,7 @@ z_chip_top inst_chip_top (
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//irq
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//irq
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,.PO_irq (irq )// Interrupt signal in the chip, high level active
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,.PO_irq (irq )// Interrupt signal in the chip, high level active
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//Attenuator Control Bit\u200c
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//Attenuator Control Bit\u200c
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,.PO_ch0_att (PO_ch0_att ) // CH0 Attenuator Control Bit
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,.PO_ch0_att ( ) // CH0 Attenuator Control Bit
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`ifdef CHANNEL_IS_FOUR
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`ifdef CHANNEL_IS_FOUR
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,.PO_ch1_att ( ) // CH1 Attenuator Control Bit
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,.PO_ch1_att ( ) // CH1 Attenuator Control Bit
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,.PO_ch2_att ( ) // CH2 Attenuator Control Bit
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,.PO_ch2_att ( ) // CH2 Attenuator Control Bit
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@ -303,26 +279,26 @@ z_chip_top inst_chip_top (
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,.afc_end_flag ( )
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,.afc_end_flag ( )
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,.clk_resv ( )
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,.clk_resv ( )
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//------------------------------Ch0 DAC cfg pin----------------------------------------------------
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//------------------------------Ch0 DAC cfg pin----------------------------------------------------
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,.ch0_dac_addr (ch0_dac_addr )
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,.ch0_dac_addr ()
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,.ch0_dac_dw (ch0_dac_dw )
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,.ch0_dac_dw ()
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,.ch0_dac_ref (ch0_dac_ref )
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,.ch0_dac_ref ()
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,.ch0_dac_Prbs_rst0 (ch0_dac_Prbs_rst0 )
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,.ch0_dac_Prbs_rst0 ()
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,.ch0_dac_Prbs_set0 (ch0_dac_Prbs_set0 )
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,.ch0_dac_Prbs_set0 ()
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,.ch0_dac_Prbs_rst1 (ch0_dac_Prbs_rst1 )
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,.ch0_dac_Prbs_rst1 ()
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,.ch0_dac_Prbs_set1 (ch0_dac_Prbs_set1 )
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,.ch0_dac_Prbs_set1 ()
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,.ch0_dac_Cal_sig (ch0_dac_Cal_sig )
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,.ch0_dac_Cal_sig ()
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,.ch0_dac_Cal_rstn (ch0_dac_Cal_rstn )
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,.ch0_dac_Cal_rstn ()
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,.ch0_dac_Cal_div_rstn(ch0_dac_Cal_div_rstn)
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,.ch0_dac_Cal_div_rstn()
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,.ch0_dac_Cal_end (ch0_dac_Cal_end)
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,.ch0_dac_Cal_end (ch0_dac_Cal_end)
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,.ch0_dac_Ctrlp (ch0_dac_Ctrlp )
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,.ch0_dac_Ctrlp ()
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,.ch0_dac_Ctrln (ch0_dac_Ctrln )
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,.ch0_dac_Ctrln ()
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//------------------------------Ch0 DC Bias cfg pin----------------------------------------------------
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//------------------------------Ch0 DC Bias cfg pin----------------------------------------------------
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,.ch0_dc_addr (ch0_dc_addr )
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,.ch0_dc_addr ()
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,.ch0_dc_dw (ch0_dc_dw )
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,.ch0_dc_dw ()
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,.ch0_dc_ref (ch0_dc_ref )
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,.ch0_dc_ref ()
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,.ch0_dc_Cal_sig (ch0_dc_Cal_sig )
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,.ch0_dc_Cal_sig ()
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,.ch0_dc_Cal_rstn (ch0_dc_Cal_rstn )
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,.ch0_dc_Cal_rstn ()
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,.ch0_dc_Cal_div_rstn (ch0_dc_Cal_div_rstn)
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,.ch0_dc_Cal_div_rstn ()
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,.ch0_dc_Cal_end (ch0_dc_Cal_end)
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,.ch0_dc_Cal_end (ch0_dc_Cal_end)
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`ifdef CHANNEL_IS_FOUR
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`ifdef CHANNEL_IS_FOUR
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//------------------------------Ch1 DAC cfg pin----------------------------------------------------
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//------------------------------Ch1 DAC cfg pin----------------------------------------------------
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@ -406,8 +382,9 @@ z_chip_top inst_chip_top (
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,.ch0_z_DEM_LSB_OUT1 (ch0_z_DEM_LSB_OUT1)
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,.ch0_z_DEM_LSB_OUT1 (ch0_z_DEM_LSB_OUT1)
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,.ch0_z_DEM_LSB_OUT2 (ch0_z_DEM_LSB_OUT2)
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,.ch0_z_DEM_LSB_OUT2 (ch0_z_DEM_LSB_OUT2)
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,.ch0_z_DEM_LSB_OUT3 (ch0_z_DEM_LSB_OUT3)
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,.ch0_z_DEM_LSB_OUT3 (ch0_z_DEM_LSB_OUT3)
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,.ch0_dc_bias_o (ch0_dc_bias_o )
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,.ch0_z_DEM_MSB_vld (ch0_z_DEM_MSB_vld )
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,.ch0_dc_bias_latch (ch0_dc_bias_latch )
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,.ch0_dc_bias_o ( )
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,.ch0_dc_bias_latch ( )
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`endif
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`endif
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`ifdef CHANNEL_IS_FOUR
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`ifdef CHANNEL_IS_FOUR
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//------------------------------Ch1 DSP data out----------------------------------------------------
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//------------------------------Ch1 DSP data out----------------------------------------------------
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@ -424,6 +401,7 @@ z_chip_top inst_chip_top (
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,.ch1_z_DEM_LSB_OUT1 ( )
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,.ch1_z_DEM_LSB_OUT1 ( )
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,.ch1_z_DEM_LSB_OUT2 ( )
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,.ch1_z_DEM_LSB_OUT2 ( )
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,.ch1_z_DEM_LSB_OUT3 ( )
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,.ch1_z_DEM_LSB_OUT3 ( )
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,.ch1_z_DEM_MSB_vld ( )
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,.ch1_dc_bias_o ( )
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,.ch1_dc_bias_o ( )
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,.ch1_dc_bias_latch ( )
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,.ch1_dc_bias_latch ( )
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`endif
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`endif
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@ -441,6 +419,7 @@ z_chip_top inst_chip_top (
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,.ch2_z_DEM_LSB_OUT1 ( )
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,.ch2_z_DEM_LSB_OUT1 ( )
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,.ch2_z_DEM_LSB_OUT2 ( )
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,.ch2_z_DEM_LSB_OUT2 ( )
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,.ch2_z_DEM_LSB_OUT3 ( )
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,.ch2_z_DEM_LSB_OUT3 ( )
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,.ch2_z_DEM_MSB_vld ( )
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,.ch2_dc_bias_o ( )
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,.ch2_dc_bias_o ( )
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,.ch2_dc_bias_latch ( )
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,.ch2_dc_bias_latch ( )
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`endif
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`endif
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@ -458,6 +437,7 @@ z_chip_top inst_chip_top (
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,.ch3_z_DEM_LSB_OUT1 ( )
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,.ch3_z_DEM_LSB_OUT1 ( )
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,.ch3_z_DEM_LSB_OUT2 ( )
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,.ch3_z_DEM_LSB_OUT2 ( )
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,.ch3_z_DEM_LSB_OUT3 ( )
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,.ch3_z_DEM_LSB_OUT3 ( )
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,.ch3_z_DEM_MSB_vld ( )
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,.ch3_dc_bias_o ( )
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,.ch3_dc_bias_o ( )
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,.ch3_dc_bias_latch ( )
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,.ch3_dc_bias_latch ( )
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`endif
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`endif
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