diff --git a/script_m/DataShow.m b/script_m/DataShow.m new file mode 100644 index 0000000..ac12adb --- /dev/null +++ b/script_m/DataShow.m @@ -0,0 +1,45 @@ +clc;clear +%conver case from bin2dec +data_bin = textread("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/case/TC_SingleWaveCombine_bin.txt",'%s'); +data_dec = bin2dec(data_bin); +data_hex = string(dec2hex(data_dec,8)); +%% +%read data +clc;clear;close all +dout0 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout0.dat")-32768; +dout1 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout1.dat")-32768; +dout2 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout2.dat")-32768; +dout3 = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/dout3.dat")-32768; +en = importdata("/home/thfu/work/Z-noSFQ/EZQ-Z-M-v1.0/FIL/sim/en.dat" ) ; + +N_all = length(dout0); +cs_wave_all(1:4:4*N_all) = dout0; +cs_wave_all(2:4:4*N_all) = dout1; +cs_wave_all(3:4:4*N_all) = dout2; +cs_wave_all(4:4:4*N_all) = dout3; + +start_indices = find(en(1:end-1) == 0 & en(2:end) == 1) + 1; %point from 0 to 1 +end_indices = find(en(1:end-1) == 1 & en(2:end) == 0); + +figure() +for i = 1:length(start_indices) + N = end_indices(i) - start_indices(i) + 1; + cs_wave{i}(1:4:4*N) = dout0(start_indices(i):end_indices(i)); + cs_wave{i}(2:4:4*N) = dout1(start_indices(i):end_indices(i)); + cs_wave{i}(3:4:4*N) = dout2(start_indices(i):end_indices(i)); + cs_wave{i}(4:4:4*N) = dout3(start_indices(i):end_indices(i)); + subplot(20,5,i); + plot(cs_wave{i}); +end + +% signalAnalyzer(cs_wave_all,'SampleRate',1); +%% +N = 31; % length of data +fs = 1; +fe = 0.3; % center frequency +D = 1; +nfft = 32; +[y,freq]=exzfft_ma(cs_wave_split{1},fe,fs,nfft,D); + +figure(1) +plot(freq,abs(y)) diff --git a/script_m/exzfft_ma.m b/script_m/exzfft_ma.m new file mode 100644 index 0000000..8098776 --- /dev/null +++ b/script_m/exzfft_ma.m @@ -0,0 +1,24 @@ +function [y,freq,c]=exzfft_ma(x,fe,fs,nfft,D) + +nt=length(x); % ¼ÆËã¶ÁÈëÊý¾Ý³¤¶È +fi=fe-fs/D/2; % ¼ÆËãϸ»¯½ØֹƵÂÊÏÂÏÞ +fa=fi+fs/D; % ¼ÆËãϸ»¯½ØֹƵÂÊÉÏÏÞ +na=round(0.5 * nt/D+1); % È·¶¨µÍͨÂ˲¨Æ÷½ØֹƵÂʶÔÓ¦µÄÆ×ÏßÌõÊý +% ƵÒÆ +n=0: nt-1; % ÐòÁÐË÷ÒýºÅ +b=n*pi* (fi+fa)/fs; % ÉèÖõ¥Î»ÐýתÒò×Ó +y=x.*exp(-1i*b); % ½øÐÐƵÒÆ +b= fft(y, nt); % FFT +% µÍͨÂ˲¨ºÍϲÉÑù +a(1: na) =b(1: na); % È¡ÕýƵÂʲ¿·ÖµÄµÍƵ³É·Ö +a(nt-na+2 : nt) =b(nt-na+2 : nt); % È¡¸ºÆµÂʲ¿·ÖµÄµÍƵ³É·Ö +b=ifft(a, nt); % IFFT +c=b(1 : D: nt); % ϲÉÑù +% Çóϸ»¯ÆµÆ× +y=fft(c, nfft) * 2/nfft;% ÔÙÒ»´ÎFFT +y=fftshift(y); % ÖØÐÂÅÅÁÐ +freq=fi+(0:nfft-1)*fs/D/nfft; % ƵÂÊÉèÖà + +figure +plot(freq,20*log10(y)) +grid on \ No newline at end of file diff --git a/spi_tx_rx/top/sram_z_top.v b/spi_tx_rx/top/sram_z_top.v index 83af589..428b911 100644 --- a/spi_tx_rx/top/sram_z_top.v +++ b/spi_tx_rx/top/sram_z_top.v @@ -54,48 +54,24 @@ module sram_z_top( // values are read as the chip ID number //irq ,output irq - ,output [5 :0] PO_ch0_att // CH0 Attenuator Control Bit //tx_sram port ,input [31 :0] din ,input [15 :0] data_length ,output data_done_all ,output data_out_per - + ,input ch0_dac_Cal_end + ,input ch0_dc_Cal_end //digital_top port ,output oen //rx_sram port ,input data_rden_rx ,output [31:0] Rdata_PC - // PLL LOCK - //------------------------------Ch0 DAC cfg pin---------------------------------------------------- - ,output [2 :0] ch0_dac_addr - ,output [2 :0] ch0_dac_dw - ,output [8 :0] ch0_dac_ref - ,output [16 :0] ch0_dac_Prbs_rst0 - ,output [16 :0] ch0_dac_Prbs_set0 - ,output [16 :0] ch0_dac_Prbs_rst1 - ,output [16 :0] ch0_dac_Prbs_set1 - ,output ch0_dac_Cal_sig - ,output ch0_dac_Cal_rstn - ,output ch0_dac_Cal_div_rstn - ,input ch0_dac_Cal_end - ,output [2 :0] ch0_dac_Ctrlp - ,output [2 :0] ch0_dac_Ctrln - //------------------------------Ch0 DC Bias cfg pin---------------------------------------------------- - ,output [2 :0] ch0_dc_addr - ,output [2 :0] ch0_dc_dw - ,output [8 :0] ch0_dc_ref - ,output ch0_dc_Cal_sig - ,output ch0_dc_Cal_rstn - ,output ch0_dc_Cal_div_rstn - ,input ch0_dc_Cal_end //------------------------------Ch0 DSP data out---------------------------------------------------- ,output [15 :0] ch0_z_dsp_dout0 ,output [15 :0] ch0_z_dsp_dout1 ,output [15 :0] ch0_z_dsp_dout2 ,output [15 :0] ch0_z_dsp_dout3 - ,output [15 :0] ch0_dc_bias_o - ,output ch0_dc_bias_latch + ,output ch0_z_DEM_MSB_vld ); //tx_sram signal @@ -218,7 +194,7 @@ z_chip_top inst_chip_top ( //irq ,.PO_irq (irq )// Interrupt signal in the chip, high level active //Attenuator Control Bit\u200c - ,.PO_ch0_att (PO_ch0_att ) // CH0 Attenuator Control Bit + ,.PO_ch0_att ( ) // CH0 Attenuator Control Bit `ifdef CHANNEL_IS_FOUR ,.PO_ch1_att ( ) // CH1 Attenuator Control Bit ,.PO_ch2_att ( ) // CH2 Attenuator Control Bit @@ -303,27 +279,27 @@ z_chip_top inst_chip_top ( ,.afc_end_flag ( ) ,.clk_resv ( ) //------------------------------Ch0 DAC cfg pin---------------------------------------------------- - ,.ch0_dac_addr (ch0_dac_addr ) - ,.ch0_dac_dw (ch0_dac_dw ) - ,.ch0_dac_ref (ch0_dac_ref ) - ,.ch0_dac_Prbs_rst0 (ch0_dac_Prbs_rst0 ) - ,.ch0_dac_Prbs_set0 (ch0_dac_Prbs_set0 ) - ,.ch0_dac_Prbs_rst1 (ch0_dac_Prbs_rst1 ) - ,.ch0_dac_Prbs_set1 (ch0_dac_Prbs_set1 ) - ,.ch0_dac_Cal_sig (ch0_dac_Cal_sig ) - ,.ch0_dac_Cal_rstn (ch0_dac_Cal_rstn ) - ,.ch0_dac_Cal_div_rstn(ch0_dac_Cal_div_rstn) - ,.ch0_dac_Cal_end (ch0_dac_Cal_end ) - ,.ch0_dac_Ctrlp (ch0_dac_Ctrlp ) - ,.ch0_dac_Ctrln (ch0_dac_Ctrln ) + ,.ch0_dac_addr () + ,.ch0_dac_dw () + ,.ch0_dac_ref () + ,.ch0_dac_Prbs_rst0 () + ,.ch0_dac_Prbs_set0 () + ,.ch0_dac_Prbs_rst1 () + ,.ch0_dac_Prbs_set1 () + ,.ch0_dac_Cal_sig () + ,.ch0_dac_Cal_rstn () + ,.ch0_dac_Cal_div_rstn() + ,.ch0_dac_Cal_end (ch0_dac_Cal_end) + ,.ch0_dac_Ctrlp () + ,.ch0_dac_Ctrln () //------------------------------Ch0 DC Bias cfg pin---------------------------------------------------- - ,.ch0_dc_addr (ch0_dc_addr ) - ,.ch0_dc_dw (ch0_dc_dw ) - ,.ch0_dc_ref (ch0_dc_ref ) - ,.ch0_dc_Cal_sig (ch0_dc_Cal_sig ) - ,.ch0_dc_Cal_rstn (ch0_dc_Cal_rstn ) - ,.ch0_dc_Cal_div_rstn (ch0_dc_Cal_div_rstn) - ,.ch0_dc_Cal_end (ch0_dc_Cal_end ) + ,.ch0_dc_addr () + ,.ch0_dc_dw () + ,.ch0_dc_ref () + ,.ch0_dc_Cal_sig () + ,.ch0_dc_Cal_rstn () + ,.ch0_dc_Cal_div_rstn () + ,.ch0_dc_Cal_end (ch0_dc_Cal_end) `ifdef CHANNEL_IS_FOUR //------------------------------Ch1 DAC cfg pin---------------------------------------------------- ,.ch1_dac_addr () @@ -406,8 +382,9 @@ z_chip_top inst_chip_top ( ,.ch0_z_DEM_LSB_OUT1 (ch0_z_DEM_LSB_OUT1) ,.ch0_z_DEM_LSB_OUT2 (ch0_z_DEM_LSB_OUT2) ,.ch0_z_DEM_LSB_OUT3 (ch0_z_DEM_LSB_OUT3) - ,.ch0_dc_bias_o (ch0_dc_bias_o ) - ,.ch0_dc_bias_latch (ch0_dc_bias_latch ) + ,.ch0_z_DEM_MSB_vld (ch0_z_DEM_MSB_vld ) + ,.ch0_dc_bias_o ( ) + ,.ch0_dc_bias_latch ( ) `endif `ifdef CHANNEL_IS_FOUR //------------------------------Ch1 DSP data out---------------------------------------------------- @@ -424,6 +401,7 @@ z_chip_top inst_chip_top ( ,.ch1_z_DEM_LSB_OUT1 ( ) ,.ch1_z_DEM_LSB_OUT2 ( ) ,.ch1_z_DEM_LSB_OUT3 ( ) + ,.ch1_z_DEM_MSB_vld ( ) ,.ch1_dc_bias_o ( ) ,.ch1_dc_bias_latch ( ) `endif @@ -441,6 +419,7 @@ z_chip_top inst_chip_top ( ,.ch2_z_DEM_LSB_OUT1 ( ) ,.ch2_z_DEM_LSB_OUT2 ( ) ,.ch2_z_DEM_LSB_OUT3 ( ) + ,.ch2_z_DEM_MSB_vld ( ) ,.ch2_dc_bias_o ( ) ,.ch2_dc_bias_latch ( ) `endif @@ -458,6 +437,7 @@ z_chip_top inst_chip_top ( ,.ch3_z_DEM_LSB_OUT1 ( ) ,.ch3_z_DEM_LSB_OUT2 ( ) ,.ch3_z_DEM_LSB_OUT3 ( ) + ,.ch3_z_DEM_MSB_vld ( ) ,.ch3_dc_bias_o ( ) ,.ch3_dc_bias_latch ( ) `endif