merge

rtl/z_dsp/TailCorr_top.v

@@ -914,11 +914,7 @@ always  @(posedge clk or negedge rstn)begin
     end
 end
 assign  vldo_r0_l = (dout_p0_r0 == 0  && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0);
-<<<<<<< HEAD
-assign  vldo_r0_h =  vldo_diff_r[18] == 0 &&  vldo_diff_r[17] == 1 ;
-=======
 assign  vldo_r0_h =  vldo_diff_r[16] == 0 &&  vldo_diff_r[15] == 1 ;
->>>>>>> 6e386a27436e98570e4040365931c186c7ddc629
 assign  vldo = vldo_r0;
 endmodule
 

rtl/z_dsp/diff_p.v

@@ -123,6 +123,7 @@ if(rstn==1'b0)begin
     diff_p5_r1 <= 0;
     diff_p6_r1 <= 0;
     diff_p7_r1 <= 0;
+end
 
 wire [15:0] din_wire [0:3];