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Enable of clk_div2 tested on FPGA

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unknown 2024-11-07 10:57:58 +08:00
parent b00693ce73
commit e757bd72c6
1 changed files with 4 additions and 3 deletions
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7
rtl/z_dsp_en_Test.v
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@ -34,6 +34,7 @@
module z_dsp_en_Test module z_dsp_en_Test
( (
clk, clk,
rstn, rstn,
dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode; dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve; //2'b10:Double Double data mode;2'b11:reserve;
@ -128,7 +129,7 @@ always@(posedge clk or negedge rstn)
else else
en <= ~en; en <= ~en;
reg [10:0] vldo_r; reg [13:0] vldo_r;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
@ -137,10 +138,10 @@ always@(posedge clk or negedge rstn)
end end
else else
begin begin
vldo_r <= {vldo_r[10:0], en}; vldo_r <= {vldo_r[13:0], en};
end end
assign vldo = vldo_r[10]; assign vldo = vldo_r[13];
TailCorr_top inst_TailCorr_top TailCorr_top inst_TailCorr_top
( (