From e757bd72c683829dacf9e0ebe5cdc2ef0ebb4c54 Mon Sep 17 00:00:00 2001
From: unknown <2779155576@qq.com>
Date: Thu, 7 Nov 2024 10:57:58 +0800
Subject: [PATCH] Enable of clk_div2 tested on FPGA

---
 rtl/z_dsp_en_Test.v | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/rtl/z_dsp_en_Test.v b/rtl/z_dsp_en_Test.v
index e20e351..d187b22 100644
--- a/rtl/z_dsp_en_Test.v
+++ b/rtl/z_dsp_en_Test.v
@@ -34,6 +34,7 @@
 module 	z_dsp_en_Test	 	
 (
 		 	clk,
+
 		 	rstn,
 		 	dac_mode_sel, 	//2'b00:NRZ mode;2'b01:Double data mode;
                                         //2'b10:Double Double data mode;2'b11:reserve;
@@ -128,7 +129,7 @@ always@(posedge clk or negedge rstn)
         else
 		en  <= ~en;
 
-reg	[10:0]		  vldo_r;
+reg	[13:0]		  vldo_r;
 
 always@(posedge clk or negedge rstn)
 	if(!rstn)
@@ -137,10 +138,10 @@ always@(posedge clk or negedge rstn)
 		end
 	else
 		begin
-			vldo_r	<=	{vldo_r[10:0], en};
+			vldo_r	<=	{vldo_r[13:0], en};
 		end
 
-assign		vldo = vldo_r[10];
+assign		vldo = vldo_r[13];
 
 TailCorr_top	inst_TailCorr_top
                (