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与b2支路合并 

-TailCorr_top.v需要b系数，其它模块做出对应修改
This commit is contained in:
futh0403 2025-03-13 23:33:51 +08:00
parent e297bf11e3 0cfe0c75ce
commit e32b5fa523
18 changed files with 1513 additions and 1625 deletions
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50
rtl/z_dsp/CoefGen.sv
View File

@ -34,6 +34,8 @@ module CoefGen #(
,input signed [31:0] b5_im ,input signed [31:0] b5_im
,output reg signed [31:0] a_re0 ,output reg signed [31:0] a_re0
,output reg signed [31:0] a_im0 ,output reg signed [31:0] a_im0
,output reg signed [31:0] b_re0
,output reg signed [31:0] b_im0
,output reg signed [31:0] ab_re0 ,output reg signed [31:0] ab_re0
,output reg signed [31:0] ab_im0 ,output reg signed [31:0] ab_im0
,output reg signed [31:0] abb_re0 ,output reg signed [31:0] abb_re0
@ -52,6 +54,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im0 ,output reg signed [31:0] b_pow8_im0
,output reg signed [31:0] a_re1 ,output reg signed [31:0] a_re1
,output reg signed [31:0] a_im1 ,output reg signed [31:0] a_im1
,output reg signed [31:0] b_re1
,output reg signed [31:0] b_im1
,output reg signed [31:0] ab_re1 ,output reg signed [31:0] ab_re1
,output reg signed [31:0] ab_im1 ,output reg signed [31:0] ab_im1
,output reg signed [31:0] abb_re1 ,output reg signed [31:0] abb_re1
@ -70,6 +74,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im1 ,output reg signed [31:0] b_pow8_im1
,output reg signed [31:0] a_re2 ,output reg signed [31:0] a_re2
,output reg signed [31:0] a_im2 ,output reg signed [31:0] a_im2
,output reg signed [31:0] b_re2
,output reg signed [31:0] b_im2
,output reg signed [31:0] ab_re2 ,output reg signed [31:0] ab_re2
,output reg signed [31:0] ab_im2 ,output reg signed [31:0] ab_im2
,output reg signed [31:0] abb_re2 ,output reg signed [31:0] abb_re2
@ -88,6 +94,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im2 ,output reg signed [31:0] b_pow8_im2
,output reg signed [31:0] a_re3 ,output reg signed [31:0] a_re3
,output reg signed [31:0] a_im3 ,output reg signed [31:0] a_im3
,output reg signed [31:0] b_re3
,output reg signed [31:0] b_im3
,output reg signed [31:0] ab_re3 ,output reg signed [31:0] ab_re3
,output reg signed [31:0] ab_im3 ,output reg signed [31:0] ab_im3
,output reg signed [31:0] abb_re3 ,output reg signed [31:0] abb_re3
@ -106,6 +114,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im3 ,output reg signed [31:0] b_pow8_im3
,output reg signed [31:0] a_re4 ,output reg signed [31:0] a_re4
,output reg signed [31:0] a_im4 ,output reg signed [31:0] a_im4
,output reg signed [31:0] b_re4
,output reg signed [31:0] b_im4
,output reg signed [31:0] ab_re4 ,output reg signed [31:0] ab_re4
,output reg signed [31:0] ab_im4 ,output reg signed [31:0] ab_im4
,output reg signed [31:0] abb_re4 ,output reg signed [31:0] abb_re4
@ -124,6 +134,8 @@ module CoefGen #(
,output reg signed [31:0] b_pow8_im4 ,output reg signed [31:0] b_pow8_im4
,output reg signed [31:0] a_re5 ,output reg signed [31:0] a_re5
,output reg signed [31:0] a_im5 ,output reg signed [31:0] a_im5
,output reg signed [31:0] b_re5
,output reg signed [31:0] b_im5
,output reg signed [31:0] ab_re5 ,output reg signed [31:0] ab_re5
,output reg signed [31:0] ab_im5 ,output reg signed [31:0] ab_im5
,output reg signed [31:0] abb_re5 ,output reg signed [31:0] abb_re5
@ -267,7 +279,7 @@ mult_C
,.B_width(data_in_width) ,.B_width(data_in_width)
,.C_width(coef_width) ,.C_width(coef_width)
,.D_width(coef_width) ,.D_width(coef_width)
,.frac_coef_width(frac_coef_width) ,.o_width(data_in_width)
) )
inst_c1 ( inst_c1 (
.clk (clk ), .clk (clk ),
@ -290,7 +302,7 @@ mult_C
,.B_width(data_in_width) ,.B_width(data_in_width)
,.C_width(coef_width) ,.C_width(coef_width)
,.D_width(coef_width) ,.D_width(coef_width)
,.frac_coef_width(frac_coef_width) ,.o_width(data_in_width)
) )
inst_c2 ( inst_c2 (
.clk (clk ), .clk (clk ),
@ -320,11 +332,13 @@ reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
reg signed [coef_width-1 :0] ab_pow6_im_r1 ; reg signed [coef_width-1 :0] ab_pow6_im_r1 ;
reg signed [coef_width-1 :0] ab_pow7_re_r1 ; reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
reg signed [coef_width-1 :0] ab_pow7_im_r1 ; reg signed [coef_width-1 :0] ab_pow7_im_r1 ;
reg signed [coef_width-1 :0] bo_re_r1 ;
reg signed [coef_width-1 :0] bo_im_r1 ;
reg signed [coef_width-1 :0] b_pow8_re_r1 ; reg signed [coef_width-1 :0] b_pow8_re_r1 ;
reg signed [coef_width-1 :0] b_pow8_im_r1 ; reg signed [coef_width-1 :0] b_pow8_im_r1 ;
always @(posedge clk or negedge rstn)begin always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin if(!rstn)begin
ao_re_r1 <= 0; ao_re_r1 <= 0;
ao_im_r1 <= 0; ao_im_r1 <= 0;
ab_re_r1 <= 0; ab_re_r1 <= 0;
@ -341,12 +355,16 @@ always @(posedge clk or negedge rstn)begin
ab_pow6_im_r1 <= 0; ab_pow6_im_r1 <= 0;
ab_pow7_re_r1 <= 0; ab_pow7_re_r1 <= 0;
ab_pow7_im_r1 <= 0; ab_pow7_im_r1 <= 0;
bo_re_r1 <= 0;
bo_im_r1 <= 0;
b_pow8_re_r1 <= 0; b_pow8_re_r1 <= 0;
b_pow8_im_r1 <= 0; b_pow8_im_r1 <= 0;
end end
else if(add_cnt0 && cnt0 == 1 && en_r1)begin else if(add_cnt0 && cnt0 == 1 && en_r1)begin
ao_re_r1 <= abo_re; ao_re_r1 <= abo_re;
ao_im_r1 <= abo_im; ao_im_r1 <= abo_im;
bo_re_r1 <= bin_re;
bo_im_r1 <= bin_im;
end end
else if(add_cnt0 && cnt0 == 2 && en_r1)begin else if(add_cnt0 && cnt0 == 2 && en_r1)begin
ab_re_r1 <= abo_re; ab_re_r1 <= abo_re;
@ -404,9 +422,11 @@ sirv_gnrl_dffr #(6) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn); sirv_gnrl_dffr #(6) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn);
sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn); sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn);
always @(posedge clk or negedge rstn) begin always @(posedge clk or negedge rstn) begin
if(rstn == 1'b0) begin if(!rstn) begin
a_re0 <= 0; a_re0 <= 0;
a_im0 <= 0; a_im0 <= 0;
b_re0 <= 0;
b_im0 <= 0;
ab_re0 <= 0; ab_re0 <= 0;
ab_im0 <= 0; ab_im0 <= 0;
abb_re0 <= 0; abb_re0 <= 0;
@ -425,6 +445,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im0 <= 0; b_pow8_im0 <= 0;
a_re1 <= 0; a_re1 <= 0;
a_im1 <= 0; a_im1 <= 0;
b_re1 <= 0;
b_im1 <= 0;
ab_re1 <= 0; ab_re1 <= 0;
ab_im1 <= 0; ab_im1 <= 0;
abb_re1 <= 0; abb_re1 <= 0;
@ -443,6 +465,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im1 <= 0; b_pow8_im1 <= 0;
a_re2 <= 0; a_re2 <= 0;
a_im2 <= 0; a_im2 <= 0;
b_re2 <= 0;
b_im2 <= 0;
ab_re2 <= 0; ab_re2 <= 0;
ab_im2 <= 0; ab_im2 <= 0;
abb_re2 <= 0; abb_re2 <= 0;
@ -461,6 +485,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im2 <= 0; b_pow8_im2 <= 0;
a_re3 <= 0; a_re3 <= 0;
a_im3 <= 0; a_im3 <= 0;
b_re3 <= 0;
b_im3 <= 0;
ab_re3 <= 0; ab_re3 <= 0;
ab_im3 <= 0; ab_im3 <= 0;
abb_re3 <= 0; abb_re3 <= 0;
@ -479,6 +505,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im3 <= 0; b_pow8_im3 <= 0;
a_re4 <= 0; a_re4 <= 0;
a_im4 <= 0; a_im4 <= 0;
b_re4 <= 0;
b_im4 <= 0;
ab_re4 <= 0; ab_re4 <= 0;
ab_im4 <= 0; ab_im4 <= 0;
abb_re4 <= 0; abb_re4 <= 0;
@ -497,6 +525,8 @@ always @(posedge clk or negedge rstn) begin
b_pow8_im4 <= 0; b_pow8_im4 <= 0;
a_re5 <= 0; a_re5 <= 0;
a_im5 <= 0; a_im5 <= 0;
b_re5 <= 0;
b_im5 <= 0;
ab_re5 <= 0; ab_re5 <= 0;
ab_im5 <= 0; ab_im5 <= 0;
abb_re5 <= 0; abb_re5 <= 0;
@ -519,6 +549,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[0]: begin vldi_r10[0]: begin
a_re0 <= ao_re_r1 ; a_re0 <= ao_re_r1 ;
a_im0 <= ao_im_r1 ; a_im0 <= ao_im_r1 ;
b_re0 <= bo_re_r1 ;
b_im0 <= bo_im_r1 ;
ab_re0 <= ab_re_r1 ; ab_re0 <= ab_re_r1 ;
ab_im0 <= ab_im_r1 ; ab_im0 <= ab_im_r1 ;
abb_re0 <= abb_re_r1 ; abb_re0 <= abb_re_r1 ;
@ -539,6 +571,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[1]: begin vldi_r10[1]: begin
a_re1 <= ao_re_r1 ; a_re1 <= ao_re_r1 ;
a_im1 <= ao_im_r1 ; a_im1 <= ao_im_r1 ;
b_re1 <= bo_re_r1 ;
b_im1 <= bo_im_r1 ;
ab_re1 <= ab_re_r1 ; ab_re1 <= ab_re_r1 ;
ab_im1 <= ab_im_r1 ; ab_im1 <= ab_im_r1 ;
abb_re1 <= abb_re_r1 ; abb_re1 <= abb_re_r1 ;
@ -559,6 +593,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[2]: begin vldi_r10[2]: begin
a_re2 <= ao_re_r1 ; a_re2 <= ao_re_r1 ;
a_im2 <= ao_im_r1 ; a_im2 <= ao_im_r1 ;
b_re2 <= bo_re_r1 ;
b_im2 <= bo_im_r1 ;
ab_re2 <= ab_re_r1 ; ab_re2 <= ab_re_r1 ;
ab_im2 <= ab_im_r1 ; ab_im2 <= ab_im_r1 ;
abb_re2 <= abb_re_r1 ; abb_re2 <= abb_re_r1 ;
@ -579,6 +615,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[3]: begin vldi_r10[3]: begin
a_re3 <= ao_re_r1 ; a_re3 <= ao_re_r1 ;
a_im3 <= ao_im_r1 ; a_im3 <= ao_im_r1 ;
b_re3 <= bo_re_r1 ;
b_im3 <= bo_im_r1 ;
ab_re3 <= ab_re_r1 ; ab_re3 <= ab_re_r1 ;
ab_im3 <= ab_im_r1 ; ab_im3 <= ab_im_r1 ;
abb_re3 <= abb_re_r1 ; abb_re3 <= abb_re_r1 ;
@ -599,6 +637,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[4]: begin vldi_r10[4]: begin
a_re4 <= ao_re_r1 ; a_re4 <= ao_re_r1 ;
a_im4 <= ao_im_r1 ; a_im4 <= ao_im_r1 ;
b_re4 <= bo_re_r1 ;
b_im4 <= bo_im_r1 ;
ab_re4 <= ab_re_r1 ; ab_re4 <= ab_re_r1 ;
ab_im4 <= ab_im_r1 ; ab_im4 <= ab_im_r1 ;
abb_re4 <= abb_re_r1 ; abb_re4 <= abb_re_r1 ;
@ -619,6 +659,8 @@ always @(posedge clk or negedge rstn) begin
vldi_r10[5]: begin vldi_r10[5]: begin
a_re5 <= ao_re_r1 ; a_re5 <= ao_re_r1 ;
a_im5 <= ao_im_r1 ; a_im5 <= ao_im_r1 ;
b_re5 <= bo_re_r1 ;
b_im5 <= bo_im_r1 ;
ab_re5 <= ab_re_r1 ; ab_re5 <= ab_re_r1 ;
ab_im5 <= ab_im_r1 ; ab_im5 <= ab_im_r1 ;
abb_re5 <= abb_re_r1 ; abb_re5 <= abb_re_r1 ;

38
rtl/z_dsp/FixRound.v
View File

@ -1,38 +0,0 @@
module FixRound #(
parameter integer Data_width = 8
,parameter integer Fix_frac_coef_width = 31//division
)
(
input clk
,input rstn
,input en
,input signed [Data_width-1:0] din
,output signed [Data_width-1:0] dout
);
reg signed [Data_width-1:0] din_round;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
din_round <= 'h0;
end
else if(en) begin
if(din[Data_width-1] == 1'b0)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
end
else if (din[Data_width-1] == 1'b1)
begin
din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
end
end
else begin
din_round <= din_round;
end
assign dout = din_round;
endmodule

132
rtl/z_dsp/IIR_Filter_p1.v Normal file
View File

@ -0,0 +1,132 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter_p1.v
// Department :
// Author : hdzhang
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.0 2025-03-09 hdzhang
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p1 #(
parameter coef_width = 32
,parameter data_in_width = 16
,parameter cascade_in_width = 37
,parameter temp_var_width = cascade_in_width - 1
,parameter data_out_width = cascade_in_width - 2
)
//H(z) = a / (1 - b*z^-1)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1 :0] din_re // Re(x(t))
,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1))
,input signed [cascade_in_width-1:0] dout_r1_im // Im(y(t-1))
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] b_re
,input signed [coef_width-1 :0] b_im
,output signed [data_out_width-1:0] dout_re // Re(y(t-16))
,output signed [data_out_width-1:0] dout_im // Im(y(t-16))
);
wire signed [temp_var_width-1 :0] x1_re;
wire signed [temp_var_width-1 :0] x1_im;
wire signed [temp_var_width-1 :0] y1_re;
wire signed [temp_var_width-1 :0] y1_im;
wire signed [temp_var_width :0] y_re;
wire signed [temp_var_width :0] y_im;
wire signed [data_out_width-1:0] y_re_trunc;
wire signed [data_out_width-1:0] y_im_trunc;
// x1 = a * din delay M = a*x(t-8)
mult_x
#(
.A_width (data_in_width )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (temp_var_width )
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din_re ),
.c (a_re ),
.d (a_im ),
.Re (x1_re ),
.Im (x1_im )
);
// y1 = b * dout_r1 delay M = b*y(t-9)
// y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8)
mult_C
#(
.A_width (cascade_in_width )
,.B_width (cascade_in_width )
,.C_width (coef_width )
,.D_width (coef_width )
,.o_width (temp_var_width )
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dout_r1_re ),
.b (dout_r1_im ),
.c (b_re ),
.d (b_im ),
.Re (y1_re ),
.Im (y1_im )
);
assign y_re = x1_re + y1_re;
assign y_im = x1_im + y1_im;
// dout = round(y) delay M = round(y(t-16))
trunc #(
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
trunc #(
.diw (temp_var_width+1 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
assign dout_re = y_re_trunc;
assign dout_im = y_im_trunc;
endmodule

215
rtl/z_dsp/IIR_Filter_p8.v
View File

@ -1,42 +1,44 @@
module IIR_Filter_p8 #( module IIR_Filter_p8 #(
parameter data_in_width = 16 parameter coef_width = 32
,parameter coef_width = 32 ,parameter data_in_width = 16
,parameter frac_data_out_width = 20//X for in,5 ,parameter data_out_width = 37
,parameter frac_coef_width = 31//division ,parameter temp_var_width = data_out_width+5
) )
// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8)
( (
input rstn input rstn
,input clk ,input clk
,input en ,input en
,input signed [data_in_width-1:0] dinp0 ,input signed [data_in_width-1 :0] dinp0 //x(8n+16)
,input signed [data_in_width-1:0] dinp1 ,input signed [data_in_width-1 :0] dinp1 //x(8n+15)
,input signed [data_in_width-1:0] dinp2 ,input signed [data_in_width-1 :0] dinp2 //x(8n+14)
,input signed [data_in_width-1:0] dinp3 ,input signed [data_in_width-1 :0] dinp3 //x(8n+13)
,input signed [data_in_width-1:0] dinp4 ,input signed [data_in_width-1 :0] dinp4 //x(8n+12)
,input signed [data_in_width-1:0] dinp5 ,input signed [data_in_width-1 :0] dinp5 //x(8n+11)
,input signed [data_in_width-1:0] dinp6 ,input signed [data_in_width-1 :0] dinp6 //x(8n+10)
,input signed [data_in_width-1:0] dinp7 ,input signed [data_in_width-1 :0] dinp7 //x(8n+9)
,input signed [coef_width-1 :0] a_re ,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im ,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re ,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im ,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] abb_re ,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] abb_im ,input signed [coef_width-1 :0] abb_im
,input signed [coef_width-1 :0] ab_pow3_re ,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow3_im ,input signed [coef_width-1 :0] ab_pow3_im
,input signed [coef_width-1 :0] ab_pow4_re ,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow4_im ,input signed [coef_width-1 :0] ab_pow4_im
,input signed [coef_width-1 :0] ab_pow5_re ,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow5_im ,input signed [coef_width-1 :0] ab_pow5_im
,input signed [coef_width-1 :0] ab_pow6_re ,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow6_im ,input signed [coef_width-1 :0] ab_pow6_im
,input signed [coef_width-1 :0] ab_pow7_re ,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow7_im ,input signed [coef_width-1 :0] ab_pow7_im
,input signed [coef_width-1 :0] b_pow8_re ,input signed [coef_width-1 :0] b_pow8_re
,input signed [coef_width-1 :0] b_pow8_im ,input signed [coef_width-1 :0] b_pow8_im
,output signed [data_in_width-1:0] dout ,output signed [data_out_width-1:0] dout_re // Re(y(8n-8))
,output signed [data_out_width-1:0] dout_im // Im(y(8n-8))
); );
wire signed [data_in_width-1 :0] dinp [7:0]; wire signed [data_in_width-1 :0] dinp [7:0];
@ -69,39 +71,57 @@ assign ab_pow_im[2] = abb_im;
assign ab_pow_im[1] = ab_im; assign ab_pow_im[1] = ab_im;
assign ab_pow_im[0] = a_im; assign ab_pow_im[0] = a_im;
wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7];
wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7];
wire signed [temp_var_width-1 :0] x_re [0:7];
wire signed [temp_var_width-1 :0] x_im [0:7];
wire signed [temp_var_width+3 :0] v_re;
wire signed [temp_var_width+3 :0] v_im;
reg signed [temp_var_width+3 :0] v1_re;
reg signed [temp_var_width+3 :0] v1_im;
wire signed [temp_var_width+3 :0] y_re;
wire signed [temp_var_width+3 :0] y_im;
wire signed [temp_var_width+3 :0] y1_re;
wire signed [temp_var_width+3 :0] y1_im;
wire signed [data_out_width-1:0] y_re_trunc;
wire signed [data_out_width-1:0] y_im_trunc;
// x[0] = (dinp0 * a_re) delay M = a*x(8n+8)
// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7)
// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6)
// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5)
// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4)
// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3)
// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2)
// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1)
genvar i; genvar i;
generate generate
for (i = 0; i < 8; i = i + 1) begin: mult_x_inst for (i = 0; i < 8; i = i + 1) begin: mult_c_inst
mult_x #( mult_x #(
.A_width(data_in_width), .A_width (data_in_width ),
.C_width(coef_width+frac_data_out_width), .C_width (coef_width ),
.D_width(coef_width+frac_data_out_width), .D_width (coef_width ),
.frac_coef_width(frac_coef_width) .o_width (temp_var_width )
) inst_mult_x ( ) inst_c (
.clk (clk), .clk (clk ),
.rstn (rstn), .rstn (rstn ),
.en (en), .en (en ),
.a (dinp[i]), .a (dinp[i] ),
.c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}), .c (ab_pow_re[i] ),
.d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}), .d (ab_pow_im[i] ),
.Re (x_re[i]), .Re (x_re[i] ),
.Im (x_im[i]) .Im (x_im[i] )
); );
end end
endgenerate endgenerate
wire signed [data_in_width+frac_data_out_width+3:0] v_re;
wire signed [data_in_width+frac_data_out_width+3:0] v_im;
// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)}
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7]; assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7];
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7]; assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7];
reg signed [data_in_width+frac_data_out_width+3:0] v1_re;
reg signed [data_in_width+frac_data_out_width+3:0] v1_im;
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
begin begin
@ -119,76 +139,47 @@ always @(posedge clk or negedge rstn)
v1_im <= v1_im; v1_im <= v1_im;
end end
wire signed [data_in_width+frac_data_out_width+3:0] y_re;
wire signed [data_in_width+frac_data_out_width+3:0] y_im;
wire signed [data_in_width+frac_data_out_width+3:0] y1_re;
wire signed [data_in_width+frac_data_out_width+3:0] y1_im;
reg signed [data_in_width-1:0] dout_re;
// y1 = (b^8 * y) delay M = b^8*y(8n-8)
// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n)
mult_C mult_C
#( #(
.A_width(data_in_width+frac_data_out_width+4) .A_width (temp_var_width+4 )
,.B_width(data_in_width+frac_data_out_width+4) ,.B_width (temp_var_width+4 )
,.C_width(coef_width) ,.C_width (coef_width )
,.D_width(coef_width) ,.D_width (coef_width )
,.frac_coef_width(frac_coef_width) ,.o_width (temp_var_width+4 )
) )
inst_c9 ( inst_c9 (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.a (y_re ), .a (y_re ),
.b (y_im ), .b (y_im ),
.c (b_pow8_re ), .c (b_pow8_re ),
.d (b_pow8_im ), .d (b_pow8_im ),
.Re (y1_re ),//b^8*y(n-1) .Re (y1_re ),
.Im (y1_im ) .Im (y1_im )
); );
assign y_re = v1_re + y1_re; assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im; assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+3:0] dout_round; // dout = round(y) delay M = round(y(8n-8))
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u1 (clk, rstn, en, y_re, y_re_trunc);
trunc #(
.diw (temp_var_width+4 )
,.msb (temp_var_width-1 )
,.lsb (temp_var_width-data_out_width )
) round_u2 (clk, rstn, en, y_im, y_im_trunc);
FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn) assign dout_re = y_re_trunc;
if (!rstn) assign dout_im = y_im_trunc;
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule endmodule

532
rtl/z_dsp/IIR_top.v
View File

@ -1,322 +1,234 @@
module IIR_top module IIR_top #(
parameter data_out_width = 23
,parameter temp_var_width = data_out_width + 14
)
( (
input rstn input rstn
,input clk ,input clk
,input en ,input en
,input signed [15 :0] IIRin_p0 ,input signed [15 :0] IIRin_p0 // x(8n+9)
,input signed [15 :0] IIRin_p1 ,input signed [15 :0] IIRin_p1 // x(8n+10)
,input signed [15 :0] IIRin_p2 ,input signed [15 :0] IIRin_p2 // x(8n+11)
,input signed [15 :0] IIRin_p3 ,input signed [15 :0] IIRin_p3 // x(8n+12)
,input signed [15 :0] IIRin_p4 ,input signed [15 :0] IIRin_p4 // x(8n+13)
,input signed [15 :0] IIRin_p5 ,input signed [15 :0] IIRin_p5 // x(8n+14)
,input signed [15 :0] IIRin_p6 ,input signed [15 :0] IIRin_p6 // x(8n+15)
,input signed [15 :0] IIRin_p7 ,input signed [15 :0] IIRin_p7 // x(8n+16)
,input signed [31 :0] a_re ,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7)
,input signed [31 :0] a_im ,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22)
,input signed [31 :0] ab_re ,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37)
,input signed [31 :0] ab_im ,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52)
,input signed [31 :0] abb_re ,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67)
,input signed [31 :0] abb_im ,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82)
,input signed [31 :0] ab_pow3_re ,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97)
,input signed [31 :0] ab_pow3_im ,input signed [31 :0] a_re
,input signed [31 :0] ab_pow4_re ,input signed [31 :0] a_im
,input signed [31 :0] ab_pow4_im ,input signed [31 :0] b_re
,input signed [31 :0] ab_pow5_re ,input signed [31 :0] b_im
,input signed [31 :0] ab_pow5_im ,input signed [31 :0] ab_re
,input signed [31 :0] ab_pow6_re ,input signed [31 :0] ab_im
,input signed [31 :0] ab_pow6_im ,input signed [31 :0] abb_re
,input signed [31 :0] ab_pow7_re ,input signed [31 :0] abb_im
,input signed [31 :0] ab_pow7_im ,input signed [31 :0] ab_pow3_re
,input signed [31 :0] b_pow8_re ,input signed [31 :0] ab_pow3_im
,input signed [31 :0] b_pow8_im ,input signed [31 :0] ab_pow4_re
,input signed [31 :0] ab_pow4_im
,input signed [31 :0] ab_pow5_re
,input signed [31 :0] ab_pow5_im
,input signed [31 :0] ab_pow6_re
,input signed [31 :0] ab_pow6_im
,input signed [31 :0] ab_pow7_re
,input signed [31 :0] ab_pow7_im
,input signed [31 :0] b_pow8_re
,input signed [31 :0] b_pow8_im
,output signed [15 :0] IIRout_p0 ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8)
,output signed [15 :0] IIRout_p1 ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23)
,output signed [15 :0] IIRout_p2 ,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38)
,output signed [15 :0] IIRout_p3 ,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53)
,output signed [15 :0] IIRout_p4 ,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68)
,output signed [15 :0] IIRout_p5 ,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83)
,output signed [15 :0] IIRout_p6 ,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98)
,output signed [15 :0] IIRout_p7 ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113)
); );
wire signed [15:0] IIRin_p_r1 [7:1];
wire signed [15 : 0] IIRin_p [7:0];
assign IIRin_p[7] = IIRin_p7;
assign IIRin_p[6] = IIRin_p6;
assign IIRin_p[5] = IIRin_p5;
assign IIRin_p[4] = IIRin_p4;
assign IIRin_p[3] = IIRin_p3;
assign IIRin_p[2] = IIRin_p2;
assign IIRin_p[1] = IIRin_p1;
assign IIRin_p[0] = IIRin_p0;
sirv_gnrl_dfflr #(16) dff_IIRin_p7_1(en,IIRin_p[7], IIRin_p_r1[7] ,clk,rstn); wire signed [temp_var_width- 1:0] IIRout_p0_re;
sirv_gnrl_dfflr #(16) dff_IIRin_p6_1(en,IIRin_p[6], IIRin_p_r1[6] ,clk,rstn); wire signed [temp_var_width- 3:0] IIRout_p1_re;
sirv_gnrl_dfflr #(16) dff_IIRin_p5_1(en,IIRin_p[5], IIRin_p_r1[5] ,clk,rstn); wire signed [temp_var_width- 5:0] IIRout_p2_re;
sirv_gnrl_dfflr #(16) dff_IIRin_p4_1(en,IIRin_p[4], IIRin_p_r1[4] ,clk,rstn); wire signed [temp_var_width- 7:0] IIRout_p3_re;
sirv_gnrl_dfflr #(16) dff_IIRin_p3_1(en,IIRin_p[3], IIRin_p_r1[3] ,clk,rstn); wire signed [temp_var_width- 9:0] IIRout_p4_re;
sirv_gnrl_dfflr #(16) dff_IIRin_p2_1(en,IIRin_p[2], IIRin_p_r1[2] ,clk,rstn); wire signed [temp_var_width-11:0] IIRout_p5_re;
sirv_gnrl_dfflr #(16) dff_IIRin_p1_1(en,IIRin_p[1], IIRin_p_r1[1] ,clk,rstn); wire signed [temp_var_width-13:0] IIRout_p6_re;
wire signed [temp_var_width-15:0] IIRout_p7_re;
wire signed [temp_var_width- 1:0] IIRout_p0_im;
wire signed [temp_var_width- 3:0] IIRout_p1_im;
wire signed [temp_var_width- 5:0] IIRout_p2_im;
wire signed [temp_var_width- 7:0] IIRout_p3_im;
wire signed [temp_var_width- 9:0] IIRout_p4_im;
wire signed [temp_var_width-11:0] IIRout_p5_im;
wire signed [temp_var_width-13:0] IIRout_p6_im;
wire signed [temp_var_width-15:0] IIRout_p7_im;
IIR_Filter_p8 inst_iir_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[0] ),
.dinp1 (IIRin_p_r1[7] ),
.dinp2 (IIRin_p_r1[6] ),
.dinp3 (IIRin_p_r1[5] ),
.dinp4 (IIRin_p_r1[4] ),
.dinp5 (IIRin_p_r1[3] ),
.dinp6 (IIRin_p_r1[2] ),
.dinp7 (IIRin_p_r1[1] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p0 )
);
IIR_Filter_p8 inst_iir_p1 (
.clk (clk ), IIR_Filter_p8 #(
.rstn (rstn ), .data_out_width (temp_var_width )
.en (en ), ) inst_iir_p0 (
.dinp0 (IIRin_p[1] ), .clk (clk ),
.dinp1 (IIRin_p[0] ), .rstn (rstn ),
.dinp2 (IIRin_p_r1[7] ), .en (en ),
.dinp3 (IIRin_p_r1[6] ), .dinp0 (IIRin_p7 ), // x(8n+16)
.dinp4 (IIRin_p_r1[5] ), .dinp1 (IIRin_p6 ), // x(8n+15)
.dinp5 (IIRin_p_r1[4] ), .dinp2 (IIRin_p5 ), // x(8n+14)
.dinp6 (IIRin_p_r1[3] ), .dinp3 (IIRin_p4 ), // x(8n+13)
.dinp7 (IIRin_p_r1[2] ), .dinp4 (IIRin_p3 ), // x(8n+12)
.a_re (a_re ), .dinp5 (IIRin_p2 ), // x(8n+11)
.a_im (a_im ), .dinp6 (IIRin_p1 ), // x(8n+10)
.ab_re (ab_re ), .dinp7 (IIRin_p0 ), // x(8n+9)
.ab_im (ab_im ), .a_re (a_re ),
.abb_re (abb_re ), .a_im (a_im ),
.abb_im (abb_im ), .ab_re (ab_re ),
.ab_pow3_re (ab_pow3_re ), .ab_im (ab_im ),
.ab_pow3_im (ab_pow3_im ), .abb_re (abb_re ),
.ab_pow4_re (ab_pow4_re ), .abb_im (abb_im ),
.ab_pow4_im (ab_pow4_im ), .ab_pow3_re (ab_pow3_re ),
.ab_pow5_re (ab_pow5_re ), .ab_pow3_im (ab_pow3_im ),
.ab_pow5_im (ab_pow5_im ), .ab_pow4_re (ab_pow4_re ),
.ab_pow6_re (ab_pow6_re ), .ab_pow4_im (ab_pow4_im ),
.ab_pow6_im (ab_pow6_im ), .ab_pow5_re (ab_pow5_re ),
.ab_pow7_re (ab_pow7_re ), .ab_pow5_im (ab_pow5_im ),
.ab_pow7_im (ab_pow7_im ), .ab_pow6_re (ab_pow6_re ),
.b_pow8_re (b_pow8_re ), .ab_pow6_im (ab_pow6_im ),
.b_pow8_im (b_pow8_im ), .ab_pow7_re (ab_pow7_re ),
.dout (IIRout_p1 ) .ab_pow7_im (ab_pow7_im ),
); .b_pow8_re (b_pow8_re ),
IIR_Filter_p8 inst_iir_p2 ( .b_pow8_im (b_pow8_im ),
.clk (clk ), .dout_re (IIRout_p0_re ), // Re(y(8n-8))
.rstn (rstn ), .dout_im (IIRout_p0_im ) // Im(y(8n-8))
.en (en ), );
.dinp0 (IIRin_p[2] ),
.dinp1 (IIRin_p[1] ), IIR_Filter_p1 #(
.dinp2 (IIRin_p[0] ), .cascade_in_width (temp_var_width )
.dinp3 (IIRin_p_r1[7] ), ) inst_iir_p1(
.dinp4 (IIRin_p_r1[6] ), .clk (clk ),
.dinp5 (IIRin_p_r1[5] ), .rstn (rstn ),
.dinp6 (IIRin_p_r1[4] ), .en (en ),
.dinp7 (IIRin_p_r1[3] ), .din_re (IIRin_p0_r2 ), // x(8n-7)
.a_re (a_re ), .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8))
.a_im (a_im ), .dout_r1_im (IIRout_p0_im ), // Im(y(8n-8))
.ab_re (ab_re ), .a_re (a_re ),
.ab_im (ab_im ), .a_im (a_im ),
.abb_re (abb_re ), .b_re (b_re ),
.abb_im (abb_im ), .b_im (b_im ),
.ab_pow3_re (ab_pow3_re ), .dout_re (IIRout_p1_re ), // Re(y(8n-23))
.ab_pow3_im (ab_pow3_im ), .dout_im (IIRout_p1_im ) // Im(y(8n-23))
.ab_pow4_re (ab_pow4_re ), );
.ab_pow4_im (ab_pow4_im ), IIR_Filter_p1 #(
.ab_pow5_re (ab_pow5_re ), .cascade_in_width (temp_var_width-2 )
.ab_pow5_im (ab_pow5_im ), ) inst_iir_p2 (
.ab_pow6_re (ab_pow6_re ), .clk (clk ),
.ab_pow6_im (ab_pow6_im ), .rstn (rstn ),
.ab_pow7_re (ab_pow7_re ), .en (en ),
.ab_pow7_im (ab_pow7_im ), .din_re (IIRin_p1_r4 ), // x(8n-22)
.b_pow8_re (b_pow8_re ), .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23))
.b_pow8_im (b_pow8_im ), .dout_r1_im (IIRout_p1_im ), // Im(y(8n-23))
.dout (IIRout_p2 ) .a_re (a_re ),
); .a_im (a_im ),
IIR_Filter_p8 inst_iir_p3 ( .b_re (b_re ),
.clk (clk ), .b_im (b_im ),
.rstn (rstn ), .dout_re (IIRout_p2_re ), // Re(y(8n-38))
.en (en ), .dout_im (IIRout_p2_im ) // Im(y(8n-38))
.dinp0 (IIRin_p[3] ), );
.dinp1 (IIRin_p[2] ), IIR_Filter_p1 #(
.dinp2 (IIRin_p[1] ), .cascade_in_width (temp_var_width-4 )
.dinp3 (IIRin_p[0] ), ) inst_iir_p3 (
.dinp4 (IIRin_p_r1[7] ), .clk (clk ),
.dinp5 (IIRin_p_r1[6] ), .rstn (rstn ),
.dinp6 (IIRin_p_r1[5] ), .en (en ),
.dinp7 (IIRin_p_r1[4] ), .din_re (IIRin_p2_r6 ), // x(8n-37)
.a_re (a_re ), .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38))
.a_im (a_im ), .dout_r1_im (IIRout_p2_im ), // Im(y(8n-38))
.ab_re (ab_re ), .a_re (a_re ),
.ab_im (ab_im ), .a_im (a_im ),
.abb_re (abb_re ), .b_re (b_re ),
.abb_im (abb_im ), .b_im (b_im ),
.ab_pow3_re (ab_pow3_re ), .dout_re (IIRout_p3_re ), // Re(y(8n-53))
.ab_pow3_im (ab_pow3_im ), .dout_im (IIRout_p3_im ) // Im(y(8n-53))
.ab_pow4_re (ab_pow4_re ), );
.ab_pow4_im (ab_pow4_im ), IIR_Filter_p1 #(
.ab_pow5_re (ab_pow5_re ), .cascade_in_width (temp_var_width-6 )
.ab_pow5_im (ab_pow5_im ), ) inst_iir_p4 (
.ab_pow6_re (ab_pow6_re ), .clk (clk ),
.ab_pow6_im (ab_pow6_im ), .rstn (rstn ),
.ab_pow7_re (ab_pow7_re ), .en (en ),
.ab_pow7_im (ab_pow7_im ), .din_re (IIRin_p3_r8 ), // x(8n-52)
.b_pow8_re (b_pow8_re ), .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53))
.b_pow8_im (b_pow8_im ), .dout_r1_im (IIRout_p3_im ), // Im(y(8n-53))
.dout (IIRout_p3 ) .a_re (a_re ),
); .a_im (a_im ),
IIR_Filter_p8 inst_iir_p4 ( .b_re (b_re ),
.clk (clk ), .b_im (b_im ),
.rstn (rstn ), .dout_re (IIRout_p4_re ), // Re(y(8n-68))
.en (en ), .dout_im (IIRout_p4_im ) // Im(y(8n-68))
.dinp0 (IIRin_p[4] ), );
.dinp1 (IIRin_p[3] ), IIR_Filter_p1 #(
.dinp2 (IIRin_p[2] ), .cascade_in_width (temp_var_width-8 )
.dinp3 (IIRin_p[1] ), ) inst_iir_p5 (
.dinp4 (IIRin_p[0] ), .clk (clk ),
.dinp5 (IIRin_p_r1[7] ), .rstn (rstn ),
.dinp6 (IIRin_p_r1[6] ), .en (en ),
.dinp7 (IIRin_p_r1[5] ), .din_re (IIRin_p4_r10 ), // x(8n-67)
.a_re (a_re ), .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68))
.a_im (a_im ), .dout_r1_im (IIRout_p4_im ), // Im(y(8n-68))
.ab_re (ab_re ), .a_re (a_re ),
.ab_im (ab_im ), .a_im (a_im ),
.abb_re (abb_re ), .b_re (b_re ),
.abb_im (abb_im ), .b_im (b_im ),
.ab_pow3_re (ab_pow3_re ), .dout_re (IIRout_p5_re ), // Re(y(8n-83))
.ab_pow3_im (ab_pow3_im ), .dout_im (IIRout_p5_im ) // Im(y(8n-83))
.ab_pow4_re (ab_pow4_re ), );
.ab_pow4_im (ab_pow4_im ), IIR_Filter_p1 #(
.ab_pow5_re (ab_pow5_re ), .cascade_in_width (temp_var_width-10 )
.ab_pow5_im (ab_pow5_im ), ) inst_iir_p6 (
.ab_pow6_re (ab_pow6_re ), .clk (clk ),
.ab_pow6_im (ab_pow6_im ), .rstn (rstn ),
.ab_pow7_re (ab_pow7_re ), .en (en ),
.ab_pow7_im (ab_pow7_im ), .din_re (IIRin_p5_r12 ), // x(8n-82)
.b_pow8_re (b_pow8_re ), .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83))
.b_pow8_im (b_pow8_im ), .dout_r1_im (IIRout_p5_im ), // Im(y(8n-83))
.dout (IIRout_p4 ) .a_re (a_re ),
); .a_im (a_im ),
IIR_Filter_p8 inst_iir_p5 ( .b_re (b_re ),
.clk (clk ), .b_im (b_im ),
.rstn (rstn ), .dout_re (IIRout_p6_re ), // Re(y(8n-98))
.en (en ), .dout_im (IIRout_p6_im ) // Im(y(8n-98))
.dinp0 (IIRin_p[5] ), );
.dinp1 (IIRin_p[4] ), IIR_Filter_p1 #(
.dinp2 (IIRin_p[3] ), .cascade_in_width (temp_var_width-12 )
.dinp3 (IIRin_p[2] ), ) inst_iir_p7 (
.dinp4 (IIRin_p[1] ), .clk (clk ),
.dinp5 (IIRin_p[0] ), .rstn (rstn ),
.dinp6 (IIRin_p_r1[7] ), .en (en ),
.dinp7 (IIRin_p_r1[6] ), .din_re (IIRin_p6_r14 ), // x(8n-97)
.a_re (a_re ), .dout_r1_re (IIRout_p6_re ), // Re(y(8n-98))
.a_im (a_im ), .dout_r1_im (IIRout_p6_im ), // Im(y(8n-98))
.ab_re (ab_re ), .a_re (a_re ),
.ab_im (ab_im ), .a_im (a_im ),
.abb_re (abb_re ), .b_re (b_re ),
.abb_im (abb_im ), .b_im (b_im ),
.ab_pow3_re (ab_pow3_re ), .dout_re (IIRout_p7_re ), // Re(y(8n-113))
.ab_pow3_im (ab_pow3_im ), .dout_im (IIRout_p7_im ) // Im(y(8n-113))
.ab_pow4_re (ab_pow4_re ), );
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ), assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8)
.ab_pow5_im (ab_pow5_im ), assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23)
.ab_pow6_re (ab_pow6_re ), assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38)
.ab_pow6_im (ab_pow6_im ), assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53)
.ab_pow7_re (ab_pow7_re ), assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68)
.ab_pow7_im (ab_pow7_im ), assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83)
.b_pow8_re (b_pow8_re ), assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98)
.b_pow8_im (b_pow8_im ), assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113)
.dout (IIRout_p5 )
);
IIR_Filter_p8 inst_iir_p6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[6] ),
.dinp1 (IIRin_p[5] ),
.dinp2 (IIRin_p[4] ),
.dinp3 (IIRin_p[3] ),
.dinp4 (IIRin_p[2] ),
.dinp5 (IIRin_p[1] ),
.dinp6 (IIRin_p[0] ),
.dinp7 (IIRin_p_r1[7] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p6 )
);
IIR_Filter_p8 inst_iir_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p[7] ),
.dinp1 (IIRin_p[6] ),
.dinp2 (IIRin_p[5] ),
.dinp3 (IIRin_p[4] ),
.dinp4 (IIRin_p[3] ),
.dinp5 (IIRin_p[2] ),
.dinp6 (IIRin_p[1] ),
.dinp7 (IIRin_p[0] ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p7 )
);
endmodule endmodule

1003
rtl/z_dsp/TailCorr_top.v
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File diff suppressed because it is too large Load Diff

56
rtl/z_dsp/Trunc.v Normal file
View File

@ -0,0 +1,56 @@
module trunc #(
parameter integer diw = 8
//,parameter integer dow = msb - (lsb -1)
,parameter integer msb = 7
,parameter integer lsb = 1
,parameter integer half_precision = 0
)
(
input clk
,input rstn
,input en
,input signed [diw - 1 :0] din
,output signed [msb - lsb:0] dout
);
reg signed [msb - lsb : 0] d_tmp;
generate
if(lsb!=0 && half_precision != 0) begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
d_tmp <= 'h0;
end
else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else
d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]};
end
else begin
d_tmp <= d_tmp;
end
end
end
else begin
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
d_tmp <= 'h0;
end
else if(en) begin
if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
else
d_tmp <= din[msb:lsb];
end
else begin
d_tmp <= d_tmp;
end
end
end
endgenerate
assign dout = d_tmp;
endmodule

96
rtl/z_dsp/mult_C.v
View File

@ -36,7 +36,7 @@ module mult_C #(
,parameter integer B_width = 8 ,parameter integer B_width = 8
,parameter integer C_width = 8 ,parameter integer C_width = 8
,parameter integer D_width = 8 ,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division ,parameter integer o_width = 31//division
) )
@ -46,66 +46,72 @@ module mult_C #(
en, en,
a, a,
b, b,
c, c,
d, d,
Re, Re,
Im Im
); );
input rstn; input rstn;
input clk; input clk;
input en; input en;
input signed [A_width-1:0] a; input signed [A_width-1 :0] a;
input signed [B_width-1:0] b; input signed [B_width-1 :0] b;
input signed [C_width-1:0] c; input signed [C_width-1 :0] c;
input signed [D_width-1:0] d; input signed [D_width-1 :0] d;
output signed [A_width+C_width-frac_coef_width-2:0] Re; output signed [o_width-1 :0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im; output signed [o_width-1 :0] Im;
wire signed [A_width+C_width-1:0] ac; wire signed [A_width+C_width-1:0] ac;
wire signed [B_width+D_width-1:0] bd; wire signed [B_width+D_width-1:0] bd;
wire signed [A_width+D_width-1:0] ad; wire signed [A_width+D_width-1:0] ad;
wire signed [B_width+C_width-1:0] bc; wire signed [B_width+C_width-1:0] bc;
wire signed [A_width+C_width :0] Re_tmp;
wire signed [A_width+D_width :0] Im_tmp;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (ac )
);
DW02_mult #(A_width,C_width) inst_c1( .A (a ), DW02_mult #(B_width,D_width) inst_c2( .A (b ),
.B (c ), .B (d ),
.TC (1'b1 ), .TC (1'b1 ),
.PRODUCT (ac ) .PRODUCT (bd )
); );
DW02_mult #(B_width,D_width) inst_c2( .A (b ), DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ), .B (d ),
.TC (1'b1 ), .TC (1'b1 ),
.PRODUCT (bd ) .PRODUCT (ad )
); );
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
DW02_mult #(A_width,D_width) inst_c3( .A (a ), .B (c ),
.B (d ), .TC (1'b1 ),
.TC (1'b1 ), .PRODUCT (bc )
.PRODUCT (ad ) );
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
);
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac - bd; assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc; assign Im_tmp = ad + bc;
wire signed [A_width+C_width:0] Re_round; trunc #(
wire signed [A_width+D_width:0] Im_round; .diw (A_width+C_width+1 )
,.msb (A_width+C_width-2 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); ,.lsb (A_width+C_width-o_width-1 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); ) u_round1 (clk, rstn, en, Re_tmp, Re_trunc);
trunc #(
.diw (A_width+D_width+1 )
,.msb (A_width+D_width-2 )
,.lsb (A_width+C_width-o_width-1 )
) u_round2 (clk, rstn, en, Im_tmp, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width]; assign Re = Re_trunc;
assign Im = Im_round[A_width+D_width-2:frac_coef_width]; assign Im = Im_trunc;
endmodule endmodule

42
rtl/z_dsp/mult_x.v
View File

@ -35,7 +35,7 @@ module mult_x #(
parameter integer A_width = 8 parameter integer A_width = 8
,parameter integer C_width = 8 ,parameter integer C_width = 8
,parameter integer D_width = 8 ,parameter integer D_width = 8
,parameter integer frac_coef_width = 31//division ,parameter integer o_width = 31//division
) )
@ -53,15 +53,17 @@ module mult_x #(
input rstn; input rstn;
input clk; input clk;
input en; input en;
input signed [A_width-1:0] a; input signed [A_width-1 :0] a;
input signed [C_width-1:0] c; input signed [C_width-1 :0] c;
input signed [D_width-1:0] d; input signed [D_width-1 :0] d;
output signed [A_width+C_width-frac_coef_width-2:0] Re; output signed [o_width-1 :0] Re;
output signed [A_width+D_width-frac_coef_width-2:0] Im; output signed [o_width-1 :0] Im;
wire signed [A_width+C_width-1:0] ac; wire signed [A_width+C_width-1:0] ac;
wire signed [A_width+D_width-1:0] ad; wire signed [A_width+D_width-1:0] ad;
wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc;
@ -71,27 +73,27 @@ DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.PRODUCT (ac ) .PRODUCT (ac )
); );
DW02_mult #(A_width,D_width) inst_c3( .A (a ), DW02_mult #(A_width,D_width) inst_c3( .A (a ),
.B (d ), .B (d ),
.TC (1'b1 ), .TC (1'b1 ),
.PRODUCT (ad ) .PRODUCT (ad )
); );
wire signed [A_width+C_width:0] Re_tmp;
wire signed [A_width+D_width:0] Im_tmp;
assign Re_tmp = ac;
assign Im_tmp = ad;
wire signed [A_width+C_width:0] Re_round; trunc #(
wire signed [A_width+D_width:0] Im_round; .diw (A_width+C_width )
,.msb (A_width+C_width-2 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); ,.lsb (A_width+C_width-o_width-1 )
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); ) u_round1 (clk, rstn, en, ac, Re_trunc);
trunc #(
.diw (A_width+D_width )
,.msb (A_width+D_width-2 )
,.lsb (A_width+D_width-o_width-1 )
) u_round2 (clk, rstn, en, ad, Im_trunc);
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign Re = Re_round[A_width+D_width-2:frac_coef_width]; assign Re = Re_trunc;
assign Im = Im_round[A_width+D_width-2:frac_coef_width]; assign Im = Im_trunc;
endmodule endmodule

64
rtl/z_dsp/z_dsp.sv → rtl/z_dsp/z_dsp.v
View File

@ -48,24 +48,26 @@ module z_dsp
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;
reg signed [31:0] ao_re [5:0]; wire signed [31:0] ao_re [5:0];
reg signed [31:0] ao_im [5:0]; wire signed [31:0] ao_im [5:0];
reg signed [31:0] ab_re [5:0]; wire signed [31:0] ab_re [5:0];
reg signed [31:0] ab_im [5:0]; wire signed [31:0] ab_im [5:0];
reg signed [31:0] abb_re [5:0]; wire signed [31:0] abb_re [5:0];
reg signed [31:0] abb_im [5:0]; wire signed [31:0] abb_im [5:0];
reg signed [31:0] ab_pow3_re [5:0]; wire signed [31:0] ab_pow3_re [5:0];
reg signed [31:0] ab_pow3_im [5:0]; wire signed [31:0] ab_pow3_im [5:0];
reg signed [31:0] ab_pow4_re [5:0]; wire signed [31:0] ab_pow4_re [5:0];
reg signed [31:0] ab_pow4_im [5:0]; wire signed [31:0] ab_pow4_im [5:0];
reg signed [31:0] ab_pow5_re [5:0]; wire signed [31:0] ab_pow5_re [5:0];
reg signed [31:0] ab_pow5_im [5:0]; wire signed [31:0] ab_pow5_im [5:0];
reg signed [31:0] ab_pow6_re [5:0]; wire signed [31:0] ab_pow6_re [5:0];
reg signed [31:0] ab_pow6_im [5:0]; wire signed [31:0] ab_pow6_im [5:0];
reg signed [31:0] ab_pow7_re [5:0]; wire signed [31:0] ab_pow7_re [5:0];
reg signed [31:0] ab_pow7_im [5:0]; wire signed [31:0] ab_pow7_im [5:0];
reg signed [31:0] b_pow8_re [5:0]; wire signed [31:0] bo_re [5:0];
reg signed [31:0] b_pow8_im [5:0]; wire signed [31:0] bo_im [5:0];
wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0];
CoefGen inst_CoefGen( CoefGen inst_CoefGen(
.clk (clk ), .clk (clk ),
@ -97,6 +99,8 @@ CoefGen inst_CoefGen(
.b5_im (b5_im ), .b5_im (b5_im ),
.a_re0 (ao_re[0] ), .a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ), .a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ), .ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ), .ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ), .abb_re0 (abb_re[0] ),
@ -115,6 +119,8 @@ CoefGen inst_CoefGen(
.b_pow8_im0 (b_pow8_im[0] ), .b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ), .a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ), .a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ), .ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ), .ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ), .abb_re1 (abb_re[1] ),
@ -133,6 +139,8 @@ CoefGen inst_CoefGen(
.b_pow8_im1 (b_pow8_im[1] ), .b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ), .a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ), .a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ), .ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ), .ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ), .abb_re2 (abb_re[2] ),
@ -151,6 +159,8 @@ CoefGen inst_CoefGen(
.b_pow8_im2 (b_pow8_im[2] ), .b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ), .a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ), .a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ), .ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ), .ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ), .abb_re3 (abb_re[3] ),
@ -169,6 +179,8 @@ CoefGen inst_CoefGen(
.b_pow8_im3 (b_pow8_im[3] ), .b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ), .a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ), .a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ), .ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ), .ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ), .abb_re4 (abb_re[4] ),
@ -187,6 +199,8 @@ CoefGen inst_CoefGen(
.b_pow8_im4 (b_pow8_im[4] ), .b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ), .a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ), .a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ), .ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ), .ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ), .abb_re5 (abb_re[5] ),
@ -213,7 +227,7 @@ wire signed [15:0] dout_4;
wire signed [15:0] dout_5; wire signed [15:0] dout_5;
wire signed [15:0] dout_6; wire signed [15:0] dout_6;
wire signed [15:0] dout_7; wire signed [15:0] dout_7;
reg vldo_TC; wire vldo_TC;
TailCorr_top inst_TailCorr_top TailCorr_top inst_TailCorr_top
( (
.clk (clk ), .clk (clk ),
@ -228,6 +242,8 @@ TailCorr_top inst_TailCorr_top
.din3 (din3 ), .din3 (din3 ),
.a_re0 (ao_re[0] ), .a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ), .a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ), .ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ), .ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ), .abb_re0 (abb_re[0] ),
@ -246,6 +262,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im0 (b_pow8_im[0] ), .b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ), .a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ), .a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ), .ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ), .ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ), .abb_re1 (abb_re[1] ),
@ -264,6 +282,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im1 (b_pow8_im[1] ), .b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ), .a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ), .a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ), .ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ), .ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ), .abb_re2 (abb_re[2] ),
@ -282,6 +302,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im2 (b_pow8_im[2] ), .b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ), .a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ), .a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ), .ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ), .ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ), .abb_re3 (abb_re[3] ),
@ -300,6 +322,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im3 (b_pow8_im[3] ), .b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ), .a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ), .a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ), .ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ), .ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ), .abb_re4 (abb_re[4] ),
@ -318,6 +342,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im4 (b_pow8_im[4] ), .b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ), .a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ), .a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ), .ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ), .ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ), .abb_re5 (abb_re[5] ),

565
script_m/z_dsp.m
View File

@ -1,565 +0,0 @@
classdef z_dsp < handle
properties
%input
fs_L;
fs_H;
TargetFrequency;
G;
simulink_time;
intp_mode;
dac_mode_sel;
route_num;
env_num;
%output
Ideal2Low;
Ideal2Target;
wave_pre;
wave_preL;
amp_real;
amp_imag;
time_real;
time_imag;
name;
wave_revised;
wave_revisedL;
DownsamplingBy12GDataAlign;
HardwareMeanIntpDataAlign;
Delay;
Delay_mode;
pause_time;
filename;
rpt_num;
FallingEdge;
Amp;
itv_time; %信号具有周期性时的间隔
end
methods
function obj = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel)
obj.fs_L = fs_L;
obj.fs_H = fs_H;
obj.TargetFrequency = TargetFrequency;
obj.G = G;
obj.simulink_time = simulink_time;
obj.intp_mode = intp_mode;
obj.dac_mode_sel = dac_mode_sel;
obj.Ideal2Low = fs_H/(fs_L/2);
obj.Ideal2Target = fs_H/TargetFrequency;
obj.name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第一组S21参数_acz_持续时间30ns_下降沿",...
"第一组S21参数_acz_持续时间50ns_下降沿";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第二组S21参数_acz_持续时间30ns_下降沿",...
"第二组S21参数_acz_持续时间50ns_下降沿";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第三组S21参数_acz_持续时间30ns_下降沿",...
"第三组S21参数_acz_持续时间50ns_下降沿";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第四组S21参数_acz_持续时间30ns_下降沿",...
"第四组S21参数_acz_持续时间50ns_下降沿";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
"第五组S21参数_acz_持续时间30ns_下降沿",...
"第五组S21参数_acz_持续时间50ns_下降沿";
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第一组S21参数_acz_持续时间30ns_下降沿后",...
"第一组S21参数_acz_持续时间50ns_下降沿后";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第二组S21参数_acz_持续时间30ns_下降沿后",...
"第二组S21参数_acz_持续时间50ns_下降沿后";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第三组S21参数_acz_持续时间30ns_下降沿后",...
"第三组S21参数_acz_持续时间50ns_下降沿后";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第四组S21参数_acz_持续时间30ns_下降沿后",...
"第四组S21参数_acz_持续时间50ns_下降沿后";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
"第五组S21参数_acz_持续时间30ns_下降沿后",...
"第五组S21参数_acz_持续时间50ns_下降沿后";
];
obj.pause_time = 0.5;
obj.Amp = 1.5e4;
end
function env(obj)
cd("D:\Work\EnvData\acz");
obj1 = py.importlib.import_module('acz');
py.importlib.reload(obj1);
%按点数产生理想方波
% amp_rect = 1.5e4;
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
%
% for i = 1:2
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
% end
%flattop波
A = 1.5e4;
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
[edge(2), length_flattop(2)] = deal(4,30);
[edge(3), length_flattop(3)] = deal(4,50);
[edge(4), length_flattop(4)] = deal(4,1000);
[edge(5), length_flattop(5)] = deal(100,10000);
for i = 1:length(length_flattop)
[edge_H(i), length_H(i)] = deal(edge(i)*obj.fs_H/1e9,length_flattop(i)*obj.fs_H/1e9);
obj.wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
end
%acz波
amplitude = 1.5e4;
carrierFreq = 0.000000;
carrierPhase = 0.000000;
dragAlpha = 0.000000;
thf = 0.864;
thi = 0.05;
lam2 = -0.18;
lam3 = 0.04;
length_acz(1) = 30;
length_acz(2) = 50;
for i = 1:length(length_acz)
length_acz_H(i) = int32(length_acz(i)*obj.fs_H/1e9);
obj.wave_pre{i+length(length_flattop)} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
end
obj.env_num = length(length_flattop) + length(length_acz);
for i = 1:obj.env_num
obj.wave_pre{i} = cat(2,repmat(cat(2,obj.wave_pre{i},zeros(1,round(30e-9*obj.fs_H))),1,obj.rpt_num),zeros(1,floor(obj.simulink_time*obj.fs_H))); %校正前的高频信号
obj.wave_preL{i} = obj.wave_pre{i}(1:obj.Ideal2Low:end); %校正前的低频信号
end
assignin("base",'wave_preL',obj.wave_preL);
obj.FallingEdge = [30e-9,30e-9,50e-9,1000e-9,10000e-9,30e-9,50e-9];
end
function route(obj)
obj.amp_real{1}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{1}= [0 0 0 0 0 0];
obj.time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{1} = [0 0 0 0 0 0];
obj.amp_real{2}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{2}= [0 0 0 0 0 0];
obj.time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{2} = [0 -1/300 -1/500 0 0 0];
obj.amp_real{3}= [0.025 0.009 0.0002 0.2 0 0];
obj.amp_imag{3}= [0 0.012 0 0 0 0];
obj.time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
obj.time_imag{3} = [0 -1/300 -1/500 0 0 0];
obj.amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
obj.amp_imag{4}= [0 0 0 0 0 0];
obj.time_real{4} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
obj.time_imag{4} = [0 -1/15 -1/50 0 0 0];
obj.amp_real{5}= [0.025 0.009 0.0002 0.2 0 0];
obj.amp_imag{5}= [0 0.012 0 0 0 0];
obj.time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
obj.time_imag{5} = [0 -1/15 -1/50 0 0 0];
[m,n] = size(obj.amp_real);
obj.route_num = n;
end
function py_cal(obj)
cd("D:\Work\TailCorr_20241008_NoGit");
obj2 = py.importlib.import_module('wave_calculation');
py.importlib.reload(obj2);
cd("D:\Work\TailCorr");
convolve_bound = int8(3);
calibration_time = int32(20e3);
cal_method = int8(1);
sampling_rateL = int64(obj.fs_L/2);
sampling_rate = int64(obj.fs_H);
%校正后的高频信号
for m = 1:obj.route_num
for n = 1:obj.env_num
wave_cal = cell(py.wave_calculation.wave_cal(obj.wave_pre{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rate));
obj.wave_revised{m,n} = double(wave_cal{1,1});
wave_calL = cell(py.wave_calculation.wave_cal(obj.wave_preL{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rateL));
obj.wave_revisedL{m,n} = double(wave_calL{1,1});
end
alpha{m} = double(wave_calL{1,2});
beta{m} = double(wave_calL{1,3});
end
alpha_wideth=32;
beta_width=32;
%定点化系数
for i = 1:obj.route_num
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
end
assignin('base', 'alphaFixRe', alphaFixRe);
assignin('base', 'alphaFixIm', alphaFixIm);
assignin('base', 'betaFixRe' , betaFixRe);
assignin('base', 'betaFixIm' , betaFixIm);
end
function FIL(obj)
for m = 1:obj.route_num
assignin('base', 'm', m);
for n = 1:obj.env_num
assignin('base', 'n', n);
optnons=simset('SrcWorkspace','current');
sim('z_dsp_FIL',[0,obj.simulink_time]);
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
dout0{m,n} = sim2m("dout0");
dout1{m,n} = sim2m("dout1");
dout2{m,n} = sim2m("dout2");
dout3{m,n} = sim2m("dout3");
N = length(dout0{m,n});
cs_wave{m,n} = zeros(4*N,1);
cs_wave{m,n}(1:4:4*N) = dout0{m,n};
cs_wave{m,n}(2:4:4*N) = dout1{m,n};
cs_wave{m,n}(3:4:4*N) = dout2{m,n};
cs_wave{m,n}(4:4:4*N) = dout3{m,n};
HardwareMeanIntpData{m,n} = cs_wave{m,n};%硬件校正后内插
DownsamplingBy12GData{m,n} = obj.wave_revised{m,n}(1:obj.Ideal2Target:end);
[obj.DownsamplingBy12GDataAlign{m,n},obj.HardwareMeanIntpDataAlign{m,n},obj.Delay(m,n)] = ...
alignsignals(DownsamplingBy12GData{m,n}(1:round(obj.TargetFrequency*20e-6)),HardwareMeanIntpData{m,n}(1:round(obj.TargetFrequency*20e-6)),"Method","xcorr");
end
end
obj.Delay_mode = mode(obj.Delay,'all');
fprintf('Delay_mode = %d\n',obj.Delay_mode);
end
function DataShow(obj,save)
close all;
fileID = fopen(obj.filename, 'w');
if fileID == -1
disp('文件打开失败');
else
disp('文件打开成功');
end
start_time = abs(obj.Delay_mode)/(obj.TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
if(obj.rpt_num == 1)
for m = 1:obj.route_num
for n = 1:obj.env_num
edge_Align(n) = obj.FallingEdge(n) + start_time;
tmp(n) = edge_Align(n) + 10e-9;
a{n} = [start_time-5e-9 tmp(n)];%[1/obj.fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
b{n} = [tmp(n) 20e-6];
figure('Units','normalized','Position',[0.0004 0.5174 0.4992 0.4229]);
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',a{n},obj.Amp,edge_Align(n),fileID);
if(save == "save")
savefig(obj.name(m,n));
end
figure('Units','normalized','Position',[0.0004 0.0340 0.4992 0.4229]);
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m+5,n),'硬件与脚本的差值',b{n},obj.Amp,edge_Align(n),fileID);
if(save == "save")
savefig(obj.name(m+5,n));
end
end
end
else
for m = 1:obj.route_num
for n = 1:obj.env_num
figure('Units','normalized','Position',[0 0.0333 1.0000 0.9125]);
title(obj.name(m,n),Interpreter="none");
tiledlayout('vertical','TileSpacing','tight')
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',obj.FallingEdge(n)+obj.itv_time,obj.Amp,start_time,fileID);
if(save == "save")
savefig(obj.name(m,n));
end
end
end
end
fclose(fileID);
end
function RouteShow(obj,save)
t = 0:1/(1e2):10000;
for i = 1:5
amp_routing{i} = obj.amp_real{1,i} + 1j*obj.amp_imag{1,i};
time_routing{i} = obj.time_real{1,i} + 1j*obj.time_imag{1,i};
tau{i} = -1./time_routing{i};
end
figure()
set(gcf,"Position",[1 49 2560 1314])
tiledlayout('flow','TileSpacing','tight');
title_name = ["第一组S_{21}参数","第二组S_{21}参数","第三组S_{21}参数","第四组S_{21}参数","第五组S_{21}参数"];
for m = 1:obj.route_num
for n = 1:1:length(amp_routing{1,m})
S21_time{m}(:,n) = amp_routing{1,m}(n)*exp(time_routing{1,m}(n)*t);
end
nexttile
plot(t*1e-9,real(sum(S21_time{m},2)));
grid on
title(title_name(m));
end
if(save == "save")
savefig("S21线路参数");
end
end
function FigDisplay(obj)
if(obj.rpt_num == 1)
for m = 1:obj.route_num*obj.env_num
figure(2*m-1)
figure(2*m)
pause(obj.pause_time);
end
else
for m = 1:obj.route_num*obj.env_num
figure(m)
pause(obj.pause_time);
end
end
end
function LoadFigAndDisplay(obj)
for n = 1:obj.route_num
for m = 1:obj.env_num
open(strcat(obj.name(n,m),'.fig'));
open(strcat(obj.name(n+5,m),'.fig'));
pause(obj.pause_time);
end
end
end
function ErrAny(obj,save)
fid = fopen(obj.filename,'r');
if(obj.rpt_num == 1)
data = textscan(fid,'Falling edge of 20ns~40ns mean :%s std :%s Falling edge of 1us~1.1us mean :%s std :%s The mean and std stably less than 1e-4 is :%s s');
fclose(fid);
data{1} = cellfun(@str2num,data{1});
data{2} = cellfun(@str2num,data{2});
data{3} = cellfun(@str2num,data{3});
data{4} = cellfun(@str2num,data{4});
data{5} = cellfun(@str2num,data{5});
title_name = ["下降沿后20ns~40ns误差的平均值","下降沿后20ns~40ns误差的标准差","下降沿后1us~1.1us误差的平均值","下降沿后1us~1.1us误差的标准差","加窗参数"];
err_threshold = [1e-3 1e-3 1e-4 3e-4 5e-6];
else
data = textscan(fid,'每个周期拖尾误差均值的标准差 = %s s');
fclose(fid);
data{1} = cellfun(@str2num,data{1});
title_name = ["多周期误差平均值的标准差"];
err_threshold = [0.5e-3];
end
[h,v] = size(data);
figure()
tiledlayout('flow','TileSpacing','tight')
colors = lines(obj.route_num);
set(gcf,'Position', [1 49 2560 1314]);
for m = 1:v
nexttile
hold on
for i = 1:(obj.route_num)
idx = (i-1)*(length(data{m})/obj.route_num) + 1 : i*(length(data{m})/obj.route_num);
plot(idx,abs(data{m}(idx)),'-o','Color', colors(i, :));
end
yline(err_threshold(m),'--r');
title(title_name(m));
set(gca,'YScale','log');
legend("第一组线路","第二组线路","第三组线路","第四组线路","第五组线路",'Location','northwest');
end
if(obj.rpt_num == 1)
if(save == "save")
savefig("单周期误差分析")
end
else
if(save == "save")
savefig("多周期误差分析")
end
end
end
%compare FIL with python script
function diff_plot_py(obj,fs,iir_out, Script_out,title1,title2,a,amp,edge,fileID)
%输入数据长度不等时取其公共部分
N = min(length(iir_out),length(Script_out));
iir_out = iir_out(1:N);
Script_out = Script_out(1:N);
diff = (iir_out - Script_out)/amp;%求差，并归一化
n = (0:1:N-1)/fs;
%找出关心的数据点
if(obj.rpt_num == 1)
n_edge = find(n>=edge-1e-12);%edge代表下降沿
n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
ne(1) = 1;
window_length = 100e-9*fs;
diff_mean_window = movmean(diff,window_length);
diff_std_window = movstd(diff,window_length);
n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
n_common = max(n_mean_window(end),n_std_window(end));
%原始数据作图
tiledlayout(2,1)
ax1 = nexttile;
plot(n,iir_out,n,Script_out)
legend('硬件','软件');
xlabel('t/s')
xlim(a);
title(title1,Interpreter="none");
grid on
hold on
%差值做图
ax2 = nexttile;
plot(n,diff)
xlabel('t/s')
title('diff')
grid on
hold on
xlim(a)
title('硬件与脚本的差值',Interpreter="none");
linkaxes([ax1,ax2],'x');
plot_p = @(x)[
plot(n(x),diff(x),'r*');
text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
];
ne(1) = 1;
% [diff_max,R_mpos] = max(abs(diff));%误差最大值
% plot_p(R_mpos);
if a(2) <= 5e-6
plot_p(n_edge(1));%下降沿
% plot_p(R_mpos);
elseif a(2) == 20e-6
plot_p(n50(1)); %下降沿20ns
plot_p(n1000(1)); %下降沿1us
plot_p(ne(end)); %误差小于万分之一
fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100)));
% fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
% fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
end
else
n_start = find(n>=edge-1e-12);%edge代表下降沿
% 确定周期长度对应的采样点数量
T = a; %在这种情况下，a这个参数用不到了，使用其传递周期，也就是说a这个参数有两种不同的涵义
samples_per_period = round(T * fs); % 每个周期采样点数
num_periods = obj.rpt_num; % 总周期数
period_means = zeros(1, num_periods); % 存储每周期均值
for i = 1:num_periods
% 提取当前周期的起止索引
start_idx(i) = n_start(1) + (i - 1) * samples_per_period;
end_idx(i) = n_start(1) + i * samples_per_period;
% 提取当前周期的数据
period_data = diff(start_idx(i):end_idx(i));
% 计算当前周期的均值
period_means(i) = mean(period_data);
end
fprintf(fileID,"每个周期拖尾误差均值的标准差 = %.4e s\n",std(period_means));
ax1 = nexttile;
plot(n,iir_out,n,Script_out);
hold on
plot(n(start_idx), Script_out(start_idx), 'r*'); % 标记每个周期的起始点
plot(n(end_idx), Script_out(end_idx), 'g*'); % 标记每个周期的起始点
legend('硬件','软件');
xlabel('t/s');
title(title1,Interpreter="none");
ax2 = nexttile;
hold on
plot(n, diff); hold on; % 原始信号
plot(n(end_idx), diff(end_idx), 'g*'); % 标记每个周期的起始点
xlabel('t/s');
ylabel('归一化误差');
linkaxes([ax1,ax2],'x');
xlim([0,n(end_idx(end)) + 5e-7]);
title(title2,Interpreter="none");
end
end
end
end

66
script_m/z_dsp_top.m
View File

@ -1,66 +0,0 @@
clc;clear;close all
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
fs_L = 0.75e9; %硬件频率
fs_H = 12e9; %以高频近似理想信号
TargetFrequency = 3e9;
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
route_num = 1; %线路个数
env_num = 1; %包络个数
alpha_wideth=32; %滤波器系数定点化
beta_width=32;
G = 1;
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
z_dsp1 = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel);
z_dsp1.filename = 'output.txt';
z_dsp1.rpt_num = 1;
if(z_dsp1.rpt_num > 1)
z_dsp1.name = [
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第一组S21参数_acz_持续时间30ns_重复100次",...
"第一组S21参数_acz_持续时间50ns_重复100次";
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第二组S21参数_acz_持续时间30ns_重复100次",...
"第二组S21参数_acz_持续时间50ns_重复100次";
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第三组S21参数_acz_持续时间30ns_重复100次",...
"第三组S21参数_acz_持续时间50ns_重复100次";
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第四组S21参数_acz_持续时间30ns_重复100次",...
"第四组S21参数_acz_持续时间50ns_重复100次";
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
"第五组S21参数_acz_持续时间30ns_重复100次",...
"第五组S21参数_acz_持续时间50ns_重复100次";
];
z_dsp1.FallingEdge = [30e-9 30e-9 50e-9 30e-9 50e-9];
z_dsp1.itv_time = 30e-9;
end
z_dsp1.env(); %产生理想z信号
z_dsp1.route(); %配置线路参数
% z_dsp1.route_num = 1;
% z_dsp1.env_num = 1;
z_dsp1.py_cal(); %12G采样率，基于python脚本计算校正后的波形
z_dsp1.FIL(); %调用FIL模块计算校正后的波形
z_dsp1.DataShow("save"); %计算结束后展示波形，有save时保存图片
%%
z_dsp1.FigDisplay(); %图片播放
%%
z_dsp1.RouteShow("save"); %可视化线路参数
%%
z_dsp1.ErrAny("save") %对关心的指标进行可视化处理
%%
close all
z_dsp1.pause_time = 0.3;
z_dsp1.LoadFigAndDisplay()

5
sim/TailCorr_en/files.f
View File

@ -1,10 +1,13 @@
../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/FixRound.v ../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/TailCorr_top.v ../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v ../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/IIR_Filter_p8.v ../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v ../../rtl/model/DW02_mult.v
tb_TailCorr_en.v tb_TailCorr_en.v

78
sim/TailCorr_en/tb_TailCorr_en.v
View File

@ -1,36 +1,4 @@
module TB(); module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : tb_TailCorr_en.v
// Department : HFNL
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 2025-03-03 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
reg [1 :0] source_mode; reg [1 :0] source_mode;
@ -48,6 +16,8 @@ end
reg rstn; reg rstn;
reg [31:0] a_re0; reg [31:0] a_re0;
reg [31:0] a_im0; reg [31:0] a_im0;
reg [31:0] b_re0;
reg [31:0] b_im0;
reg [31:0] ab_re0; reg [31:0] ab_re0;
reg [31:0] ab_im0; reg [31:0] ab_im0;
reg [31:0] abb_re0; reg [31:0] abb_re0;
@ -66,6 +36,8 @@ reg [31:0] b_pow8_re0;
reg [31:0] b_pow8_im0; reg [31:0] b_pow8_im0;
reg [31:0] a_re1; reg [31:0] a_re1;
reg [31:0] a_im1; reg [31:0] a_im1;
reg [31:0] b_re1;
reg [31:0] b_im1;
reg [31:0] ab_re1; reg [31:0] ab_re1;
reg [31:0] ab_im1; reg [31:0] ab_im1;
reg [31:0] abb_re1; reg [31:0] abb_re1;
@ -84,6 +56,8 @@ reg [31:0] b_pow8_re1;
reg [31:0] b_pow8_im1; reg [31:0] b_pow8_im1;
reg [31:0] a_re2; reg [31:0] a_re2;
reg [31:0] a_im2; reg [31:0] a_im2;
reg [31:0] b_re2;
reg [31:0] b_im2;
reg [31:0] ab_re2; reg [31:0] ab_re2;
reg [31:0] ab_im2; reg [31:0] ab_im2;
reg [31:0] abb_re2; reg [31:0] abb_re2;
@ -102,6 +76,8 @@ reg [31:0] b_pow8_re2;
reg [31:0] b_pow8_im2; reg [31:0] b_pow8_im2;
reg [31:0] a_re3; reg [31:0] a_re3;
reg [31:0] a_im3; reg [31:0] a_im3;
reg [31:0] b_re3;
reg [31:0] b_im3;
reg [31:0] ab_re3; reg [31:0] ab_re3;
reg [31:0] ab_im3; reg [31:0] ab_im3;
reg [31:0] abb_re3; reg [31:0] abb_re3;
@ -120,6 +96,8 @@ reg [31:0] b_pow8_re3;
reg [31:0] b_pow8_im3; reg [31:0] b_pow8_im3;
reg [31:0] a_re4; reg [31:0] a_re4;
reg [31:0] a_im4; reg [31:0] a_im4;
reg [31:0] b_re4;
reg [31:0] b_im4;
reg [31:0] ab_re4; reg [31:0] ab_re4;
reg [31:0] ab_im4; reg [31:0] ab_im4;
reg [31:0] abb_re4; reg [31:0] abb_re4;
@ -138,6 +116,8 @@ reg [31:0] b_pow8_re4;
reg [31:0] b_pow8_im4; reg [31:0] b_pow8_im4;
reg [31:0] a_re5; reg [31:0] a_re5;
reg [31:0] a_im5; reg [31:0] a_im5;
reg [31:0] b_re5;
reg [31:0] b_im5;
reg [31:0] ab_re5; reg [31:0] ab_re5;
reg [31:0] ab_im5; reg [31:0] ab_im5;
reg [31:0] abb_re5; reg [31:0] abb_re5;
@ -180,6 +160,18 @@ begin
a_im3 = 32'd0; a_im3 = 32'd0;
a_im4 = 32'd0; a_im4 = 32'd0;
a_im5 = 32'd0; a_im5 = 32'd0;
b_re0 = 32'd2143083068;
b_re1 = 32'd2145807236;
b_re2 = 32'd2146812530;
b_re3 = 32'd2147483648;
b_re4 = 32'd0;
b_re5 = 32'd0;
b_im0 = 32'd0;
b_im1 = 32'd0;
b_im2 = 32'd0;
b_im3 = 32'd0;
b_im4 = 32'd0;
b_im5 = 32'd0;
ab_re0 = 32'd54894517; ab_re0 = 32'd54894517;
ab_re1 = 32'd32664510; ab_re1 = 32'd32664510;
ab_re2 = 32'd429381 ; ab_re2 = 32'd429381 ;
@ -268,7 +260,7 @@ begin
b_pow8_re0 = 32'd2112530470; b_pow8_re0 = 32'd2112530470;
b_pow8_re1 = 32'd2134108939; b_pow8_re1 = 32'd2134108939;
b_pow8_re2 = 32'd2142120573; b_pow8_re2 = 32'd2142120573;
b_pow8_re3 = 32'd0; b_pow8_re3 = 32'd2147483648;
b_pow8_re4 = 32'd0; b_pow8_re4 = 32'd0;
b_pow8_re5 = 32'd0; b_pow8_re5 = 32'd0;
b_pow8_im0 = 32'd0; b_pow8_im0 = 32'd0;
@ -412,6 +404,7 @@ assign dac_mode_sel = 2'b00;
wire tc_bypass; wire tc_bypass;
wire vldo; wire vldo;
//wire vldo_ref;
assign tc_bypass = 1'b0; assign tc_bypass = 1'b0;
@ -441,6 +434,8 @@ TailCorr_top inst_TailCorr_top
.din3 (iir_in[3]), .din3 (iir_in[3]),
.a_re0 (a_re0), .a_re0 (a_re0),
.a_im0 (a_im0), .a_im0 (a_im0),
.b_re0 (b_re0),
.b_im0 (b_im0),
.ab_re0 (ab_re0), .ab_re0 (ab_re0),
.ab_im0 (ab_im0), .ab_im0 (ab_im0),
.abb_re0 (abb_re0), .abb_re0 (abb_re0),
@ -459,6 +454,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im0 (b_pow8_im0), .b_pow8_im0 (b_pow8_im0),
.a_re1 (a_re1), .a_re1 (a_re1),
.a_im1 (a_im1), .a_im1 (a_im1),
.b_re1 (b_re1),
.b_im1 (b_im1),
.ab_re1 (ab_re1), .ab_re1 (ab_re1),
.ab_im1 (ab_im1), .ab_im1 (ab_im1),
.abb_re1 (abb_re1), .abb_re1 (abb_re1),
@ -477,6 +474,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im1 (b_pow8_im1), .b_pow8_im1 (b_pow8_im1),
.a_re2 (a_re2), .a_re2 (a_re2),
.a_im2 (a_im2), .a_im2 (a_im2),
.b_re2 (b_re2),
.b_im2 (b_im2),
.ab_re2 (ab_re2), .ab_re2 (ab_re2),
.ab_im2 (ab_im2), .ab_im2 (ab_im2),
.abb_re2 (abb_re2), .abb_re2 (abb_re2),
@ -495,6 +494,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im2 (b_pow8_im2), .b_pow8_im2 (b_pow8_im2),
.a_re3 (a_re3), .a_re3 (a_re3),
.a_im3 (a_im3), .a_im3 (a_im3),
.b_re3 (b_re3),
.b_im3 (b_im3),
.ab_re3 (ab_re3), .ab_re3 (ab_re3),
.ab_im3 (ab_im3), .ab_im3 (ab_im3),
.abb_re3 (abb_re3), .abb_re3 (abb_re3),
@ -513,6 +514,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im3 (b_pow8_im3), .b_pow8_im3 (b_pow8_im3),
.a_re4 (a_re4), .a_re4 (a_re4),
.a_im4 (a_im4), .a_im4 (a_im4),
.b_re4 (b_re4),
.b_im4 (b_im4),
.ab_re4 (ab_re4), .ab_re4 (ab_re4),
.ab_im4 (ab_im4), .ab_im4 (ab_im4),
.abb_re4 (abb_re4), .abb_re4 (abb_re4),
@ -531,6 +534,8 @@ TailCorr_top inst_TailCorr_top
.b_pow8_im4 (b_pow8_im4), .b_pow8_im4 (b_pow8_im4),
.a_re5 (a_re5), .a_re5 (a_re5),
.a_im5 (a_im5), .a_im5 (a_im5),
.b_re5 (b_re5),
.b_im5 (b_im5),
.ab_re5 (ab_re5), .ab_re5 (ab_re5),
.ab_im5 (ab_im5), .ab_im5 (ab_im5),
.abb_re5 (abb_re5), .abb_re5 (abb_re5),
@ -560,7 +565,6 @@ TailCorr_top inst_TailCorr_top
); );
integer signed In_fid[0:3]; integer signed In_fid[0:3];
integer signed dout_fid[0:7]; integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
@ -581,9 +585,6 @@ always @(posedge clk) begin
for (int i = 0; i < 4; i = i + 1) begin for (int i = 0; i < 4; i = i + 1) begin
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); $fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
end end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(In_fid[i]);
// end
end end
end end
@ -592,9 +593,6 @@ always @(posedge clk) begin
for (int i = 0; i < 8; i = i + 1) begin for (int i = 0; i < 8; i = i + 1) begin
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
end end
// for (int i = 0; i < 8; i = i + 1) begin
// $fclose(dout_fid[i]);
// end
end end
end end
endmodule endmodule

5
sim/tb_CoefGen/files.f
View File

@ -1,6 +1,7 @@
../../rtl/z_dsp/CoefGen.v ../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/sirv_gnrl_dffs.v
../../rtl/model/DW02_mult.v ../../rtl/model/DW02_mult.v
tb_CoefGen.v tb_CoefGen.v

174
sim/tb_CoefGen/tb_CoefGen.v
View File

@ -39,6 +39,8 @@ wire signed [31:0] ab_pow6_re [5:0];
wire signed [31:0] ab_pow6_im [5:0]; wire signed [31:0] ab_pow6_im [5:0];
wire signed [31:0] ab_pow7_re [5:0]; wire signed [31:0] ab_pow7_re [5:0];
wire signed [31:0] ab_pow7_im [5:0]; wire signed [31:0] ab_pow7_im [5:0];
wire signed [31:0] bo_re [5:0];
wire signed [31:0] bo_im [5:0];
wire signed [31:0] b_pow8_re [5:0]; wire signed [31:0] b_pow8_re [5:0];
wire signed [31:0] b_pow8_im [5:0]; wire signed [31:0] b_pow8_im [5:0];
@ -48,36 +50,158 @@ parameter CYCLE = 20;
parameter RST_TIME = 3 ; parameter RST_TIME = 3 ;
CoefGen inst_CoefGen(
CoefGen uut(
.clk (clk ), .clk (clk ),
.rstn (rst_n ), .rstn (rst_n ),
.vldi (vldi ), .vldi (vldi ),
.a_re (a_re ), .a0_re (a_re[0] ),
.a_im (a_im ), .a0_im (a_im[0] ),
.b_re (b_re ), .b0_re (b_re[0] ),
.b_im (b_im ), .b0_im (b_im[0] ),
.ao_re (ao_re ), .a1_re (a_re[1] ),
.ao_im (ao_im ), .a1_im (a_im[1] ),
.ab_re (ab_re ), .b1_re (b_re[1] ),
.ab_im (ab_im ), .b1_im (b_im[1] ),
.abb_re (abb_re ), .a2_re (a_re[2] ),
.abb_im (abb_im ), .a2_im (a_im[2] ),
.ab_pow3_re (ab_pow3_re ), .b2_re (b_re[2] ),
.ab_pow3_im (ab_pow3_im ), .b2_im (b_im[2] ),
.ab_pow4_re (ab_pow4_re ), .a3_re (a_re[3] ),
.ab_pow4_im (ab_pow4_im ), .a3_im (a_im[3] ),
.ab_pow5_re (ab_pow5_re ), .b3_re (b_re[3] ),
.ab_pow5_im (ab_pow5_im ), .b3_im (b_im[3] ),
.ab_pow6_re (ab_pow6_re ), .a4_re (a_re[4] ),
.ab_pow6_im (ab_pow6_im ), .a4_im (a_im[4] ),
.ab_pow7_re (ab_pow7_re ), .b4_re (b_re[4] ),
.ab_pow7_im (ab_pow7_im ), .b4_im (b_im[4] ),
.b_pow8_re (b_pow8_re ), .a5_re (a_re[5] ),
.b_pow8_im (b_pow8_im ) .a5_im (a_im[5] ),
.b5_re (b_re[5] ),
.b5_im (b_im[5] ),
.a_re0 (ao_re[0] ),
.a_im0 (ao_im[0] ),
.b_re0 (bo_re[0] ),
.b_im0 (bo_im[0] ),
.ab_re0 (ab_re[0] ),
.ab_im0 (ab_im[0] ),
.abb_re0 (abb_re[0] ),
.abb_im0 (abb_im[0] ),
.ab_pow3_re0 (ab_pow3_re[0]),
.ab_pow3_im0 (ab_pow3_im[0]),
.ab_pow4_re0 (ab_pow4_re[0]),
.ab_pow4_im0 (ab_pow4_im[0]),
.ab_pow5_re0 (ab_pow5_re[0]),
.ab_pow5_im0 (ab_pow5_im[0]),
.ab_pow6_re0 (ab_pow6_re[0]),
.ab_pow6_im0 (ab_pow6_im[0]),
.ab_pow7_re0 (ab_pow7_re[0]),
.ab_pow7_im0 (ab_pow7_im[0]),
.b_pow8_re0 (b_pow8_re[0] ),
.b_pow8_im0 (b_pow8_im[0] ),
.a_re1 (ao_re[1] ),
.a_im1 (ao_im[1] ),
.b_re1 (bo_re[1] ),
.b_im1 (bo_im[1] ),
.ab_re1 (ab_re[1] ),
.ab_im1 (ab_im[1] ),
.abb_re1 (abb_re[1] ),
.abb_im1 (abb_im[1] ),
.ab_pow3_re1 (ab_pow3_re[1]),
.ab_pow3_im1 (ab_pow3_im[1]),
.ab_pow4_re1 (ab_pow4_re[1]),
.ab_pow4_im1 (ab_pow4_im[1]),
.ab_pow5_re1 (ab_pow5_re[1]),
.ab_pow5_im1 (ab_pow5_im[1]),
.ab_pow6_re1 (ab_pow6_re[1]),
.ab_pow6_im1 (ab_pow6_im[1]),
.ab_pow7_re1 (ab_pow7_re[1]),
.ab_pow7_im1 (ab_pow7_im[1]),
.b_pow8_re1 (b_pow8_re[1] ),
.b_pow8_im1 (b_pow8_im[1] ),
.a_re2 (ao_re[2] ),
.a_im2 (ao_im[2] ),
.b_re2 (bo_re[2] ),
.b_im2 (bo_im[2] ),
.ab_re2 (ab_re[2] ),
.ab_im2 (ab_im[2] ),
.abb_re2 (abb_re[2] ),
.abb_im2 (abb_im[2] ),
.ab_pow3_re2 (ab_pow3_re[2]),
.ab_pow3_im2 (ab_pow3_im[2]),
.ab_pow4_re2 (ab_pow4_re[2]),
.ab_pow4_im2 (ab_pow4_im[2]),
.ab_pow5_re2 (ab_pow5_re[2]),
.ab_pow5_im2 (ab_pow5_im[2]),
.ab_pow6_re2 (ab_pow6_re[2]),
.ab_pow6_im2 (ab_pow6_im[2]),
.ab_pow7_re2 (ab_pow7_re[2]),
.ab_pow7_im2 (ab_pow7_im[2]),
.b_pow8_re2 (b_pow8_re[2] ),
.b_pow8_im2 (b_pow8_im[2] ),
.a_re3 (ao_re[3] ),
.a_im3 (ao_im[3] ),
.b_re3 (bo_re[3] ),
.b_im3 (bo_im[3] ),
.ab_re3 (ab_re[3] ),
.ab_im3 (ab_im[3] ),
.abb_re3 (abb_re[3] ),
.abb_im3 (abb_im[3] ),
.ab_pow3_re3 (ab_pow3_re[3]),
.ab_pow3_im3 (ab_pow3_im[3]),
.ab_pow4_re3 (ab_pow4_re[3]),
.ab_pow4_im3 (ab_pow4_im[3]),
.ab_pow5_re3 (ab_pow5_re[3]),
.ab_pow5_im3 (ab_pow5_im[3]),
.ab_pow6_re3 (ab_pow6_re[3]),
.ab_pow6_im3 (ab_pow6_im[3]),
.ab_pow7_re3 (ab_pow7_re[3]),
.ab_pow7_im3 (ab_pow7_im[3]),
.b_pow8_re3 (b_pow8_re[3] ),
.b_pow8_im3 (b_pow8_im[3] ),
.a_re4 (ao_re[4] ),
.a_im4 (ao_im[4] ),
.b_re4 (bo_re[4] ),
.b_im4 (bo_im[4] ),
.ab_re4 (ab_re[4] ),
.ab_im4 (ab_im[4] ),
.abb_re4 (abb_re[4] ),
.abb_im4 (abb_im[4] ),
.ab_pow3_re4 (ab_pow3_re[4]),
.ab_pow3_im4 (ab_pow3_im[4]),
.ab_pow4_re4 (ab_pow4_re[4]),
.ab_pow4_im4 (ab_pow4_im[4]),
.ab_pow5_re4 (ab_pow5_re[4]),
.ab_pow5_im4 (ab_pow5_im[4]),
.ab_pow6_re4 (ab_pow6_re[4]),
.ab_pow6_im4 (ab_pow6_im[4]),
.ab_pow7_re4 (ab_pow7_re[4]),
.ab_pow7_im4 (ab_pow7_im[4]),
.b_pow8_re4 (b_pow8_re[4] ),
.b_pow8_im4 (b_pow8_im[4] ),
.a_re5 (ao_re[5] ),
.a_im5 (ao_im[5] ),
.b_re5 (bo_re[5] ),
.b_im5 (bo_im[5] ),
.ab_re5 (ab_re[5] ),
.ab_im5 (ab_im[5] ),
.abb_re5 (abb_re[5] ),
.abb_im5 (abb_im[5] ),
.ab_pow3_re5 (ab_pow3_re[5]),
.ab_pow3_im5 (ab_pow3_im[5]),
.ab_pow4_re5 (ab_pow4_re[5]),
.ab_pow4_im5 (ab_pow4_im[5]),
.ab_pow5_re5 (ab_pow5_re[5]),
.ab_pow5_im5 (ab_pow5_im[5]),
.ab_pow6_re5 (ab_pow6_re[5]),
.ab_pow6_im5 (ab_pow6_im[5]),
.ab_pow7_re5 (ab_pow7_re[5]),
.ab_pow7_im5 (ab_pow7_im[5]),
.b_pow8_re5 (b_pow8_re[5] ),
.b_pow8_im5 (b_pow8_im[5] )
); );
initial begin initial begin
clk = 0; clk = 0;

5
sim/z_dsp/files.f
View File

@ -1,12 +1,13 @@
../../rtl/z_dsp/z_dsp.sv ../../rtl/z_dsp/z_dsp.sv
../../rtl/z_dsp/TailCorr_top.v ../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/rate_adapter.v ../../rtl/z_dsp/rate_adapter.v
../../rtl/z_dsp/IIR_top.v
../../rtl/z_dsp/IIR_Filter_p1.v
../../rtl/z_dsp/IIR_Filter_p8.v ../../rtl/z_dsp/IIR_Filter_p8.v
../../rtl/z_dsp/CoefGen.sv ../../rtl/z_dsp/CoefGen.sv
../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/diff_p.v
../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/s2p_2.v
../../rtl/z_dsp/FixRound.v ../../rtl/z_dsp/Trunc.v
../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/mult_x.v ../../rtl/z_dsp/mult_x.v
../../rtl/z_dsp/syncer.v ../../rtl/z_dsp/syncer.v

12
sim/z_dsp/tb_z_dsp.v
View File

@ -40,6 +40,18 @@ initial begin
vldi_data <= 0; vldi_data <= 0;
vldi_coef <= 0; vldi_coef <= 0;
din_rect = 16'd0; din_rect = 16'd0;
a_re[3] <= 0;
a_im[3] <= 0;
b_re[3] <= 0;
b_im[3] <= 0;
a_re[4] <= 0;
a_im[4] <= 0;
b_re[4] <= 0;
b_im[4] <= 0;
a_re[5] <= 0;
a_im[5] <= 0;
b_re[5] <= 0;
b_im[5] <= 0;
repeat(3) @(posedge clk); repeat(3) @(posedge clk);
vldi_coef[0] <= 1; vldi_coef[0] <= 1;
rstn = 1; rstn = 1;