From 30cc4e3d35fd564e36e6dfe407d84ec4e13f3fa5 Mon Sep 17 00:00:00 2001 From: dada Date: Wed, 12 Mar 2025 14:36:22 +0800 Subject: [PATCH 1/5] =?UTF-8?q?=E5=85=AB=E8=B7=AF=E5=B9=B6=E8=A1=8C?= =?UTF-8?q?=EF=BC=8C=E4=B8=80=E8=B7=AF=E8=B6=85=E5=89=8D=E8=AE=A1=E7=AE=97?= =?UTF-8?q?=EF=BC=8C=E4=B8=83=E8=B7=AF=E8=BF=9B=E4=BD=8D=E9=93=BE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 2st --- rtl/{z_dsp => ref}/FixRound.v | 1 - rtl/ref/IIR_Filter_p8.v | 345 ++++++++++ rtl/ref/IIR_top.v | 379 +++++++++++ rtl/ref/TailCorr_top.v | 900 +++++++++++++++++++++++++ rtl/ref/diff_p.v | 236 +++++++ rtl/ref/mult_C.v | 110 +++ rtl/ref/s2p_2.v | 121 ++++ rtl/z_dsp/CoefGen.sv | 693 ------------------- rtl/z_dsp/IIR_Filter_p1.v | 132 ++++ rtl/z_dsp/IIR_Filter_p8.v | 182 ++--- rtl/z_dsp/IIR_top.v | 645 +++++++++--------- rtl/z_dsp/TailCorr_top.v | 563 +++++++++++----- rtl/z_dsp/Trunc.v | 55 ++ rtl/z_dsp/diff_p.v | 236 +++---- rtl/z_dsp/mult_C.v | 20 +- rtl/z_dsp/mult_x.v | 21 +- rtl/z_dsp/rate_adapter.v | 89 --- rtl/z_dsp/sirv_gnrl_dffs.v | 326 --------- rtl/z_dsp/syncer.v | 58 -- rtl/z_dsp/z_dsp.sv | 402 ----------- sim/{TailCorr_en => }/Makefile | 0 sim/TailCorr_en/files.f | 11 - sim/files.f | 20 + sim/s2p_2/Makefile | 17 - sim/s2p_2/files.f | 2 - sim/s2p_2/tb_s2p_2.v | 130 ---- sim/tb_CoefGen/Makefile | 24 - sim/tb_CoefGen/files.f | 6 - sim/tb_CoefGen/tb_CoefGen.v | 162 ----- sim/{TailCorr_en => }/tb_TailCorr_en.v | 185 ++++- sim/z_dsp/Makefile | 24 - sim/z_dsp/files.f | 16 - sim/z_dsp/tb_z_dsp.v | 328 --------- 33 files changed, 3385 insertions(+), 3054 deletions(-) rename rtl/{z_dsp => ref}/FixRound.v (99%) create mode 100644 rtl/ref/IIR_Filter_p8.v create mode 100644 rtl/ref/IIR_top.v create mode 100644 rtl/ref/TailCorr_top.v create mode 100644 rtl/ref/diff_p.v create mode 100644 rtl/ref/mult_C.v create mode 100644 rtl/ref/s2p_2.v delete mode 100644 rtl/z_dsp/CoefGen.sv create mode 100644 rtl/z_dsp/IIR_Filter_p1.v create mode 100644 rtl/z_dsp/Trunc.v delete mode 100644 rtl/z_dsp/rate_adapter.v delete mode 100644 rtl/z_dsp/sirv_gnrl_dffs.v delete mode 100644 rtl/z_dsp/syncer.v delete mode 100644 rtl/z_dsp/z_dsp.sv rename sim/{TailCorr_en => }/Makefile (100%) delete mode 100644 sim/TailCorr_en/files.f create mode 100644 sim/files.f delete mode 100644 sim/s2p_2/Makefile delete mode 100644 sim/s2p_2/files.f delete mode 100644 sim/s2p_2/tb_s2p_2.v delete mode 100644 sim/tb_CoefGen/Makefile delete mode 100644 sim/tb_CoefGen/files.f delete mode 100644 sim/tb_CoefGen/tb_CoefGen.v rename sim/{TailCorr_en => }/tb_TailCorr_en.v (67%) delete mode 100644 sim/z_dsp/Makefile delete mode 100644 sim/z_dsp/files.f delete mode 100644 sim/z_dsp/tb_z_dsp.v diff --git a/rtl/z_dsp/FixRound.v b/rtl/ref/FixRound.v similarity index 99% rename from rtl/z_dsp/FixRound.v rename to rtl/ref/FixRound.v index ccb6904..7701c11 100644 --- a/rtl/z_dsp/FixRound.v +++ b/rtl/ref/FixRound.v @@ -35,4 +35,3 @@ always@(posedge clk or negedge rstn) assign dout = din_round; endmodule - diff --git a/rtl/ref/IIR_Filter_p8.v b/rtl/ref/IIR_Filter_p8.v new file mode 100644 index 0000000..1b9602d --- /dev/null +++ b/rtl/ref/IIR_Filter_p8.v @@ -0,0 +1,345 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : IIR_Filter.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.4 2024-05-28 thfu +//2024-05-28 10:22:49 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module IIR_Filter_p8_ref #( + parameter data_in_width = 16 +,parameter coef_width = 32 +,parameter frac_data_out_width = 20//X for in,5 +,parameter frac_coef_width = 31//division +) +( + input rstn +,input clk +,input en +,input signed [data_in_width-1:0] dinp0 +,input signed [data_in_width-1:0] dinp1 +,input signed [data_in_width-1:0] dinp2 +,input signed [data_in_width-1:0] dinp3 +,input signed [data_in_width-1:0] dinp4 +,input signed [data_in_width-1:0] dinp5 +,input signed [data_in_width-1:0] dinp6 +,input signed [data_in_width-1:0] dinp7 + +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] ab_re +,input signed [coef_width-1 :0] ab_im +,input signed [coef_width-1 :0] abb_re +,input signed [coef_width-1 :0] abb_im +,input signed [coef_width-1 :0] ab_pow3_re +,input signed [coef_width-1 :0] ab_pow3_im +,input signed [coef_width-1 :0] ab_pow4_re +,input signed [coef_width-1 :0] ab_pow4_im +,input signed [coef_width-1 :0] ab_pow5_re +,input signed [coef_width-1 :0] ab_pow5_im +,input signed [coef_width-1 :0] ab_pow6_re +,input signed [coef_width-1 :0] ab_pow6_im +,input signed [coef_width-1 :0] ab_pow7_re +,input signed [coef_width-1 :0] ab_pow7_im + +,input signed [coef_width-1 :0] b_pow8_re +,input signed [coef_width-1 :0] b_pow8_im +,output signed [data_in_width-1:0] dout +); + + +wire signed [data_in_width+frac_data_out_width:0] x1_re; +wire signed [data_in_width+frac_data_out_width:0] x1_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp0 ), + .b (16'b0 ), + .c ({a_re,{frac_data_out_width{1'b0}}}), + .d ({a_im,{frac_data_out_width{1'b0}}}), + .Re (x1_re ),//a*x*dinp0 + .Im (x1_im ) + ); + +wire signed [data_in_width+frac_data_out_width:0] x2_re; +wire signed [data_in_width+frac_data_out_width:0] x2_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp1 ), + .b (16'd0 ), + .c ({ab_re,{frac_data_out_width{1'b0}}} ), + .d ({ab_im,{frac_data_out_width{1'b0}}} ), + .Re (x2_re ),//a*b*dinp1 + .Im (x2_im ) + ); + +wire signed [data_in_width+frac_data_out_width:0] x3_re; +wire signed [data_in_width+frac_data_out_width:0] x3_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp2 ), + .b (16'd0 ), + .c ({abb_re,{frac_data_out_width{1'b0}}} ), + .d ({abb_im,{frac_data_out_width{1'b0}}} ), + .Re (x3_re ),//a*b*b*dinp2 + .Im (x3_im ) + ); +wire signed [data_in_width+frac_data_out_width:0] x4_re; +wire signed [data_in_width+frac_data_out_width:0] x4_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp3 ), + .b (16'd0 ), + .c ({ab_pow3_re,{frac_data_out_width{1'b0}}} ), + .d ({ab_pow3_im,{frac_data_out_width{1'b0}}} ), + .Re (x4_re ),//a*b^3*dinp3 + .Im (x4_im ) + ); +wire signed [data_in_width+frac_data_out_width:0] x5_re; +wire signed [data_in_width+frac_data_out_width:0] x5_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp4 ), + .b (16'd0 ), + .c ({ab_pow4_re,{frac_data_out_width{1'b0}}} ), + .d ({ab_pow4_im,{frac_data_out_width{1'b0}}} ), + .Re (x5_re ),//a*b^4*dinp4 + .Im (x5_im ) + ); +wire signed [data_in_width+frac_data_out_width:0] x6_re; +wire signed [data_in_width+frac_data_out_width:0] x6_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c6 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp5 ), + .b (16'd0 ), + .c ({ab_pow5_re,{frac_data_out_width{1'b0}}} ), + .d ({ab_pow5_im,{frac_data_out_width{1'b0}}} ), + .Re (x6_re ),//a*b^5*dinp5 + .Im (x6_im ) + ); +wire signed [data_in_width+frac_data_out_width:0] x7_re; +wire signed [data_in_width+frac_data_out_width:0] x7_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c7 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp6 ), + .b (16'd0 ), + .c ({ab_pow6_re,{frac_data_out_width{1'b0}}} ), + .d ({ab_pow6_im,{frac_data_out_width{1'b0}}} ), + .Re (x7_re ),//a*b^6*dinp6 + .Im (x7_im ) + ); +wire signed [data_in_width+frac_data_out_width:0] x8_re; +wire signed [data_in_width+frac_data_out_width:0] x8_im; +mult_C_ref +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c8 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp7 ), + .b (16'd0 ), + .c ({ab_pow7_re,{frac_data_out_width{1'b0}}} ), + .d ({ab_pow7_im,{frac_data_out_width{1'b0}}} ), + .Re (x8_re ),//a*b^7*dinp7 + .Im (x8_im ) + ); + +wire signed [data_in_width+frac_data_out_width+1:0] v_re; +wire signed [data_in_width+frac_data_out_width+1:0] v_im; + +assign v_re = x1_re + x2_re + x3_re + x4_re + x5_re + x6_re + x7_re + x8_re; +assign v_im = x1_im + x2_im + x3_im + x4_im + x5_im + x6_im + x7_im + x8_im; + +reg signed [data_in_width+frac_data_out_width+1:0] v1_re; +reg signed [data_in_width+frac_data_out_width+1:0] v1_im; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + v1_re <= 'h0; + v1_im <= 'h0; + end + else if(en) + begin + v1_re <= v_re; + v1_im <= v_im; + end + else + begin + v1_re <= v1_re; + v1_im <= v1_im; + end + +wire signed [data_in_width+frac_data_out_width+1:0] y_re; +wire signed [data_in_width+frac_data_out_width+1:0] y_im; +reg signed [data_in_width+frac_data_out_width+2:0] y1_re; +reg signed [data_in_width+frac_data_out_width+2:0] y1_im; + +reg signed [data_in_width-1:0] dout_re; + +mult_C_ref +#( + .A_width(data_in_width+frac_data_out_width+2) +,.B_width(data_in_width+frac_data_out_width+2) +,.C_width(coef_width) +,.D_width(coef_width) +,.frac_coef_width(frac_coef_width) +) +inst_c9 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y_re ), + .b (y_im ), + .c (b_pow8_re ), + .d (b_pow8_im ), + .Re (y1_re ),//b^8*y(n-1) + .Im (y1_im ) + ); + +assign y_re = v1_re + y1_re; +assign y_im = v1_im + y1_im; + +wire signed [data_in_width+frac_data_out_width+1:0] dout_round; + +FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round); + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_re <= 'h0; + end + else if(en) + begin + dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width]; + end + else + begin + dout_re <= dout_re; + end + +reg signed [data_in_width-1:0] dout_clip; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_clip <= 'h0; + end + else if(en) + begin + if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01) + dout_clip <= 16'd32767; + else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10) + dout_clip <= -16'd32768; + else + dout_clip <= dout_re; + end + else + begin + dout_clip <= dout_clip; + end + +assign dout = dout_clip; + +endmodule + diff --git a/rtl/ref/IIR_top.v b/rtl/ref/IIR_top.v new file mode 100644 index 0000000..296643d --- /dev/null +++ b/rtl/ref/IIR_top.v @@ -0,0 +1,379 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : TailCorr_top.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.3 2024-05-15 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module IIR_top_ref + +( +input rstn +,input clk +,input en +,input signed [15:0] IIRin_p0 +,input signed [15:0] IIRin_p1 +,input signed [15:0] IIRin_p2 +,input signed [15:0] IIRin_p3 +,input signed [15:0] IIRin_p4 +,input signed [15:0] IIRin_p5 +,input signed [15:0] IIRin_p6 +,input signed [15:0] IIRin_p7 +,input signed [31 :0] a_re +,input signed [31 :0] a_im +,input signed [31 :0] ab_re +,input signed [31 :0] ab_im +,input signed [31 :0] abb_re +,input signed [31 :0] abb_im +,input signed [31 :0] ab_pow3_re +,input signed [31 :0] ab_pow3_im +,input signed [31 :0] ab_pow4_re +,input signed [31 :0] ab_pow4_im +,input signed [31 :0] ab_pow5_re +,input signed [31 :0] ab_pow5_im +,input signed [31 :0] ab_pow6_re +,input signed [31 :0] ab_pow6_im +,input signed [31 :0] ab_pow7_re +,input signed [31 :0] ab_pow7_im +,input signed [31 :0] b_pow8_re +,input signed [31 :0] b_pow8_im + +,output signed [15:0] IIRout_p0 +,output signed [15:0] IIRout_p1 +,output signed [15:0] IIRout_p2 +,output signed [15:0] IIRout_p3 +,output signed [15:0] IIRout_p4 +,output signed [15:0] IIRout_p5 +,output signed [15:0] IIRout_p6 +,output signed [15:0] IIRout_p7 + ); + +reg signed [15:0] IIRin_p0_r1; +reg signed [15:0] IIRin_p1_r1; +reg signed [15:0] IIRin_p2_r1; +reg signed [15:0] IIRin_p3_r1; +reg signed [15:0] IIRin_p4_r1; +reg signed [15:0] IIRin_p5_r1; +reg signed [15:0] IIRin_p6_r1; +reg signed [15:0] IIRin_p7_r1; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + IIRin_p0_r1 <= 'h0; + IIRin_p1_r1 <= 'h0; + IIRin_p2_r1 <= 'h0; + IIRin_p3_r1 <= 'h0; + IIRin_p4_r1 <= 'h0; + IIRin_p5_r1 <= 'h0; + IIRin_p6_r1 <= 'h0; + IIRin_p7_r1 <= 'h0; + end + else if(en) + begin + IIRin_p0_r1 <= IIRin_p0; + IIRin_p1_r1 <= IIRin_p1; + IIRin_p2_r1 <= IIRin_p2; + IIRin_p3_r1 <= IIRin_p3; + IIRin_p4_r1 <= IIRin_p4; + IIRin_p5_r1 <= IIRin_p5; + IIRin_p6_r1 <= IIRin_p6; + IIRin_p7_r1 <= IIRin_p7; + end + else + begin + IIRin_p0_r1 <= IIRin_p0_r1; + IIRin_p1_r1 <= IIRin_p1_r1; + IIRin_p2_r1 <= IIRin_p2_r1; + IIRin_p3_r1 <= IIRin_p3_r1; + IIRin_p4_r1 <= IIRin_p4_r1; + IIRin_p5_r1 <= IIRin_p5_r1; + IIRin_p6_r1 <= IIRin_p6_r1; + IIRin_p7_r1 <= IIRin_p7_r1; + end + +IIR_Filter_p8_ref inst_iir_0_p0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p0 ), + .dinp1 (IIRin_p7_r1 ), + .dinp2 (IIRin_p6_r1 ), + .dinp3 (IIRin_p5_r1 ), + .dinp4 (IIRin_p4_r1 ), + .dinp5 (IIRin_p3_r1 ), + .dinp6 (IIRin_p2_r1 ), + .dinp7 (IIRin_p1_r1 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p0 ) + ); + +IIR_Filter_p8_ref inst_iir_o_p1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p1 ), + .dinp1 (IIRin_p0 ), + .dinp2 (IIRin_p7_r1 ), + .dinp3 (IIRin_p6_r1 ), + .dinp4 (IIRin_p5_r1 ), + .dinp5 (IIRin_p4_r1 ), + .dinp6 (IIRin_p3_r1 ), + .dinp7 (IIRin_p2_r1 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p1 ) + ); +IIR_Filter_p8_ref inst_iir_0_p2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p2 ), + .dinp1 (IIRin_p1 ), + .dinp2 (IIRin_p0 ), + .dinp3 (IIRin_p7_r1 ), + .dinp4 (IIRin_p6_r1 ), + .dinp5 (IIRin_p5_r1 ), + .dinp6 (IIRin_p4_r1 ), + .dinp7 (IIRin_p3_r1 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p2 ) + ); +IIR_Filter_p8_ref inst_iir_0_p3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p3 ), + .dinp1 (IIRin_p2 ), + .dinp2 (IIRin_p1 ), + .dinp3 (IIRin_p0 ), + .dinp4 (IIRin_p7_r1 ), + .dinp5 (IIRin_p6_r1 ), + .dinp6 (IIRin_p5_r1 ), + .dinp7 (IIRin_p4_r1 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p3 ) + ); +IIR_Filter_p8_ref inst_iir_0_p4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p4 ), + .dinp1 (IIRin_p3 ), + .dinp2 (IIRin_p2 ), + .dinp3 (IIRin_p1 ), + .dinp4 (IIRin_p0 ), + .dinp5 (IIRin_p7_r1 ), + .dinp6 (IIRin_p6_r1 ), + .dinp7 (IIRin_p5_r1 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p4 ) + ); +IIR_Filter_p8_ref inst_iir_0_p5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p5 ), + .dinp1 (IIRin_p4 ), + .dinp2 (IIRin_p3 ), + .dinp3 (IIRin_p2 ), + .dinp4 (IIRin_p1 ), + .dinp5 (IIRin_p0 ), + .dinp6 (IIRin_p7_r1 ), + .dinp7 (IIRin_p6_r1 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p5 ) + ); +IIR_Filter_p8_ref inst_iir_0_p6 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p6 ), + .dinp1 (IIRin_p5 ), + .dinp2 (IIRin_p4 ), + .dinp3 (IIRin_p3 ), + .dinp4 (IIRin_p2 ), + .dinp5 (IIRin_p1 ), + .dinp6 (IIRin_p0 ), + .dinp7 (IIRin_p7_r1 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p6 ) + ); +IIR_Filter_p8_ref inst_iir_0_p7 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p7 ), + .dinp1 (IIRin_p6 ), + .dinp2 (IIRin_p5 ), + .dinp3 (IIRin_p4 ), + .dinp4 (IIRin_p3 ), + .dinp5 (IIRin_p2 ), + .dinp6 (IIRin_p1 ), + .dinp7 (IIRin_p0 ), + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout (IIRout_p7 ) + ); + +endmodule + diff --git a/rtl/ref/TailCorr_top.v b/rtl/ref/TailCorr_top.v new file mode 100644 index 0000000..0f99801 --- /dev/null +++ b/rtl/ref/TailCorr_top.v @@ -0,0 +1,900 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : TailCorr_top.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.3 2025-02-28 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module TailCorr_top_ref + +( + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,input signed [31:0] a_re0 +,input signed [31:0] a_im0 +,input signed [31:0] ab_re0 +,input signed [31:0] ab_im0 +,input signed [31:0] abb_re0 +,input signed [31:0] abb_im0 +,input signed [31:0] ab_pow3_re0 +,input signed [31:0] ab_pow3_im0 +,input signed [31:0] ab_pow4_re0 +,input signed [31:0] ab_pow4_im0 +,input signed [31:0] ab_pow5_re0 +,input signed [31:0] ab_pow5_im0 +,input signed [31:0] ab_pow6_re0 +,input signed [31:0] ab_pow6_im0 +,input signed [31:0] ab_pow7_re0 +,input signed [31:0] ab_pow7_im0 +,input signed [31:0] b_pow8_re0 +,input signed [31:0] b_pow8_im0 +,input signed [31:0] a_re1 +,input signed [31:0] a_im1 +,input signed [31:0] ab_re1 +,input signed [31:0] ab_im1 +,input signed [31:0] abb_re1 +,input signed [31:0] abb_im1 +,input signed [31:0] ab_pow3_re1 +,input signed [31:0] ab_pow3_im1 +,input signed [31:0] ab_pow4_re1 +,input signed [31:0] ab_pow4_im1 +,input signed [31:0] ab_pow5_re1 +,input signed [31:0] ab_pow5_im1 +,input signed [31:0] ab_pow6_re1 +,input signed [31:0] ab_pow6_im1 +,input signed [31:0] ab_pow7_re1 +,input signed [31:0] ab_pow7_im1 +,input signed [31:0] b_pow8_re1 +,input signed [31:0] b_pow8_im1 +,input signed [31:0] a_re2 +,input signed [31:0] a_im2 +,input signed [31:0] ab_re2 +,input signed [31:0] ab_im2 +,input signed [31:0] abb_re2 +,input signed [31:0] abb_im2 +,input signed [31:0] ab_pow3_re2 +,input signed [31:0] ab_pow3_im2 +,input signed [31:0] ab_pow4_re2 +,input signed [31:0] ab_pow4_im2 +,input signed [31:0] ab_pow5_re2 +,input signed [31:0] ab_pow5_im2 +,input signed [31:0] ab_pow6_re2 +,input signed [31:0] ab_pow6_im2 +,input signed [31:0] ab_pow7_re2 +,input signed [31:0] ab_pow7_im2 +,input signed [31:0] b_pow8_re2 +,input signed [31:0] b_pow8_im2 +,input signed [31:0] a_re3 +,input signed [31:0] a_im3 +,input signed [31:0] ab_re3 +,input signed [31:0] ab_im3 +,input signed [31:0] abb_re3 +,input signed [31:0] abb_im3 +,input signed [31:0] ab_pow3_re3 +,input signed [31:0] ab_pow3_im3 +,input signed [31:0] ab_pow4_re3 +,input signed [31:0] ab_pow4_im3 +,input signed [31:0] ab_pow5_re3 +,input signed [31:0] ab_pow5_im3 +,input signed [31:0] ab_pow6_re3 +,input signed [31:0] ab_pow6_im3 +,input signed [31:0] ab_pow7_re3 +,input signed [31:0] ab_pow7_im3 +,input signed [31:0] b_pow8_re3 +,input signed [31:0] b_pow8_im3 +,input signed [31:0] a_re4 +,input signed [31:0] a_im4 +,input signed [31:0] ab_re4 +,input signed [31:0] ab_im4 +,input signed [31:0] abb_re4 +,input signed [31:0] abb_im4 +,input signed [31:0] ab_pow3_re4 +,input signed [31:0] ab_pow3_im4 +,input signed [31:0] ab_pow4_re4 +,input signed [31:0] ab_pow4_im4 +,input signed [31:0] ab_pow5_re4 +,input signed [31:0] ab_pow5_im4 +,input signed [31:0] ab_pow6_re4 +,input signed [31:0] ab_pow6_im4 +,input signed [31:0] ab_pow7_re4 +,input signed [31:0] ab_pow7_im4 +,input signed [31:0] b_pow8_re4 +,input signed [31:0] b_pow8_im4 +,input signed [31:0] a_re5 +,input signed [31:0] a_im5 +,input signed [31:0] ab_re5 +,input signed [31:0] ab_im5 +,input signed [31:0] abb_re5 +,input signed [31:0] abb_im5 +,input signed [31:0] ab_pow3_re5 +,input signed [31:0] ab_pow3_im5 +,input signed [31:0] ab_pow4_re5 +,input signed [31:0] ab_pow4_im5 +,input signed [31:0] ab_pow5_re5 +,input signed [31:0] ab_pow5_im5 +,input signed [31:0] ab_pow6_re5 +,input signed [31:0] ab_pow6_im5 +,input signed [31:0] ab_pow7_re5 +,input signed [31:0] ab_pow7_im5 +,input signed [31:0] b_pow8_re5 +,input signed [31:0] b_pow8_im5 + +,output signed [15:0] dout_p0 +,output signed [15:0] dout_p1 +,output signed [15:0] dout_p2 +,output signed [15:0] dout_p3 +,output signed [15:0] dout_p4 +,output signed [15:0] dout_p5 +,output signed [15:0] dout_p6 +,output signed [15:0] dout_p7 +,output vldo + ); + +wire signed [15:0] din_p0; +wire signed [15:0] din_p1; +wire signed [15:0] din_p2; +wire signed [15:0] din_p3; +wire signed [15:0] din_p4; +wire signed [15:0] din_p5; +wire signed [15:0] din_p6; +wire signed [15:0] din_p7; +wire signed [15:0] IIRin_p0; +wire signed [15:0] IIRin_p1; +wire signed [15:0] IIRin_p2; +wire signed [15:0] IIRin_p3; +wire signed [15:0] IIRin_p4; +wire signed [15:0] IIRin_p5; +wire signed [15:0] IIRin_p6; +wire signed [15:0] IIRin_p7; +wire vldo_diff; +diff_p_ref inst_diff_p_ref ( + .rstn (rstn), + .clk (clk ), + .en (en ), + .vldi (vldi), + .din0 (din0), + .din1 (din1), + .din2 (din2), + .din3 (din3), + .vldo (vldo_diff), + .dout_p0 (din_p0), + .dout_p1 (din_p1), + .dout_p2 (din_p2), + .dout_p3 (din_p3), + .dout_p4 (din_p4), + .dout_p5 (din_p5), + .dout_p6 (din_p6), + .dout_p7 (din_p7), + .diff_p0 (IIRin_p0), + .diff_p1 (IIRin_p1), + .diff_p2 (IIRin_p2), + .diff_p3 (IIRin_p3), + .diff_p4 (IIRin_p4), + .diff_p5 (IIRin_p5), + .diff_p6 (IIRin_p6), + .diff_p7 (IIRin_p7) +); + +reg signed [15:0] din_p0_r1; +reg signed [15:0] din_p0_r2; +reg signed [15:0] din_p0_r3; +reg signed [15:0] din_p0_r4; +reg signed [15:0] din_p0_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p0_r1 <= 'h0; + din_p0_r2 <= 'h0; + din_p0_r3 <= 'h0; + din_p0_r4 <= 'h0; + din_p0_r5 <= 'h0; + end + else if(en) + begin + din_p0_r1 <= din_p0; + din_p0_r2 <= din_p0_r1; + din_p0_r3 <= din_p0_r2; + din_p0_r4 <= din_p0_r3; + din_p0_r5 <= din_p0_r4; + end + else + begin + din_p0_r1 <= din_p0_r1; + din_p0_r2 <= din_p0_r2; + din_p0_r3 <= din_p0_r3; + din_p0_r4 <= din_p0_r4; + din_p0_r5 <= din_p0_r5; + end +reg signed [15:0] din_p1_r1; +reg signed [15:0] din_p1_r2; +reg signed [15:0] din_p1_r3; +reg signed [15:0] din_p1_r4; +reg signed [15:0] din_p1_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p1_r1 <= 'h0; + din_p1_r2 <= 'h0; + din_p1_r3 <= 'h0; + din_p1_r4 <= 'h0; + din_p1_r5 <= 'h0; + end + else if(en) + begin + din_p1_r1 <= din_p1; + din_p1_r2 <= din_p1_r1; + din_p1_r3 <= din_p1_r2; + din_p1_r4 <= din_p1_r3; + din_p1_r5 <= din_p1_r4; + end + else + begin + din_p1_r1 <= din_p1_r1; + din_p1_r2 <= din_p1_r2; + din_p1_r3 <= din_p1_r3; + din_p1_r4 <= din_p1_r4; + din_p1_r5 <= din_p1_r5; + end +reg signed [15:0] din_p2_r1; +reg signed [15:0] din_p2_r2; +reg signed [15:0] din_p2_r3; +reg signed [15:0] din_p2_r4; +reg signed [15:0] din_p2_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p2_r1 <= 'h0; + din_p2_r2 <= 'h0; + din_p2_r3 <= 'h0; + din_p2_r4 <= 'h0; + din_p2_r5 <= 'h0; + end + else if(en) + begin + din_p2_r1 <= din_p2; + din_p2_r2 <= din_p2_r1; + din_p2_r3 <= din_p2_r2; + din_p2_r4 <= din_p2_r3; + din_p2_r5 <= din_p2_r4; + end + else + begin + din_p2_r1 <= din_p2_r1; + din_p2_r2 <= din_p2_r2; + din_p2_r3 <= din_p2_r3; + din_p2_r4 <= din_p2_r4; + din_p2_r5 <= din_p2_r5; + end +reg signed [15:0] din_p3_r1; +reg signed [15:0] din_p3_r2; +reg signed [15:0] din_p3_r3; +reg signed [15:0] din_p3_r4; +reg signed [15:0] din_p3_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p3_r1 <= 'h0; + din_p3_r2 <= 'h0; + din_p3_r3 <= 'h0; + din_p3_r4 <= 'h0; + din_p3_r5 <= 'h0; + end + else if(en) + begin + din_p3_r1 <= din_p3; + din_p3_r2 <= din_p3_r1; + din_p3_r3 <= din_p3_r2; + din_p3_r4 <= din_p3_r3; + din_p3_r5 <= din_p3_r4; + end + else + begin + din_p3_r1 <= din_p3_r1; + din_p3_r2 <= din_p3_r2; + din_p3_r3 <= din_p3_r3; + din_p3_r4 <= din_p3_r4; + din_p3_r5 <= din_p3_r5; + end +reg signed [15:0] din_p4_r1; +reg signed [15:0] din_p4_r2; +reg signed [15:0] din_p4_r3; +reg signed [15:0] din_p4_r4; +reg signed [15:0] din_p4_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p4_r1 <= 'h0; + din_p4_r2 <= 'h0; + din_p4_r3 <= 'h0; + din_p4_r4 <= 'h0; + din_p4_r5 <= 'h0; + end + else if(en) + begin + din_p4_r1 <= din_p4; + din_p4_r2 <= din_p4_r1; + din_p4_r3 <= din_p4_r2; + din_p4_r4 <= din_p4_r3; + din_p4_r5 <= din_p4_r4; + end + else + begin + din_p4_r1 <= din_p4_r1; + din_p4_r2 <= din_p4_r2; + din_p4_r3 <= din_p4_r3; + din_p4_r4 <= din_p4_r4; + din_p4_r5 <= din_p4_r5; + end +reg signed [15:0] din_p5_r1; +reg signed [15:0] din_p5_r2; +reg signed [15:0] din_p5_r3; +reg signed [15:0] din_p5_r4; +reg signed [15:0] din_p5_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p5_r1 <= 'h0; + din_p5_r2 <= 'h0; + din_p5_r3 <= 'h0; + din_p5_r4 <= 'h0; + din_p5_r5 <= 'h0; + end + else if(en) + begin + din_p5_r1 <= din_p5; + din_p5_r2 <= din_p5_r1; + din_p5_r3 <= din_p5_r2; + din_p5_r4 <= din_p5_r3; + din_p5_r5 <= din_p5_r4; + end + else + begin + din_p5_r1 <= din_p5_r1; + din_p5_r2 <= din_p5_r2; + din_p5_r3 <= din_p5_r3; + din_p5_r4 <= din_p5_r4; + din_p5_r5 <= din_p5_r5; + end +reg signed [15:0] din_p6_r1; +reg signed [15:0] din_p6_r2; +reg signed [15:0] din_p6_r3; +reg signed [15:0] din_p6_r4; +reg signed [15:0] din_p6_r5; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p6_r1 <= 'h0; + din_p6_r2 <= 'h0; + din_p6_r3 <= 'h0; + din_p6_r4 <= 'h0; + din_p6_r5 <= 'h0; + end + else if(en) + begin + din_p6_r1 <= din_p6; + din_p6_r2 <= din_p6_r1; + din_p6_r3 <= din_p6_r2; + din_p6_r4 <= din_p6_r3; + din_p6_r5 <= din_p6_r4; + end + else + begin + din_p6_r1 <= din_p6_r1; + din_p6_r2 <= din_p6_r2; + din_p6_r3 <= din_p6_r3; + din_p6_r4 <= din_p6_r4; + din_p6_r5 <= din_p6_r5; + end +reg signed [15:0] din_p7_r1; +reg signed [15:0] din_p7_r2; +reg signed [15:0] din_p7_r3; +reg signed [15:0] din_p7_r4; +reg signed [15:0] din_p7_r5; +reg signed [15:0] din_p7_r6; +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p7_r1 <= 'h0; + din_p7_r2 <= 'h0; + din_p7_r3 <= 'h0; + din_p7_r4 <= 'h0; + din_p7_r5 <= 'h0; + end + else if(en) + begin + din_p7_r1 <= din_p7; + din_p7_r2 <= din_p7_r1; + din_p7_r3 <= din_p7_r2; + din_p7_r4 <= din_p7_r3; + din_p7_r5 <= din_p7_r4; + end + else + begin + din_p7_r1 <= din_p7_r1; + din_p7_r2 <= din_p7_r2; + din_p7_r3 <= din_p7_r3; + din_p7_r4 <= din_p7_r4; + din_p7_r5 <= din_p7_r5; + end + +wire signed [15:0] IIRout0_p0; +wire signed [15:0] IIRout0_p1; +wire signed [15:0] IIRout0_p2; +wire signed [15:0] IIRout0_p3; +wire signed [15:0] IIRout0_p4; +wire signed [15:0] IIRout0_p5; +wire signed [15:0] IIRout0_p6; +wire signed [15:0] IIRout0_p7; +IIR_top_ref inst_IIR_top_ref_0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re0 ), + .a_im (a_im0 ), + .ab_re (ab_re0 ), + .ab_im (ab_im0 ), + .abb_re (abb_re0 ), + .abb_im (abb_im0 ), + .ab_pow3_re (ab_pow3_re0 ), + .ab_pow3_im (ab_pow3_im0 ), + .ab_pow4_re (ab_pow4_re0 ), + .ab_pow4_im (ab_pow4_im0 ), + .ab_pow5_re (ab_pow5_re0 ), + .ab_pow5_im (ab_pow5_im0 ), + .ab_pow6_re (ab_pow6_re0 ), + .ab_pow6_im (ab_pow6_im0 ), + .ab_pow7_re (ab_pow7_re0 ), + .ab_pow7_im (ab_pow7_im0 ), + .b_pow8_re (b_pow8_re0 ), + .b_pow8_im (b_pow8_im0 ), + .IIRout_p0 (IIRout0_p0 ), + .IIRout_p1 (IIRout0_p1 ), + .IIRout_p2 (IIRout0_p2 ), + .IIRout_p3 (IIRout0_p3 ), + .IIRout_p4 (IIRout0_p4 ), + .IIRout_p5 (IIRout0_p5 ), + .IIRout_p6 (IIRout0_p6 ), + .IIRout_p7 (IIRout0_p7 ) + ); +wire signed [15:0] IIRout1_p0; +wire signed [15:0] IIRout1_p1; +wire signed [15:0] IIRout1_p2; +wire signed [15:0] IIRout1_p3; +wire signed [15:0] IIRout1_p4; +wire signed [15:0] IIRout1_p5; +wire signed [15:0] IIRout1_p6; +wire signed [15:0] IIRout1_p7; +IIR_top_ref inst_IIR_top_ref_1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re1 ), + .a_im (a_im1 ), + .ab_re (ab_re1 ), + .ab_im (ab_im1 ), + .abb_re (abb_re1 ), + .abb_im (abb_im1 ), + .ab_pow3_re (ab_pow3_re1 ), + .ab_pow3_im (ab_pow3_im1 ), + .ab_pow4_re (ab_pow4_re1 ), + .ab_pow4_im (ab_pow4_im1 ), + .ab_pow5_re (ab_pow5_re1 ), + .ab_pow5_im (ab_pow5_im1 ), + .ab_pow6_re (ab_pow6_re1 ), + .ab_pow6_im (ab_pow6_im1 ), + .ab_pow7_re (ab_pow7_re1 ), + .ab_pow7_im (ab_pow7_im1 ), + .b_pow8_re (b_pow8_re1 ), + .b_pow8_im (b_pow8_im1 ), + .IIRout_p0 (IIRout1_p0 ), + .IIRout_p1 (IIRout1_p1 ), + .IIRout_p2 (IIRout1_p2 ), + .IIRout_p3 (IIRout1_p3 ), + .IIRout_p4 (IIRout1_p4 ), + .IIRout_p5 (IIRout1_p5 ), + .IIRout_p6 (IIRout1_p6 ), + .IIRout_p7 (IIRout1_p7 ) + ); +wire signed [15:0] IIRout2_p0; +wire signed [15:0] IIRout2_p1; +wire signed [15:0] IIRout2_p2; +wire signed [15:0] IIRout2_p3; +wire signed [15:0] IIRout2_p4; +wire signed [15:0] IIRout2_p5; +wire signed [15:0] IIRout2_p6; +wire signed [15:0] IIRout2_p7; +IIR_top_ref inst_IIR_top_ref_2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re2 ), + .a_im (a_im2 ), + .ab_re (ab_re2 ), + .ab_im (ab_im2 ), + .abb_re (abb_re2 ), + .abb_im (abb_im2 ), + .ab_pow3_re (ab_pow3_re2 ), + .ab_pow3_im (ab_pow3_im2 ), + .ab_pow4_re (ab_pow4_re2 ), + .ab_pow4_im (ab_pow4_im2 ), + .ab_pow5_re (ab_pow5_re2 ), + .ab_pow5_im (ab_pow5_im2 ), + .ab_pow6_re (ab_pow6_re2 ), + .ab_pow6_im (ab_pow6_im2 ), + .ab_pow7_re (ab_pow7_re2 ), + .ab_pow7_im (ab_pow7_im2 ), + .b_pow8_re (b_pow8_re2 ), + .b_pow8_im (b_pow8_im2 ), + .IIRout_p0 (IIRout2_p0 ), + .IIRout_p1 (IIRout2_p1 ), + .IIRout_p2 (IIRout2_p2 ), + .IIRout_p3 (IIRout2_p3 ), + .IIRout_p4 (IIRout2_p4 ), + .IIRout_p5 (IIRout2_p5 ), + .IIRout_p6 (IIRout2_p6 ), + .IIRout_p7 (IIRout2_p7 ) + ); +wire signed [15:0] IIRout3_p0; +wire signed [15:0] IIRout3_p1; +wire signed [15:0] IIRout3_p2; +wire signed [15:0] IIRout3_p3; +wire signed [15:0] IIRout3_p4; +wire signed [15:0] IIRout3_p5; +wire signed [15:0] IIRout3_p6; +wire signed [15:0] IIRout3_p7; +IIR_top_ref inst_IIR_top_ref_3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re3 ), + .a_im (a_im3 ), + .ab_re (ab_re3 ), + .ab_im (ab_im3 ), + .abb_re (abb_re3 ), + .abb_im (abb_im3 ), + .ab_pow3_re (ab_pow3_re3 ), + .ab_pow3_im (ab_pow3_im3 ), + .ab_pow4_re (ab_pow4_re3 ), + .ab_pow4_im (ab_pow4_im3 ), + .ab_pow5_re (ab_pow5_re3 ), + .ab_pow5_im (ab_pow5_im3 ), + .ab_pow6_re (ab_pow6_re3 ), + .ab_pow6_im (ab_pow6_im3 ), + .ab_pow7_re (ab_pow7_re3 ), + .ab_pow7_im (ab_pow7_im3 ), + .b_pow8_re (b_pow8_re3 ), + .b_pow8_im (b_pow8_im3 ), + .IIRout_p0 (IIRout3_p0 ), + .IIRout_p1 (IIRout3_p1 ), + .IIRout_p2 (IIRout3_p2 ), + .IIRout_p3 (IIRout3_p3 ), + .IIRout_p4 (IIRout3_p4 ), + .IIRout_p5 (IIRout3_p5 ), + .IIRout_p6 (IIRout3_p6 ), + .IIRout_p7 (IIRout3_p7 ) + ); +wire signed [15:0] IIRout4_p0; +wire signed [15:0] IIRout4_p1; +wire signed [15:0] IIRout4_p2; +wire signed [15:0] IIRout4_p3; +wire signed [15:0] IIRout4_p4; +wire signed [15:0] IIRout4_p5; +wire signed [15:0] IIRout4_p6; +wire signed [15:0] IIRout4_p7; +IIR_top_ref inst_IIR_top_ref_4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re4 ), + .a_im (a_im4 ), + .ab_re (ab_re4 ), + .ab_im (ab_im4 ), + .abb_re (abb_re4 ), + .abb_im (abb_im4 ), + .ab_pow3_re (ab_pow3_re4 ), + .ab_pow3_im (ab_pow3_im4 ), + .ab_pow4_re (ab_pow4_re4 ), + .ab_pow4_im (ab_pow4_im4 ), + .ab_pow5_re (ab_pow5_re4 ), + .ab_pow5_im (ab_pow5_im4 ), + .ab_pow6_re (ab_pow6_re4 ), + .ab_pow6_im (ab_pow6_im4 ), + .ab_pow7_re (ab_pow7_re4 ), + .ab_pow7_im (ab_pow7_im4 ), + .b_pow8_re (b_pow8_re4 ), + .b_pow8_im (b_pow8_im4 ), + .IIRout_p0 (IIRout4_p0 ), + .IIRout_p1 (IIRout4_p1 ), + .IIRout_p2 (IIRout4_p2 ), + .IIRout_p3 (IIRout4_p3 ), + .IIRout_p4 (IIRout4_p4 ), + .IIRout_p5 (IIRout4_p5 ), + .IIRout_p6 (IIRout4_p6 ), + .IIRout_p7 (IIRout4_p7 ) + ); +wire signed [15:0] IIRout5_p0; +wire signed [15:0] IIRout5_p1; +wire signed [15:0] IIRout5_p2; +wire signed [15:0] IIRout5_p3; +wire signed [15:0] IIRout5_p4; +wire signed [15:0] IIRout5_p5; +wire signed [15:0] IIRout5_p6; +wire signed [15:0] IIRout5_p7; +IIR_top_ref inst_IIR_top_ref_5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .a_re (a_re5 ), + .a_im (a_im5 ), + .ab_re (ab_re5 ), + .ab_im (ab_im5 ), + .abb_re (abb_re5 ), + .abb_im (abb_im5 ), + .ab_pow3_re (ab_pow3_re5 ), + .ab_pow3_im (ab_pow3_im5 ), + .ab_pow4_re (ab_pow4_re5 ), + .ab_pow4_im (ab_pow4_im5 ), + .ab_pow5_re (ab_pow5_re5 ), + .ab_pow5_im (ab_pow5_im5 ), + .ab_pow6_re (ab_pow6_re5 ), + .ab_pow6_im (ab_pow6_im5 ), + .ab_pow7_re (ab_pow7_re5 ), + .ab_pow7_im (ab_pow7_im5 ), + .b_pow8_re (b_pow8_re5 ), + .b_pow8_im (b_pow8_im5 ), + .IIRout_p0 (IIRout5_p0 ), + .IIRout_p1 (IIRout5_p1 ), + .IIRout_p2 (IIRout5_p2 ), + .IIRout_p3 (IIRout5_p3 ), + .IIRout_p4 (IIRout5_p4 ), + .IIRout_p5 (IIRout5_p5 ), + .IIRout_p6 (IIRout5_p6 ), + .IIRout_p7 (IIRout5_p7 ) + ); + + +wire signed [18:0] dout_p0_r0; +wire signed [18:0] dout_p1_r0; +wire signed [18:0] dout_p2_r0; +wire signed [18:0] dout_p3_r0; +wire signed [18:0] dout_p4_r0; +wire signed [18:0] dout_p5_r0; +wire signed [18:0] dout_p6_r0; +wire signed [18:0] dout_p7_r0; + +assign dout_p0_r0 = din_p0_r5 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0; +assign dout_p1_r0 = din_p1_r5 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1; +assign dout_p2_r0 = din_p2_r5 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2; +assign dout_p3_r0 = din_p3_r5 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3; +assign dout_p4_r0 = din_p4_r5 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4; +assign dout_p5_r0 = din_p5_r5 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5; +assign dout_p6_r0 = din_p6_r5 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6; +assign dout_p7_r0 = din_p7_r5 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7; + +reg signed [18:0] dout_p0_r1; + +reg signed [15:0] dout_p [7:0]; +wire signed [18:0] dout_p_r0 [0:7]; +assign dout_p_r0[0] = dout_p0_r0; +assign dout_p_r0[1] = dout_p1_r0; +assign dout_p_r0[2] = dout_p2_r0; +assign dout_p_r0[3] = dout_p3_r0; +assign dout_p_r0[4] = dout_p4_r0; +assign dout_p_r0[5] = dout_p5_r0; +assign dout_p_r0[6] = dout_p6_r0; +assign dout_p_r0[7] = dout_p7_r0; + +integer i; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 8; i = i + 1) begin + dout_p[i] <= 'h0; + end + end + else if (en) begin + for (i = 0; i < 8; i = i + 1) begin + if (dout_p_r0[i][16:15] == 2'b01) + dout_p[i] <= 16'd32767; + else if (dout_p_r0[i][16:15] == 2'b10) + dout_p[i] <= -16'd32768; + else + dout_p[i] <= dout_p_r0[i][15:0]; + end + end +end + +assign dout_p0 = dout_p[0]; +assign dout_p1 = dout_p[1]; +assign dout_p2 = dout_p[2]; +assign dout_p3 = dout_p[3]; +assign dout_p4 = dout_p[4]; +assign dout_p5 = dout_p[5]; +assign dout_p6 = dout_p[6]; +assign dout_p7 = dout_p[7]; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_p0_r1 <= 16'd0; + end + else if(en) + begin + dout_p0_r1 <= dout_p0_r0; + end + else + begin + dout_p0_r1 <= dout_p0_r1; + end + +reg signed [18:0] dout_p0_r2; +reg signed [18:0] dout_p0_r3; +reg signed [18:0] dout_p0_r4; +reg signed [18:0] dout_p0_r5; +reg signed [18:0] dout_p0_r6; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + dout_p0_r2 <= 16'd0; + dout_p0_r3 <= 16'd0; + dout_p0_r4 <= 16'd0; + dout_p0_r5 <= 16'd0; + dout_p0_r6 <= 16'd0; + end + else if(en) + begin + dout_p0_r2 <= dout_p0_r1; + dout_p0_r3 <= dout_p0_r2; + dout_p0_r4 <= dout_p0_r3; + dout_p0_r5 <= dout_p0_r4; + dout_p0_r6 <= dout_p0_r5; + end + else + begin + dout_p0_r2 <= dout_p0_r2; + dout_p0_r3 <= dout_p0_r3; + dout_p0_r4 <= dout_p0_r4; + dout_p0_r5 <= dout_p0_r5; + dout_p0_r6 <= dout_p0_r6; + end + +reg vldo_diff_r1; +reg vldo_diff_r2; +reg vldo_diff_r3; +reg vldo_diff_r4; +reg vldo_diff_r5; +reg vldo_diff_r6; +reg vldo_diff_r7; +reg vldo_diff_r8; + +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + vldo_diff_r1 <= 16'd0; + vldo_diff_r2 <= 16'd0; + vldo_diff_r3 <= 16'd0; + vldo_diff_r4 <= 16'd0; + vldo_diff_r5 <= 16'd0; + vldo_diff_r6 <= 16'd0; + vldo_diff_r7 <= 16'd0; + vldo_diff_r8 <= 16'd0; + end + else if(en) begin + vldo_diff_r1 <= vldo_diff; + vldo_diff_r2 <= vldo_diff_r1; + vldo_diff_r3 <= vldo_diff_r2; + vldo_diff_r4 <= vldo_diff_r3; + vldo_diff_r5 <= vldo_diff_r4; + vldo_diff_r6 <= vldo_diff_r5; + vldo_diff_r7 <= vldo_diff_r6; + vldo_diff_r8 <= vldo_diff_r7; + end + else begin + vldo_diff_r1 <= vldo_diff_r1; + vldo_diff_r2 <= vldo_diff_r2; + vldo_diff_r3 <= vldo_diff_r3; + vldo_diff_r4 <= vldo_diff_r4; + vldo_diff_r5 <= vldo_diff_r5; + vldo_diff_r6 <= vldo_diff_r6; + vldo_diff_r7 <= vldo_diff_r7; + vldo_diff_r8 <= vldo_diff_r8; + end +end +wire vldo_r0_h; +wire vldo_r0_l; +reg vldo_r0; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + vldo_r0 <= 0; + end + else if(vldo_r0_h)begin + vldo_r0 <= 1; + end + else if(vldo_r0_l)begin + vldo_r0 <= 0; + end +end +assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); +assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ; +assign vldo = vldo_r0; +endmodule + diff --git a/rtl/ref/diff_p.v b/rtl/ref/diff_p.v new file mode 100644 index 0000000..f54a4be --- /dev/null +++ b/rtl/ref/diff_p.v @@ -0,0 +1,236 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : TailCorr_top.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.3 2024-05-15 thfu +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- + +module diff_p_ref + +( + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,output vldo +,output signed [15:0] dout_p0 +,output signed [15:0] dout_p1 +,output signed [15:0] dout_p2 +,output signed [15:0] dout_p3 +,output signed [15:0] dout_p4 +,output signed [15:0] dout_p5 +,output signed [15:0] dout_p6 +,output signed [15:0] dout_p7 +,output signed [15:0] diff_p0 +,output signed [15:0] diff_p1 +,output signed [15:0] diff_p2 +,output signed [15:0] diff_p3 +,output signed [15:0] diff_p4 +,output signed [15:0] diff_p5 +,output signed [15:0] diff_p6 +,output signed [15:0] diff_p7 + + ); + +wire signed [15:0] din_p0_r0; +wire signed [15:0] din_p1_r0; +wire signed [15:0] din_p2_r0; +wire signed [15:0] din_p3_r0; +wire signed [15:0] din_p4_r0; +wire signed [15:0] din_p5_r0; +wire signed [15:0] din_p6_r0; +wire signed [15:0] din_p7_r0; + +s2p_2_ref inst1_s2p_2_ref ( + .clk (clk), + .rst_n (rstn), + .din (din0), + .en (vldi), + .dout0 (din_p0_r0), + .dout1 (din_p4_r0) + ,.vldo( vldo) + ); +s2p_2_ref inst2_s2p_2_ref ( + .clk (clk), + .rst_n (rstn), + .din (din1), + .en (vldi), + .dout0 (din_p1_r0), + .dout1 (din_p5_r0) + ,.vldo( ) + ); +s2p_2_ref inst3_s2p_2_ref ( + .clk (clk), + .rst_n (rstn), + .din (din2), + .en (vldi), + .dout0 (din_p2_r0), + .dout1 (din_p6_r0) + ,.vldo( ) + ); +s2p_2_ref inst4_s2p_2_ref ( + .clk (clk), + .rst_n (rstn), + .din (din3), + .en (vldi), + .dout0 (din_p3_r0), + .dout1 (din_p7_r0) + ,.vldo( ) + ); + + +reg signed [15:0] din_p0_r1; +reg signed [15:0] din_p1_r1; +reg signed [15:0] din_p2_r1; +reg signed [15:0] din_p3_r1; +reg signed [15:0] din_p4_r1; +reg signed [15:0] din_p5_r1; +reg signed [15:0] din_p6_r1; +reg signed [15:0] din_p7_r1; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + din_p0_r1 <= 'h0; + din_p1_r1 <= 'h0; + din_p2_r1 <= 'h0; + din_p3_r1 <= 'h0; + din_p4_r1 <= 'h0; + din_p5_r1 <= 'h0; + din_p6_r1 <= 'h0; + din_p7_r1 <= 'h0; + end + else if(en) + begin + din_p0_r1 <= din_p0_r0; + din_p1_r1 <= din_p1_r0; + din_p2_r1 <= din_p2_r0; + din_p3_r1 <= din_p3_r0; + din_p4_r1 <= din_p4_r0; + din_p5_r1 <= din_p5_r0; + din_p6_r1 <= din_p6_r0; + din_p7_r1 <= din_p7_r0; + end + else + begin + din_p0_r1 <= din_p0_r1; + din_p1_r1 <= din_p1_r1; + din_p2_r1 <= din_p2_r1; + din_p3_r1 <= din_p3_r1; + din_p4_r1 <= din_p4_r1; + din_p5_r1 <= din_p5_r1; + din_p6_r1 <= din_p6_r1; + din_p7_r1 <= din_p7_r1; + end + +assign dout_p0 = din_p0_r1; +assign dout_p1 = din_p1_r1; +assign dout_p2 = din_p2_r1; +assign dout_p3 = din_p3_r1; +assign dout_p4 = din_p4_r1; +assign dout_p5 = din_p5_r1; +assign dout_p6 = din_p6_r1; +assign dout_p7 = din_p7_r1; + +wire signed [15:0] diff_p0_r0; +wire signed [15:0] diff_p1_r0; +wire signed [15:0] diff_p2_r0; +wire signed [15:0] diff_p3_r0; +wire signed [15:0] diff_p4_r0; +wire signed [15:0] diff_p5_r0; +wire signed [15:0] diff_p6_r0; +wire signed [15:0] diff_p7_r0; + +assign diff_p0_r0 = din_p0_r0 - din_p7_r1; +assign diff_p1_r0 = din_p1_r0 - din_p0_r0; +assign diff_p2_r0 = din_p2_r0 - din_p1_r0; +assign diff_p3_r0 = din_p3_r0 - din_p2_r0; +assign diff_p4_r0 = din_p4_r0 - din_p3_r0; +assign diff_p5_r0 = din_p5_r0 - din_p4_r0; +assign diff_p6_r0 = din_p6_r0 - din_p5_r0; +assign diff_p7_r0 = din_p7_r0 - din_p6_r0; + +reg signed [15:0] diff_p0_r1; +reg signed [15:0] diff_p1_r1; +reg signed [15:0] diff_p2_r1; +reg signed [15:0] diff_p3_r1; +reg signed [15:0] diff_p4_r1; +reg signed [15:0] diff_p5_r1; +reg signed [15:0] diff_p6_r1; +reg signed [15:0] diff_p7_r1; + +always @(posedge clk or negedge rstn)begin +if(rstn==1'b0)begin + diff_p0_r1 <= 0; + diff_p1_r1 <= 0; + diff_p2_r1 <= 0; + diff_p3_r1 <= 0; + diff_p4_r1 <= 0; + diff_p5_r1 <= 0; + diff_p6_r1 <= 0; + diff_p7_r1 <= 0; + +end +else if(en)begin + diff_p0_r1 <= diff_p0_r0; + diff_p1_r1 <= diff_p1_r0; + diff_p2_r1 <= diff_p2_r0; + diff_p3_r1 <= diff_p3_r0; + diff_p4_r1 <= diff_p4_r0; + diff_p5_r1 <= diff_p5_r0; + diff_p6_r1 <= diff_p6_r0; + diff_p7_r1 <= diff_p7_r0; +end +else begin + diff_p0_r1 <= diff_p0_r1; + diff_p1_r1 <= diff_p1_r1; + diff_p2_r1 <= diff_p2_r1; + diff_p3_r1 <= diff_p3_r1; + diff_p4_r1 <= diff_p4_r1; + diff_p5_r1 <= diff_p5_r1; + diff_p6_r1 <= diff_p6_r1; + diff_p7_r1 <= diff_p7_r1; +end +end + +assign diff_p0 = diff_p0_r1; +assign diff_p1 = diff_p1_r1; +assign diff_p2 = diff_p2_r1; +assign diff_p3 = diff_p3_r1; +assign diff_p4 = diff_p4_r1; +assign diff_p5 = diff_p5_r1; +assign diff_p6 = diff_p6_r1; +assign diff_p7 = diff_p7_r1; + +endmodule + diff --git a/rtl/ref/mult_C.v b/rtl/ref/mult_C.v new file mode 100644 index 0000000..0e66ae4 --- /dev/null +++ b/rtl/ref/mult_C.v @@ -0,0 +1,110 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : mult_C.v +// Department : +// Author : thfu +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.1 2024-05-28 thfu +//2024-05-28 10:22:18 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module mult_C_ref #( + parameter integer A_width = 8 +,parameter integer B_width = 8 +,parameter integer C_width = 8 +,parameter integer D_width = 8 +,parameter integer frac_coef_width = 31//division + +) + +( + clk, + rstn, + en, + a, + b, + c, + d, + Re, + Im +); + +input rstn; +input clk; +input en; +input signed [A_width-1:0] a; +input signed [B_width-1:0] b; +input signed [C_width-1:0] c; +input signed [D_width-1:0] d; + +output signed [A_width+C_width-frac_coef_width-1:0] Re; +output signed [A_width+D_width-frac_coef_width-1:0] Im; + +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; + + + +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); + +DW02_mult #(B_width,D_width) inst_c2( .A (b ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (bd ) + ); + +DW02_mult #(A_width,D_width) inst_c3( .A (a ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (ad ) + ); +DW02_mult #(B_width,C_width) inst_c4( .A (b ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (bc ) + ); +wire signed [A_width+C_width:0] Re_tmp; +wire signed [A_width+D_width:0] Im_tmp; + +assign Re_tmp = ac - bd; +assign Im_tmp = ad + bc; + +wire signed [A_width+C_width:0] Re_round; +wire signed [A_width+D_width:0] Im_round; + +FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); +FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); + +assign Re = Re_round[A_width+D_width-1:frac_coef_width]; +assign Im = Im_round[A_width+D_width-1:frac_coef_width]; + +endmodule diff --git a/rtl/ref/s2p_2.v b/rtl/ref/s2p_2.v new file mode 100644 index 0000000..e8c1364 --- /dev/null +++ b/rtl/ref/s2p_2.v @@ -0,0 +1,121 @@ +module s2p_2_ref ( + input clk, + input rst_n, + input [15:0] din, + input en, + output [15:0] dout0, + output [15:0] dout1, + output vldo +); + +reg en_r1; +reg en_r2; +reg en_r3; + +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + en_r1 <= 0; + en_r2 <= 0; + en_r3 <= 0; + end + else begin + en_r1 <= en; + en_r2 <= en_r1; + end +end +assign vldo = en_r2; + +reg cnt; +wire add_cnt; +wire end_cnt; + +always @(posedge clk or negedge rst_n)begin + if(!rst_n)begin + cnt <= 0; + end + else if(add_cnt)begin + if(end_cnt) + cnt <= 0; + else + cnt <= cnt + 1; + end + else begin + cnt <= 0; + end +end + +assign add_cnt = en == 1'b1; +assign end_cnt = add_cnt && cnt== 2 - 1 ; + + +reg [ 15: 0] dout0_r0; +reg [ 15: 0] dout1_r0; +wire dout0_en; +wire dout1_en; +wire dout0_hold; +wire dout1_hold; + +always @(*)begin + if(rst_n==1'b0)begin + dout0_r0 = 16'd0; + dout1_r0 = 16'd0; + end + else if(dout0_en)begin + dout0_r0 = din; + end + else if(dout1_en)begin + dout1_r0 = din; + end + else begin + dout0_r0 = 16'd0; + dout1_r0 = 16'd0; + + end +end +assign dout0_en = add_cnt && cnt == 0; +assign dout1_en = add_cnt && cnt == 1; + +reg [ 15: 0] dout0_r1; +reg [ 15: 0] dout1_r1; +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + dout0_r1 <= 16'd0; + dout1_r1 <= 16'd0; + end + else if(en)begin + dout0_r1 <= dout0_r0; + dout1_r1 <= dout1_r0; + end + else if(dout0_hold)begin + dout0_r1 <= dout0_r1; + dout1_r1 <= 16'd0; + end + else if(dout1_hold)begin + dout0_r1 <= 16'd0; + dout1_r1 <= dout1_r1; + end + else begin + dout0_r1 <= 16'd0; + dout1_r1 <= 16'd0; + end + +end +assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1; +assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0; + +reg [ 15: 0] dout0_r2; +always @(posedge clk or negedge rst_n)begin + if(rst_n==1'b0)begin + dout0_r2 <= 16'd0; + end + else begin + dout0_r2 <= dout0_r1; + end +end + +assign dout0 = dout0_r2; +assign dout1 = dout1_r1; + + +endmodule + diff --git a/rtl/z_dsp/CoefGen.sv b/rtl/z_dsp/CoefGen.sv deleted file mode 100644 index edf68a6..0000000 --- a/rtl/z_dsp/CoefGen.sv +++ /dev/null @@ -1,693 +0,0 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : IIR_Filter.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.4 2024-05-28 thfu -//2024-05-28 10:22:49 -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- -module CoefGen #( - parameter data_in_width = 32 -,parameter coef_width = 32 -,parameter frac_data_out_width = 20//X for in,5 -,parameter frac_coef_width = 31//division -) -( - input rstn -,input clk -,input [5:0] vldi -,input signed [31:0] a0_re -,input signed [31:0] a0_im -,input signed [31:0] b0_re -,input signed [31:0] b0_im -,input signed [31:0] a1_re -,input signed [31:0] a1_im -,input signed [31:0] b1_re -,input signed [31:0] b1_im -,input signed [31:0] a2_re -,input signed [31:0] a2_im -,input signed [31:0] b2_re -,input signed [31:0] b2_im -,input signed [31:0] a3_re -,input signed [31:0] a3_im -,input signed [31:0] b3_re -,input signed [31:0] b3_im -,input signed [31:0] a4_re -,input signed [31:0] a4_im -,input signed [31:0] b4_re -,input signed [31:0] b4_im -,input signed [31:0] a5_re -,input signed [31:0] a5_im -,input signed [31:0] b5_re -,input signed [31:0] b5_im -,output reg signed [31:0] a_re0 -,output reg signed [31:0] a_im0 -,output reg signed [31:0] ab_re0 -,output reg signed [31:0] ab_im0 -,output reg signed [31:0] abb_re0 -,output reg signed [31:0] abb_im0 -,output reg signed [31:0] ab_pow3_re0 -,output reg signed [31:0] ab_pow3_im0 -,output reg signed [31:0] ab_pow4_re0 -,output reg signed [31:0] ab_pow4_im0 -,output reg signed [31:0] ab_pow5_re0 -,output reg signed [31:0] ab_pow5_im0 -,output reg signed [31:0] ab_pow6_re0 -,output reg signed [31:0] ab_pow6_im0 -,output reg signed [31:0] ab_pow7_re0 -,output reg signed [31:0] ab_pow7_im0 -,output reg signed [31:0] b_pow8_re0 -,output reg signed [31:0] b_pow8_im0 -,output reg signed [31:0] a_re1 -,output reg signed [31:0] a_im1 -,output reg signed [31:0] ab_re1 -,output reg signed [31:0] ab_im1 -,output reg signed [31:0] abb_re1 -,output reg signed [31:0] abb_im1 -,output reg signed [31:0] ab_pow3_re1 -,output reg signed [31:0] ab_pow3_im1 -,output reg signed [31:0] ab_pow4_re1 -,output reg signed [31:0] ab_pow4_im1 -,output reg signed [31:0] ab_pow5_re1 -,output reg signed [31:0] ab_pow5_im1 -,output reg signed [31:0] ab_pow6_re1 -,output reg signed [31:0] ab_pow6_im1 -,output reg signed [31:0] ab_pow7_re1 -,output reg signed [31:0] ab_pow7_im1 -,output reg signed [31:0] b_pow8_re1 -,output reg signed [31:0] b_pow8_im1 -,output reg signed [31:0] a_re2 -,output reg signed [31:0] a_im2 -,output reg signed [31:0] ab_re2 -,output reg signed [31:0] ab_im2 -,output reg signed [31:0] abb_re2 -,output reg signed [31:0] abb_im2 -,output reg signed [31:0] ab_pow3_re2 -,output reg signed [31:0] ab_pow3_im2 -,output reg signed [31:0] ab_pow4_re2 -,output reg signed [31:0] ab_pow4_im2 -,output reg signed [31:0] ab_pow5_re2 -,output reg signed [31:0] ab_pow5_im2 -,output reg signed [31:0] ab_pow6_re2 -,output reg signed [31:0] ab_pow6_im2 -,output reg signed [31:0] ab_pow7_re2 -,output reg signed [31:0] ab_pow7_im2 -,output reg signed [31:0] b_pow8_re2 -,output reg signed [31:0] b_pow8_im2 -,output reg signed [31:0] a_re3 -,output reg signed [31:0] a_im3 -,output reg signed [31:0] ab_re3 -,output reg signed [31:0] ab_im3 -,output reg signed [31:0] abb_re3 -,output reg signed [31:0] abb_im3 -,output reg signed [31:0] ab_pow3_re3 -,output reg signed [31:0] ab_pow3_im3 -,output reg signed [31:0] ab_pow4_re3 -,output reg signed [31:0] ab_pow4_im3 -,output reg signed [31:0] ab_pow5_re3 -,output reg signed [31:0] ab_pow5_im3 -,output reg signed [31:0] ab_pow6_re3 -,output reg signed [31:0] ab_pow6_im3 -,output reg signed [31:0] ab_pow7_re3 -,output reg signed [31:0] ab_pow7_im3 -,output reg signed [31:0] b_pow8_re3 -,output reg signed [31:0] b_pow8_im3 -,output reg signed [31:0] a_re4 -,output reg signed [31:0] a_im4 -,output reg signed [31:0] ab_re4 -,output reg signed [31:0] ab_im4 -,output reg signed [31:0] abb_re4 -,output reg signed [31:0] abb_im4 -,output reg signed [31:0] ab_pow3_re4 -,output reg signed [31:0] ab_pow3_im4 -,output reg signed [31:0] ab_pow4_re4 -,output reg signed [31:0] ab_pow4_im4 -,output reg signed [31:0] ab_pow5_re4 -,output reg signed [31:0] ab_pow5_im4 -,output reg signed [31:0] ab_pow6_re4 -,output reg signed [31:0] ab_pow6_im4 -,output reg signed [31:0] ab_pow7_re4 -,output reg signed [31:0] ab_pow7_im4 -,output reg signed [31:0] b_pow8_re4 -,output reg signed [31:0] b_pow8_im4 -,output reg signed [31:0] a_re5 -,output reg signed [31:0] a_im5 -,output reg signed [31:0] ab_re5 -,output reg signed [31:0] ab_im5 -,output reg signed [31:0] abb_re5 -,output reg signed [31:0] abb_im5 -,output reg signed [31:0] ab_pow3_re5 -,output reg signed [31:0] ab_pow3_im5 -,output reg signed [31:0] ab_pow4_re5 -,output reg signed [31:0] ab_pow4_im5 -,output reg signed [31:0] ab_pow5_re5 -,output reg signed [31:0] ab_pow5_im5 -,output reg signed [31:0] ab_pow6_re5 -,output reg signed [31:0] ab_pow6_im5 -,output reg signed [31:0] ab_pow7_re5 -,output reg signed [31:0] ab_pow7_im5 -,output reg signed [31:0] b_pow8_re5 -,output reg signed [31:0] b_pow8_im5 -); - - -reg vldi_or_r1; -wire vldi_or = | vldi; -always @(posedge clk or negedge rstn)begin - if(rstn==1'b0)begin - vldi_or_r1 <= 'h0; - end - else begin - vldi_or_r1 <= vldi_or; - end -end - -reg signed [data_in_width-1:0] a_re_r1; -reg signed [data_in_width-1:0] a_im_r1; -reg signed [data_in_width-1:0] b_re_r1; -reg signed [data_in_width-1:0] b_im_r1; - -always @(posedge clk or negedge rstn) begin - if(rstn == 1'b0) begin - a_re_r1 <= 'h0; - a_im_r1 <= 'h0; - b_re_r1 <= 'h0; - b_im_r1 <= 'h0; - end - else if(|vldi) begin - case(1'b1) - vldi[0]: begin - a_re_r1 <= a0_re; - a_im_r1 <= a0_im; - b_re_r1 <= b0_re; - b_im_r1 <= b0_im; - end - vldi[1]: begin - a_re_r1 <= a1_re; - a_im_r1 <= a1_im; - b_re_r1 <= b1_re; - b_im_r1 <= b1_im; - end - vldi[2]: begin - a_re_r1 <= a2_re; - a_im_r1 <= a2_im; - b_re_r1 <= b2_re; - b_im_r1 <= b2_im; - end - vldi[3]: begin - a_re_r1 <= a3_re; - a_im_r1 <= a3_im; - b_re_r1 <= b3_re; - b_im_r1 <= b3_im; - end - vldi[4]: begin - a_re_r1 <= a4_re; - a_im_r1 <= a4_im; - b_re_r1 <= b4_re; - b_im_r1 <= b4_im; - end - vldi[5]: begin - a_re_r1 <= a5_re; - a_im_r1 <= a5_im; - b_re_r1 <= b5_re; - b_im_r1 <= b5_im; - end -// default: begin -// a_re_r1 <= a_re[0]; -// a_im_r1 <= a_im[0]; -// b_re_r1 <= b_re[0]; -// b_im_r1 <= b_im[0]; -// end - endcase - end -end - -reg en; -reg en_r1; -reg [3:0] cnt0; -wire add_cnt0; -wire end_cnt0; -always @(posedge clk or negedge rstn)begin - if(!rstn)begin - cnt0 <= 0; - end - else if(add_cnt0)begin - if(end_cnt0) - cnt0 <= 0; - else - cnt0 <= cnt0 + 1; - end -end - -assign add_cnt0 = en; -assign end_cnt0 = add_cnt0 && cnt0== 8-1; - -wire en_l; -wire en_h; -always @(posedge clk or negedge rstn)begin - if(rstn==1'b0)begin - en <= 0; - end - else if(en_h)begin - en <= 1; - end - else if(en_l)begin - en <= 0; - end -end - -assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0; -assign en_l = end_cnt0; - -always @(posedge clk or negedge rstn)begin - if(rstn==1'b0)begin - en_r1 <= 'h0; - end - else begin - en_r1 <= en; - end -end - -reg signed [data_in_width-1:0] bin_re; -reg signed [data_in_width-1:0] bin_im; -wire signed [data_in_width-1:0] bout_re; -wire signed [data_in_width-1:0] bout_im; -always @(*)begin - if(en_r1) begin - bin_re <= bout_re; - bin_im <= bout_im; - end - else begin - bin_re <= 32'd2147483647; - bin_im <= 0; - end -end - -mult_C -#( - .A_width(data_in_width) -,.B_width(data_in_width) -,.C_width(coef_width) -,.D_width(coef_width) -,.frac_coef_width(frac_coef_width) -) -inst_c1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (bin_re ), - .b (bin_im ), - .c (b_re_r1 ), - .d (b_im_r1 ), - .Re (bout_re ), - .Im (bout_im ) - ); - - -wire signed [data_in_width-1:0] abo_re; -wire signed [data_in_width-1:0] abo_im; -mult_C -#( - .A_width(data_in_width) -,.B_width(data_in_width) -,.C_width(coef_width) -,.D_width(coef_width) -,.frac_coef_width(frac_coef_width) -) -inst_c2 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (bin_re ), - .b (bin_im ), - .c (a_re_r1 ), - .d (a_im_r1 ), - .Re (abo_re ), - .Im (abo_im ) - ); - -reg signed [coef_width-1 :0] ao_re_r1 ; -reg signed [coef_width-1 :0] ao_im_r1 ; -reg signed [coef_width-1 :0] ab_re_r1 ; -reg signed [coef_width-1 :0] ab_im_r1 ; -reg signed [coef_width-1 :0] abb_re_r1 ; -reg signed [coef_width-1 :0] abb_im_r1 ; -reg signed [coef_width-1 :0] ab_pow3_re_r1 ; -reg signed [coef_width-1 :0] ab_pow3_im_r1 ; -reg signed [coef_width-1 :0] ab_pow4_re_r1 ; -reg signed [coef_width-1 :0] ab_pow4_im_r1 ; -reg signed [coef_width-1 :0] ab_pow5_re_r1 ; -reg signed [coef_width-1 :0] ab_pow5_im_r1 ; -reg signed [coef_width-1 :0] ab_pow6_re_r1 ; -reg signed [coef_width-1 :0] ab_pow6_im_r1 ; -reg signed [coef_width-1 :0] ab_pow7_re_r1 ; -reg signed [coef_width-1 :0] ab_pow7_im_r1 ; -reg signed [coef_width-1 :0] b_pow8_re_r1 ; -reg signed [coef_width-1 :0] b_pow8_im_r1 ; - -always @(posedge clk or negedge rstn)begin - if(rstn==1'b0)begin - ao_re_r1 <= 0; - ao_im_r1 <= 0; - ab_re_r1 <= 0; - ab_im_r1 <= 0; - abb_re_r1 <= 0; - abb_im_r1 <= 0; - ab_pow3_re_r1 <= 0; - ab_pow3_im_r1 <= 0; - ab_pow4_re_r1 <= 0; - ab_pow4_im_r1 <= 0; - ab_pow5_re_r1 <= 0; - ab_pow5_im_r1 <= 0; - ab_pow6_re_r1 <= 0; - ab_pow6_im_r1 <= 0; - ab_pow7_re_r1 <= 0; - ab_pow7_im_r1 <= 0; - b_pow8_re_r1 <= 0; - b_pow8_im_r1 <= 0; - end - else if(add_cnt0 && cnt0 == 1 && en_r1)begin - ao_re_r1 <= abo_re; - ao_im_r1 <= abo_im; - end - else if(add_cnt0 && cnt0 == 2 && en_r1)begin - ab_re_r1 <= abo_re; - ab_im_r1 <= abo_im; - end - else if(add_cnt0 && cnt0 == 3 && en_r1)begin - abb_re_r1 <= abo_re; - abb_im_r1 <= abo_im; - end - else if(add_cnt0 && cnt0 == 4 && en_r1)begin - ab_pow3_re_r1 <= abo_re; - ab_pow3_im_r1 <= abo_im; - end - else if(add_cnt0 && cnt0 == 5 && en_r1)begin - ab_pow4_re_r1 <= abo_re; - ab_pow4_im_r1 <= abo_im; - end - else if(add_cnt0 && cnt0 == 6 && en_r1)begin - ab_pow5_re_r1 <= abo_re; - ab_pow5_im_r1 <= abo_im; - end - else if(add_cnt0 && cnt0 == 7 && en_r1)begin - ab_pow6_re_r1 <= abo_re; - ab_pow6_im_r1 <= abo_im; - end - else if(cnt0 == 0 && en_r1)begin - ab_pow7_re_r1 <= abo_re; - ab_pow7_im_r1 <= abo_im; - b_pow8_re_r1 <= bin_re; - b_pow8_im_r1 <= bin_im; - end -// else begin -// end -end - -reg [5:0] vldi_r10; -syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10); - -always @(posedge clk or negedge rstn) begin - if(rstn == 1'b0) begin - a_re0 <= 0; - a_im0 <= 0; - ab_re0 <= 0; - ab_im0 <= 0; - abb_re0 <= 0; - abb_im0 <= 0; - ab_pow3_re0 <= 0; - ab_pow3_im0 <= 0; - ab_pow4_re0 <= 0; - ab_pow4_im0 <= 0; - ab_pow5_re0 <= 0; - ab_pow5_im0 <= 0; - ab_pow6_re0 <= 0; - ab_pow6_im0 <= 0; - ab_pow7_re0 <= 0; - ab_pow7_im0 <= 0; - b_pow8_re0 <= 0; - b_pow8_im0 <= 0; - a_re1 <= 0; - a_im1 <= 0; - ab_re1 <= 0; - ab_im1 <= 0; - abb_re1 <= 0; - abb_im1 <= 0; - ab_pow3_re1 <= 0; - ab_pow3_im1 <= 0; - ab_pow4_re1 <= 0; - ab_pow4_im1 <= 0; - ab_pow5_re1 <= 0; - ab_pow5_im1 <= 0; - ab_pow6_re1 <= 0; - ab_pow6_im1 <= 0; - ab_pow7_re1 <= 0; - ab_pow7_im1 <= 0; - b_pow8_re1 <= 0; - b_pow8_im1 <= 0; - a_re2 <= 0; - a_im2 <= 0; - ab_re2 <= 0; - ab_im2 <= 0; - abb_re2 <= 0; - abb_im2 <= 0; - ab_pow3_re2 <= 0; - ab_pow3_im2 <= 0; - ab_pow4_re2 <= 0; - ab_pow4_im2 <= 0; - ab_pow5_re2 <= 0; - ab_pow5_im2 <= 0; - ab_pow6_re2 <= 0; - ab_pow6_im2 <= 0; - ab_pow7_re2 <= 0; - ab_pow7_im2 <= 0; - b_pow8_re2 <= 0; - b_pow8_im2 <= 0; - a_re3 <= 0; - a_im3 <= 0; - ab_re3 <= 0; - ab_im3 <= 0; - abb_re3 <= 0; - abb_im3 <= 0; - ab_pow3_re3 <= 0; - ab_pow3_im3 <= 0; - ab_pow4_re3 <= 0; - ab_pow4_im3 <= 0; - ab_pow5_re3 <= 0; - ab_pow5_im3 <= 0; - ab_pow6_re3 <= 0; - ab_pow6_im3 <= 0; - ab_pow7_re3 <= 0; - ab_pow7_im3 <= 0; - b_pow8_re3 <= 0; - b_pow8_im3 <= 0; - a_re4 <= 0; - a_im4 <= 0; - ab_re4 <= 0; - ab_im4 <= 0; - abb_re4 <= 0; - abb_im4 <= 0; - ab_pow3_re4 <= 0; - ab_pow3_im4 <= 0; - ab_pow4_re4 <= 0; - ab_pow4_im4 <= 0; - ab_pow5_re4 <= 0; - ab_pow5_im4 <= 0; - ab_pow6_re4 <= 0; - ab_pow6_im4 <= 0; - ab_pow7_re4 <= 0; - ab_pow7_im4 <= 0; - b_pow8_re4 <= 0; - b_pow8_im4 <= 0; - a_re5 <= 0; - a_im5 <= 0; - ab_re5 <= 0; - ab_im5 <= 0; - abb_re5 <= 0; - abb_im5 <= 0; - ab_pow3_re5 <= 0; - ab_pow3_im5 <= 0; - ab_pow4_re5 <= 0; - ab_pow4_im5 <= 0; - ab_pow5_re5 <= 0; - ab_pow5_im5 <= 0; - ab_pow6_re5 <= 0; - ab_pow6_im5 <= 0; - ab_pow7_re5 <= 0; - ab_pow7_im5 <= 0; - b_pow8_re5 <= 0; - b_pow8_im5 <= 0; - end - else if(|vldi_r10) begin - case(1'b1) - vldi_r10[0]: begin - a_re0 <= ao_re_r1 ; - a_im0 <= ao_im_r1 ; - ab_re0 <= ab_re_r1 ; - ab_im0 <= ab_im_r1 ; - abb_re0 <= abb_re_r1 ; - abb_im0 <= abb_im_r1 ; - ab_pow3_re0 <= ab_pow3_re_r1; - ab_pow3_im0 <= ab_pow3_im_r1; - ab_pow4_re0 <= ab_pow4_re_r1; - ab_pow4_im0 <= ab_pow4_im_r1; - ab_pow5_re0 <= ab_pow5_re_r1; - ab_pow5_im0 <= ab_pow5_im_r1; - ab_pow6_re0 <= ab_pow6_re_r1; - ab_pow6_im0 <= ab_pow6_im_r1; - ab_pow7_re0 <= ab_pow7_re_r1; - ab_pow7_im0 <= ab_pow7_im_r1; - b_pow8_re0 <= b_pow8_re_r1 ; - b_pow8_im0 <= b_pow8_im_r1 ; - end - vldi_r10[1]: begin - a_re1 <= ao_re_r1 ; - a_im1 <= ao_im_r1 ; - ab_re1 <= ab_re_r1 ; - ab_im1 <= ab_im_r1 ; - abb_re1 <= abb_re_r1 ; - abb_im1 <= abb_im_r1 ; - ab_pow3_re1 <= ab_pow3_re_r1; - ab_pow3_im1 <= ab_pow3_im_r1; - ab_pow4_re1 <= ab_pow4_re_r1; - ab_pow4_im1 <= ab_pow4_im_r1; - ab_pow5_re1 <= ab_pow5_re_r1; - ab_pow5_im1 <= ab_pow5_im_r1; - ab_pow6_re1 <= ab_pow6_re_r1; - ab_pow6_im1 <= ab_pow6_im_r1; - ab_pow7_re1 <= ab_pow7_re_r1; - ab_pow7_im1 <= ab_pow7_im_r1; - b_pow8_re1 <= b_pow8_re_r1 ; - b_pow8_im1 <= b_pow8_im_r1 ; - end - vldi_r10[2]: begin - a_re2 <= ao_re_r1 ; - a_im2 <= ao_im_r1 ; - ab_re2 <= ab_re_r1 ; - ab_im2 <= ab_im_r1 ; - abb_re2 <= abb_re_r1 ; - abb_im2 <= abb_im_r1 ; - ab_pow3_re2 <= ab_pow3_re_r1; - ab_pow3_im2 <= ab_pow3_im_r1; - ab_pow4_re2 <= ab_pow4_re_r1; - ab_pow4_im2 <= ab_pow4_im_r1; - ab_pow5_re2 <= ab_pow5_re_r1; - ab_pow5_im2 <= ab_pow5_im_r1; - ab_pow6_re2 <= ab_pow6_re_r1; - ab_pow6_im2 <= ab_pow6_im_r1; - ab_pow7_re2 <= ab_pow7_re_r1; - ab_pow7_im2 <= ab_pow7_im_r1; - b_pow8_re2 <= b_pow8_re_r1 ; - b_pow8_im2 <= b_pow8_im_r1 ; - end - vldi_r10[3]: begin - a_re3 <= ao_re_r1 ; - a_im3 <= ao_im_r1 ; - ab_re3 <= ab_re_r1 ; - ab_im3 <= ab_im_r1 ; - abb_re3 <= abb_re_r1 ; - abb_im3 <= abb_im_r1 ; - ab_pow3_re3 <= ab_pow3_re_r1; - ab_pow3_im3 <= ab_pow3_im_r1; - ab_pow4_re3 <= ab_pow4_re_r1; - ab_pow4_im3 <= ab_pow4_im_r1; - ab_pow5_re3 <= ab_pow5_re_r1; - ab_pow5_im3 <= ab_pow5_im_r1; - ab_pow6_re3 <= ab_pow6_re_r1; - ab_pow6_im3 <= ab_pow6_im_r1; - ab_pow7_re3 <= ab_pow7_re_r1; - ab_pow7_im3 <= ab_pow7_im_r1; - b_pow8_re3 <= b_pow8_re_r1 ; - b_pow8_im3 <= b_pow8_im_r1 ; - end - vldi_r10[4]: begin - a_re4 <= ao_re_r1 ; - a_im4 <= ao_im_r1 ; - ab_re4 <= ab_re_r1 ; - ab_im4 <= ab_im_r1 ; - abb_re4 <= abb_re_r1 ; - abb_im4 <= abb_im_r1 ; - ab_pow3_re4 <= ab_pow3_re_r1; - ab_pow3_im4 <= ab_pow3_im_r1; - ab_pow4_re4 <= ab_pow4_re_r1; - ab_pow4_im4 <= ab_pow4_im_r1; - ab_pow5_re4 <= ab_pow5_re_r1; - ab_pow5_im4 <= ab_pow5_im_r1; - ab_pow6_re4 <= ab_pow6_re_r1; - ab_pow6_im4 <= ab_pow6_im_r1; - ab_pow7_re4 <= ab_pow7_re_r1; - ab_pow7_im4 <= ab_pow7_im_r1; - b_pow8_re4 <= b_pow8_re_r1 ; - b_pow8_im4 <= b_pow8_im_r1 ; - end - vldi_r10[5]: begin - a_re5 <= ao_re_r1 ; - a_im5 <= ao_im_r1 ; - ab_re5 <= ab_re_r1 ; - ab_im5 <= ab_im_r1 ; - abb_re5 <= abb_re_r1 ; - abb_im5 <= abb_im_r1 ; - ab_pow3_re5 <= ab_pow3_re_r1; - ab_pow3_im5 <= ab_pow3_im_r1; - ab_pow4_re5 <= ab_pow4_re_r1; - ab_pow4_im5 <= ab_pow4_im_r1; - ab_pow5_re5 <= ab_pow5_re_r1; - ab_pow5_im5 <= ab_pow5_im_r1; - ab_pow6_re5 <= ab_pow6_re_r1; - ab_pow6_im5 <= ab_pow6_im_r1; - ab_pow7_re5 <= ab_pow7_re_r1; - ab_pow7_im5 <= ab_pow7_im_r1; - b_pow8_re5 <= b_pow8_re_r1 ; - b_pow8_im5 <= b_pow8_im_r1 ; - end -// default: begin -// ao_re[0] <= 'h0; -// ao_im[0] <= 'h0; -// ab_re[0] <= 'h0; -// ab_im[0] <= 'h0; -// abb_re[0] <= 'h0; -// abb_im[0] <= 'h0; -// ab_pow3_re[0] <= 'h0; -// ab_pow3_im[0] <= 'h0; -// ab_pow4_re[0] <= 'h0; -// ab_pow4_im[0] <= 'h0; -// ab_pow5_re[0] <= 'h0; -// ab_pow5_im[0] <= 'h0; -// ab_pow6_re[0] <= 'h0; -// ab_pow6_im[0] <= 'h0; -// ab_pow7_re[0] <= 'h0; -// ab_pow7_im[0] <= 'h0; -// b_pow8_re[0] <= 'h0; -// b_pow8_im[0] <= 'h0; -// end - endcase - end -end - -endmodule - diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v new file mode 100644 index 0000000..687b9fc --- /dev/null +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -0,0 +1,132 @@ +//+FHDR-------------------------------------------------------------------------------------------------------- +// Company: +//----------------------------------------------------------------------------------------------------------------- +// File Name : IIR_Filter_p1.v +// Department : +// Author : hdzhang +// Author's Tel : +//----------------------------------------------------------------------------------------------------------------- +// Relese History +// Version Date Author Description +// 0.0 2025-03-09 hdzhang +//2024-05-28 10:22:49 +//----------------------------------------------------------------------------------------------------------------- +// Keywords : +// +//----------------------------------------------------------------------------------------------------------------- +// Parameter +// +//----------------------------------------------------------------------------------------------------------------- +// Purpose : +// +//----------------------------------------------------------------------------------------------------------------- +// Target Device: +// Tool versions: +//----------------------------------------------------------------------------------------------------------------- +// Reuse Issues +// Reset Strategy: +// Clock Domains: +// Critical Timing: +// Asynchronous I/F: +// Synthesizable (y/n): +// Other: +//-FHDR-------------------------------------------------------------------------------------------------------- +module IIR_Filter_p1 #( + parameter data_in_width = 16 +,parameter coef_width = 32 +,parameter frac_data_out_width = 20//X for in,5 +,parameter frac_coef_width = 31//division +) +//H(z) = a / (1 - b*z^-1) +( + input rstn +,input clk +,input en +,input signed [data_in_width-1:0] din_re // Re(x(t)) +//,input signed [data_in_width-1:0] din_im // Im(x(t)) +,input signed [data_in_width-1:0] dout_r1_re // Re(y(t-1)) +,input signed [data_in_width-1:0] dout_r1_im // Im(y(t-1)) +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] b_re +,input signed [coef_width-1 :0] b_im + +,output signed [data_in_width-1:0] dout_re // Re(y(t-16)) +,output signed [data_in_width-1:0] dout_im // Im(y(t-16)) +); + + +wire signed [data_in_width+frac_data_out_width-1:0] x1_re; +wire signed [data_in_width+frac_data_out_width-1:0] x1_im; + +wire signed [data_in_width+frac_data_out_width-1:0] y1_re; +wire signed [data_in_width+frac_data_out_width-1:0] y1_im; +wire signed [data_in_width+frac_data_out_width :0] y_re; +wire signed [data_in_width+frac_data_out_width :0] y_im; + +wire signed [data_in_width-1:0] y_re_trunc; +wire signed [data_in_width-1:0] y_im_trunc; + + +// x1 = a * din delay M = a*x(t-8) +mult_x +#( + .A_width (data_in_width ) + ,.C_width (coef_width+frac_data_out_width ) + ,.D_width (coef_width+frac_data_out_width ) + ,.frac_coef_width (frac_coef_width ) +) +inst_c1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (din_re ), + .c ({a_re,{frac_data_out_width{1'b0}}} ), + .d ({a_im,{frac_data_out_width{1'b0}}} ), + .Re (x1_re ), + .Im (x1_im ) +); + + +// y1 = b * dout_r1 delay M = b*y(t-9) +// y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) +mult_C +#( + .A_width(data_in_width) +,.B_width(data_in_width) +,.C_width(coef_width+frac_data_out_width) +,.D_width(coef_width+frac_data_out_width) +,.frac_coef_width(frac_coef_width) +) +inst_c3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dout_r1_re ), + .b (dout_r1_im ), + .c ({b_re,{frac_data_out_width{1'b0}}} ), + .d ({b_im,{frac_data_out_width{1'b0}}} ), + .Re (y1_re ), + .Im (y1_im ) +); + +assign y_re = x1_re + y1_re; +assign y_im = x1_im + y1_im; + + +// dout = round(y) delay M = round(y(t-16)) +trunc #( + .diw (data_in_width+frac_data_out_width+1 ) + ,.msb (data_in_width+frac_data_out_width-1 ) + ,.lsb (frac_data_out_width ) +) round_u1 (clk, rstn, en, y_re, y_re_trunc); +trunc #( + .diw (data_in_width+frac_data_out_width+1 ) + ,.msb (data_in_width+frac_data_out_width-1 ) + ,.lsb (frac_data_out_width ) +) round_u2 (clk, rstn, en, y_im, y_im_trunc); + +assign dout_re = y_re_trunc; +assign dout_im = y_im_trunc; + +endmodule diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index f43f6cf..e6b86ba 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -37,18 +37,19 @@ module IIR_Filter_p8 #( ,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_coef_width = 31//division ) +// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) ( input rstn ,input clk ,input en -,input signed [data_in_width-1:0] dinp0 -,input signed [data_in_width-1:0] dinp1 -,input signed [data_in_width-1:0] dinp2 -,input signed [data_in_width-1:0] dinp3 -,input signed [data_in_width-1:0] dinp4 -,input signed [data_in_width-1:0] dinp5 -,input signed [data_in_width-1:0] dinp6 -,input signed [data_in_width-1:0] dinp7 +,input signed [data_in_width-1:0] dinp0 //x(8n+16) +,input signed [data_in_width-1:0] dinp1 //x(8n+15) +,input signed [data_in_width-1:0] dinp2 //x(8n+14) +,input signed [data_in_width-1:0] dinp3 //x(8n+13) +,input signed [data_in_width-1:0] dinp4 //x(8n+12) +,input signed [data_in_width-1:0] dinp5 //x(8n+11) +,input signed [data_in_width-1:0] dinp6 //x(8n+10) +,input signed [data_in_width-1:0] dinp7 //x(8n+9) ,input signed [coef_width-1 :0] a_re ,input signed [coef_width-1 :0] a_im @@ -69,72 +70,64 @@ module IIR_Filter_p8 #( ,input signed [coef_width-1 :0] b_pow8_re ,input signed [coef_width-1 :0] b_pow8_im -,output signed [data_in_width-1:0] dout +,output signed [data_in_width-1:0] dout_re // Re(y(8n-8)) +,output signed [data_in_width-1:0] dout_im // Im(y(8n-8)) ); -wire signed [data_in_width-1 :0] dinp [7:0]; -assign dinp[7] = dinp7; -assign dinp[6] = dinp6; -assign dinp[5] = dinp5; -assign dinp[4] = dinp4; -assign dinp[3] = dinp3; -assign dinp[2] = dinp2; -assign dinp[1] = dinp1; -assign dinp[0] = dinp0; +wire signed [data_in_width-1:0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0}; +wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; +wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; -wire signed [coef_width-1 :0] ab_pow_re [7:0]; -assign ab_pow_re[7] = ab_pow7_re; -assign ab_pow_re[6] = ab_pow6_re; -assign ab_pow_re[5] = ab_pow5_re; -assign ab_pow_re[4] = ab_pow4_re; -assign ab_pow_re[3] = ab_pow3_re; -assign ab_pow_re[2] = abb_re; -assign ab_pow_re[1] = ab_re; -assign ab_pow_re[0] = a_re; +wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7]; +wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7]; -wire signed [coef_width-1 :0] ab_pow_im [7:0]; -assign ab_pow_im[7] = ab_pow7_im; -assign ab_pow_im[6] = ab_pow6_im; -assign ab_pow_im[5] = ab_pow5_im; -assign ab_pow_im[4] = ab_pow4_im; -assign ab_pow_im[3] = ab_pow3_im; -assign ab_pow_im[2] = abb_im; -assign ab_pow_im[1] = ab_im; -assign ab_pow_im[0] = a_im; +wire signed [data_in_width+frac_data_out_width+3:0] v_re; +wire signed [data_in_width+frac_data_out_width+3:0] v_im; +reg signed [data_in_width+frac_data_out_width+3:0] v1_re; +reg signed [data_in_width+frac_data_out_width+3:0] v1_im; -wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7]; -wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7]; +wire signed [data_in_width+frac_data_out_width+3:0] y_re; +wire signed [data_in_width+frac_data_out_width+3:0] y_im; +reg signed [data_in_width+frac_data_out_width+3:0] y1_re; +reg signed [data_in_width+frac_data_out_width+3:0] y1_im; +wire signed [data_in_width-1:0] y_re_trunc; +wire signed [data_in_width-1:0] y_im_trunc; + +// x[0] = (dinp0 * a_re) delay M = a*x(8n+8) +// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7) +// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6) +// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5) +// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4) +// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3) +// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2) +// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1) genvar i; generate - for (i = 0; i < 8; i = i + 1) begin: mult_x_inst + for (i = 0; i < 8; i = i + 1) begin: mult_c_inst mult_x #( - .A_width(data_in_width), - .C_width(coef_width+frac_data_out_width), - .D_width(coef_width+frac_data_out_width), - .frac_coef_width(frac_coef_width) - ) inst_mult_x ( - .clk (clk), - .rstn (rstn), - .en (en), - .a (dinp[i]), - .c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}), - .d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}), - .Re (x_re[i]), - .Im (x_im[i]) + .A_width (data_in_width ), + .C_width (coef_width+frac_data_out_width ), + .D_width (coef_width+frac_data_out_width ), + .frac_coef_width (frac_coef_width ) + ) inst_c ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp[i] ), + .c ({ab_pow_re[i],{frac_data_out_width{1'b0}}} ), + .d ({ab_pow_im[i],{frac_data_out_width{1'b0}}} ), + .Re (x_re[i] ), + .Im (x_im[i] ) ); end endgenerate -wire signed [data_in_width+frac_data_out_width+3:0] v_re; -wire signed [data_in_width+frac_data_out_width+3:0] v_im; +// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7]; assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7]; -reg signed [data_in_width+frac_data_out_width+3:0] v1_re; -reg signed [data_in_width+frac_data_out_width+3:0] v1_im; - always @(posedge clk or negedge rstn) if (!rstn) begin @@ -152,22 +145,18 @@ always @(posedge clk or negedge rstn) v1_im <= v1_im; end -wire signed [data_in_width+frac_data_out_width+3:0] y_re; -wire signed [data_in_width+frac_data_out_width+3:0] y_im; -wire signed [data_in_width+frac_data_out_width+3:0] y1_re; -wire signed [data_in_width+frac_data_out_width+3:0] y1_im; - -reg signed [data_in_width-1:0] dout_re; +// y1 = (b^8 * y) delay M = b^8*y(8n-8) +// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) mult_C #( - .A_width(data_in_width+frac_data_out_width+4) -,.B_width(data_in_width+frac_data_out_width+4) -,.C_width(coef_width) -,.D_width(coef_width) -,.frac_coef_width(frac_coef_width) + .A_width (data_in_width+frac_data_out_width+4 ) + ,.B_width (data_in_width+frac_data_out_width+4 ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.frac_coef_width (frac_coef_width ) ) -inst_c9 ( +inst_c9 ( .clk (clk ), .rstn (rstn ), .en (en ), @@ -175,53 +164,28 @@ inst_c9 ( .b (y_im ), .c (b_pow8_re ), .d (b_pow8_im ), - .Re (y1_re ),//b^8*y(n-1) + .Re (y1_re ), .Im (y1_im ) - ); +); assign y_re = v1_re + y1_re; assign y_im = v1_im + y1_im; -wire signed [data_in_width+frac_data_out_width+3:0] dout_round; +// dout = round(y) delay M = round(y(8n-8)) +trunc #( + .diw (data_in_width+frac_data_out_width+4 ) + ,.msb (data_in_width+frac_data_out_width-1 ) + ,.lsb (frac_data_out_width ) +) round_u1 (clk, rstn, en, y_re, y_re_trunc); +trunc #( + .diw (data_in_width+frac_data_out_width+4 ) + ,.msb (data_in_width+frac_data_out_width-1 ) + ,.lsb (frac_data_out_width ) +) round_u2 (clk, rstn, en, y_im, y_im_trunc); -FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round); -always @(posedge clk or negedge rstn) - if (!rstn) - begin - dout_re <= 'h0; - end - else if(en) - begin - dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width]; - end - else - begin - dout_re <= dout_re; - end - -reg signed [data_in_width-1:0] dout_clip; - -always @(posedge clk or negedge rstn) - if (!rstn) - begin - dout_clip <= 'h0; - end - else if(en) - begin - if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01) - dout_clip <= 16'd32767; - else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10) - dout_clip <= -16'd32768; - else - dout_clip <= dout_re; - end - else - begin - dout_clip <= dout_clip; - end - -assign dout = dout_clip; +assign dout_re = y_re_trunc; +assign dout_im = y_im_trunc; endmodule diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index df02efe..091cc7b 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -31,330 +31,359 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- -module IIR_top +module IIR_top ( input rstn ,input clk ,input en -,input signed [15 :0] IIRin_p0 -,input signed [15 :0] IIRin_p1 -,input signed [15 :0] IIRin_p2 -,input signed [15 :0] IIRin_p3 -,input signed [15 :0] IIRin_p4 -,input signed [15 :0] IIRin_p5 -,input signed [15 :0] IIRin_p6 -,input signed [15 :0] IIRin_p7 -,input signed [31 :0] a_re -,input signed [31 :0] a_im -,input signed [31 :0] ab_re -,input signed [31 :0] ab_im -,input signed [31 :0] abb_re -,input signed [31 :0] abb_im -,input signed [31 :0] ab_pow3_re -,input signed [31 :0] ab_pow3_im -,input signed [31 :0] ab_pow4_re -,input signed [31 :0] ab_pow4_im -,input signed [31 :0] ab_pow5_re -,input signed [31 :0] ab_pow5_im -,input signed [31 :0] ab_pow6_re -,input signed [31 :0] ab_pow6_im -,input signed [31 :0] ab_pow7_re -,input signed [31 :0] ab_pow7_im -,input signed [31 :0] b_pow8_re -,input signed [31 :0] b_pow8_im +,input signed [15 :0] IIRin_p0 // x(8n+9) +,input signed [15 :0] IIRin_p1 // x(8n+10) +,input signed [15 :0] IIRin_p2 // x(8n+11) +,input signed [15 :0] IIRin_p3 // x(8n+12) +,input signed [15 :0] IIRin_p4 // x(8n+13) +,input signed [15 :0] IIRin_p5 // x(8n+14) +,input signed [15 :0] IIRin_p6 // x(8n+15) +,input signed [15 :0] IIRin_p7 // x(8n+16) +,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) +,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) +,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) +,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) +,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) +,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) +,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) +,input signed [31 :0] a_re +,input signed [31 :0] a_im +,input signed [31 :0] b_re +,input signed [31 :0] b_im +,input signed [31 :0] ab_re +,input signed [31 :0] ab_im +,input signed [31 :0] abb_re +,input signed [31 :0] abb_im +,input signed [31 :0] ab_pow3_re +,input signed [31 :0] ab_pow3_im +,input signed [31 :0] ab_pow4_re +,input signed [31 :0] ab_pow4_im +,input signed [31 :0] ab_pow5_re +,input signed [31 :0] ab_pow5_im +,input signed [31 :0] ab_pow6_re +,input signed [31 :0] ab_pow6_im +,input signed [31 :0] ab_pow7_re +,input signed [31 :0] ab_pow7_im +,input signed [31 :0] b_pow8_re +,input signed [31 :0] b_pow8_im -,output signed [15 :0] IIRout_p0 -,output signed [15 :0] IIRout_p1 -,output signed [15 :0] IIRout_p2 -,output signed [15 :0] IIRout_p3 -,output signed [15 :0] IIRout_p4 -,output signed [15 :0] IIRout_p5 -,output signed [15 :0] IIRout_p6 -,output signed [15 :0] IIRout_p7 - ); -reg signed [15:0] IIRin_p_r1 [7:1]; -wire signed [15 : 0] IIRin_p [7:0]; -assign IIRin_p[7] = IIRin_p7; -assign IIRin_p[6] = IIRin_p6; -assign IIRin_p[5] = IIRin_p5; -assign IIRin_p[4] = IIRin_p4; -assign IIRin_p[3] = IIRin_p3; -assign IIRin_p[2] = IIRin_p2; -assign IIRin_p[1] = IIRin_p1; -assign IIRin_p[0] = IIRin_p0; -integer i; +,output signed [15 :0] IIRout_p0 // y(8n-8) +,output signed [15 :0] IIRout_p1 // y(8n-23) +,output signed [15 :0] IIRout_p2 // y(8n-38) +,output signed [15 :0] IIRout_p3 // y(8n-53) +,output signed [15 :0] IIRout_p4 // y(8n-68) +,output signed [15 :0] IIRout_p5 // y(8n-83) +,output signed [15 :0] IIRout_p6 // y(8n-98) +,output signed [15 :0] IIRout_p7 // y(8n-113) + ); +/*reg signed [15:0] IIRin_p0_r [1 :0]; +reg signed [15:0] IIRin_p1_r [3 :0]; +reg signed [15:0] IIRin_p2_r [5 :0]; +reg signed [15:0] IIRin_p3_r [7 :0]; +reg signed [15:0] IIRin_p4_r [9 :0]; +reg signed [15:0] IIRin_p5_r [11:0]; +reg signed [15:0] IIRin_p6_r [13:0];//*/ + +wire signed [15:0] IIRout_p0_re; +wire signed [15:0] IIRout_p1_re; +wire signed [15:0] IIRout_p2_re; +wire signed [15:0] IIRout_p3_re; +wire signed [15:0] IIRout_p4_re; +wire signed [15:0] IIRout_p5_re; +wire signed [15:0] IIRout_p6_re; +wire signed [15:0] IIRout_p7_re; +wire signed [15:0] IIRout_p0_im; +wire signed [15:0] IIRout_p1_im; +wire signed [15:0] IIRout_p2_im; +wire signed [15:0] IIRout_p3_im; +wire signed [15:0] IIRout_p4_im; +wire signed [15:0] IIRout_p5_im; +wire signed [15:0] IIRout_p6_im; +wire signed [15:0] IIRout_p7_im; + +/*reg signed [15:0] IIRout_p0_r [13:0]; +reg signed [15:0] IIRout_p1_r [12:0]; +reg signed [15:0] IIRout_p2_r [10:0]; +reg signed [15:0] IIRout_p3_r [8 :0]; +reg signed [15:0] IIRout_p4_r [6 :0]; +reg signed [15:0] IIRout_p5_r [4 :0]; +reg signed [15:0] IIRout_p6_r [2 :0]; +reg signed [15:0] IIRout_p7_r;//*/ + + +/*integer i; always @(posedge clk or negedge rstn) begin if (!rstn) begin - for (i = 1; i < 8; i = i + 1) begin - IIRin_p_r1[i] <= 'h0; + for (i = 0; i < 2; i = i + 1) begin + IIRin_p0_r[i] <= 'h0; + end + for (i = 0; i < 4; i = i + 1) begin + IIRin_p1_r[i] <= 'h0; + end + for (i = 0; i < 6; i = i + 1) begin + IIRin_p2_r[i] <= 'h0; + end + for (i = 0; i < 8; i = i + 1) begin + IIRin_p3_r[i] <= 'h0; + end + for (i = 0; i <10; i = i + 1) begin + IIRin_p4_r[i] <= 'h0; + end + for (i = 0; i <12; i = i + 1) begin + IIRin_p5_r[i] <= 'h0; + end + for (i = 0; i <14; i = i + 1) begin + IIRin_p6_r[i] <= 'h0; end end else if (en) begin - for (i = 1; i < 8; i = i + 1) begin - IIRin_p_r1[i] <= IIRin_p[i]; + IIRin_p0_r[0] <= IIRin_p0; + IIRin_p1_r[0] <= IIRin_p1; + IIRin_p2_r[0] <= IIRin_p2; + IIRin_p3_r[0] <= IIRin_p3; + IIRin_p4_r[0] <= IIRin_p4; + IIRin_p5_r[0] <= IIRin_p5; + IIRin_p6_r[0] <= IIRin_p6; + for (i = 0; i < 1; i = i + 1) begin + IIRin_p0_r[i+1] <= IIRin_p0_r[i]; + end + for (i = 0; i < 3; i = i + 1) begin + IIRin_p1_r[i+1] <= IIRin_p1_r[i]; + end + for (i = 0; i < 5; i = i + 1) begin + IIRin_p2_r[i+1] <= IIRin_p2_r[i]; + end + for (i = 0; i < 7; i = i + 1) begin + IIRin_p3_r[i+1] <= IIRin_p3_r[i]; + end + for (i = 0; i < 9; i = i + 1) begin + IIRin_p4_r[i+1] <= IIRin_p4_r[i]; + end + for (i = 0; i <11; i = i + 1) begin + IIRin_p5_r[i+1] <= IIRin_p5_r[i]; + end + for (i = 0; i <13; i = i + 1) begin + IIRin_p6_r[i+1] <= IIRin_p6_r[i]; end end -end +end //*/ -IIR_Filter_p8 inst_iir_p0 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[0] ), - .dinp1 (IIRin_p_r1[7] ), - .dinp2 (IIRin_p_r1[6] ), - .dinp3 (IIRin_p_r1[5] ), - .dinp4 (IIRin_p_r1[4] ), - .dinp5 (IIRin_p_r1[3] ), - .dinp6 (IIRin_p_r1[2] ), - .dinp7 (IIRin_p_r1[1] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p0 ) - ); +IIR_Filter_p8 inst_iir_p0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .dinp0 (IIRin_p7 ), // x(8n+16) + .dinp1 (IIRin_p6 ), // x(8n+15) + .dinp2 (IIRin_p5 ), // x(8n+14) + .dinp3 (IIRin_p4 ), // x(8n+13) + .dinp4 (IIRin_p3 ), // x(8n+12) + .dinp5 (IIRin_p2 ), // x(8n+11) + .dinp6 (IIRin_p1 ), // x(8n+10) + .dinp7 (IIRin_p0 ), // x(8n+9) + .a_re (a_re ), + .a_im (a_im ), + .ab_re (ab_re ), + .ab_im (ab_im ), + .abb_re (abb_re ), + .abb_im (abb_im ), + .ab_pow3_re (ab_pow3_re ), + .ab_pow3_im (ab_pow3_im ), + .ab_pow4_re (ab_pow4_re ), + .ab_pow4_im (ab_pow4_im ), + .ab_pow5_re (ab_pow5_re ), + .ab_pow5_im (ab_pow5_im ), + .ab_pow6_re (ab_pow6_re ), + .ab_pow6_im (ab_pow6_im ), + .ab_pow7_re (ab_pow7_re ), + .ab_pow7_im (ab_pow7_im ), + .b_pow8_re (b_pow8_re ), + .b_pow8_im (b_pow8_im ), + .dout_re (IIRout_p0_re ), // Re(y(8n-8)) + .dout_im (IIRout_p0_im ) // Im(y(8n-8)) +); -IIR_Filter_p8 inst_iir_p1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[1] ), - .dinp1 (IIRin_p[0] ), - .dinp2 (IIRin_p_r1[7] ), - .dinp3 (IIRin_p_r1[6] ), - .dinp4 (IIRin_p_r1[5] ), - .dinp5 (IIRin_p_r1[4] ), - .dinp6 (IIRin_p_r1[3] ), - .dinp7 (IIRin_p_r1[2] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p1 ) - ); -IIR_Filter_p8 inst_iir_p2 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[2] ), - .dinp1 (IIRin_p[1] ), - .dinp2 (IIRin_p[0] ), - .dinp3 (IIRin_p_r1[7] ), - .dinp4 (IIRin_p_r1[6] ), - .dinp5 (IIRin_p_r1[5] ), - .dinp6 (IIRin_p_r1[4] ), - .dinp7 (IIRin_p_r1[3] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p2 ) - ); -IIR_Filter_p8 inst_iir_p3 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[3] ), - .dinp1 (IIRin_p[2] ), - .dinp2 (IIRin_p[1] ), - .dinp3 (IIRin_p[0] ), - .dinp4 (IIRin_p_r1[7] ), - .dinp5 (IIRin_p_r1[6] ), - .dinp6 (IIRin_p_r1[5] ), - .dinp7 (IIRin_p_r1[4] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p3 ) - ); -IIR_Filter_p8 inst_iir_p4 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[4] ), - .dinp1 (IIRin_p[3] ), - .dinp2 (IIRin_p[2] ), - .dinp3 (IIRin_p[1] ), - .dinp4 (IIRin_p[0] ), - .dinp5 (IIRin_p_r1[7] ), - .dinp6 (IIRin_p_r1[6] ), - .dinp7 (IIRin_p_r1[5] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p4 ) - ); -IIR_Filter_p8 inst_iir_p5 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[5] ), - .dinp1 (IIRin_p[4] ), - .dinp2 (IIRin_p[3] ), - .dinp3 (IIRin_p[2] ), - .dinp4 (IIRin_p[1] ), - .dinp5 (IIRin_p[0] ), - .dinp6 (IIRin_p_r1[7] ), - .dinp7 (IIRin_p_r1[6] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p5 ) - ); -IIR_Filter_p8 inst_iir_p6 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[6] ), - .dinp1 (IIRin_p[5] ), - .dinp2 (IIRin_p[4] ), - .dinp3 (IIRin_p[3] ), - .dinp4 (IIRin_p[2] ), - .dinp5 (IIRin_p[1] ), - .dinp6 (IIRin_p[0] ), - .dinp7 (IIRin_p_r1[7] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p6 ) - ); -IIR_Filter_p8 inst_iir_p7 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p[7] ), - .dinp1 (IIRin_p[6] ), - .dinp2 (IIRin_p[5] ), - .dinp3 (IIRin_p[4] ), - .dinp4 (IIRin_p[3] ), - .dinp5 (IIRin_p[2] ), - .dinp6 (IIRin_p[1] ), - .dinp7 (IIRin_p[0] ), - .a_re (a_re ), - .a_im (a_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout (IIRout_p7 ) - ); +IIR_Filter_p1 inst_iir_p1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p0_r2 ), // x(8n-7) + .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) + .dout_r1_im (IIRout_p0_im ), // Im(y(8n-8)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p1_re ), // Re(y(8n-23)) + .dout_im (IIRout_p1_im ) // Im(y(8n-23)) +); +IIR_Filter_p1 inst_iir_p2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p1_r4 ), // x(8n-22) + .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) + .dout_r1_im (IIRout_p1_im ), // Im(y(8n-23)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p2_re ), // Re(y(8n-38)) + .dout_im (IIRout_p2_im ) // Im(y(8n-38)) +); +IIR_Filter_p1 inst_iir_p3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p2_r6 ), // x(8n-37) + .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) + .dout_r1_im (IIRout_p2_im ), // Im(y(8n-38)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p3_re ), // Re(y(8n-53)) + .dout_im (IIRout_p3_im ) // Im(y(8n-53)) +); +IIR_Filter_p1 inst_iir_p4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p3_r8 ), // x(8n-52) + .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) + .dout_r1_im (IIRout_p3_im ), // Im(y(8n-53)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p4_re ), // Re(y(8n-68)) + .dout_im (IIRout_p4_im ) // Im(y(8n-68)) +); +IIR_Filter_p1 inst_iir_p5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p4_r10 ), // x(8n-67) + .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) + .dout_r1_im (IIRout_p4_im ), // Im(y(8n-68)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p5_re ), // Re(y(8n-83)) + .dout_im (IIRout_p5_im ) // Im(y(8n-83)) +); +IIR_Filter_p1 inst_iir_p6 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p5_r12 ), // x(8n-82) + .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) + .dout_r1_im (IIRout_p5_im ), // Im(y(8n-83)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p6_re ), // Re(y(8n-98)) + .dout_im (IIRout_p6_im ) // Im(y(8n-98)) +); +IIR_Filter_p1 inst_iir_p7 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p6_r14 ), // x(8n-97) + .dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) + .dout_r1_im (IIRout_p6_im ), // Im(y(8n-98)) + .a_re (a_re ), + .a_im (a_im ), + .b_re (b_re ), + .b_im (b_im ), + .dout_re (IIRout_p7_re ), // Re(y(8n-113)) + .dout_im (IIRout_p7_im ) // Im(y(8n-113)) +); + + + +/*integer i; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 2; i = i + 1) begin + IIRout_p6_r[i] <= 'h0; + end + for (i = 0; i < 4; i = i + 1) begin + IIRout_p5_r[i] <= 'h0; + end + for (i = 0; i < 6; i = i + 1) begin + IIRout_p4_r[i] <= 'h0; + end + for (i = 0; i < 8; i = i + 1) begin + IIRout_p3_r[i] <= 'h0; + end + for (i = 0; i <10; i = i + 1) begin + IIRout_p2_r[i] <= 'h0; + end + for (i = 0; i <12; i = i + 1) begin + IIRout_p1_r[i] <= 'h0; + end + for (i = 0; i <14; i = i + 1) begin + IIRout_p0_r[i] <= 'h0; + end + end + else if (en) begin + IIRout_p7_r <= IIRout_p7_re; + IIRout_p6_r[0] <= IIRout_p6_re; + IIRout_p5_r[0] <= IIRout_p5_re; + IIRout_p4_r[0] <= IIRout_p4_re; + IIRout_p3_r[0] <= IIRout_p3_re; + IIRout_p2_r[0] <= IIRout_p2_re; + IIRout_p1_r[0] <= IIRout_p1_re; + IIRout_p0_r[0] <= IIRout_p0_re; + for (i = 0; i < 2; i = i + 1) begin + IIRout_p6_r[i+1] <= IIRout_p6_r[i]; + end + for (i = 0; i < 4; i = i + 1) begin + IIRout_p5_r[i+1] <= IIRout_p5_r[i]; + end + for (i = 0; i < 6; i = i + 1) begin + IIRout_p4_r[i+1] <= IIRout_p4_r[i]; + end + for (i = 0; i < 8; i = i + 1) begin + IIRout_p3_r[i+1] <= IIRout_p3_r[i]; + end + for (i = 0; i <10; i = i + 1) begin + IIRout_p2_r[i+1] <= IIRout_p2_r[i]; + end + for (i = 0; i <12; i = i + 1) begin + IIRout_p1_r[i+1] <= IIRout_p1_r[i]; + end + for (i = 0; i <13; i = i + 1) begin + IIRout_p0_r[i+1] <= IIRout_p0_r[i]; + end + end +end +assign IIRout_p0 = IIRout_p1_r[12]; // y(8n-127) +assign IIRout_p1 = IIRout_p2_r[10]; // y(8n-126) +assign IIRout_p2 = IIRout_p3_r[8]; // y(8n-125) +assign IIRout_p3 = IIRout_p4_r[6]; // y(8n-124) +assign IIRout_p4 = IIRout_p5_r[4]; // y(8n-123) +assign IIRout_p5 = IIRout_p6_r[2]; // y(8n-122) +assign IIRout_p6 = IIRout_p7_r; // y(8n-121) +assign IIRout_p7 = IIRout_p0_r[13]; // y(8n-120)//*/ + +assign IIRout_p0 = IIRout_p0_re; // y(8n-8) +assign IIRout_p1 = IIRout_p1_re; // y(8n-23) +assign IIRout_p2 = IIRout_p2_re; // y(8n-38) +assign IIRout_p3 = IIRout_p3_re; // y(8n-53) +assign IIRout_p4 = IIRout_p4_re; // y(8n-68) +assign IIRout_p5 = IIRout_p5_re; // y(8n-83) +assign IIRout_p6 = IIRout_p6_re; // y(8n-98) +assign IIRout_p7 = IIRout_p7_re; // y(8n-113) endmodule diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index 4bf4bbb..022d006 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -8,7 +8,6 @@ //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description - // 0.3 2025-02-28 thfu //----------------------------------------------------------------------------------------------------------------- // Keywords : @@ -45,6 +44,8 @@ module TailCorr_top ,input signed [15:0] din3 ,input signed [31:0] a_re0 ,input signed [31:0] a_im0 +,input signed [31:0] b_re0 +,input signed [31:0] b_im0 ,input signed [31:0] ab_re0 ,input signed [31:0] ab_im0 ,input signed [31:0] abb_re0 @@ -63,6 +64,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im0 ,input signed [31:0] a_re1 ,input signed [31:0] a_im1 +,input signed [31:0] b_re1 +,input signed [31:0] b_im1 ,input signed [31:0] ab_re1 ,input signed [31:0] ab_im1 ,input signed [31:0] abb_re1 @@ -81,6 +84,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im1 ,input signed [31:0] a_re2 ,input signed [31:0] a_im2 +,input signed [31:0] b_re2 +,input signed [31:0] b_im2 ,input signed [31:0] ab_re2 ,input signed [31:0] ab_im2 ,input signed [31:0] abb_re2 @@ -99,6 +104,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im2 ,input signed [31:0] a_re3 ,input signed [31:0] a_im3 +,input signed [31:0] b_re3 +,input signed [31:0] b_im3 ,input signed [31:0] ab_re3 ,input signed [31:0] ab_im3 ,input signed [31:0] abb_re3 @@ -117,6 +124,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im3 ,input signed [31:0] a_re4 ,input signed [31:0] a_im4 +,input signed [31:0] b_re4 +,input signed [31:0] b_im4 ,input signed [31:0] ab_re4 ,input signed [31:0] ab_im4 ,input signed [31:0] abb_re4 @@ -135,6 +144,8 @@ module TailCorr_top ,input signed [31:0] b_pow8_im4 ,input signed [31:0] a_re5 ,input signed [31:0] a_im5 +,input signed [31:0] b_re5 +,input signed [31:0] b_im5 ,input signed [31:0] ab_re5 ,input signed [31:0] ab_im5 ,input signed [31:0] abb_re5 @@ -171,14 +182,61 @@ wire signed [15:0] din_p4; wire signed [15:0] din_p5; wire signed [15:0] din_p6; wire signed [15:0] din_p7; -wire signed [15:0] IIRin_p0; -wire signed [15:0] IIRin_p1; -wire signed [15:0] IIRin_p2; -wire signed [15:0] IIRin_p3; -wire signed [15:0] IIRin_p4; -wire signed [15:0] IIRin_p5; -wire signed [15:0] IIRin_p6; -wire signed [15:0] IIRin_p7; +wire signed [15:0] IIRin_p0; // iirin_x(8n+9) +wire signed [15:0] IIRin_p1; // iirin_x(8n+10) +wire signed [15:0] IIRin_p2; // iirin_x(8n+11) +wire signed [15:0] IIRin_p3; // iirin_x(8n+12) +wire signed [15:0] IIRin_p4; // iirin_x(8n+13) +wire signed [15:0] IIRin_p5; // iirin_x(8n+14) +wire signed [15:0] IIRin_p6; // iirin_x(8n+15) +wire signed [15:0] IIRin_p7; // iirin_x(8n+16) +wire signed [15:0] IIRout_p0 [5:0]; // iirout_y(8n-8) +wire signed [15:0] IIRout_p1 [5:0]; // iirout_y(8n-23) +wire signed [15:0] IIRout_p2 [5:0]; // iirout_y(8n-38) +wire signed [15:0] IIRout_p3 [5:0]; // iirout_y(8n-53) +wire signed [15:0] IIRout_p4 [5:0]; // iirout_y(8n-68) +wire signed [15:0] IIRout_p5 [5:0]; // iirout_y(8n-83) +wire signed [15:0] IIRout_p6 [5:0]; // iirout_y(8n-98) +wire signed [15:0] IIRout_p7 [5:0]; // iirout_y(8n-113) +wire signed [15:0] sum_IIRout_p0; +wire signed [15:0] sum_IIRout_p1; +wire signed [15:0] sum_IIRout_p2; +wire signed [15:0] sum_IIRout_p3; +wire signed [15:0] sum_IIRout_p4; +wire signed [15:0] sum_IIRout_p5; +wire signed [15:0] sum_IIRout_p6; +wire signed [15:0] sum_IIRout_p7; +reg signed [15:0] din_p0_r [15:0]; +reg signed [15:0] din_p1_r [15:0]; +reg signed [15:0] din_p2_r [15:0]; +reg signed [15:0] din_p3_r [15:0]; +reg signed [15:0] din_p4_r [15:0]; +reg signed [15:0] din_p5_r [15:0]; +reg signed [15:0] din_p6_r [15:0]; +reg signed [15:0] din_p7_r [15:0]; +reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7) +reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22) +reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37) +reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53) +reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67) +reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82) +reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97) +reg signed [18:0] sum_IIRout_p0_r [12:0]; +reg signed [18:0] sum_IIRout_p1_r [11:0]; +reg signed [18:0] sum_IIRout_p2_r [9 :0]; +reg signed [18:0] sum_IIRout_p3_r [7 :0]; +reg signed [18:0] sum_IIRout_p4_r [5 :0]; +reg signed [18:0] sum_IIRout_p5_r [3 :0]; +reg signed [18:0] sum_IIRout_p6_r [1 :0]; +wire signed [18:0] dout_p0_r0; +wire signed [18:0] dout_p1_r0; +wire signed [18:0] dout_p2_r0; +wire signed [18:0] dout_p3_r0; +wire signed [18:0] dout_p4_r0; +wire signed [18:0] dout_p5_r0; +wire signed [18:0] dout_p6_r0; +wire signed [18:0] dout_p7_r0; + wire vldo_diff; diff_p inst_diff_p ( .rstn (rstn), @@ -207,14 +265,104 @@ diff_p inst_diff_p ( .diff_p6 (IIRin_p6), .diff_p7 (IIRin_p7) ); -wire signed [15:0] IIRout0_p0; -wire signed [15:0] IIRout0_p1; -wire signed [15:0] IIRout0_p2; -wire signed [15:0] IIRout0_p3; -wire signed [15:0] IIRout0_p4; -wire signed [15:0] IIRout0_p5; -wire signed [15:0] IIRout0_p6; -wire signed [15:0] IIRout0_p7; + +integer i; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 17; i = i + 1) begin + din_p0_r[i] <= 'h0; + din_p1_r[i] <= 'h0; + din_p2_r[i] <= 'h0; + din_p3_r[i] <= 'h0; + din_p4_r[i] <= 'h0; + din_p5_r[i] <= 'h0; + din_p6_r[i] <= 'h0; + din_p7_r[i] <= 'h0; + end + end + else if (en) begin + din_p0_r[0] <= din_p0; + din_p1_r[0] <= din_p1; + din_p2_r[0] <= din_p2; + din_p3_r[0] <= din_p3; + din_p4_r[0] <= din_p4; + din_p5_r[0] <= din_p5; + din_p6_r[0] <= din_p6; + din_p7_r[0] <= din_p7; + for (i = 0; i < 15; i = i + 1) begin + din_p0_r[i+1] <= din_p0_r[i]; + din_p1_r[i+1] <= din_p1_r[i]; + din_p2_r[i+1] <= din_p2_r[i]; + din_p3_r[i+1] <= din_p3_r[i]; + din_p4_r[i+1] <= din_p4_r[i]; + din_p5_r[i+1] <= din_p5_r[i]; + din_p6_r[i+1] <= din_p6_r[i]; + din_p7_r[i+1] <= din_p7_r[i]; + end + end +end + + +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 2; i = i + 1) begin + IIRin_p0_r[i] <= 'h0; + end + for (i = 0; i < 4; i = i + 1) begin + IIRin_p1_r[i] <= 'h0; + end + for (i = 0; i < 6; i = i + 1) begin + IIRin_p2_r[i] <= 'h0; + end + for (i = 0; i < 8; i = i + 1) begin + IIRin_p3_r[i] <= 'h0; + end + for (i = 0; i <10; i = i + 1) begin + IIRin_p4_r[i] <= 'h0; + end + for (i = 0; i <12; i = i + 1) begin + IIRin_p5_r[i] <= 'h0; + end + for (i = 0; i <14; i = i + 1) begin + IIRin_p6_r[i] <= 'h0; + end + end + else if (en) begin + IIRin_p0_r[0] <= IIRin_p0; + IIRin_p1_r[0] <= IIRin_p1; + IIRin_p2_r[0] <= IIRin_p2; + IIRin_p3_r[0] <= IIRin_p3; + IIRin_p4_r[0] <= IIRin_p4; + IIRin_p5_r[0] <= IIRin_p5; + IIRin_p6_r[0] <= IIRin_p6; + for (i = 0; i < 1; i = i + 1) begin + IIRin_p0_r[i+1] <= IIRin_p0_r[i]; + end + for (i = 0; i < 3; i = i + 1) begin + IIRin_p1_r[i+1] <= IIRin_p1_r[i]; + end + for (i = 0; i < 5; i = i + 1) begin + IIRin_p2_r[i+1] <= IIRin_p2_r[i]; + end + for (i = 0; i < 7; i = i + 1) begin + IIRin_p3_r[i+1] <= IIRin_p3_r[i]; + end + for (i = 0; i < 9; i = i + 1) begin + IIRin_p4_r[i+1] <= IIRin_p4_r[i]; + end + for (i = 0; i <11; i = i + 1) begin + IIRin_p5_r[i+1] <= IIRin_p5_r[i]; + end + for (i = 0; i <13; i = i + 1) begin + IIRin_p6_r[i+1] <= IIRin_p6_r[i]; + end + end +end + + + + + IIR_top inst_iir_top_0 ( .clk (clk ), .rstn (rstn ), @@ -227,8 +375,17 @@ IIR_top inst_iir_top_0 ( .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1]), + .IIRin_p1_r4 (IIRin_p1_r[3]), + .IIRin_p2_r6 (IIRin_p2_r[5]), + .IIRin_p3_r8 (IIRin_p3_r[7]), + .IIRin_p4_r10 (IIRin_p4_r[9]), + .IIRin_p5_r12 (IIRin_p5_r[11]), + .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re0 ), .a_im (a_im0 ), + .b_re (b_re0 ), + .b_im (b_im0 ), .ab_re (ab_re0 ), .ab_im (ab_im0 ), .abb_re (abb_re0 ), @@ -245,23 +402,16 @@ IIR_top inst_iir_top_0 ( .ab_pow7_im (ab_pow7_im0 ), .b_pow8_re (b_pow8_re0 ), .b_pow8_im (b_pow8_im0 ), - .IIRout_p0 (IIRout0_p0 ), - .IIRout_p1 (IIRout0_p1 ), - .IIRout_p2 (IIRout0_p2 ), - .IIRout_p3 (IIRout0_p3 ), - .IIRout_p4 (IIRout0_p4 ), - .IIRout_p5 (IIRout0_p5 ), - .IIRout_p6 (IIRout0_p6 ), - .IIRout_p7 (IIRout0_p7 ) + .IIRout_p0 (IIRout_p0[0] ), + .IIRout_p1 (IIRout_p1[0] ), + .IIRout_p2 (IIRout_p2[0] ), + .IIRout_p3 (IIRout_p3[0] ), + .IIRout_p4 (IIRout_p4[0] ), + .IIRout_p5 (IIRout_p5[0] ), + .IIRout_p6 (IIRout_p6[0] ), + .IIRout_p7 (IIRout_p7[0] ) ); -wire signed [15:0] IIRout1_p0; -wire signed [15:0] IIRout1_p1; -wire signed [15:0] IIRout1_p2; -wire signed [15:0] IIRout1_p3; -wire signed [15:0] IIRout1_p4; -wire signed [15:0] IIRout1_p5; -wire signed [15:0] IIRout1_p6; -wire signed [15:0] IIRout1_p7; + IIR_top inst_iir_top_1 ( .clk (clk ), .rstn (rstn ), @@ -274,8 +424,17 @@ IIR_top inst_iir_top_1 ( .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1]), + .IIRin_p1_r4 (IIRin_p1_r[3]), + .IIRin_p2_r6 (IIRin_p2_r[5]), + .IIRin_p3_r8 (IIRin_p3_r[7]), + .IIRin_p4_r10 (IIRin_p4_r[9]), + .IIRin_p5_r12 (IIRin_p5_r[11]), + .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re1 ), .a_im (a_im1 ), + .b_re (b_re1 ), + .b_im (b_im1 ), .ab_re (ab_re1 ), .ab_im (ab_im1 ), .abb_re (abb_re1 ), @@ -292,23 +451,16 @@ IIR_top inst_iir_top_1 ( .ab_pow7_im (ab_pow7_im1 ), .b_pow8_re (b_pow8_re1 ), .b_pow8_im (b_pow8_im1 ), - .IIRout_p0 (IIRout1_p0 ), - .IIRout_p1 (IIRout1_p1 ), - .IIRout_p2 (IIRout1_p2 ), - .IIRout_p3 (IIRout1_p3 ), - .IIRout_p4 (IIRout1_p4 ), - .IIRout_p5 (IIRout1_p5 ), - .IIRout_p6 (IIRout1_p6 ), - .IIRout_p7 (IIRout1_p7 ) + .IIRout_p0 (IIRout_p0[1] ), + .IIRout_p1 (IIRout_p1[1] ), + .IIRout_p2 (IIRout_p2[1] ), + .IIRout_p3 (IIRout_p3[1] ), + .IIRout_p4 (IIRout_p4[1] ), + .IIRout_p5 (IIRout_p5[1] ), + .IIRout_p6 (IIRout_p6[1] ), + .IIRout_p7 (IIRout_p7[1] ) ); -wire signed [15:0] IIRout2_p0; -wire signed [15:0] IIRout2_p1; -wire signed [15:0] IIRout2_p2; -wire signed [15:0] IIRout2_p3; -wire signed [15:0] IIRout2_p4; -wire signed [15:0] IIRout2_p5; -wire signed [15:0] IIRout2_p6; -wire signed [15:0] IIRout2_p7; + IIR_top inst_iir_top_2 ( .clk (clk ), .rstn (rstn ), @@ -321,8 +473,17 @@ IIR_top inst_iir_top_2 ( .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1]), + .IIRin_p1_r4 (IIRin_p1_r[3]), + .IIRin_p2_r6 (IIRin_p2_r[5]), + .IIRin_p3_r8 (IIRin_p3_r[7]), + .IIRin_p4_r10 (IIRin_p4_r[9]), + .IIRin_p5_r12 (IIRin_p5_r[11]), + .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re2 ), .a_im (a_im2 ), + .b_re (b_re2 ), + .b_im (b_im2 ), .ab_re (ab_re2 ), .ab_im (ab_im2 ), .abb_re (abb_re2 ), @@ -339,23 +500,16 @@ IIR_top inst_iir_top_2 ( .ab_pow7_im (ab_pow7_im2 ), .b_pow8_re (b_pow8_re2 ), .b_pow8_im (b_pow8_im2 ), - .IIRout_p0 (IIRout2_p0 ), - .IIRout_p1 (IIRout2_p1 ), - .IIRout_p2 (IIRout2_p2 ), - .IIRout_p3 (IIRout2_p3 ), - .IIRout_p4 (IIRout2_p4 ), - .IIRout_p5 (IIRout2_p5 ), - .IIRout_p6 (IIRout2_p6 ), - .IIRout_p7 (IIRout2_p7 ) + .IIRout_p0 (IIRout_p0[2] ), + .IIRout_p1 (IIRout_p1[2] ), + .IIRout_p2 (IIRout_p2[2] ), + .IIRout_p3 (IIRout_p3[2] ), + .IIRout_p4 (IIRout_p4[2] ), + .IIRout_p5 (IIRout_p5[2] ), + .IIRout_p6 (IIRout_p6[2] ), + .IIRout_p7 (IIRout_p7[2] ) ); -wire signed [15:0] IIRout3_p0; -wire signed [15:0] IIRout3_p1; -wire signed [15:0] IIRout3_p2; -wire signed [15:0] IIRout3_p3; -wire signed [15:0] IIRout3_p4; -wire signed [15:0] IIRout3_p5; -wire signed [15:0] IIRout3_p6; -wire signed [15:0] IIRout3_p7; + IIR_top inst_iir_top_3 ( .clk (clk ), .rstn (rstn ), @@ -368,8 +522,17 @@ IIR_top inst_iir_top_3 ( .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1]), + .IIRin_p1_r4 (IIRin_p1_r[3]), + .IIRin_p2_r6 (IIRin_p2_r[5]), + .IIRin_p3_r8 (IIRin_p3_r[7]), + .IIRin_p4_r10 (IIRin_p4_r[9]), + .IIRin_p5_r12 (IIRin_p5_r[11]), + .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re3 ), .a_im (a_im3 ), + .b_re (b_re3 ), + .b_im (b_im3 ), .ab_re (ab_re3 ), .ab_im (ab_im3 ), .abb_re (abb_re3 ), @@ -386,23 +549,16 @@ IIR_top inst_iir_top_3 ( .ab_pow7_im (ab_pow7_im3 ), .b_pow8_re (b_pow8_re3 ), .b_pow8_im (b_pow8_im3 ), - .IIRout_p0 (IIRout3_p0 ), - .IIRout_p1 (IIRout3_p1 ), - .IIRout_p2 (IIRout3_p2 ), - .IIRout_p3 (IIRout3_p3 ), - .IIRout_p4 (IIRout3_p4 ), - .IIRout_p5 (IIRout3_p5 ), - .IIRout_p6 (IIRout3_p6 ), - .IIRout_p7 (IIRout3_p7 ) + .IIRout_p0 (IIRout_p0[3] ), + .IIRout_p1 (IIRout_p1[3] ), + .IIRout_p2 (IIRout_p2[3] ), + .IIRout_p3 (IIRout_p3[3] ), + .IIRout_p4 (IIRout_p4[3] ), + .IIRout_p5 (IIRout_p5[3] ), + .IIRout_p6 (IIRout_p6[3] ), + .IIRout_p7 (IIRout_p7[3] ) ); -wire signed [15:0] IIRout4_p0; -wire signed [15:0] IIRout4_p1; -wire signed [15:0] IIRout4_p2; -wire signed [15:0] IIRout4_p3; -wire signed [15:0] IIRout4_p4; -wire signed [15:0] IIRout4_p5; -wire signed [15:0] IIRout4_p6; -wire signed [15:0] IIRout4_p7; + IIR_top inst_iir_top_4 ( .clk (clk ), .rstn (rstn ), @@ -415,8 +571,17 @@ IIR_top inst_iir_top_4 ( .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1]), + .IIRin_p1_r4 (IIRin_p1_r[3]), + .IIRin_p2_r6 (IIRin_p2_r[5]), + .IIRin_p3_r8 (IIRin_p3_r[7]), + .IIRin_p4_r10 (IIRin_p4_r[9]), + .IIRin_p5_r12 (IIRin_p5_r[11]), + .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re4 ), .a_im (a_im4 ), + .b_re (b_re4 ), + .b_im (b_im4 ), .ab_re (ab_re4 ), .ab_im (ab_im4 ), .abb_re (abb_re4 ), @@ -433,23 +598,16 @@ IIR_top inst_iir_top_4 ( .ab_pow7_im (ab_pow7_im4 ), .b_pow8_re (b_pow8_re4 ), .b_pow8_im (b_pow8_im4 ), - .IIRout_p0 (IIRout4_p0 ), - .IIRout_p1 (IIRout4_p1 ), - .IIRout_p2 (IIRout4_p2 ), - .IIRout_p3 (IIRout4_p3 ), - .IIRout_p4 (IIRout4_p4 ), - .IIRout_p5 (IIRout4_p5 ), - .IIRout_p6 (IIRout4_p6 ), - .IIRout_p7 (IIRout4_p7 ) + .IIRout_p0 (IIRout_p0[4] ), + .IIRout_p1 (IIRout_p1[4] ), + .IIRout_p2 (IIRout_p2[4] ), + .IIRout_p3 (IIRout_p3[4] ), + .IIRout_p4 (IIRout_p4[4] ), + .IIRout_p5 (IIRout_p5[4] ), + .IIRout_p6 (IIRout_p6[4] ), + .IIRout_p7 (IIRout_p7[4] ) ); -wire signed [15:0] IIRout5_p0; -wire signed [15:0] IIRout5_p1; -wire signed [15:0] IIRout5_p2; -wire signed [15:0] IIRout5_p3; -wire signed [15:0] IIRout5_p4; -wire signed [15:0] IIRout5_p5; -wire signed [15:0] IIRout5_p6; -wire signed [15:0] IIRout5_p7; + IIR_top inst_iir_top_5 ( .clk (clk ), .rstn (rstn ), @@ -462,8 +620,17 @@ IIR_top inst_iir_top_5 ( .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1]), + .IIRin_p1_r4 (IIRin_p1_r[3]), + .IIRin_p2_r6 (IIRin_p2_r[5]), + .IIRin_p3_r8 (IIRin_p3_r[7]), + .IIRin_p4_r10 (IIRin_p4_r[9]), + .IIRin_p5_r12 (IIRin_p5_r[11]), + .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re5 ), .a_im (a_im5 ), + .b_re (b_re5 ), + .b_im (b_im5 ), .ab_re (ab_re5 ), .ab_im (ab_im5 ), .abb_re (abb_re5 ), @@ -480,56 +647,99 @@ IIR_top inst_iir_top_5 ( .ab_pow7_im (ab_pow7_im5 ), .b_pow8_re (b_pow8_re5 ), .b_pow8_im (b_pow8_im5 ), - .IIRout_p0 (IIRout5_p0 ), - .IIRout_p1 (IIRout5_p1 ), - .IIRout_p2 (IIRout5_p2 ), - .IIRout_p3 (IIRout5_p3 ), - .IIRout_p4 (IIRout5_p4 ), - .IIRout_p5 (IIRout5_p5 ), - .IIRout_p6 (IIRout5_p6 ), - .IIRout_p7 (IIRout5_p7 ) + .IIRout_p0 (IIRout_p0[5] ), + .IIRout_p1 (IIRout_p1[5] ), + .IIRout_p2 (IIRout_p2[5] ), + .IIRout_p3 (IIRout_p3[5] ), + .IIRout_p4 (IIRout_p4[5] ), + .IIRout_p5 (IIRout_p5[5] ), + .IIRout_p6 (IIRout_p6[5] ), + .IIRout_p7 (IIRout_p7[5] ) ); -reg signed [15:0] din_p0_r6; -reg signed [15:0] din_p1_r6; -reg signed [15:0] din_p2_r6; -reg signed [15:0] din_p3_r6; -reg signed [15:0] din_p4_r6; -reg signed [15:0] din_p5_r6; -reg signed [15:0] din_p6_r6; -reg signed [15:0] din_p7_r6; -syncer #(16, 12) sync_din_p0_syncer (clk, rstn, din_p0, din_p0_r6); -syncer #(16, 12) sync_din_p1_syncer (clk, rstn, din_p1, din_p1_r6); -syncer #(16, 12) sync_din_p2_syncer (clk, rstn, din_p2, din_p2_r6); -syncer #(16, 12) sync_din_p3_syncer (clk, rstn, din_p3, din_p3_r6); -syncer #(16, 12) sync_din_p4_syncer (clk, rstn, din_p4, din_p4_r6); -syncer #(16, 12) sync_din_p5_syncer (clk, rstn, din_p5, din_p5_r6); -syncer #(16, 12) sync_din_p6_syncer (clk, rstn, din_p6, din_p6_r6); -syncer #(16, 12) sync_din_p7_syncer (clk, rstn, din_p7, din_p7_r6); +assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] +IIRout_p0[2] +IIRout_p0[3] +IIRout_p0[4] +IIRout_p0[5]; +assign sum_IIRout_p1 = IIRout_p1[0] + IIRout_p1[1] +IIRout_p1[2] +IIRout_p1[3] +IIRout_p1[4] +IIRout_p1[5]; +assign sum_IIRout_p2 = IIRout_p2[0] + IIRout_p2[1] +IIRout_p2[2] +IIRout_p2[3] +IIRout_p2[4] +IIRout_p2[5]; +assign sum_IIRout_p3 = IIRout_p3[0] + IIRout_p3[1] +IIRout_p3[2] +IIRout_p3[3] +IIRout_p3[4] +IIRout_p3[5]; +assign sum_IIRout_p4 = IIRout_p4[0] + IIRout_p4[1] +IIRout_p4[2] +IIRout_p4[3] +IIRout_p4[4] +IIRout_p4[5]; +assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] +IIRout_p5[2] +IIRout_p5[3] +IIRout_p5[4] +IIRout_p5[5]; +assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] +IIRout_p6[2] +IIRout_p6[3] +IIRout_p6[4] +IIRout_p6[5]; +assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] +IIRout_p7[2] +IIRout_p7[3] +IIRout_p7[4] +IIRout_p7[5]; -wire signed [18:0] dout_p0_r0; -wire signed [18:0] dout_p1_r0; -wire signed [18:0] dout_p2_r0; -wire signed [18:0] dout_p3_r0; -wire signed [18:0] dout_p4_r0; -wire signed [18:0] dout_p5_r0; -wire signed [18:0] dout_p6_r0; -wire signed [18:0] dout_p7_r0; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (i = 0; i < 2; i = i + 1) begin + sum_IIRout_p6_r[i] <= 'h0; + end + for (i = 0; i < 4; i = i + 1) begin + sum_IIRout_p5_r[i] <= 'h0; + end + for (i = 0; i < 6; i = i + 1) begin + sum_IIRout_p4_r[i] <= 'h0; + end + for (i = 0; i < 8; i = i + 1) begin + sum_IIRout_p3_r[i] <= 'h0; + end + for (i = 0; i <10; i = i + 1) begin + sum_IIRout_p2_r[i] <= 'h0; + end + for (i = 0; i <12; i = i + 1) begin + sum_IIRout_p1_r[i] <= 'h0; + end + for (i = 0; i <13; i = i + 1) begin + sum_IIRout_p0_r[i] <= 'h0; + end + end + else if (en) begin + sum_IIRout_p6_r[0] <= sum_IIRout_p6; + sum_IIRout_p5_r[0] <= sum_IIRout_p5; + sum_IIRout_p4_r[0] <= sum_IIRout_p4; + sum_IIRout_p3_r[0] <= sum_IIRout_p3; + sum_IIRout_p2_r[0] <= sum_IIRout_p2; + sum_IIRout_p1_r[0] <= sum_IIRout_p1; + sum_IIRout_p0_r[0] <= sum_IIRout_p0; + for (i = 0; i < 1; i = i + 1) begin + sum_IIRout_p6_r[i+1] <= sum_IIRout_p6_r[i]; + end + for (i = 0; i < 3; i = i + 1) begin + sum_IIRout_p5_r[i+1] <= sum_IIRout_p5_r[i]; + end + for (i = 0; i < 5; i = i + 1) begin + sum_IIRout_p4_r[i+1] <= sum_IIRout_p4_r[i]; + end + for (i = 0; i < 7; i = i + 1) begin + sum_IIRout_p3_r[i+1] <= sum_IIRout_p3_r[i]; + end + for (i = 0; i < 9; i = i + 1) begin + sum_IIRout_p2_r[i+1] <= sum_IIRout_p2_r[i]; + end + for (i = 0; i <11; i = i + 1) begin + sum_IIRout_p1_r[i+1] <= sum_IIRout_p1_r[i]; + end + for (i = 0; i <12; i = i + 1) begin + sum_IIRout_p0_r[i+1] <= sum_IIRout_p0_r[i]; + end + end +end -assign dout_p0_r0 = din_p0_r6 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0; -assign dout_p1_r0 = din_p1_r6 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1; -assign dout_p2_r0 = din_p2_r6 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2; -assign dout_p3_r0 = din_p3_r6 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3; -assign dout_p4_r0 = din_p4_r6 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4; -assign dout_p5_r0 = din_p5_r6 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5; -assign dout_p6_r0 = din_p6_r6 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6; -assign dout_p7_r0 = din_p7_r6 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7; +assign dout_p0_r0 = din_p0_r[15] + sum_IIRout_p1_r[11]; // y(8n-119) +assign dout_p1_r0 = din_p1_r[15] + sum_IIRout_p2_r[9]; // y(8n-118) +assign dout_p2_r0 = din_p2_r[15] + sum_IIRout_p3_r[7]; // y(8n-117) +assign dout_p3_r0 = din_p3_r[15] + sum_IIRout_p4_r[5]; // y(8n-116) +assign dout_p4_r0 = din_p4_r[15] + sum_IIRout_p5_r[3]; // y(8n-115) +assign dout_p5_r0 = din_p5_r[15] + sum_IIRout_p6_r[1]; // y(8n-114) +assign dout_p6_r0 = din_p6_r[15] + sum_IIRout_p7; // y(8n-113) +assign dout_p7_r0 = din_p7_r[15] + sum_IIRout_p0_r[12]; // y(8n-112) -reg signed [18:0] dout_p0_r1; -reg signed [15:0] dout_p [7:0]; -wire signed [18:0] dout_p_r0 [0:7]; + + + + + +reg signed [15:0] dout_p [7:0]; +wire signed [18:0] dout_p_r0 [0:7]; assign dout_p_r0[0] = dout_p0_r0; assign dout_p_r0[1] = dout_p1_r0; assign dout_p_r0[2] = dout_p2_r0; @@ -539,24 +749,12 @@ assign dout_p_r0[5] = dout_p5_r0; assign dout_p_r0[6] = dout_p6_r0; assign dout_p_r0[7] = dout_p7_r0; -integer i; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (i = 0; i < 8; i = i + 1) begin - dout_p[i] <= 'h0; - end - end - else if (en) begin - for (i = 0; i < 8; i = i + 1) begin - if (dout_p_r0[i][16:15] == 2'b01) - dout_p[i] <= 16'd32767; - else if (dout_p_r0[i][16:15] == 2'b10) - dout_p[i] <= -16'd32768; - else - dout_p[i] <= dout_p_r0[i][15:0]; - end +genvar j; +generate + for (j = 0; j < 8; j = j + 1) begin: trunc + trunc #(19,15,0) round_u (clk, rstn, en, dout_p_r0[j], dout_p[j]); end -end +endgenerate assign dout_p0 = dout_p[0]; assign dout_p1 = dout_p[1]; @@ -567,25 +765,14 @@ assign dout_p5 = dout_p[5]; assign dout_p6 = dout_p[6]; assign dout_p7 = dout_p[7]; -always @(posedge clk or negedge rstn) - if (!rstn) - begin - dout_p0_r1 <= 16'd0; - end - else if(en) - begin - dout_p0_r1 <= dout_p0_r0; - end - else - begin - dout_p0_r1 <= dout_p0_r1; - end -reg signed [18:0] dout_p0_r2; -reg signed [18:0] dout_p0_r3; -reg signed [18:0] dout_p0_r4; -reg signed [18:0] dout_p0_r5; -reg signed [18:0] dout_p0_r6; + +// +reg signed [15:0] dout_p0_r2; +reg signed [15:0] dout_p0_r3; +reg signed [15:0] dout_p0_r4; +reg signed [15:0] dout_p0_r5; +reg signed [15:0] dout_p0_r6; always @(posedge clk or negedge rstn) if (!rstn) @@ -598,7 +785,7 @@ always @(posedge clk or negedge rstn) end else if(en) begin - dout_p0_r2 <= dout_p0_r1; + dout_p0_r2 <= dout_p[0]; dout_p0_r3 <= dout_p0_r2; dout_p0_r4 <= dout_p0_r3; dout_p0_r5 <= dout_p0_r4; @@ -613,11 +800,21 @@ always @(posedge clk or negedge rstn) dout_p0_r6 <= dout_p0_r6; end -reg vldo_diff_r7; -reg vldo_diff_r8; -syncer #(1, 13) sync_diff7_syncer (clk, rstn, vldo_diff, vldo_diff_r7); -syncer #(1, 14) sync_diff8_syncer (clk, rstn, vldo_diff, vldo_diff_r8); - +reg [18:0] vldo_diff_r; +always @(posedge clk or negedge rstn)begin + if(rstn==1'b0)begin + vldo_diff_r <= 19'b0; + end + else if(en) begin + vldo_diff_r[0] <= vldo_diff; + for(i=0; i<18; i=i+1) begin + vldo_diff_r[i+1] <= vldo_diff_r[i]; + end + end + else begin + vldo_diff_r <= vldo_diff_r; + end +end wire vldo_r0_h; wire vldo_r0_l; reg vldo_r0; @@ -632,8 +829,8 @@ always @(posedge clk or negedge rstn)begin vldo_r0 <= 0; end end -assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); -assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ; +assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p[0] == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); +assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ; assign vldo = vldo_r0; endmodule diff --git a/rtl/z_dsp/Trunc.v b/rtl/z_dsp/Trunc.v new file mode 100644 index 0000000..dd92f70 --- /dev/null +++ b/rtl/z_dsp/Trunc.v @@ -0,0 +1,55 @@ +module trunc #( + parameter integer diw = 8 +//,parameter integer dow = msb - (lsb -1) +,parameter integer msb = 7 +,parameter integer lsb = 1 +) +( + input clk +,input rstn +,input en +,input signed [diw - 1 :0] din +,output signed [msb - lsb:0] dout +); + + +reg signed [msb - lsb : 0] d_tmp; + +generate + if(lsb==0) begin + always @(posedge clk or negedge rstn) begin + if (!rstn) begin + d_tmp <= 'h0; + end + else if(en) begin + if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) + d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; + else + d_tmp <= din[msb:lsb]; + end + else begin + d_tmp <= d_tmp; + end + end + end + else begin + always @(posedge clk or negedge rstn) begin + if (!rstn) begin + d_tmp <= 'h0; + end + else if(en) begin + if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) + d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; + else + d_tmp <= din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]}; + end + else begin + d_tmp <= d_tmp; + end + end + end +endgenerate + +assign dout = d_tmp; + +endmodule diff --git a/rtl/z_dsp/diff_p.v b/rtl/z_dsp/diff_p.v index 0aeca77..b21aea1 100644 --- a/rtl/z_dsp/diff_p.v +++ b/rtl/z_dsp/diff_p.v @@ -1,4 +1,3 @@ - //+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- @@ -35,14 +34,14 @@ module diff_p ( - input rstn -,input clk -,input en -,input vldi -,input signed [15:0] din0 -,input signed [15:0] din1 -,input signed [15:0] din2 -,input signed [15:0] din3 + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 ,output vldo ,output signed [15:0] dout_p0 ,output signed [15:0] dout_p1 @@ -63,154 +62,89 @@ module diff_p ); -wire signed [15:0] din_p0_r0; -wire signed [15:0] din_p1_r0; -wire signed [15:0] din_p2_r0; -wire signed [15:0] din_p3_r0; -wire signed [15:0] din_p4_r0; -wire signed [15:0] din_p5_r0; -wire signed [15:0] din_p6_r0; -wire signed [15:0] din_p7_r0; -s2p_2 inst1_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din0), - .en (vldi), - .dout0 (din_p0_r0), - .dout1 (din_p4_r0) - ,.vldo( vldo) - ); -s2p_2 inst2_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din1), - .en (vldi), - .dout0 (din_p1_r0), - .dout1 (din_p5_r0) - ,.vldo( ) - ); -s2p_2 inst3_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din2), - .en (vldi), - .dout0 (din_p2_r0), - .dout1 (din_p6_r0) - ,.vldo( ) - ); -s2p_2 inst4_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din3), - .en (vldi), - .dout0 (din_p3_r0), - .dout1 (din_p7_r0) - ,.vldo( ) - ); +wire [15:0] din_wire [0:3]; + +assign din_wire[0] = din0; +assign din_wire[1] = din1; +assign din_wire[2] = din2; +assign din_wire[3] = din3; -reg signed [15:0] din_p0_r1; -reg signed [15:0] din_p1_r1; -reg signed [15:0] din_p2_r1; -reg signed [15:0] din_p3_r1; -reg signed [15:0] din_p4_r1; -reg signed [15:0] din_p5_r1; -reg signed [15:0] din_p6_r1; -reg signed [15:0] din_p7_r1; +wire [3:0] vldo_temp; +wire signed [15:0] dinp_r0 [7:0]; +genvar i; +generate + for (i = 0; i < 4; i = i + 1) begin: s2p_inst + s2p_2 inst_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din_wire[i]), + .en (vldi), + .dout0 (dinp_r0[i]), + .dout1 (dinp_r0[i+4]), + .vldo (vldo_temp[i]) + ); + end +endgenerate +assign vldo = vldo_temp[0]; -always @(posedge clk or negedge rstn) - if (!rstn) - begin - din_p7_r1 <= 'h0; - end - else if(en) - begin - din_p7_r1 <= din_p7_r0; - end - else - begin - din_p7_r1 <= din_p7_r1; - end - -assign dout_p0 = din_p0_r0; -assign dout_p1 = din_p1_r0; -assign dout_p2 = din_p2_r0; -assign dout_p3 = din_p3_r0; -assign dout_p4 = din_p4_r0; -assign dout_p5 = din_p5_r0; -assign dout_p6 = din_p6_r0; -assign dout_p7 = din_p7_r0; - -//wire signed [15:0] diff_p0_r0; -//wire signed [15:0] diff_p1_r0; -//wire signed [15:0] diff_p2_r0; -//wire signed [15:0] diff_p3_r0; -//wire signed [15:0] diff_p4_r0; -//wire signed [15:0] diff_p5_r0; -//wire signed [15:0] diff_p6_r0; -//wire signed [15:0] diff_p7_r0; -// -//assign diff_p0_r0 = din_p0_r0 - din_p7_r1; -//assign diff_p1_r0 = din_p1_r0 - din_p0_r0; -//assign diff_p2_r0 = din_p2_r0 - din_p1_r0; -//assign diff_p3_r0 = din_p3_r0 - din_p2_r0; -//assign diff_p4_r0 = din_p4_r0 - din_p3_r0; -//assign diff_p5_r0 = din_p5_r0 - din_p4_r0; -//assign diff_p6_r0 = din_p6_r0 - din_p5_r0; -//assign diff_p7_r0 = din_p7_r0 - din_p6_r0; - -reg signed [15:0] diff_p0_r1; -reg signed [15:0] diff_p1_r1; -reg signed [15:0] diff_p2_r1; -reg signed [15:0] diff_p3_r1; -reg signed [15:0] diff_p4_r1; -reg signed [15:0] diff_p5_r1; -reg signed [15:0] diff_p6_r1; -reg signed [15:0] diff_p7_r1; - -always @(posedge clk or negedge rstn)begin -if(rstn==1'b0)begin - diff_p0_r1 <= 0; - diff_p1_r1 <= 0; - diff_p2_r1 <= 0; - diff_p3_r1 <= 0; - diff_p4_r1 <= 0; - diff_p5_r1 <= 0; - diff_p6_r1 <= 0; - diff_p7_r1 <= 0; - -end -else if(en)begin - diff_p0_r1 <= din_p0_r0 - din_p7_r1; - diff_p1_r1 <= din_p1_r0 - din_p0_r0; - diff_p2_r1 <= din_p2_r0 - din_p1_r0; - diff_p3_r1 <= din_p3_r0 - din_p2_r0; - diff_p4_r1 <= din_p4_r0 - din_p3_r0; - diff_p5_r1 <= din_p5_r0 - din_p4_r0; - diff_p6_r1 <= din_p6_r0 - din_p5_r0; - diff_p7_r1 <= din_p7_r0 - din_p6_r0; -end -else begin - diff_p0_r1 <= diff_p0_r1; - diff_p1_r1 <= diff_p1_r1; - diff_p2_r1 <= diff_p2_r1; - diff_p3_r1 <= diff_p3_r1; - diff_p4_r1 <= diff_p4_r1; - diff_p5_r1 <= diff_p5_r1; - diff_p6_r1 <= diff_p6_r1; - diff_p7_r1 <= diff_p7_r1; -end +reg signed [15:0] dinp_r1 [0:7]; +integer j; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (j = 0; j < 8; j = j + 1) begin + dinp_r1[j] <= 'h0; + end + end + else if (en) begin + for (j = 0; j < 8; j = j + 1) begin + dinp_r1[j] <= dinp_r0[j]; + end + end end -assign diff_p0 = diff_p0_r1; -assign diff_p1 = diff_p1_r1; -assign diff_p2 = diff_p2_r1; -assign diff_p3 = diff_p3_r1; -assign diff_p4 = diff_p4_r1; -assign diff_p5 = diff_p5_r1; -assign diff_p6 = diff_p6_r1; -assign diff_p7 = diff_p7_r1; +wire signed [15:0] diffp_r0 [0:7]; +generate + for (i = 0; i < 8; i = i + 1) begin: diff_assign + if (i == 0) + assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7]; + else + assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1]; + end +endgenerate + +assign dout_p0 = dinp_r1[0]; +assign dout_p1 = dinp_r1[1]; +assign dout_p2 = dinp_r1[2]; +assign dout_p3 = dinp_r1[3]; +assign dout_p4 = dinp_r1[4]; +assign dout_p5 = dinp_r1[5]; +assign dout_p6 = dinp_r1[6]; +assign dout_p7 = dinp_r1[7]; + +reg signed [15:0] diffp_r1 [0:7]; +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (j = 0; j < 8; j = j + 1) begin + diffp_r1[j] <= 0; + end + end + else if (en) begin + for (j = 0; j < 8; j = j + 1) begin + diffp_r1[j] <= diffp_r0[j]; + end + end +end + +assign diff_p0 = diffp_r1[0]; +assign diff_p1 = diffp_r1[1]; +assign diff_p2 = diffp_r1[2]; +assign diff_p3 = diffp_r1[3]; +assign diff_p4 = diffp_r1[4]; +assign diff_p5 = diffp_r1[5]; +assign diff_p6 = diffp_r1[6]; +assign diff_p7 = diffp_r1[7]; endmodule diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v index 9504bf7..47f097d 100644 --- a/rtl/z_dsp/mult_C.v +++ b/rtl/z_dsp/mult_C.v @@ -98,14 +98,22 @@ wire signed [A_width+D_width:0] Im_tmp; assign Re_tmp = ac - bd; assign Im_tmp = ad + bc; -wire signed [A_width+C_width:0] Re_round; -wire signed [A_width+D_width:0] Im_round; +wire signed [A_width+C_width-frac_coef_width-2:0] Re_trunc; +wire signed [A_width+D_width-frac_coef_width-2:0] Im_trunc; -FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); -FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); +trunc #( + .diw (A_width+C_width+1 ) + ,.msb (A_width+C_width-2 ) + ,.lsb (frac_coef_width ) +) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); +trunc #( + .diw (A_width+D_width+1 ) + ,.msb (A_width+D_width-2 ) + ,.lsb (frac_coef_width ) +) u_round2 (clk, rstn, en, Re_tmp, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. -assign Re = Re_round[A_width+D_width-2:frac_coef_width]; -assign Im = Im_round[A_width+D_width-2:frac_coef_width]; +assign Re = Re_trunc; +assign Im = Im_trunc; endmodule diff --git a/rtl/z_dsp/mult_x.v b/rtl/z_dsp/mult_x.v index efdff64..a4ddbe1 100644 --- a/rtl/z_dsp/mult_x.v +++ b/rtl/z_dsp/mult_x.v @@ -71,7 +71,6 @@ DW02_mult #(A_width,C_width) inst_c1( .A (a ), .PRODUCT (ac ) ); - DW02_mult #(A_width,D_width) inst_c3( .A (a ), .B (d ), .TC (1'b1 ), @@ -84,14 +83,22 @@ wire signed [A_width+D_width:0] Im_tmp; assign Re_tmp = ac; assign Im_tmp = ad; -wire signed [A_width+C_width:0] Re_round; -wire signed [A_width+D_width:0] Im_round; +wire signed [A_width+C_width-frac_coef_width-2:0] Re_trunc; +wire signed [A_width+D_width-frac_coef_width-2:0] Im_trunc; -FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round); -FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round); +trunc #( + .diw (A_width+C_width+1 ) + ,.msb (A_width+C_width-2 ) + ,.lsb (frac_coef_width ) +) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); +trunc #( + .diw (A_width+D_width+1 ) + ,.msb (A_width+D_width-2 ) + ,.lsb (frac_coef_width ) +) u_round2 (clk, rstn, en, Re_tmp, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. -assign Re = Re_round[A_width+D_width-2:frac_coef_width]; -assign Im = Im_round[A_width+D_width-2:frac_coef_width]; +assign Re = Re_trunc; +assign Im = Im_trunc; endmodule diff --git a/rtl/z_dsp/rate_adapter.v b/rtl/z_dsp/rate_adapter.v deleted file mode 100644 index 05ad0e6..0000000 --- a/rtl/z_dsp/rate_adapter.v +++ /dev/null @@ -1,89 +0,0 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : Z_dsp.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- - -module rate_adapter -( - input rstn -,input clk -,input en -,input vldi -,input signed [15:0] din0 -,input signed [15:0] din1 -,input signed [15:0] din2 -,input signed [15:0] din3 -,input signed [15:0] din4 -,input signed [15:0] din5 -,input signed [15:0] din6 -,input signed [15:0] din7 -,output signed [15:0] dout0 -,output signed [15:0] dout1 -,output signed [15:0] dout2 -,output signed [15:0] dout3 -,output reg vldo - ); - - - -reg signed [15:0] doutf_0; -reg signed [15:0] doutf_1; -reg signed [15:0] doutf_2; -reg signed [15:0] doutf_3; - -always@(posedge clk or negedge rstn) - if(!rstn) begin - doutf_0 <= 0; - doutf_1 <= 0; - doutf_2 <= 0; - doutf_3 <= 0; - end - else if(!en) begin - doutf_0 <= din0; - doutf_1 <= din1; - doutf_2 <= din2; - doutf_3 <= din3; - end - else begin - doutf_0 <= din4; - doutf_1 <= din5; - doutf_2 <= din6; - doutf_3 <= din7; - end - -assign dout0 = doutf_0; -assign dout1 = doutf_1; -assign dout2 = doutf_2; -assign dout3 = doutf_3; - -syncer #(1, 1) sync_diff7_syncer (clk, rstn, vldi, vldo); - -endmodule diff --git a/rtl/z_dsp/sirv_gnrl_dffs.v b/rtl/z_dsp/sirv_gnrl_dffs.v deleted file mode 100644 index 09e8ba1..0000000 --- a/rtl/z_dsp/sirv_gnrl_dffs.v +++ /dev/null @@ -1,326 +0,0 @@ - /* - Copyright 2018-2020 Nuclei System Technology, Inc. - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - */ - - - -//===================================================================== -// -// Designer : Bob Hu -// -// Description: -// All of the general DFF and Latch modules -// -// ==================================================================== - -// - - -// -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is 1 -// -// =========================================================================== -`define DISABLE_SV_ASSERTION -`define dly #0.2 -module sirv_gnrl_dfflrs # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLRS_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b1}}; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is 0 -// -// =========================================================================== - -module sirv_gnrl_dfflr # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLR_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b0}}; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable and Reset -// Default reset value is input -// -// =========================================================================== - -module sirv_gnrl_dfflrd # ( - parameter DW = 32 -) ( - input [DW-1:0] init, - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFLR_PROC - if (rst_n == 1'b0) - qout_r <= init; - else if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule - -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Load-enable, no reset -// -// =========================================================================== - -module sirv_gnrl_dffl # ( - parameter DW = 32 -) ( - - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk -); - -reg [DW-1:0] qout_r; - -always @(posedge clk) -begin : DFFL_PROC - if (lden == 1'b1) - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -sirv_gnrl_xchecker # ( - .DW(1) -) sirv_gnrl_xchecker( - .i_dat(lden), - .clk (clk) -); -//synopsys translate_on -`endif//} -`endif//} - - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Reset, no load-enable -// Default reset value is 1 -// -// =========================================================================== - -module sirv_gnrl_dffrs # ( - parameter DW = 32 -) ( - - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFRS_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b1}}; - else - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -endmodule -// =========================================================================== -// -// Description: -// Verilog module sirv_gnrl DFF with Reset, no load-enable -// Default reset value is 0 -// -// =========================================================================== - -module sirv_gnrl_dffr # ( - parameter DW = 32 -) ( - - input [DW-1:0] dnxt, - output [DW-1:0] qout, - - input clk, - input rst_n -); - -reg [DW-1:0] qout_r; - -always @(posedge clk or negedge rst_n) -begin : DFFR_PROC - if (rst_n == 1'b0) - qout_r <= {DW{1'b0}}; - else - qout_r <= `dly dnxt; -end - -assign qout = qout_r; - -endmodule -// =========================================================================== -// -// Description: -// Verilog module for general latch -// -// =========================================================================== - -module sirv_gnrl_ltch # ( - parameter DW = 32 -) ( - - //input test_mode, - input lden, - input [DW-1:0] dnxt, - output [DW-1:0] qout -); - -reg [DW-1:0] qout_r; - -always @ * -begin : LTCH_PROC - if (lden == 1'b1) - qout_r <= dnxt; -end - -//assign qout = test_mode ? dnxt : qout_r; -assign qout = qout_r; - -`ifndef FPGA_SOURCE//{ -`ifndef DISABLE_SV_ASSERTION//{ -//synopsys translate_off -always_comb -begin - CHECK_THE_X_VALUE: - assert (lden !== 1'bx) - else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); -end - -//synopsys translate_on -`endif//} -`endif//} - - -endmodule diff --git a/rtl/z_dsp/syncer.v b/rtl/z_dsp/syncer.v deleted file mode 100644 index 6d4e0a2..0000000 --- a/rtl/z_dsp/syncer.v +++ /dev/null @@ -1,58 +0,0 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : syncer.v -// Department : -// Author : PWY -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.1 2024-03-13 PWY AWG dedicated register file -// 0.2 2024-05-13 PWY -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- - - -module syncer # ( - parameter width = 1 - ,parameter stage = 2 - ) - ( - input clk_d - ,input rstn_d - ,input [width-1:0] data_s - ,output [width-1:0] data_d -); - -generate - genvar i; - wire [width-1:0] data_temp[stage-1:0]; - sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d); - for(i=1;i files.f - -clean: - rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog diff --git a/sim/s2p_2/files.f b/sim/s2p_2/files.f deleted file mode 100644 index 7e37e57..0000000 --- a/sim/s2p_2/files.f +++ /dev/null @@ -1,2 +0,0 @@ -../../rtl/z_dsp/s2p_2.v -tb_s2p_2.v diff --git a/sim/s2p_2/tb_s2p_2.v b/sim/s2p_2/tb_s2p_2.v deleted file mode 100644 index ca93d1c..0000000 --- a/sim/s2p_2/tb_s2p_2.v +++ /dev/null @@ -1,130 +0,0 @@ - -`timescale 1ns/1ps - -module TB(); - -initial -begin - $fsdbDumpfile("TB.fsdb"); - $fsdbDumpvars(0, TB); -end - - - reg clk; - reg rst_n; - reg [15:0] din; - reg enable; - reg [21:0] cnt; - wire [15:0] dout0; - wire [15:0] dout1; - - - s2p_2 uut ( - .clk (clk), - .rst_n (rst_n), - .din (din), - .en (enable), - .dout0 (dout0), - .dout1 (dout1) - ); - -reg[15:0] din_r1; -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - din_r1 <= 0; - end - else begin - din_r1 <= din; - end -end - -wire signed [15:0] diff; -assign diff = din - din_r1; - -reg[15:0] dout1_r1; -reg[15:0] dout1_r2; -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - dout1_r1 <= 0; - dout1_r2 <= 0; - end - else begin - dout1_r1 <= dout1; - dout1_r2 <= dout1_r1; - - end -end - -wire signed [15:0] diff12; -wire signed [15:0] diff23; -assign diff12 = dout0 - dout1_r2; -assign diff23 = dout1 - dout0; - - initial begin - rst_n = 0; - enable = 0; - clk = 1'b0; - din = 16'h0000; - - - #20; - rst_n = 1; - - - #10; - - end - - - always #5 clk = ~clk; - - - always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - cnt <= 22'd0; - end else begin - cnt <= cnt + 22'd1; - end - end - - -reg [15:0] enable_cnt; - -always @(posedge clk or negedge rst_n) begin - if (rst_n == 1'b0) begin - enable <= 0; - din <= 16'd0; - enable_cnt <= 0; - end else begin - - if (cnt < 1000) begin - if (enable_cnt == 0) begin - if ($urandom % 2 == 0) begin - enable <= 1; - enable_cnt <= $urandom % 10 + 5; - din <= $urandom; - end else begin - enable <= 0; - din <= 16'd0; - end - end else begin - - enable <= 1; - enable_cnt <= enable_cnt - 1; - din <= $urandom; - end - end else begin - enable <= 0; - din <= 16'd0; - end - end -end - - - initial begin - wait(cnt[11] == 1); - $finish; - end - - -endmodule diff --git a/sim/tb_CoefGen/Makefile b/sim/tb_CoefGen/Makefile deleted file mode 100644 index 3869c30..0000000 --- a/sim/tb_CoefGen/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -ifdef seed - vcs_run_opts += +ntb_random_seed=${seed} -else - vcs_run_opts += +ntb_random_seed_automatic -endif - -VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log -SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta -all:comp run - -comp: - ${VCS} -f files.f - -run: - ${SIMV} - -dbg: - verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb & -file: - find ../ -name "*.*v" > files.f - -clean: - rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog - diff --git a/sim/tb_CoefGen/files.f b/sim/tb_CoefGen/files.f deleted file mode 100644 index fd1321e..0000000 --- a/sim/tb_CoefGen/files.f +++ /dev/null @@ -1,6 +0,0 @@ -../../rtl/z_dsp/CoefGen.v -../../rtl/z_dsp/FixRound.v -../../rtl/z_dsp/mult_C.v -../../rtl/model/DW02_mult.v -tb_CoefGen.v - diff --git a/sim/tb_CoefGen/tb_CoefGen.v b/sim/tb_CoefGen/tb_CoefGen.v deleted file mode 100644 index 057e6ea..0000000 --- a/sim/tb_CoefGen/tb_CoefGen.v +++ /dev/null @@ -1,162 +0,0 @@ - -`timescale 1 ns/1 ns - -module TB(); -initial -begin - $fsdbDumpfile("TB.fsdb"); - $fsdbDumpvars(0, TB); - $fsdbDumpMDA(); -end - - - -reg clk ; -reg en; -reg [5:0] vldi; -reg rst_n; - - -reg signed [31:0] a_re [5:0]; -reg signed [31:0] a_im [5:0]; -reg signed [31:0] b_re [5:0]; -reg signed [31:0] b_im [5:0]; - - -wire signed [31:0] ao_re [5:0]; -wire signed [31:0] ao_im [5:0]; -wire signed [31:0] ab_re [5:0]; -wire signed [31:0] ab_im [5:0]; -wire signed [31:0] abb_re [5:0]; -wire signed [31:0] abb_im [5:0]; -wire signed [31:0] ab_pow3_re [5:0]; -wire signed [31:0] ab_pow3_im [5:0]; -wire signed [31:0] ab_pow4_re [5:0]; -wire signed [31:0] ab_pow4_im [5:0]; -wire signed [31:0] ab_pow5_re [5:0]; -wire signed [31:0] ab_pow5_im [5:0]; -wire signed [31:0] ab_pow6_re [5:0]; -wire signed [31:0] ab_pow6_im [5:0]; -wire signed [31:0] ab_pow7_re [5:0]; -wire signed [31:0] ab_pow7_im [5:0]; -wire signed [31:0] b_pow8_re [5:0]; -wire signed [31:0] b_pow8_im [5:0]; - - -parameter CYCLE = 20; - - -parameter RST_TIME = 3 ; - - -CoefGen uut( - .clk (clk ), - .rstn (rst_n ), - .vldi (vldi ), - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .ao_re (ao_re ), - .ao_im (ao_im ), - .ab_re (ab_re ), - .ab_im (ab_im ), - .abb_re (abb_re ), - .abb_im (abb_im ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), - .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), - .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ) - ); - - - -initial begin - clk = 0; - forever - #(CYCLE/2) - clk=~clk; -end -reg [15:0] st1; -reg [15:0] st2; -reg [15:0] st3; -reg [15:0] st4; - -initial begin - rst_n = 0; - vldi <= 0; - st1 = 100; - st2 = 101; - st3 = 110; - st4 = 111; - repeat(3) @(posedge clk); - vldi[0] <= 1; - rst_n = 1; - a_re[0] <= 55007237; - a_im[0] <= 0; - b_re[0] <= 2143083068; - b_im[0] <= 0; - @(posedge clk); - vldi[0] <= 0; - a_re[0] <= 0; - a_im[0] <= 0; - b_re[0] <= 0; - b_im[0] <= 0; - repeat(8) @(posedge clk); - vldi[1] <= 1; - rst_n = 1; - a_re[1] <= 32690030; - a_im[1] <= 0; - b_re[1] <= 2145807236; - b_im[1] <= 0; - @(posedge clk); - vldi[1] <= 0; - a_re[1] <= 0; - a_im[1] <= 0; - b_re[1] <= 0; - b_im[1] <= 0; - repeat(8) @(posedge clk); - vldi[2] <= 1; - rst_n = 1; - a_re[2] <= 429516; - a_im[2] <= 0; - b_re[2] <= 2146812530; - b_im[2] <= 0; - @(posedge clk); - vldi[2] <= 0; - a_re[2] <= 0; - a_im[2] <= 0; - b_re[2] <= 0; - b_im[2] <= 0; - -end - - -reg [21:0] cnt; -always@(posedge clk or negedge rst_n) - if(!rst_n) begin - cnt <= 22'd0; - end - else begin - cnt <= cnt + 22'd1; - end - -initial -begin - wait(cnt[16]==1'b1) - $finish(0); -end - - - - -endmodule - diff --git a/sim/TailCorr_en/tb_TailCorr_en.v b/sim/tb_TailCorr_en.v similarity index 67% rename from sim/TailCorr_en/tb_TailCorr_en.v rename to sim/tb_TailCorr_en.v index 3077aab..2323ffd 100644 --- a/sim/TailCorr_en/tb_TailCorr_en.v +++ b/sim/tb_TailCorr_en.v @@ -48,6 +48,8 @@ end reg rstn; reg [31:0] a_re0; reg [31:0] a_im0; +reg [31:0] b_re0; +reg [31:0] b_im0; reg [31:0] ab_re0; reg [31:0] ab_im0; reg [31:0] abb_re0; @@ -66,6 +68,8 @@ reg [31:0] b_pow8_re0; reg [31:0] b_pow8_im0; reg [31:0] a_re1; reg [31:0] a_im1; +reg [31:0] b_re1; +reg [31:0] b_im1; reg [31:0] ab_re1; reg [31:0] ab_im1; reg [31:0] abb_re1; @@ -84,6 +88,8 @@ reg [31:0] b_pow8_re1; reg [31:0] b_pow8_im1; reg [31:0] a_re2; reg [31:0] a_im2; +reg [31:0] b_re2; +reg [31:0] b_im2; reg [31:0] ab_re2; reg [31:0] ab_im2; reg [31:0] abb_re2; @@ -102,6 +108,8 @@ reg [31:0] b_pow8_re2; reg [31:0] b_pow8_im2; reg [31:0] a_re3; reg [31:0] a_im3; +reg [31:0] b_re3; +reg [31:0] b_im3; reg [31:0] ab_re3; reg [31:0] ab_im3; reg [31:0] abb_re3; @@ -120,6 +128,8 @@ reg [31:0] b_pow8_re3; reg [31:0] b_pow8_im3; reg [31:0] a_re4; reg [31:0] a_im4; +reg [31:0] b_re4; +reg [31:0] b_im4; reg [31:0] ab_re4; reg [31:0] ab_im4; reg [31:0] abb_re4; @@ -138,6 +148,8 @@ reg [31:0] b_pow8_re4; reg [31:0] b_pow8_im4; reg [31:0] a_re5; reg [31:0] a_im5; +reg [31:0] b_re5; +reg [31:0] b_im5; reg [31:0] ab_re5; reg [31:0] ab_im5; reg [31:0] abb_re5; @@ -180,6 +192,18 @@ begin a_im3 = 32'd0; a_im4 = 32'd0; a_im5 = 32'd0; + b_re0 = 32'd2143083068; + b_re1 = 32'd2145807236; + b_re2 = 32'd2146812530; + b_re3 = 32'd2147483648; + b_re4 = 32'd0; + b_re5 = 32'd0; + b_im0 = 32'd0; + b_im1 = 32'd0; + b_im2 = 32'd0; + b_im3 = 32'd0; + b_im4 = 32'd0; + b_im5 = 32'd0; ab_re0 = 32'd54894517; ab_re1 = 32'd32664510; ab_re2 = 32'd429381 ; @@ -268,7 +292,7 @@ begin b_pow8_re0 = 32'd2112530470; b_pow8_re1 = 32'd2134108939; b_pow8_re2 = 32'd2142120573; - b_pow8_re3 = 32'd0; + b_pow8_re3 = 32'd2147483648; b_pow8_re4 = 32'd0; b_pow8_re5 = 32'd0; b_pow8_im0 = 32'd0; @@ -412,6 +436,7 @@ assign dac_mode_sel = 2'b00; wire tc_bypass; wire vldo; +wire vldo_ref; assign tc_bypass = 1'b0; @@ -425,6 +450,7 @@ always @(posedge clk or negedge rstn)begin end end wire signed [15:0] dout_p[7:0]; +wire signed [15:0] dout_ref_p[7:0]; TailCorr_top inst_TailCorr_top @@ -441,6 +467,8 @@ TailCorr_top inst_TailCorr_top .din3 (iir_in[3]), .a_re0 (a_re0), .a_im0 (a_im0), + .b_re0 (b_re0), + .b_im0 (b_im0), .ab_re0 (ab_re0), .ab_im0 (ab_im0), .abb_re0 (abb_re0), @@ -459,6 +487,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im0 (b_pow8_im0), .a_re1 (a_re1), .a_im1 (a_im1), + .b_re1 (b_re1), + .b_im1 (b_im1), .ab_re1 (ab_re1), .ab_im1 (ab_im1), .abb_re1 (abb_re1), @@ -477,6 +507,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im1 (b_pow8_im1), .a_re2 (a_re2), .a_im2 (a_im2), + .b_re2 (b_re2), + .b_im2 (b_im2), .ab_re2 (ab_re2), .ab_im2 (ab_im2), .abb_re2 (abb_re2), @@ -495,6 +527,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im2 (b_pow8_im2), .a_re3 (a_re3), .a_im3 (a_im3), + .b_re3 (b_re3), + .b_im3 (b_im3), .ab_re3 (ab_re3), .ab_im3 (ab_im3), .abb_re3 (abb_re3), @@ -513,6 +547,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im3 (b_pow8_im3), .a_re4 (a_re4), .a_im4 (a_im4), + .b_re4 (b_re4), + .b_im4 (b_im4), .ab_re4 (ab_re4), .ab_im4 (ab_im4), .abb_re4 (abb_re4), @@ -531,6 +567,8 @@ TailCorr_top inst_TailCorr_top .b_pow8_im4 (b_pow8_im4), .a_re5 (a_re5), .a_im5 (a_im5), + .b_re5 (b_re5), + .b_im5 (b_im5), .ab_re5 (ab_re5), .ab_im5 (ab_im5), .abb_re5 (abb_re5), @@ -560,6 +598,151 @@ TailCorr_top inst_TailCorr_top ); +TailCorr_top_ref refm_TailCorr_top + ( + .clk (clk ), + .en (en ), + .rstn (rstn ), + .vldi (vldi_matlab[0] ), +// .dac_mode_sel (dac_mode_sel ), +// .intp_mode (intp_mode ), + .din0 (iir_in[0]), + .din1 (iir_in[1]), + .din2 (iir_in[2]), + .din3 (iir_in[3]), + .a_re0 (a_re0), + .a_im0 (a_im0), + //.b_re0 (b_re0), + //.b_im0 (b_im0), + .ab_re0 (ab_re0), + .ab_im0 (ab_im0), + .abb_re0 (abb_re0), + .abb_im0 (abb_im0), + .ab_pow3_re0 (ab_pow3_re0), + .ab_pow3_im0 (ab_pow3_im0), + .ab_pow4_re0 (ab_pow4_re0), + .ab_pow4_im0 (ab_pow4_im0), + .ab_pow5_re0 (ab_pow5_re0), + .ab_pow5_im0 (ab_pow5_im0), + .ab_pow6_re0 (ab_pow6_re0), + .ab_pow6_im0 (ab_pow6_im0), + .ab_pow7_re0 (ab_pow7_re0), + .ab_pow7_im0 (ab_pow7_im0), + .b_pow8_re0 (b_pow8_re0), + .b_pow8_im0 (b_pow8_im0), + .a_re1 (a_re1), + .a_im1 (a_im1), + //.b_re1 (b_re1), + //.b_im1 (b_im1), + .ab_re1 (ab_re1), + .ab_im1 (ab_im1), + .abb_re1 (abb_re1), + .abb_im1 (abb_im1), + .ab_pow3_re1 (ab_pow3_re1), + .ab_pow3_im1 (ab_pow3_im1), + .ab_pow4_re1 (ab_pow4_re1), + .ab_pow4_im1 (ab_pow4_im1), + .ab_pow5_re1 (ab_pow5_re1), + .ab_pow5_im1 (ab_pow5_im1), + .ab_pow6_re1 (ab_pow6_re1), + .ab_pow6_im1 (ab_pow6_im1), + .ab_pow7_re1 (ab_pow7_re1), + .ab_pow7_im1 (ab_pow7_im1), + .b_pow8_re1 (b_pow8_re1), + .b_pow8_im1 (b_pow8_im1), + .a_re2 (a_re2), + .a_im2 (a_im2), + //.b_re2 (b_re2), + //.b_im2 (b_im2), + .ab_re2 (ab_re2), + .ab_im2 (ab_im2), + .abb_re2 (abb_re2), + .abb_im2 (abb_im2), + .ab_pow3_re2 (ab_pow3_re2), + .ab_pow3_im2 (ab_pow3_im2), + .ab_pow4_re2 (ab_pow4_re2), + .ab_pow4_im2 (ab_pow4_im2), + .ab_pow5_re2 (ab_pow5_re2), + .ab_pow5_im2 (ab_pow5_im2), + .ab_pow6_re2 (ab_pow6_re2), + .ab_pow6_im2 (ab_pow6_im2), + .ab_pow7_re2 (ab_pow7_re2), + .ab_pow7_im2 (ab_pow7_im2), + .b_pow8_re2 (b_pow8_re2), + .b_pow8_im2 (b_pow8_im2), + .a_re3 (a_re3), + .a_im3 (a_im3), + //.b_re3 (b_re3), + //.b_im3 (b_im3), + .ab_re3 (ab_re3), + .ab_im3 (ab_im3), + .abb_re3 (abb_re3), + .abb_im3 (abb_im3), + .ab_pow3_re3 (ab_pow3_re3), + .ab_pow3_im3 (ab_pow3_im3), + .ab_pow4_re3 (ab_pow4_re3), + .ab_pow4_im3 (ab_pow4_im3), + .ab_pow5_re3 (ab_pow5_re3), + .ab_pow5_im3 (ab_pow5_im3), + .ab_pow6_re3 (ab_pow6_re3), + .ab_pow6_im3 (ab_pow6_im3), + .ab_pow7_re3 (ab_pow7_re3), + .ab_pow7_im3 (ab_pow7_im3), + .b_pow8_re3 (b_pow8_re3), + .b_pow8_im3 (b_pow8_im3), + .a_re4 (a_re4), + .a_im4 (a_im4), + //.b_re4 (b_re4), + //.b_im4 (b_im4), + .ab_re4 (ab_re4), + .ab_im4 (ab_im4), + .abb_re4 (abb_re4), + .abb_im4 (abb_im4), + .ab_pow3_re4 (ab_pow3_re4), + .ab_pow3_im4 (ab_pow3_im4), + .ab_pow4_re4 (ab_pow4_re4), + .ab_pow4_im4 (ab_pow4_im4), + .ab_pow5_re4 (ab_pow5_re4), + .ab_pow5_im4 (ab_pow5_im4), + .ab_pow6_re4 (ab_pow6_re4), + .ab_pow6_im4 (ab_pow6_im4), + .ab_pow7_re4 (ab_pow7_re4), + .ab_pow7_im4 (ab_pow7_im4), + .b_pow8_re4 (b_pow8_re4), + .b_pow8_im4 (b_pow8_im4), + .a_re5 (a_re5), + .a_im5 (a_im5), + //.b_re5 (b_re5), + //.b_im5 (b_im5), + .ab_re5 (ab_re5), + .ab_im5 (ab_im5), + .abb_re5 (abb_re5), + .abb_im5 (abb_im5), + .ab_pow3_re5 (ab_pow3_re5), + .ab_pow3_im5 (ab_pow3_im5), + .ab_pow4_re5 (ab_pow4_re5), + .ab_pow4_im5 (ab_pow4_im5), + .ab_pow5_re5 (ab_pow5_re5), + .ab_pow5_im5 (ab_pow5_im5), + .ab_pow6_re5 (ab_pow6_re5), + .ab_pow6_im5 (ab_pow6_im5), + .ab_pow7_re5 (ab_pow7_re5), + .ab_pow7_im5 (ab_pow7_im5), + .b_pow8_re5 (b_pow8_re5), + .b_pow8_im5 (b_pow8_im5), + .dout_p0 (dout_ref_p[0] ), + .dout_p1 (dout_ref_p[1] ), + .dout_p2 (dout_ref_p[2] ), + .dout_p3 (dout_ref_p[3] ), + .dout_p4 (dout_ref_p[4] ), + .dout_p5 (dout_ref_p[5] ), + .dout_p6 (dout_ref_p[6] ), + .dout_p7 (dout_ref_p[7] ), + + .vldo (vldo_ref ) + + ); + integer signed In_fid[0:3]; integer signed dout_fid[0:7]; diff --git a/sim/z_dsp/Makefile b/sim/z_dsp/Makefile deleted file mode 100644 index 3869c30..0000000 --- a/sim/z_dsp/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -ifdef seed - vcs_run_opts += +ntb_random_seed=${seed} -else - vcs_run_opts += +ntb_random_seed_automatic -endif - -VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log -SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta -all:comp run - -comp: - ${VCS} -f files.f - -run: - ${SIMV} - -dbg: - verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb & -file: - find ../ -name "*.*v" > files.f - -clean: - rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog - diff --git a/sim/z_dsp/files.f b/sim/z_dsp/files.f deleted file mode 100644 index 943bbc0..0000000 --- a/sim/z_dsp/files.f +++ /dev/null @@ -1,16 +0,0 @@ -../../rtl/z_dsp/z_dsp.sv -../../rtl/z_dsp/TailCorr_top.v -../../rtl/z_dsp/IIR_top.v -../../rtl/z_dsp/rate_adapter.v -../../rtl/z_dsp/IIR_Filter_p8.v -../../rtl/z_dsp/CoefGen.sv -../../rtl/z_dsp/diff_p.v -../../rtl/z_dsp/s2p_2.v -../../rtl/z_dsp/FixRound.v -../../rtl/z_dsp/mult_C.v -../../rtl/z_dsp/mult_x.v -../../rtl/z_dsp/syncer.v -../../rtl/z_dsp/sirv_gnrl_dffs.v -../../rtl/model/DW02_mult.v -tb_z_dsp.v - diff --git a/sim/z_dsp/tb_z_dsp.v b/sim/z_dsp/tb_z_dsp.v deleted file mode 100644 index a2b6caf..0000000 --- a/sim/z_dsp/tb_z_dsp.v +++ /dev/null @@ -1,328 +0,0 @@ -`timescale 1 ns/1 ns -module TB(); -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : tb_TailCorr_en.v -// Department : HFNL -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 2025-03-03 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- - - -reg [1 :0] source_mode; - -initial -begin - $fsdbDumpfile("TB.fsdb"); - $fsdbDumpvars(0, TB); - $fsdbDumpMDA(); -// $srandom(417492050); - source_mode = 2'd3; //1 for rect;2 for random;3 from matlab -end - -reg rstn; - -reg [15:0] din_rect; -reg [ 5:0] vldi_coef; -reg vldi_data; - -parameter CYCLE = 20; - -reg clk; -initial begin - clk = 0; - forever - #(CYCLE/2) - clk=~clk; -end - - -reg signed [31:0] a_re [5:0]; -reg signed [31:0] a_im [5:0]; -reg signed [31:0] b_re [5:0]; -reg signed [31:0] b_im [5:0]; - -initial begin - rstn = 0; - vldi_data <= 0; - vldi_coef <= 0; - din_rect = 16'd0; - repeat(3) @(posedge clk); - vldi_coef[0] <= 1; - rstn = 1; - a_re[0] <= 55007237; - a_im[0] <= 0; - b_re[0] <= 2143083068; - b_im[0] <= 0; - @(posedge clk); - vldi_coef[0] <= 0; - a_re[0] <= 0; - a_im[0] <= 0; - b_re[0] <= 0; - b_im[0] <= 0; - repeat(8) @(posedge clk); - vldi_coef[1] <= 1; - rstn = 1; - a_re[1] <= 32690030; - a_im[1] <= 0; - b_re[1] <= 2145807236; - b_im[1] <= 0; - @(posedge clk); - vldi_coef[1] <= 0; - a_re[1] <= 0; - a_im[1] <= 0; - b_re[1] <= 0; - b_im[1] <= 0; - repeat(8) @(posedge clk); - vldi_coef[2] <= 1; - rstn = 1; - a_re[2] <= 429516; - a_im[2] <= 0; - b_re[2] <= 2146812530; - b_im[2] <= 0; - @(posedge clk); - vldi_coef[2] <= 0; - a_re[2] <= 0; - a_im[2] <= 0; - b_re[2] <= 0; - b_im[2] <= 0; - repeat(108) @(posedge clk); - vldi_data <= 1; -// repeat(10000) @(posedge clk); -// vldi_data <= 0; - -end - -reg [21:0] cnt; -always@(posedge clk or negedge rstn) - if(!rstn) - cnt <= 22'd0; - else - cnt <= cnt + 22'd1; - -initial -begin - wait(cnt[16]==1'b1) - $finish(0); -end - -reg vldi_data_r1; -always@(posedge clk or negedge rstn) - if(!rstn) - vldi_data_r1 <= 1'b0; - else - begin - vldi_data_r1 <= vldi_data; - end - -always@(posedge clk or negedge rstn) - if(!rstn) - din_rect <= 22'd0; - else if(vldi_data) - begin - din_rect <= 16'd30000; - end - else - begin - din_rect <= 16'd0; - end - -reg signed [15:0] random_in [0:3]; - -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 4; i = i + 1) begin - random_in[i] <= 16'd0; - end - end - else if (vldi_data) begin - for (int i = 0; i < 4; i = i + 1) begin - random_in[i] <= $urandom % 30000; - end - end - else begin - for (int i = 0; i < 4; i = i + 1) begin - random_in[i] <= 16'd0; - end - end -end - -integer file[3:0]; -reg [15:0] data[3:0]; -integer status[3:0]; -reg [15:0] reg_array[3:0]; - -initial begin - string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"}; - for (int i = 0; i < 4; i = i + 1) begin - file[i] = $fopen(filenames[i], "r"); - if (file[i] == 0) begin - $display("Failed to open file: %s", filenames[i]); - $finish; - end - end -end - - always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 4; i = i + 1) begin - reg_array[i] <= 16'd0; - end - end else if(vldi_data) begin - for (int i = 0; i < 4; i = i + 1) begin - status[i] = $fscanf(file[i], "%d\n", data[i]); - if (status[i] == 1 ) begin - reg_array[i] <= data[i]; - end - else begin - reg_array[i] <= 16'd0; - vldi_data <= 0; - end - end - end - end -reg signed [15:0] iir_in[3:0]; - -always @(*) - case(source_mode) - 2'b01 : begin - for (int i = 0; i < 4; i = i + 1) begin - iir_in[i] = din_rect; - end - end - 2'b10 : begin - for (int i = 0; i < 4; i = i + 1) begin - iir_in[i] = random_in[i]; - end - end - 2'b11 : begin - for (int i = 0; i < 4; i = i + 1) begin - iir_in[i] = reg_array[i]; - end - end - endcase - -wire [1:0] intp_mode; -assign intp_mode = 2'b10; - -wire [1:0] dac_mode_sel; -assign dac_mode_sel = 2'b00; - -wire tc_bypass; -wire vldo; - -assign tc_bypass = 1'b0; - -reg en; -always @(posedge clk or negedge rstn)begin - if(rstn==1'b0)begin - en <= 1; - end - else begin - en <= ~en; - end -end -wire signed [15:0] dout_p[7:0]; - -z_dsp inst_z_dsp( - .rstn (rstn ), - .clk (clk ), - .en (en ), -// .tc_bypass (tc_bypass ), - .vldi_coef (vldi_coef ), - .vldi_data (vldi_data_r1 ), -// .intp_mode (intp_mode ), -// .dac_mode_sel (dac_mode_sel ), - .din0 (iir_in[0] ), - .din1 (iir_in[1] ), - .din2 (iir_in[2] ), - .din3 (iir_in[3] ), - .a0_re (a_re[0] ), - .a0_im (a_im[0] ), - .b0_re (b_re[0] ), - .b0_im (b_im[0] ), - .a1_re (a_re[1] ), - .a1_im (a_im[1] ), - .b1_re (b_re[1] ), - .b1_im (b_im[1] ), - .a2_re (a_re[2] ), - .a2_im (a_im[2] ), - .b2_re (b_re[2] ), - .b2_im (b_im[2] ), - .a3_re (a_re[3] ), - .a3_im (a_im[3] ), - .b3_re (b_re[3] ), - .b3_im (b_im[3] ), - .a4_re (a_re[4] ), - .a4_im (a_im[4] ), - .b4_re (b_re[4] ), - .b4_im (b_im[4] ), - .a5_re (a_re[5] ), - .a5_im (a_im[5] ), - .b5_re (b_re[5] ), - .b5_im (b_im[5] ), - .dout0 (dout_p[0] ), - .dout1 (dout_p[1] ), - .dout2 (dout_p[2] ), - .dout3 (dout_p[3] ), - .vldo ( vldo ) - ); - - -integer signed In_fid[0:3]; -integer signed dout_fid[0:7]; -string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; -string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"}; - -initial begin - #0; - for (int i = 0; i < 4; i = i + 1) begin - In_fid[i] = $fopen(filenames_in[i]); - end - for (int i = 0; i < 4; i = i + 1) begin - dout_fid[i] = $fopen(filenames_dout[i]); - end -end - -always @(posedge clk) begin - if (vldi_data_r1) begin - for (int i = 0; i < 4; i = i + 1) begin - $fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); - end - end -end - -always @(posedge clk) begin - if (vldo) begin - for (int i = 0; i < 4; i = i + 1) begin - $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); - end - end -end -endmodule - From 73bc72cfc87a0bcd2283ba1d96bdba3836fde1c3 Mon Sep 17 00:00:00 2001 From: dada Date: Wed, 12 Mar 2025 22:01:27 +0800 Subject: [PATCH 2/5] data width of multiplier ports has been modified in order to reduce ovreheads --- rtl/z_dsp/IIR_Filter_p1.v | 103 +++++++++--------- rtl/z_dsp/IIR_Filter_p8.v | 152 +++++++++++++-------------- rtl/z_dsp/IIR_top.v | 213 +++++++------------------------------- rtl/z_dsp/TailCorr_top.v | 131 +++++++++++------------ rtl/z_dsp/mult_C.v | 44 ++++---- rtl/z_dsp/mult_x.v | 41 ++++---- 6 files changed, 263 insertions(+), 421 deletions(-) diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v index 687b9fc..f3ef0c1 100644 --- a/rtl/z_dsp/IIR_Filter_p1.v +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -32,59 +32,60 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p1 #( - parameter data_in_width = 16 + parameter data_in_width = 16 ,parameter coef_width = 32 ,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_coef_width = 31//division +,parameter mult_o_width = 36 +,parameter data_out_width = 20 ) //H(z) = a / (1 - b*z^-1) ( input rstn ,input clk ,input en -,input signed [data_in_width-1:0] din_re // Re(x(t)) -//,input signed [data_in_width-1:0] din_im // Im(x(t)) -,input signed [data_in_width-1:0] dout_r1_re // Re(y(t-1)) -,input signed [data_in_width-1:0] dout_r1_im // Im(y(t-1)) -,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] a_im -,input signed [coef_width-1 :0] b_re -,input signed [coef_width-1 :0] b_im +,input signed [data_in_width-1 :0] din_re // Re(x(t)) +,input signed [data_out_width-1:0] dout_r1_re // Re(y(t-1)) +,input signed [data_out_width-1:0] dout_r1_im // Im(y(t-1)) +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] b_re +,input signed [coef_width-1 :0] b_im -,output signed [data_in_width-1:0] dout_re // Re(y(t-16)) -,output signed [data_in_width-1:0] dout_im // Im(y(t-16)) +,output signed [data_out_width-1:0] dout_re // Re(y(t-16)) +,output signed [data_out_width-1:0] dout_im // Im(y(t-16)) ); -wire signed [data_in_width+frac_data_out_width-1:0] x1_re; -wire signed [data_in_width+frac_data_out_width-1:0] x1_im; +wire signed [mult_o_width-1 :0] x1_re; +wire signed [mult_o_width-1 :0] x1_im; -wire signed [data_in_width+frac_data_out_width-1:0] y1_re; -wire signed [data_in_width+frac_data_out_width-1:0] y1_im; -wire signed [data_in_width+frac_data_out_width :0] y_re; -wire signed [data_in_width+frac_data_out_width :0] y_im; +wire signed [mult_o_width-1 :0] y1_re; +wire signed [mult_o_width-1 :0] y1_im; +wire signed [mult_o_width :0] y_re; +wire signed [mult_o_width :0] y_im; -wire signed [data_in_width-1:0] y_re_trunc; -wire signed [data_in_width-1:0] y_im_trunc; +wire signed [data_out_width-1:0] y_re_trunc; +wire signed [data_out_width-1:0] y_im_trunc; // x1 = a * din delay M = a*x(t-8) mult_x #( - .A_width (data_in_width ) - ,.C_width (coef_width+frac_data_out_width ) - ,.D_width (coef_width+frac_data_out_width ) - ,.frac_coef_width (frac_coef_width ) + .A_width (data_in_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (mult_o_width ) ) inst_c1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (din_re ), - .c ({a_re,{frac_data_out_width{1'b0}}} ), - .d ({a_im,{frac_data_out_width{1'b0}}} ), - .Re (x1_re ), - .Im (x1_im ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (din_re ), + .c (a_re ), + .d (a_im ), + .Re (x1_re ), + .Im (x1_im ) ); @@ -92,22 +93,22 @@ inst_c1 ( // y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) mult_C #( - .A_width(data_in_width) -,.B_width(data_in_width) -,.C_width(coef_width+frac_data_out_width) -,.D_width(coef_width+frac_data_out_width) -,.frac_coef_width(frac_coef_width) + .A_width (data_out_width ) + ,.B_width (data_out_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (mult_o_width ) ) inst_c3 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (dout_r1_re ), - .b (dout_r1_im ), - .c ({b_re,{frac_data_out_width{1'b0}}} ), - .d ({b_im,{frac_data_out_width{1'b0}}} ), - .Re (y1_re ), - .Im (y1_im ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dout_r1_re ), + .b (dout_r1_im ), + .c (b_re ), + .d (b_im ), + .Re (y1_re ), + .Im (y1_im ) ); assign y_re = x1_re + y1_re; @@ -116,14 +117,14 @@ assign y_im = x1_im + y1_im; // dout = round(y) delay M = round(y(t-16)) trunc #( - .diw (data_in_width+frac_data_out_width+1 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+1 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); trunc #( - .diw (data_in_width+frac_data_out_width+1 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+1 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc); assign dout_re = y_re_trunc; diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index e6b86ba..10034bd 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -36,63 +36,65 @@ module IIR_Filter_p8 #( ,parameter coef_width = 32 ,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_coef_width = 31//division +,parameter mult_o_width = 36 +,parameter data_out_width = 20 ) // H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) ( input rstn ,input clk ,input en -,input signed [data_in_width-1:0] dinp0 //x(8n+16) -,input signed [data_in_width-1:0] dinp1 //x(8n+15) -,input signed [data_in_width-1:0] dinp2 //x(8n+14) -,input signed [data_in_width-1:0] dinp3 //x(8n+13) -,input signed [data_in_width-1:0] dinp4 //x(8n+12) -,input signed [data_in_width-1:0] dinp5 //x(8n+11) -,input signed [data_in_width-1:0] dinp6 //x(8n+10) -,input signed [data_in_width-1:0] dinp7 //x(8n+9) +,input signed [data_in_width-1 :0] dinp0 //x(8n+16) +,input signed [data_in_width-1 :0] dinp1 //x(8n+15) +,input signed [data_in_width-1 :0] dinp2 //x(8n+14) +,input signed [data_in_width-1 :0] dinp3 //x(8n+13) +,input signed [data_in_width-1 :0] dinp4 //x(8n+12) +,input signed [data_in_width-1 :0] dinp5 //x(8n+11) +,input signed [data_in_width-1 :0] dinp6 //x(8n+10) +,input signed [data_in_width-1 :0] dinp7 //x(8n+9) -,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] a_im -,input signed [coef_width-1 :0] ab_re -,input signed [coef_width-1 :0] ab_im -,input signed [coef_width-1 :0] abb_re -,input signed [coef_width-1 :0] abb_im -,input signed [coef_width-1 :0] ab_pow3_re -,input signed [coef_width-1 :0] ab_pow3_im -,input signed [coef_width-1 :0] ab_pow4_re -,input signed [coef_width-1 :0] ab_pow4_im -,input signed [coef_width-1 :0] ab_pow5_re -,input signed [coef_width-1 :0] ab_pow5_im -,input signed [coef_width-1 :0] ab_pow6_re -,input signed [coef_width-1 :0] ab_pow6_im -,input signed [coef_width-1 :0] ab_pow7_re -,input signed [coef_width-1 :0] ab_pow7_im +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] ab_re +,input signed [coef_width-1 :0] ab_im +,input signed [coef_width-1 :0] abb_re +,input signed [coef_width-1 :0] abb_im +,input signed [coef_width-1 :0] ab_pow3_re +,input signed [coef_width-1 :0] ab_pow3_im +,input signed [coef_width-1 :0] ab_pow4_re +,input signed [coef_width-1 :0] ab_pow4_im +,input signed [coef_width-1 :0] ab_pow5_re +,input signed [coef_width-1 :0] ab_pow5_im +,input signed [coef_width-1 :0] ab_pow6_re +,input signed [coef_width-1 :0] ab_pow6_im +,input signed [coef_width-1 :0] ab_pow7_re +,input signed [coef_width-1 :0] ab_pow7_im -,input signed [coef_width-1 :0] b_pow8_re -,input signed [coef_width-1 :0] b_pow8_im -,output signed [data_in_width-1:0] dout_re // Re(y(8n-8)) -,output signed [data_in_width-1:0] dout_im // Im(y(8n-8)) +,input signed [coef_width-1 :0] b_pow8_re +,input signed [coef_width-1 :0] b_pow8_im +,output signed [data_out_width-1:0] dout_re // Re(y(8n-8)) +,output signed [data_out_width-1:0] dout_im // Im(y(8n-8)) ); -wire signed [data_in_width-1:0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0}; -wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; -wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; +wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0}; +wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; +wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; -wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7]; -wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7]; +wire signed [mult_o_width-1 :0] x_re [0:7]; +wire signed [mult_o_width-1 :0] x_im [0:7]; -wire signed [data_in_width+frac_data_out_width+3:0] v_re; -wire signed [data_in_width+frac_data_out_width+3:0] v_im; -reg signed [data_in_width+frac_data_out_width+3:0] v1_re; -reg signed [data_in_width+frac_data_out_width+3:0] v1_im; +wire signed [mult_o_width+3 :0] v_re; +wire signed [mult_o_width+3 :0] v_im; +reg signed [mult_o_width+3 :0] v1_re; +reg signed [mult_o_width+3 :0] v1_im; -wire signed [data_in_width+frac_data_out_width+3:0] y_re; -wire signed [data_in_width+frac_data_out_width+3:0] y_im; -reg signed [data_in_width+frac_data_out_width+3:0] y1_re; -reg signed [data_in_width+frac_data_out_width+3:0] y1_im; +wire signed [mult_o_width+3 :0] y_re; +wire signed [mult_o_width+3 :0] y_im; +reg signed [mult_o_width+3 :0] y1_re; +reg signed [mult_o_width+3 :0] y1_im; -wire signed [data_in_width-1:0] y_re_trunc; -wire signed [data_in_width-1:0] y_im_trunc; +wire signed [data_out_width-1:0] y_re_trunc; +wire signed [data_out_width-1:0] y_im_trunc; // x[0] = (dinp0 * a_re) delay M = a*x(8n+8) // x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7) @@ -106,19 +108,19 @@ genvar i; generate for (i = 0; i < 8; i = i + 1) begin: mult_c_inst mult_x #( - .A_width (data_in_width ), - .C_width (coef_width+frac_data_out_width ), - .D_width (coef_width+frac_data_out_width ), - .frac_coef_width (frac_coef_width ) + .A_width (data_in_width ), + .C_width (coef_width ), + .D_width (coef_width ), + .o_width (mult_o_width ) ) inst_c ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (dinp[i] ), - .c ({ab_pow_re[i],{frac_data_out_width{1'b0}}} ), - .d ({ab_pow_im[i],{frac_data_out_width{1'b0}}} ), - .Re (x_re[i] ), - .Im (x_im[i] ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp[i] ), + .c (ab_pow_re[i] ), + .d (ab_pow_im[i] ), + .Re (x_re[i] ), + .Im (x_im[i] ) ); end endgenerate @@ -150,22 +152,22 @@ always @(posedge clk or negedge rstn) // y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) mult_C #( - .A_width (data_in_width+frac_data_out_width+4 ) - ,.B_width (data_in_width+frac_data_out_width+4 ) - ,.C_width (coef_width ) - ,.D_width (coef_width ) - ,.frac_coef_width (frac_coef_width ) + .A_width (mult_o_width+4 ) + ,.B_width (mult_o_width+4 ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (mult_o_width+4 ) ) inst_c9 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (y_re ), - .b (y_im ), - .c (b_pow8_re ), - .d (b_pow8_im ), - .Re (y1_re ), - .Im (y1_im ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y_re ), + .b (y_im ), + .c (b_pow8_re ), + .d (b_pow8_im ), + .Re (y1_re ), + .Im (y1_im ) ); assign y_re = v1_re + y1_re; @@ -173,14 +175,14 @@ assign y_im = v1_im + y1_im; // dout = round(y) delay M = round(y(8n-8)) trunc #( - .diw (data_in_width+frac_data_out_width+4 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+4 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); trunc #( - .diw (data_in_width+frac_data_out_width+4 ) - ,.msb (data_in_width+frac_data_out_width-1 ) - ,.lsb (frac_data_out_width ) + .diw (mult_o_width+4 ) + ,.msb (mult_o_width-1 ) + ,.lsb (mult_o_width-data_out_width ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc); diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index 091cc7b..6cdc578 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -31,8 +31,10 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- -module IIR_top - +module IIR_top #( + parameter temp_var_width = 20 +,parameter data_out_width = 18 +) ( input rstn ,input clk @@ -73,106 +75,33 @@ module IIR_top ,input signed [31 :0] b_pow8_re ,input signed [31 :0] b_pow8_im -,output signed [15 :0] IIRout_p0 // y(8n-8) -,output signed [15 :0] IIRout_p1 // y(8n-23) -,output signed [15 :0] IIRout_p2 // y(8n-38) -,output signed [15 :0] IIRout_p3 // y(8n-53) -,output signed [15 :0] IIRout_p4 // y(8n-68) -,output signed [15 :0] IIRout_p5 // y(8n-83) -,output signed [15 :0] IIRout_p6 // y(8n-98) -,output signed [15 :0] IIRout_p7 // y(8n-113) +,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) +,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) +,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38) +,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53) +,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68) +,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) +,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) +,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ); -/*reg signed [15:0] IIRin_p0_r [1 :0]; -reg signed [15:0] IIRin_p1_r [3 :0]; -reg signed [15:0] IIRin_p2_r [5 :0]; -reg signed [15:0] IIRin_p3_r [7 :0]; -reg signed [15:0] IIRin_p4_r [9 :0]; -reg signed [15:0] IIRin_p5_r [11:0]; -reg signed [15:0] IIRin_p6_r [13:0];//*/ -wire signed [15:0] IIRout_p0_re; -wire signed [15:0] IIRout_p1_re; -wire signed [15:0] IIRout_p2_re; -wire signed [15:0] IIRout_p3_re; -wire signed [15:0] IIRout_p4_re; -wire signed [15:0] IIRout_p5_re; -wire signed [15:0] IIRout_p6_re; -wire signed [15:0] IIRout_p7_re; -wire signed [15:0] IIRout_p0_im; -wire signed [15:0] IIRout_p1_im; -wire signed [15:0] IIRout_p2_im; -wire signed [15:0] IIRout_p3_im; -wire signed [15:0] IIRout_p4_im; -wire signed [15:0] IIRout_p5_im; -wire signed [15:0] IIRout_p6_im; -wire signed [15:0] IIRout_p7_im; +wire signed [temp_var_width-1:0] IIRout_p0_re; +wire signed [temp_var_width-1:0] IIRout_p1_re; +wire signed [temp_var_width-1:0] IIRout_p2_re; +wire signed [temp_var_width-1:0] IIRout_p3_re; +wire signed [temp_var_width-1:0] IIRout_p4_re; +wire signed [temp_var_width-1:0] IIRout_p5_re; +wire signed [temp_var_width-1:0] IIRout_p6_re; +wire signed [temp_var_width-1:0] IIRout_p7_re; +wire signed [temp_var_width-1:0] IIRout_p0_im; +wire signed [temp_var_width-1:0] IIRout_p1_im; +wire signed [temp_var_width-1:0] IIRout_p2_im; +wire signed [temp_var_width-1:0] IIRout_p3_im; +wire signed [temp_var_width-1:0] IIRout_p4_im; +wire signed [temp_var_width-1:0] IIRout_p5_im; +wire signed [temp_var_width-1:0] IIRout_p6_im; +wire signed [temp_var_width-1:0] IIRout_p7_im; -/*reg signed [15:0] IIRout_p0_r [13:0]; -reg signed [15:0] IIRout_p1_r [12:0]; -reg signed [15:0] IIRout_p2_r [10:0]; -reg signed [15:0] IIRout_p3_r [8 :0]; -reg signed [15:0] IIRout_p4_r [6 :0]; -reg signed [15:0] IIRout_p5_r [4 :0]; -reg signed [15:0] IIRout_p6_r [2 :0]; -reg signed [15:0] IIRout_p7_r;//*/ - - -/*integer i; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (i = 0; i < 2; i = i + 1) begin - IIRin_p0_r[i] <= 'h0; - end - for (i = 0; i < 4; i = i + 1) begin - IIRin_p1_r[i] <= 'h0; - end - for (i = 0; i < 6; i = i + 1) begin - IIRin_p2_r[i] <= 'h0; - end - for (i = 0; i < 8; i = i + 1) begin - IIRin_p3_r[i] <= 'h0; - end - for (i = 0; i <10; i = i + 1) begin - IIRin_p4_r[i] <= 'h0; - end - for (i = 0; i <12; i = i + 1) begin - IIRin_p5_r[i] <= 'h0; - end - for (i = 0; i <14; i = i + 1) begin - IIRin_p6_r[i] <= 'h0; - end - end - else if (en) begin - IIRin_p0_r[0] <= IIRin_p0; - IIRin_p1_r[0] <= IIRin_p1; - IIRin_p2_r[0] <= IIRin_p2; - IIRin_p3_r[0] <= IIRin_p3; - IIRin_p4_r[0] <= IIRin_p4; - IIRin_p5_r[0] <= IIRin_p5; - IIRin_p6_r[0] <= IIRin_p6; - for (i = 0; i < 1; i = i + 1) begin - IIRin_p0_r[i+1] <= IIRin_p0_r[i]; - end - for (i = 0; i < 3; i = i + 1) begin - IIRin_p1_r[i+1] <= IIRin_p1_r[i]; - end - for (i = 0; i < 5; i = i + 1) begin - IIRin_p2_r[i+1] <= IIRin_p2_r[i]; - end - for (i = 0; i < 7; i = i + 1) begin - IIRin_p3_r[i+1] <= IIRin_p3_r[i]; - end - for (i = 0; i < 9; i = i + 1) begin - IIRin_p4_r[i+1] <= IIRin_p4_r[i]; - end - for (i = 0; i <11; i = i + 1) begin - IIRin_p5_r[i+1] <= IIRin_p5_r[i]; - end - for (i = 0; i <13; i = i + 1) begin - IIRin_p6_r[i+1] <= IIRin_p6_r[i]; - end - end -end //*/ IIR_Filter_p8 inst_iir_p0 ( @@ -306,84 +235,16 @@ IIR_Filter_p1 inst_iir_p7 ( .b_im (b_im ), .dout_re (IIRout_p7_re ), // Re(y(8n-113)) .dout_im (IIRout_p7_im ) // Im(y(8n-113)) -); +); - - -/*integer i; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (i = 0; i < 2; i = i + 1) begin - IIRout_p6_r[i] <= 'h0; - end - for (i = 0; i < 4; i = i + 1) begin - IIRout_p5_r[i] <= 'h0; - end - for (i = 0; i < 6; i = i + 1) begin - IIRout_p4_r[i] <= 'h0; - end - for (i = 0; i < 8; i = i + 1) begin - IIRout_p3_r[i] <= 'h0; - end - for (i = 0; i <10; i = i + 1) begin - IIRout_p2_r[i] <= 'h0; - end - for (i = 0; i <12; i = i + 1) begin - IIRout_p1_r[i] <= 'h0; - end - for (i = 0; i <14; i = i + 1) begin - IIRout_p0_r[i] <= 'h0; - end - end - else if (en) begin - IIRout_p7_r <= IIRout_p7_re; - IIRout_p6_r[0] <= IIRout_p6_re; - IIRout_p5_r[0] <= IIRout_p5_re; - IIRout_p4_r[0] <= IIRout_p4_re; - IIRout_p3_r[0] <= IIRout_p3_re; - IIRout_p2_r[0] <= IIRout_p2_re; - IIRout_p1_r[0] <= IIRout_p1_re; - IIRout_p0_r[0] <= IIRout_p0_re; - for (i = 0; i < 2; i = i + 1) begin - IIRout_p6_r[i+1] <= IIRout_p6_r[i]; - end - for (i = 0; i < 4; i = i + 1) begin - IIRout_p5_r[i+1] <= IIRout_p5_r[i]; - end - for (i = 0; i < 6; i = i + 1) begin - IIRout_p4_r[i+1] <= IIRout_p4_r[i]; - end - for (i = 0; i < 8; i = i + 1) begin - IIRout_p3_r[i+1] <= IIRout_p3_r[i]; - end - for (i = 0; i <10; i = i + 1) begin - IIRout_p2_r[i+1] <= IIRout_p2_r[i]; - end - for (i = 0; i <12; i = i + 1) begin - IIRout_p1_r[i+1] <= IIRout_p1_r[i]; - end - for (i = 0; i <13; i = i + 1) begin - IIRout_p0_r[i+1] <= IIRout_p0_r[i]; - end - end -end -assign IIRout_p0 = IIRout_p1_r[12]; // y(8n-127) -assign IIRout_p1 = IIRout_p2_r[10]; // y(8n-126) -assign IIRout_p2 = IIRout_p3_r[8]; // y(8n-125) -assign IIRout_p3 = IIRout_p4_r[6]; // y(8n-124) -assign IIRout_p4 = IIRout_p5_r[4]; // y(8n-123) -assign IIRout_p5 = IIRout_p6_r[2]; // y(8n-122) -assign IIRout_p6 = IIRout_p7_r; // y(8n-121) -assign IIRout_p7 = IIRout_p0_r[13]; // y(8n-120)//*/ - -assign IIRout_p0 = IIRout_p0_re; // y(8n-8) -assign IIRout_p1 = IIRout_p1_re; // y(8n-23) -assign IIRout_p2 = IIRout_p2_re; // y(8n-38) -assign IIRout_p3 = IIRout_p3_re; // y(8n-53) -assign IIRout_p4 = IIRout_p4_re; // y(8n-68) -assign IIRout_p5 = IIRout_p5_re; // y(8n-83) -assign IIRout_p6 = IIRout_p6_re; // y(8n-98) -assign IIRout_p7 = IIRout_p7_re; // y(8n-113) +assign IIRout_p0 = IIRout_p0_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-8) +assign IIRout_p1 = IIRout_p1_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-23) +assign IIRout_p2 = IIRout_p2_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-38) +assign IIRout_p3 = IIRout_p3_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-53) +assign IIRout_p4 = IIRout_p4_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-68) +assign IIRout_p5 = IIRout_p5_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-83) +assign IIRout_p6 = IIRout_p6_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-98) +assign IIRout_p7 = IIRout_p7_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-113) endmodule diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index 022d006..affe355 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -190,22 +190,22 @@ wire signed [15:0] IIRin_p4; // iirin_x(8n+13) wire signed [15:0] IIRin_p5; // iirin_x(8n+14) wire signed [15:0] IIRin_p6; // iirin_x(8n+15) wire signed [15:0] IIRin_p7; // iirin_x(8n+16) -wire signed [15:0] IIRout_p0 [5:0]; // iirout_y(8n-8) -wire signed [15:0] IIRout_p1 [5:0]; // iirout_y(8n-23) -wire signed [15:0] IIRout_p2 [5:0]; // iirout_y(8n-38) -wire signed [15:0] IIRout_p3 [5:0]; // iirout_y(8n-53) -wire signed [15:0] IIRout_p4 [5:0]; // iirout_y(8n-68) -wire signed [15:0] IIRout_p5 [5:0]; // iirout_y(8n-83) -wire signed [15:0] IIRout_p6 [5:0]; // iirout_y(8n-98) -wire signed [15:0] IIRout_p7 [5:0]; // iirout_y(8n-113) -wire signed [15:0] sum_IIRout_p0; -wire signed [15:0] sum_IIRout_p1; -wire signed [15:0] sum_IIRout_p2; -wire signed [15:0] sum_IIRout_p3; -wire signed [15:0] sum_IIRout_p4; -wire signed [15:0] sum_IIRout_p5; -wire signed [15:0] sum_IIRout_p6; -wire signed [15:0] sum_IIRout_p7; +wire signed [17:0] IIRout_p0 [5:0]; // iirout_y(8n-8) +wire signed [17:0] IIRout_p1 [5:0]; // iirout_y(8n-23) +wire signed [17:0] IIRout_p2 [5:0]; // iirout_y(8n-38) +wire signed [17:0] IIRout_p3 [5:0]; // iirout_y(8n-53) +wire signed [17:0] IIRout_p4 [5:0]; // iirout_y(8n-68) +wire signed [17:0] IIRout_p5 [5:0]; // iirout_y(8n-83) +wire signed [17:0] IIRout_p6 [5:0]; // iirout_y(8n-98) +wire signed [17:0] IIRout_p7 [5:0]; // iirout_y(8n-113) +wire signed [20:0] sum_IIRout_p0; +wire signed [20:0] sum_IIRout_p1; +wire signed [20:0] sum_IIRout_p2; +wire signed [20:0] sum_IIRout_p3; +wire signed [20:0] sum_IIRout_p4; +wire signed [20:0] sum_IIRout_p5; +wire signed [20:0] sum_IIRout_p6; +wire signed [20:0] sum_IIRout_p7; reg signed [15:0] din_p0_r [15:0]; reg signed [15:0] din_p1_r [15:0]; reg signed [15:0] din_p2_r [15:0]; @@ -221,21 +221,21 @@ reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53) reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67) reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82) reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97) -reg signed [18:0] sum_IIRout_p0_r [12:0]; -reg signed [18:0] sum_IIRout_p1_r [11:0]; -reg signed [18:0] sum_IIRout_p2_r [9 :0]; -reg signed [18:0] sum_IIRout_p3_r [7 :0]; -reg signed [18:0] sum_IIRout_p4_r [5 :0]; -reg signed [18:0] sum_IIRout_p5_r [3 :0]; -reg signed [18:0] sum_IIRout_p6_r [1 :0]; -wire signed [18:0] dout_p0_r0; -wire signed [18:0] dout_p1_r0; -wire signed [18:0] dout_p2_r0; -wire signed [18:0] dout_p3_r0; -wire signed [18:0] dout_p4_r0; -wire signed [18:0] dout_p5_r0; -wire signed [18:0] dout_p6_r0; -wire signed [18:0] dout_p7_r0; +reg signed [20:0] sum_IIRout_p0_r [12:0]; +reg signed [20:0] sum_IIRout_p1_r [11:0]; +reg signed [20:0] sum_IIRout_p2_r [9 :0]; +reg signed [20:0] sum_IIRout_p3_r [7 :0]; +reg signed [20:0] sum_IIRout_p4_r [5 :0]; +reg signed [20:0] sum_IIRout_p5_r [3 :0]; +reg signed [20:0] sum_IIRout_p6_r [1 :0]; +wire signed [20:0] dout_p0_r0; +wire signed [20:0] dout_p1_r0; +wire signed [20:0] dout_p2_r0; +wire signed [20:0] dout_p3_r0; +wire signed [20:0] dout_p4_r0; +wire signed [20:0] dout_p5_r0; +wire signed [20:0] dout_p6_r0; +wire signed [20:0] dout_p7_r0; wire vldo_diff; diff_p inst_diff_p ( @@ -666,6 +666,15 @@ assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] +IIRout_p5[2] +IIRout_p5[3 assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] +IIRout_p6[2] +IIRout_p6[3] +IIRout_p6[4] +IIRout_p6[5]; assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] +IIRout_p7[2] +IIRout_p7[3] +IIRout_p7[4] +IIRout_p7[5]; +/*trunc #(20, 19, 3) round_u0 (clk, rstn, en, sum_IIRout_p0, sum_IIRout_p0_trunc); +trunc #(20, 19, 3) round_u1 (clk, rstn, en, sum_IIRout_p1, sum_IIRout_p1_trunc); +trunc #(20, 19, 3) round_u2 (clk, rstn, en, sum_IIRout_p2, sum_IIRout_p2_trunc); +trunc #(20, 19, 3) round_u3 (clk, rstn, en, sum_IIRout_p3, sum_IIRout_p3_trunc); +trunc #(20, 19, 3) round_u4 (clk, rstn, en, sum_IIRout_p4, sum_IIRout_p4_trunc); +trunc #(20, 19, 3) round_u5 (clk, rstn, en, sum_IIRout_p5, sum_IIRout_p5_trunc); +trunc #(20, 19, 3) round_u6 (clk, rstn, en, sum_IIRout_p6, sum_IIRout_p6_trunc); +trunc #(20, 19, 3) round_u7 (clk, rstn, en, sum_IIRout_p7, sum_IIRout_p7_trunc);*/ + always @(posedge clk or negedge rstn) begin if (!rstn) begin @@ -723,47 +732,23 @@ always @(posedge clk or negedge rstn) begin end end -assign dout_p0_r0 = din_p0_r[15] + sum_IIRout_p1_r[11]; // y(8n-119) -assign dout_p1_r0 = din_p1_r[15] + sum_IIRout_p2_r[9]; // y(8n-118) -assign dout_p2_r0 = din_p2_r[15] + sum_IIRout_p3_r[7]; // y(8n-117) -assign dout_p3_r0 = din_p3_r[15] + sum_IIRout_p4_r[5]; // y(8n-116) -assign dout_p4_r0 = din_p4_r[15] + sum_IIRout_p5_r[3]; // y(8n-115) -assign dout_p5_r0 = din_p5_r[15] + sum_IIRout_p6_r[1]; // y(8n-114) -assign dout_p6_r0 = din_p6_r[15] + sum_IIRout_p7; // y(8n-113) -assign dout_p7_r0 = din_p7_r[15] + sum_IIRout_p0_r[12]; // y(8n-112) +assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],2'b0} + sum_IIRout_p1_r[11]; // y(8n-119) +assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],2'b0} + sum_IIRout_p2_r[9]; // y(8n-118) +assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],2'b0} + sum_IIRout_p3_r[7]; // y(8n-117) +assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],2'b0} + sum_IIRout_p4_r[5]; // y(8n-116) +assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],2'b0} + sum_IIRout_p5_r[3]; // y(8n-115) +assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],2'b0} + sum_IIRout_p6_r[1]; // y(8n-114) +assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],2'b0} + sum_IIRout_p7; // y(8n-113) +assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],2'b0} + sum_IIRout_p0_r[12]; // y(8n-112) - - - - - - -reg signed [15:0] dout_p [7:0]; -wire signed [18:0] dout_p_r0 [0:7]; -assign dout_p_r0[0] = dout_p0_r0; -assign dout_p_r0[1] = dout_p1_r0; -assign dout_p_r0[2] = dout_p2_r0; -assign dout_p_r0[3] = dout_p3_r0; -assign dout_p_r0[4] = dout_p4_r0; -assign dout_p_r0[5] = dout_p5_r0; -assign dout_p_r0[6] = dout_p6_r0; -assign dout_p_r0[7] = dout_p7_r0; - -genvar j; -generate - for (j = 0; j < 8; j = j + 1) begin: trunc - trunc #(19,15,0) round_u (clk, rstn, en, dout_p_r0[j], dout_p[j]); - end -endgenerate - -assign dout_p0 = dout_p[0]; -assign dout_p1 = dout_p[1]; -assign dout_p2 = dout_p[2]; -assign dout_p3 = dout_p[3]; -assign dout_p4 = dout_p[4]; -assign dout_p5 = dout_p[5]; -assign dout_p6 = dout_p[6]; -assign dout_p7 = dout_p[7]; +trunc #(21,17,2) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); +trunc #(21,17,2) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); +trunc #(21,17,2) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2); +trunc #(21,17,2) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3); +trunc #(21,17,2) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4); +trunc #(21,17,2) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5); +trunc #(21,17,2) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6); +trunc #(21,17,2) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7); @@ -785,7 +770,7 @@ always @(posedge clk or negedge rstn) end else if(en) begin - dout_p0_r2 <= dout_p[0]; + dout_p0_r2 <= dout_p0; dout_p0_r3 <= dout_p0_r2; dout_p0_r4 <= dout_p0_r3; dout_p0_r5 <= dout_p0_r4; @@ -829,7 +814,7 @@ always @(posedge clk or negedge rstn)begin vldo_r0 <= 0; end end -assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p[0] == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); +assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ; assign vldo = vldo_r0; endmodule diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v index 47f097d..3323dd8 100644 --- a/rtl/z_dsp/mult_C.v +++ b/rtl/z_dsp/mult_C.v @@ -36,7 +36,7 @@ module mult_C #( ,parameter integer B_width = 8 ,parameter integer C_width = 8 ,parameter integer D_width = 8 -,parameter integer frac_coef_width = 31//division +,parameter integer o_width = 31//division ) @@ -55,19 +55,22 @@ module mult_C #( input rstn; input clk; input en; -input signed [A_width-1:0] a; -input signed [B_width-1:0] b; -input signed [C_width-1:0] c; -input signed [D_width-1:0] d; +input signed [A_width-1 :0] a; +input signed [B_width-1 :0] b; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; -output signed [A_width+C_width-frac_coef_width-2:0] Re; -output signed [A_width+D_width-frac_coef_width-2:0] Im; - -wire signed [A_width+C_width-1:0] ac; -wire signed [B_width+D_width-1:0] bd; -wire signed [A_width+D_width-1:0] ad; -wire signed [B_width+C_width-1:0] bc; +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; +wire signed [A_width+C_width :0] Re_tmp; +wire signed [A_width+D_width :0] Im_tmp; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; DW02_mult #(A_width,C_width) inst_c1( .A (a ), @@ -92,24 +95,19 @@ DW02_mult #(B_width,C_width) inst_c4( .A (b ), .TC (1'b1 ), .PRODUCT (bc ) ); -wire signed [A_width+C_width:0] Re_tmp; -wire signed [A_width+D_width:0] Im_tmp; assign Re_tmp = ac - bd; assign Im_tmp = ad + bc; -wire signed [A_width+C_width-frac_coef_width-2:0] Re_trunc; -wire signed [A_width+D_width-frac_coef_width-2:0] Im_trunc; - trunc #( - .diw (A_width+C_width+1 ) - ,.msb (A_width+C_width-2 ) - ,.lsb (frac_coef_width ) + .diw (A_width+C_width+1 ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) ) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); trunc #( - .diw (A_width+D_width+1 ) - ,.msb (A_width+D_width-2 ) - ,.lsb (frac_coef_width ) + .diw (A_width+D_width+1 ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) ) u_round2 (clk, rstn, en, Re_tmp, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. diff --git a/rtl/z_dsp/mult_x.v b/rtl/z_dsp/mult_x.v index a4ddbe1..7a65101 100644 --- a/rtl/z_dsp/mult_x.v +++ b/rtl/z_dsp/mult_x.v @@ -35,7 +35,7 @@ module mult_x #( parameter integer A_width = 8 ,parameter integer C_width = 8 ,parameter integer D_width = 8 -,parameter integer frac_coef_width = 31//division +,parameter integer o_width = 31//division ) @@ -53,15 +53,17 @@ module mult_x #( input rstn; input clk; input en; -input signed [A_width-1:0] a; -input signed [C_width-1:0] c; -input signed [D_width-1:0] d; +input signed [A_width-1 :0] a; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; -output signed [A_width+C_width-frac_coef_width-2:0] Re; -output signed [A_width+D_width-frac_coef_width-2:0] Im; +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; -wire signed [A_width+C_width-1:0] ac; -wire signed [A_width+D_width-1:0] ad; +wire signed [A_width+C_width-1:0] ac; +wire signed [A_width+D_width-1:0] ad; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; @@ -77,25 +79,18 @@ DW02_mult #(A_width,D_width) inst_c3( .A (a ), .PRODUCT (ad ) ); -wire signed [A_width+C_width:0] Re_tmp; -wire signed [A_width+D_width:0] Im_tmp; -assign Re_tmp = ac; -assign Im_tmp = ad; - -wire signed [A_width+C_width-frac_coef_width-2:0] Re_trunc; -wire signed [A_width+D_width-frac_coef_width-2:0] Im_trunc; trunc #( - .diw (A_width+C_width+1 ) - ,.msb (A_width+C_width-2 ) - ,.lsb (frac_coef_width ) -) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); + .diw (A_width+C_width ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round1 (clk, rstn, en, ac, Re_trunc); trunc #( - .diw (A_width+D_width+1 ) - ,.msb (A_width+D_width-2 ) - ,.lsb (frac_coef_width ) -) u_round2 (clk, rstn, en, Re_tmp, Im_trunc); + .diw (A_width+D_width ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+D_width-o_width-1 ) +) u_round2 (clk, rstn, en, ad, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. assign Re = Re_trunc; From 928978f034681ba260090c9bb8c38ae06dbdf516 Mon Sep 17 00:00:00 2001 From: dada Date: Thu, 13 Mar 2025 11:16:26 +0800 Subject: [PATCH 3/5] promote precision to about half LSB --- rtl/z_dsp/IIR_Filter_p1.v | 49 ++++++++++--------- rtl/z_dsp/IIR_Filter_p8.v | 48 +++++++++---------- rtl/z_dsp/IIR_top.v | 80 ++++++++++++++++++------------- rtl/z_dsp/TailCorr_top.v | 99 ++++++++++++++++++++------------------- rtl/z_dsp/Trunc.v | 35 +++++++------- rtl/z_dsp/mult_C.v | 94 ++++++++++++++++++------------------- 6 files changed, 210 insertions(+), 195 deletions(-) diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v index f3ef0c1..1b1429c 100644 --- a/rtl/z_dsp/IIR_Filter_p1.v +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -32,12 +32,11 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p1 #( - parameter data_in_width = 16 + parameter data_in_width = 16 +,parameter cascade_in_width = 37 ,parameter coef_width = 32 -,parameter frac_data_out_width = 20//X for in,5 -,parameter frac_coef_width = 31//division -,parameter mult_o_width = 36 -,parameter data_out_width = 20 +,parameter temp_var_width = cascade_in_width - 1 +,parameter data_out_width = cascade_in_width - 2 ) //H(z) = a / (1 - b*z^-1) ( @@ -45,8 +44,8 @@ module IIR_Filter_p1 #( ,input clk ,input en ,input signed [data_in_width-1 :0] din_re // Re(x(t)) -,input signed [data_out_width-1:0] dout_r1_re // Re(y(t-1)) -,input signed [data_out_width-1:0] dout_r1_im // Im(y(t-1)) +,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1)) +,input signed [cascade_in_width-1:0] dout_r1_im // Im(y(t-1)) ,input signed [coef_width-1 :0] a_re ,input signed [coef_width-1 :0] a_im ,input signed [coef_width-1 :0] b_re @@ -57,13 +56,13 @@ module IIR_Filter_p1 #( ); -wire signed [mult_o_width-1 :0] x1_re; -wire signed [mult_o_width-1 :0] x1_im; +wire signed [temp_var_width-1 :0] x1_re; +wire signed [temp_var_width-1 :0] x1_im; -wire signed [mult_o_width-1 :0] y1_re; -wire signed [mult_o_width-1 :0] y1_im; -wire signed [mult_o_width :0] y_re; -wire signed [mult_o_width :0] y_im; +wire signed [temp_var_width-1 :0] y1_re; +wire signed [temp_var_width-1 :0] y1_im; +wire signed [temp_var_width :0] y_re; +wire signed [temp_var_width :0] y_im; wire signed [data_out_width-1:0] y_re_trunc; wire signed [data_out_width-1:0] y_im_trunc; @@ -75,7 +74,7 @@ mult_x .A_width (data_in_width ) ,.C_width (coef_width ) ,.D_width (coef_width ) - ,.o_width (mult_o_width ) + ,.o_width (temp_var_width ) ) inst_c1 ( .clk (clk ), @@ -93,11 +92,11 @@ inst_c1 ( // y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) mult_C #( - .A_width (data_out_width ) - ,.B_width (data_out_width ) - ,.C_width (coef_width ) - ,.D_width (coef_width ) - ,.o_width (mult_o_width ) + .A_width (cascade_in_width ) + ,.B_width (cascade_in_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (temp_var_width ) ) inst_c3 ( .clk (clk ), @@ -117,14 +116,14 @@ assign y_im = x1_im + y1_im; // dout = round(y) delay M = round(y(t-16)) trunc #( - .diw (mult_o_width+1 ) - ,.msb (mult_o_width-1 ) - ,.lsb (mult_o_width-data_out_width ) + .diw (temp_var_width+1 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); trunc #( - .diw (mult_o_width+1 ) - ,.msb (mult_o_width-1 ) - ,.lsb (mult_o_width-data_out_width ) + .diw (temp_var_width+1 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc); assign dout_re = y_re_trunc; diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index 10034bd..c337109 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -36,8 +36,8 @@ module IIR_Filter_p8 #( ,parameter coef_width = 32 ,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_coef_width = 31//division -,parameter mult_o_width = 36 -,parameter data_out_width = 20 +,parameter temp_var_width = 42 +,parameter data_out_width = 37 ) // H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) ( @@ -80,18 +80,18 @@ wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5 wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; -wire signed [mult_o_width-1 :0] x_re [0:7]; -wire signed [mult_o_width-1 :0] x_im [0:7]; +wire signed [temp_var_width-1 :0] x_re [0:7]; +wire signed [temp_var_width-1 :0] x_im [0:7]; -wire signed [mult_o_width+3 :0] v_re; -wire signed [mult_o_width+3 :0] v_im; -reg signed [mult_o_width+3 :0] v1_re; -reg signed [mult_o_width+3 :0] v1_im; +wire signed [temp_var_width+3 :0] v_re; +wire signed [temp_var_width+3 :0] v_im; +reg signed [temp_var_width+3 :0] v1_re; +reg signed [temp_var_width+3 :0] v1_im; -wire signed [mult_o_width+3 :0] y_re; -wire signed [mult_o_width+3 :0] y_im; -reg signed [mult_o_width+3 :0] y1_re; -reg signed [mult_o_width+3 :0] y1_im; +wire signed [temp_var_width+3 :0] y_re; +wire signed [temp_var_width+3 :0] y_im; +reg signed [temp_var_width+3 :0] y1_re; +reg signed [temp_var_width+3 :0] y1_im; wire signed [data_out_width-1:0] y_re_trunc; wire signed [data_out_width-1:0] y_im_trunc; @@ -111,7 +111,7 @@ generate .A_width (data_in_width ), .C_width (coef_width ), .D_width (coef_width ), - .o_width (mult_o_width ) + .o_width (temp_var_width ) ) inst_c ( .clk (clk ), .rstn (rstn ), @@ -152,11 +152,11 @@ always @(posedge clk or negedge rstn) // y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) mult_C #( - .A_width (mult_o_width+4 ) - ,.B_width (mult_o_width+4 ) - ,.C_width (coef_width ) - ,.D_width (coef_width ) - ,.o_width (mult_o_width+4 ) + .A_width (temp_var_width+4 ) + ,.B_width (temp_var_width+4 ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (temp_var_width+4 ) ) inst_c9 ( .clk (clk ), @@ -175,14 +175,14 @@ assign y_im = v1_im + y1_im; // dout = round(y) delay M = round(y(8n-8)) trunc #( - .diw (mult_o_width+4 ) - ,.msb (mult_o_width-1 ) - ,.lsb (mult_o_width-data_out_width ) + .diw (temp_var_width+4 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); trunc #( - .diw (mult_o_width+4 ) - ,.msb (mult_o_width-1 ) - ,.lsb (mult_o_width-data_out_width ) + .diw (temp_var_width+4 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) ) round_u2 (clk, rstn, en, y_im, y_im_trunc); diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index 6cdc578..f874101 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -32,8 +32,8 @@ //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_top #( - parameter temp_var_width = 20 -,parameter data_out_width = 18 + parameter temp_var_width = 37 +,parameter data_out_width = 23 ) ( input rstn @@ -85,22 +85,22 @@ module IIR_top #( ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ); -wire signed [temp_var_width-1:0] IIRout_p0_re; -wire signed [temp_var_width-1:0] IIRout_p1_re; -wire signed [temp_var_width-1:0] IIRout_p2_re; -wire signed [temp_var_width-1:0] IIRout_p3_re; -wire signed [temp_var_width-1:0] IIRout_p4_re; -wire signed [temp_var_width-1:0] IIRout_p5_re; -wire signed [temp_var_width-1:0] IIRout_p6_re; -wire signed [temp_var_width-1:0] IIRout_p7_re; -wire signed [temp_var_width-1:0] IIRout_p0_im; -wire signed [temp_var_width-1:0] IIRout_p1_im; -wire signed [temp_var_width-1:0] IIRout_p2_im; -wire signed [temp_var_width-1:0] IIRout_p3_im; -wire signed [temp_var_width-1:0] IIRout_p4_im; -wire signed [temp_var_width-1:0] IIRout_p5_im; -wire signed [temp_var_width-1:0] IIRout_p6_im; -wire signed [temp_var_width-1:0] IIRout_p7_im; +wire signed [temp_var_width- 1:0] IIRout_p0_re; +wire signed [temp_var_width- 3:0] IIRout_p1_re; +wire signed [temp_var_width- 5:0] IIRout_p2_re; +wire signed [temp_var_width- 7:0] IIRout_p3_re; +wire signed [temp_var_width- 9:0] IIRout_p4_re; +wire signed [temp_var_width-11:0] IIRout_p5_re; +wire signed [temp_var_width-13:0] IIRout_p6_re; +wire signed [temp_var_width-15:0] IIRout_p7_re; +wire signed [temp_var_width- 1:0] IIRout_p0_im; +wire signed [temp_var_width- 3:0] IIRout_p1_im; +wire signed [temp_var_width- 5:0] IIRout_p2_im; +wire signed [temp_var_width- 7:0] IIRout_p3_im; +wire signed [temp_var_width- 9:0] IIRout_p4_im; +wire signed [temp_var_width-11:0] IIRout_p5_im; +wire signed [temp_var_width-13:0] IIRout_p6_im; +wire signed [temp_var_width-15:0] IIRout_p7_im; @@ -138,7 +138,9 @@ IIR_Filter_p8 inst_iir_p0 ( .dout_im (IIRout_p0_im ) // Im(y(8n-8)) ); -IIR_Filter_p1 inst_iir_p1 ( +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width ) +) inst_iir_p1( .clk (clk ), .rstn (rstn ), .en (en ), @@ -152,7 +154,9 @@ IIR_Filter_p1 inst_iir_p1 ( .dout_re (IIRout_p1_re ), // Re(y(8n-23)) .dout_im (IIRout_p1_im ) // Im(y(8n-23)) ); -IIR_Filter_p1 inst_iir_p2 ( +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-2 ) +) inst_iir_p2 ( .clk (clk ), .rstn (rstn ), .en (en ), @@ -166,7 +170,9 @@ IIR_Filter_p1 inst_iir_p2 ( .dout_re (IIRout_p2_re ), // Re(y(8n-38)) .dout_im (IIRout_p2_im ) // Im(y(8n-38)) ); -IIR_Filter_p1 inst_iir_p3 ( +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-4 ) +) inst_iir_p3 ( .clk (clk ), .rstn (rstn ), .en (en ), @@ -180,7 +186,9 @@ IIR_Filter_p1 inst_iir_p3 ( .dout_re (IIRout_p3_re ), // Re(y(8n-53)) .dout_im (IIRout_p3_im ) // Im(y(8n-53)) ); -IIR_Filter_p1 inst_iir_p4 ( +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-6 ) +) inst_iir_p4 ( .clk (clk ), .rstn (rstn ), .en (en ), @@ -194,7 +202,9 @@ IIR_Filter_p1 inst_iir_p4 ( .dout_re (IIRout_p4_re ), // Re(y(8n-68)) .dout_im (IIRout_p4_im ) // Im(y(8n-68)) ); -IIR_Filter_p1 inst_iir_p5 ( +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-8 ) +) inst_iir_p5 ( .clk (clk ), .rstn (rstn ), .en (en ), @@ -208,7 +218,9 @@ IIR_Filter_p1 inst_iir_p5 ( .dout_re (IIRout_p5_re ), // Re(y(8n-83)) .dout_im (IIRout_p5_im ) // Im(y(8n-83)) ); -IIR_Filter_p1 inst_iir_p6 ( +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-10 ) +) inst_iir_p6 ( .clk (clk ), .rstn (rstn ), .en (en ), @@ -222,7 +234,9 @@ IIR_Filter_p1 inst_iir_p6 ( .dout_re (IIRout_p6_re ), // Re(y(8n-98)) .dout_im (IIRout_p6_im ) // Im(y(8n-98)) ); -IIR_Filter_p1 inst_iir_p7 ( +IIR_Filter_p1 #( + .cascade_in_width (temp_var_width-12 ) +) inst_iir_p7 ( .clk (clk ), .rstn (rstn ), .en (en ), @@ -237,14 +251,14 @@ IIR_Filter_p1 inst_iir_p7 ( .dout_im (IIRout_p7_im ) // Im(y(8n-113)) ); -assign IIRout_p0 = IIRout_p0_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-8) -assign IIRout_p1 = IIRout_p1_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-23) -assign IIRout_p2 = IIRout_p2_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-38) -assign IIRout_p3 = IIRout_p3_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-53) -assign IIRout_p4 = IIRout_p4_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-68) -assign IIRout_p5 = IIRout_p5_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-83) -assign IIRout_p6 = IIRout_p6_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-98) -assign IIRout_p7 = IIRout_p7_re[temp_var_width-1 : temp_var_width-data_out_width]; // y(8n-113) +assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8) +assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23) +assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38) +assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53) +assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68) +assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83) +assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98) +assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113) endmodule diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index affe355..f724225 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -31,8 +31,9 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- -module TailCorr_top - +module TailCorr_top #( + parameter temp_var_width = 23 +) ( input rstn ,input clk @@ -190,22 +191,22 @@ wire signed [15:0] IIRin_p4; // iirin_x(8n+13) wire signed [15:0] IIRin_p5; // iirin_x(8n+14) wire signed [15:0] IIRin_p6; // iirin_x(8n+15) wire signed [15:0] IIRin_p7; // iirin_x(8n+16) -wire signed [17:0] IIRout_p0 [5:0]; // iirout_y(8n-8) -wire signed [17:0] IIRout_p1 [5:0]; // iirout_y(8n-23) -wire signed [17:0] IIRout_p2 [5:0]; // iirout_y(8n-38) -wire signed [17:0] IIRout_p3 [5:0]; // iirout_y(8n-53) -wire signed [17:0] IIRout_p4 [5:0]; // iirout_y(8n-68) -wire signed [17:0] IIRout_p5 [5:0]; // iirout_y(8n-83) -wire signed [17:0] IIRout_p6 [5:0]; // iirout_y(8n-98) -wire signed [17:0] IIRout_p7 [5:0]; // iirout_y(8n-113) -wire signed [20:0] sum_IIRout_p0; -wire signed [20:0] sum_IIRout_p1; -wire signed [20:0] sum_IIRout_p2; -wire signed [20:0] sum_IIRout_p3; -wire signed [20:0] sum_IIRout_p4; -wire signed [20:0] sum_IIRout_p5; -wire signed [20:0] sum_IIRout_p6; -wire signed [20:0] sum_IIRout_p7; +wire signed [temp_var_width-1:0] IIRout_p0 [5:0]; // iirout_y(8n-8) +wire signed [temp_var_width-1:0] IIRout_p1 [5:0]; // iirout_y(8n-23) +wire signed [temp_var_width-1:0] IIRout_p2 [5:0]; // iirout_y(8n-38) +wire signed [temp_var_width-1:0] IIRout_p3 [5:0]; // iirout_y(8n-53) +wire signed [temp_var_width-1:0] IIRout_p4 [5:0]; // iirout_y(8n-68) +wire signed [temp_var_width-1:0] IIRout_p5 [5:0]; // iirout_y(8n-83) +wire signed [temp_var_width-1:0] IIRout_p6 [5:0]; // iirout_y(8n-98) +wire signed [temp_var_width-1:0] IIRout_p7 [5:0]; // iirout_y(8n-113) +wire signed [temp_var_width+2:0] sum_IIRout_p0; +wire signed [temp_var_width+2:0] sum_IIRout_p1; +wire signed [temp_var_width+2:0] sum_IIRout_p2; +wire signed [temp_var_width+2:0] sum_IIRout_p3; +wire signed [temp_var_width+2:0] sum_IIRout_p4; +wire signed [temp_var_width+2:0] sum_IIRout_p5; +wire signed [temp_var_width+2:0] sum_IIRout_p6; +wire signed [temp_var_width+2:0] sum_IIRout_p7; reg signed [15:0] din_p0_r [15:0]; reg signed [15:0] din_p1_r [15:0]; reg signed [15:0] din_p2_r [15:0]; @@ -221,21 +222,21 @@ reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53) reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67) reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82) reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97) -reg signed [20:0] sum_IIRout_p0_r [12:0]; -reg signed [20:0] sum_IIRout_p1_r [11:0]; -reg signed [20:0] sum_IIRout_p2_r [9 :0]; -reg signed [20:0] sum_IIRout_p3_r [7 :0]; -reg signed [20:0] sum_IIRout_p4_r [5 :0]; -reg signed [20:0] sum_IIRout_p5_r [3 :0]; -reg signed [20:0] sum_IIRout_p6_r [1 :0]; -wire signed [20:0] dout_p0_r0; -wire signed [20:0] dout_p1_r0; -wire signed [20:0] dout_p2_r0; -wire signed [20:0] dout_p3_r0; -wire signed [20:0] dout_p4_r0; -wire signed [20:0] dout_p5_r0; -wire signed [20:0] dout_p6_r0; -wire signed [20:0] dout_p7_r0; +reg signed [temp_var_width+2:0] sum_IIRout_p0_r [12:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p1_r [11:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p2_r [9 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p3_r [7 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p4_r [5 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p5_r [3 :0]; +reg signed [temp_var_width+2:0] sum_IIRout_p6_r [1 :0]; +wire signed [temp_var_width+2:0] dout_p0_r0; +wire signed [temp_var_width+2:0] dout_p1_r0; +wire signed [temp_var_width+2:0] dout_p2_r0; +wire signed [temp_var_width+2:0] dout_p3_r0; +wire signed [temp_var_width+2:0] dout_p4_r0; +wire signed [temp_var_width+2:0] dout_p5_r0; +wire signed [temp_var_width+2:0] dout_p6_r0; +wire signed [temp_var_width+2:0] dout_p7_r0; wire vldo_diff; diff_p inst_diff_p ( @@ -732,23 +733,23 @@ always @(posedge clk or negedge rstn) begin end end -assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],2'b0} + sum_IIRout_p1_r[11]; // y(8n-119) -assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],2'b0} + sum_IIRout_p2_r[9]; // y(8n-118) -assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],2'b0} + sum_IIRout_p3_r[7]; // y(8n-117) -assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],2'b0} + sum_IIRout_p4_r[5]; // y(8n-116) -assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],2'b0} + sum_IIRout_p5_r[3]; // y(8n-115) -assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],2'b0} + sum_IIRout_p6_r[1]; // y(8n-114) -assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],2'b0} + sum_IIRout_p7; // y(8n-113) -assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],2'b0} + sum_IIRout_p0_r[12]; // y(8n-112) +assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) +assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) +assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) +assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) +assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115) +assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) +assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) +assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) -trunc #(21,17,2) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); -trunc #(21,17,2) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); -trunc #(21,17,2) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2); -trunc #(21,17,2) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3); -trunc #(21,17,2) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4); -trunc #(21,17,2) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5); -trunc #(21,17,2) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6); -trunc #(21,17,2) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7); diff --git a/rtl/z_dsp/Trunc.v b/rtl/z_dsp/Trunc.v index dd92f70..461ce00 100644 --- a/rtl/z_dsp/Trunc.v +++ b/rtl/z_dsp/Trunc.v @@ -3,6 +3,7 @@ module trunc #( //,parameter integer dow = msb - (lsb -1) ,parameter integer msb = 7 ,parameter integer lsb = 1 +,parameter integer half_precision = 0 ) ( input clk @@ -16,23 +17,7 @@ module trunc #( reg signed [msb - lsb : 0] d_tmp; generate - if(lsb==0) begin - always @(posedge clk or negedge rstn) begin - if (!rstn) begin - d_tmp <= 'h0; - end - else if(en) begin - if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) - d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; - else - d_tmp <= din[msb:lsb]; - end - else begin - d_tmp <= d_tmp; - end - end - end - else begin + if(lsb!=0 && half_precision != 0) begin always @(posedge clk or negedge rstn) begin if (!rstn) begin d_tmp <= 'h0; @@ -48,6 +33,22 @@ generate end end end + else begin + always @(posedge clk or negedge rstn) begin + if (!rstn) begin + d_tmp <= 'h0; + end + else if(en) begin + if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}}) + d_tmp <= {{din[diw-1]}, {(msb-lsb){!din[diw-1]}}}; + else + d_tmp <= din[msb:lsb]; + end + else begin + d_tmp <= d_tmp; + end + end + end endgenerate assign dout = d_tmp; diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v index 3323dd8..d386159 100644 --- a/rtl/z_dsp/mult_C.v +++ b/rtl/z_dsp/mult_C.v @@ -46,72 +46,72 @@ module mult_C #( en, a, b, - c, - d, - Re, - Im + c, + d, + Re, + Im ); input rstn; input clk; input en; -input signed [A_width-1 :0] a; -input signed [B_width-1 :0] b; -input signed [C_width-1 :0] c; -input signed [D_width-1 :0] d; +input signed [A_width-1 :0] a; +input signed [B_width-1 :0] b; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; -output signed [o_width-1 :0] Re; -output signed [o_width-1 :0] Im; +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; -wire signed [A_width+C_width-1:0] ac; -wire signed [B_width+D_width-1:0] bd; -wire signed [A_width+D_width-1:0] ad; -wire signed [B_width+C_width-1:0] bc; -wire signed [A_width+C_width :0] Re_tmp; -wire signed [A_width+D_width :0] Im_tmp; -wire signed [o_width-1 :0] Re_trunc; -wire signed [o_width-1 :0] Im_trunc; +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; +wire signed [A_width+C_width :0] Re_tmp; +wire signed [A_width+D_width :0] Im_tmp; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; -DW02_mult #(A_width,C_width) inst_c1( .A (a ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (ac ) - ); +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); -DW02_mult #(B_width,D_width) inst_c2( .A (b ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (bd ) - ); +DW02_mult #(B_width,D_width) inst_c2( .A (b ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (bd ) + ); -DW02_mult #(A_width,D_width) inst_c3( .A (a ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (ad ) - ); -DW02_mult #(B_width,C_width) inst_c4( .A (b ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (bc ) - ); +DW02_mult #(A_width,D_width) inst_c3( .A (a ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (ad ) + ); +DW02_mult #(B_width,C_width) inst_c4( .A (b ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (bc ) + ); assign Re_tmp = ac - bd; assign Im_tmp = ad + bc; trunc #( - .diw (A_width+C_width+1 ) - ,.msb (A_width+C_width-2 ) - ,.lsb (A_width+C_width-o_width-1 ) + .diw (A_width+C_width+1 ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) ) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); trunc #( - .diw (A_width+D_width+1 ) - ,.msb (A_width+D_width-2 ) - ,.lsb (A_width+C_width-o_width-1 ) -) u_round2 (clk, rstn, en, Re_tmp, Im_trunc); + .diw (A_width+D_width+1 ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round2 (clk, rstn, en, Im_tmp, Im_trunc); // Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. -assign Re = Re_trunc; -assign Im = Im_trunc; +assign Re = Re_trunc; +assign Im = Im_trunc; endmodule From 601600c7609fd90eec55167a4471b9ace5be8754 Mon Sep 17 00:00:00 2001 From: dada Date: Thu, 13 Mar 2025 11:31:31 +0800 Subject: [PATCH 4/5] parameterize modules --- rtl/z_dsp/IIR_Filter_p1.v | 4 +- rtl/z_dsp/IIR_Filter_p8.v | 8 +- rtl/z_dsp/IIR_top.v | 8 +- rtl/z_dsp/TailCorr_top.v | 578 +++++++++++++++++++------------------- 4 files changed, 305 insertions(+), 293 deletions(-) diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v index 1b1429c..e6c6f01 100644 --- a/rtl/z_dsp/IIR_Filter_p1.v +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -32,9 +32,9 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p1 #( - parameter data_in_width = 16 + parameter coef_width = 32 +,parameter data_in_width = 16 ,parameter cascade_in_width = 37 -,parameter coef_width = 32 ,parameter temp_var_width = cascade_in_width - 1 ,parameter data_out_width = cascade_in_width - 2 ) diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index c337109..762f219 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -32,12 +32,10 @@ // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p8 #( - parameter data_in_width = 16 -,parameter coef_width = 32 -,parameter frac_data_out_width = 20//X for in,5 -,parameter frac_coef_width = 31//division -,parameter temp_var_width = 42 + parameter coef_width = 32 +,parameter data_in_width = 16 ,parameter data_out_width = 37 +,parameter temp_var_width = data_out_width+5 ) // H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) ( diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index f874101..d9bcd91 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -32,8 +32,8 @@ //-FHDR-------------------------------------------------------------------------------------------------------- module IIR_top #( - parameter temp_var_width = 37 -,parameter data_out_width = 23 + parameter data_out_width = 23 +,parameter temp_var_width = data_out_width + 14 ) ( input rstn @@ -104,7 +104,9 @@ wire signed [temp_var_width-15:0] IIRout_p7_im; -IIR_Filter_p8 inst_iir_p0 ( +IIR_Filter_p8 #( + .data_out_width (temp_var_width ) +) inst_iir_p0 ( .clk (clk ), .rstn (rstn ), .en (en ), diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index f724225..c7fd5d3 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -32,7 +32,7 @@ //-FHDR-------------------------------------------------------------------------------------------------------- module TailCorr_top #( - parameter temp_var_width = 23 + parameter temp_var_width = 22 ) ( input rstn @@ -364,298 +364,310 @@ end -IIR_top inst_iir_top_0 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1]), - .IIRin_p1_r4 (IIRin_p1_r[3]), - .IIRin_p2_r6 (IIRin_p2_r[5]), - .IIRin_p3_r8 (IIRin_p3_r[7]), - .IIRin_p4_r10 (IIRin_p4_r[9]), - .IIRin_p5_r12 (IIRin_p5_r[11]), - .IIRin_p6_r14 (IIRin_p6_r[13]), - .a_re (a_re0 ), - .a_im (a_im0 ), - .b_re (b_re0 ), - .b_im (b_im0 ), - .ab_re (ab_re0 ), - .ab_im (ab_im0 ), - .abb_re (abb_re0 ), - .abb_im (abb_im0 ), - .ab_pow3_re (ab_pow3_re0 ), - .ab_pow3_im (ab_pow3_im0 ), - .ab_pow4_re (ab_pow4_re0 ), - .ab_pow4_im (ab_pow4_im0 ), - .ab_pow5_re (ab_pow5_re0 ), - .ab_pow5_im (ab_pow5_im0 ), - .ab_pow6_re (ab_pow6_re0 ), - .ab_pow6_im (ab_pow6_im0 ), - .ab_pow7_re (ab_pow7_re0 ), - .ab_pow7_im (ab_pow7_im0 ), - .b_pow8_re (b_pow8_re0 ), - .b_pow8_im (b_pow8_im0 ), - .IIRout_p0 (IIRout_p0[0] ), - .IIRout_p1 (IIRout_p1[0] ), - .IIRout_p2 (IIRout_p2[0] ), - .IIRout_p3 (IIRout_p3[0] ), - .IIRout_p4 (IIRout_p4[0] ), - .IIRout_p5 (IIRout_p5[0] ), - .IIRout_p6 (IIRout_p6[0] ), - .IIRout_p7 (IIRout_p7[0] ) +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_0 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re0 ), + .a_im (a_im0 ), + .b_re (b_re0 ), + .b_im (b_im0 ), + .ab_re (ab_re0 ), + .ab_im (ab_im0 ), + .abb_re (abb_re0 ), + .abb_im (abb_im0 ), + .ab_pow3_re (ab_pow3_re0 ), + .ab_pow3_im (ab_pow3_im0 ), + .ab_pow4_re (ab_pow4_re0 ), + .ab_pow4_im (ab_pow4_im0 ), + .ab_pow5_re (ab_pow5_re0 ), + .ab_pow5_im (ab_pow5_im0 ), + .ab_pow6_re (ab_pow6_re0 ), + .ab_pow6_im (ab_pow6_im0 ), + .ab_pow7_re (ab_pow7_re0 ), + .ab_pow7_im (ab_pow7_im0 ), + .b_pow8_re (b_pow8_re0 ), + .b_pow8_im (b_pow8_im0 ), + .IIRout_p0 (IIRout_p0[0] ), + .IIRout_p1 (IIRout_p1[0] ), + .IIRout_p2 (IIRout_p2[0] ), + .IIRout_p3 (IIRout_p3[0] ), + .IIRout_p4 (IIRout_p4[0] ), + .IIRout_p5 (IIRout_p5[0] ), + .IIRout_p6 (IIRout_p6[0] ), + .IIRout_p7 (IIRout_p7[0] ) ); -IIR_top inst_iir_top_1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1]), - .IIRin_p1_r4 (IIRin_p1_r[3]), - .IIRin_p2_r6 (IIRin_p2_r[5]), - .IIRin_p3_r8 (IIRin_p3_r[7]), - .IIRin_p4_r10 (IIRin_p4_r[9]), - .IIRin_p5_r12 (IIRin_p5_r[11]), - .IIRin_p6_r14 (IIRin_p6_r[13]), - .a_re (a_re1 ), - .a_im (a_im1 ), - .b_re (b_re1 ), - .b_im (b_im1 ), - .ab_re (ab_re1 ), - .ab_im (ab_im1 ), - .abb_re (abb_re1 ), - .abb_im (abb_im1 ), - .ab_pow3_re (ab_pow3_re1 ), - .ab_pow3_im (ab_pow3_im1 ), - .ab_pow4_re (ab_pow4_re1 ), - .ab_pow4_im (ab_pow4_im1 ), - .ab_pow5_re (ab_pow5_re1 ), - .ab_pow5_im (ab_pow5_im1 ), - .ab_pow6_re (ab_pow6_re1 ), - .ab_pow6_im (ab_pow6_im1 ), - .ab_pow7_re (ab_pow7_re1 ), - .ab_pow7_im (ab_pow7_im1 ), - .b_pow8_re (b_pow8_re1 ), - .b_pow8_im (b_pow8_im1 ), - .IIRout_p0 (IIRout_p0[1] ), - .IIRout_p1 (IIRout_p1[1] ), - .IIRout_p2 (IIRout_p2[1] ), - .IIRout_p3 (IIRout_p3[1] ), - .IIRout_p4 (IIRout_p4[1] ), - .IIRout_p5 (IIRout_p5[1] ), - .IIRout_p6 (IIRout_p6[1] ), - .IIRout_p7 (IIRout_p7[1] ) +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_1 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re1 ), + .a_im (a_im1 ), + .b_re (b_re1 ), + .b_im (b_im1 ), + .ab_re (ab_re1 ), + .ab_im (ab_im1 ), + .abb_re (abb_re1 ), + .abb_im (abb_im1 ), + .ab_pow3_re (ab_pow3_re1 ), + .ab_pow3_im (ab_pow3_im1 ), + .ab_pow4_re (ab_pow4_re1 ), + .ab_pow4_im (ab_pow4_im1 ), + .ab_pow5_re (ab_pow5_re1 ), + .ab_pow5_im (ab_pow5_im1 ), + .ab_pow6_re (ab_pow6_re1 ), + .ab_pow6_im (ab_pow6_im1 ), + .ab_pow7_re (ab_pow7_re1 ), + .ab_pow7_im (ab_pow7_im1 ), + .b_pow8_re (b_pow8_re1 ), + .b_pow8_im (b_pow8_im1 ), + .IIRout_p0 (IIRout_p0[1] ), + .IIRout_p1 (IIRout_p1[1] ), + .IIRout_p2 (IIRout_p2[1] ), + .IIRout_p3 (IIRout_p3[1] ), + .IIRout_p4 (IIRout_p4[1] ), + .IIRout_p5 (IIRout_p5[1] ), + .IIRout_p6 (IIRout_p6[1] ), + .IIRout_p7 (IIRout_p7[1] ) ); -IIR_top inst_iir_top_2 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1]), - .IIRin_p1_r4 (IIRin_p1_r[3]), - .IIRin_p2_r6 (IIRin_p2_r[5]), - .IIRin_p3_r8 (IIRin_p3_r[7]), - .IIRin_p4_r10 (IIRin_p4_r[9]), - .IIRin_p5_r12 (IIRin_p5_r[11]), - .IIRin_p6_r14 (IIRin_p6_r[13]), - .a_re (a_re2 ), - .a_im (a_im2 ), - .b_re (b_re2 ), - .b_im (b_im2 ), - .ab_re (ab_re2 ), - .ab_im (ab_im2 ), - .abb_re (abb_re2 ), - .abb_im (abb_im2 ), - .ab_pow3_re (ab_pow3_re2 ), - .ab_pow3_im (ab_pow3_im2 ), - .ab_pow4_re (ab_pow4_re2 ), - .ab_pow4_im (ab_pow4_im2 ), - .ab_pow5_re (ab_pow5_re2 ), - .ab_pow5_im (ab_pow5_im2 ), - .ab_pow6_re (ab_pow6_re2 ), - .ab_pow6_im (ab_pow6_im2 ), - .ab_pow7_re (ab_pow7_re2 ), - .ab_pow7_im (ab_pow7_im2 ), - .b_pow8_re (b_pow8_re2 ), - .b_pow8_im (b_pow8_im2 ), - .IIRout_p0 (IIRout_p0[2] ), - .IIRout_p1 (IIRout_p1[2] ), - .IIRout_p2 (IIRout_p2[2] ), - .IIRout_p3 (IIRout_p3[2] ), - .IIRout_p4 (IIRout_p4[2] ), - .IIRout_p5 (IIRout_p5[2] ), - .IIRout_p6 (IIRout_p6[2] ), - .IIRout_p7 (IIRout_p7[2] ) +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_2 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re2 ), + .a_im (a_im2 ), + .b_re (b_re2 ), + .b_im (b_im2 ), + .ab_re (ab_re2 ), + .ab_im (ab_im2 ), + .abb_re (abb_re2 ), + .abb_im (abb_im2 ), + .ab_pow3_re (ab_pow3_re2 ), + .ab_pow3_im (ab_pow3_im2 ), + .ab_pow4_re (ab_pow4_re2 ), + .ab_pow4_im (ab_pow4_im2 ), + .ab_pow5_re (ab_pow5_re2 ), + .ab_pow5_im (ab_pow5_im2 ), + .ab_pow6_re (ab_pow6_re2 ), + .ab_pow6_im (ab_pow6_im2 ), + .ab_pow7_re (ab_pow7_re2 ), + .ab_pow7_im (ab_pow7_im2 ), + .b_pow8_re (b_pow8_re2 ), + .b_pow8_im (b_pow8_im2 ), + .IIRout_p0 (IIRout_p0[2] ), + .IIRout_p1 (IIRout_p1[2] ), + .IIRout_p2 (IIRout_p2[2] ), + .IIRout_p3 (IIRout_p3[2] ), + .IIRout_p4 (IIRout_p4[2] ), + .IIRout_p5 (IIRout_p5[2] ), + .IIRout_p6 (IIRout_p6[2] ), + .IIRout_p7 (IIRout_p7[2] ) ); -IIR_top inst_iir_top_3 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1]), - .IIRin_p1_r4 (IIRin_p1_r[3]), - .IIRin_p2_r6 (IIRin_p2_r[5]), - .IIRin_p3_r8 (IIRin_p3_r[7]), - .IIRin_p4_r10 (IIRin_p4_r[9]), - .IIRin_p5_r12 (IIRin_p5_r[11]), - .IIRin_p6_r14 (IIRin_p6_r[13]), - .a_re (a_re3 ), - .a_im (a_im3 ), - .b_re (b_re3 ), - .b_im (b_im3 ), - .ab_re (ab_re3 ), - .ab_im (ab_im3 ), - .abb_re (abb_re3 ), - .abb_im (abb_im3 ), - .ab_pow3_re (ab_pow3_re3 ), - .ab_pow3_im (ab_pow3_im3 ), - .ab_pow4_re (ab_pow4_re3 ), - .ab_pow4_im (ab_pow4_im3 ), - .ab_pow5_re (ab_pow5_re3 ), - .ab_pow5_im (ab_pow5_im3 ), - .ab_pow6_re (ab_pow6_re3 ), - .ab_pow6_im (ab_pow6_im3 ), - .ab_pow7_re (ab_pow7_re3 ), - .ab_pow7_im (ab_pow7_im3 ), - .b_pow8_re (b_pow8_re3 ), - .b_pow8_im (b_pow8_im3 ), - .IIRout_p0 (IIRout_p0[3] ), - .IIRout_p1 (IIRout_p1[3] ), - .IIRout_p2 (IIRout_p2[3] ), - .IIRout_p3 (IIRout_p3[3] ), - .IIRout_p4 (IIRout_p4[3] ), - .IIRout_p5 (IIRout_p5[3] ), - .IIRout_p6 (IIRout_p6[3] ), - .IIRout_p7 (IIRout_p7[3] ) +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_3 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re3 ), + .a_im (a_im3 ), + .b_re (b_re3 ), + .b_im (b_im3 ), + .ab_re (ab_re3 ), + .ab_im (ab_im3 ), + .abb_re (abb_re3 ), + .abb_im (abb_im3 ), + .ab_pow3_re (ab_pow3_re3 ), + .ab_pow3_im (ab_pow3_im3 ), + .ab_pow4_re (ab_pow4_re3 ), + .ab_pow4_im (ab_pow4_im3 ), + .ab_pow5_re (ab_pow5_re3 ), + .ab_pow5_im (ab_pow5_im3 ), + .ab_pow6_re (ab_pow6_re3 ), + .ab_pow6_im (ab_pow6_im3 ), + .ab_pow7_re (ab_pow7_re3 ), + .ab_pow7_im (ab_pow7_im3 ), + .b_pow8_re (b_pow8_re3 ), + .b_pow8_im (b_pow8_im3 ), + .IIRout_p0 (IIRout_p0[3] ), + .IIRout_p1 (IIRout_p1[3] ), + .IIRout_p2 (IIRout_p2[3] ), + .IIRout_p3 (IIRout_p3[3] ), + .IIRout_p4 (IIRout_p4[3] ), + .IIRout_p5 (IIRout_p5[3] ), + .IIRout_p6 (IIRout_p6[3] ), + .IIRout_p7 (IIRout_p7[3] ) ); -IIR_top inst_iir_top_4 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1]), - .IIRin_p1_r4 (IIRin_p1_r[3]), - .IIRin_p2_r6 (IIRin_p2_r[5]), - .IIRin_p3_r8 (IIRin_p3_r[7]), - .IIRin_p4_r10 (IIRin_p4_r[9]), - .IIRin_p5_r12 (IIRin_p5_r[11]), - .IIRin_p6_r14 (IIRin_p6_r[13]), - .a_re (a_re4 ), - .a_im (a_im4 ), - .b_re (b_re4 ), - .b_im (b_im4 ), - .ab_re (ab_re4 ), - .ab_im (ab_im4 ), - .abb_re (abb_re4 ), - .abb_im (abb_im4 ), - .ab_pow3_re (ab_pow3_re4 ), - .ab_pow3_im (ab_pow3_im4 ), - .ab_pow4_re (ab_pow4_re4 ), - .ab_pow4_im (ab_pow4_im4 ), - .ab_pow5_re (ab_pow5_re4 ), - .ab_pow5_im (ab_pow5_im4 ), - .ab_pow6_re (ab_pow6_re4 ), - .ab_pow6_im (ab_pow6_im4 ), - .ab_pow7_re (ab_pow7_re4 ), - .ab_pow7_im (ab_pow7_im4 ), - .b_pow8_re (b_pow8_re4 ), - .b_pow8_im (b_pow8_im4 ), - .IIRout_p0 (IIRout_p0[4] ), - .IIRout_p1 (IIRout_p1[4] ), - .IIRout_p2 (IIRout_p2[4] ), - .IIRout_p3 (IIRout_p3[4] ), - .IIRout_p4 (IIRout_p4[4] ), - .IIRout_p5 (IIRout_p5[4] ), - .IIRout_p6 (IIRout_p6[4] ), - .IIRout_p7 (IIRout_p7[4] ) +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_4 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re4 ), + .a_im (a_im4 ), + .b_re (b_re4 ), + .b_im (b_im4 ), + .ab_re (ab_re4 ), + .ab_im (ab_im4 ), + .abb_re (abb_re4 ), + .abb_im (abb_im4 ), + .ab_pow3_re (ab_pow3_re4 ), + .ab_pow3_im (ab_pow3_im4 ), + .ab_pow4_re (ab_pow4_re4 ), + .ab_pow4_im (ab_pow4_im4 ), + .ab_pow5_re (ab_pow5_re4 ), + .ab_pow5_im (ab_pow5_im4 ), + .ab_pow6_re (ab_pow6_re4 ), + .ab_pow6_im (ab_pow6_im4 ), + .ab_pow7_re (ab_pow7_re4 ), + .ab_pow7_im (ab_pow7_im4 ), + .b_pow8_re (b_pow8_re4 ), + .b_pow8_im (b_pow8_im4 ), + .IIRout_p0 (IIRout_p0[4] ), + .IIRout_p1 (IIRout_p1[4] ), + .IIRout_p2 (IIRout_p2[4] ), + .IIRout_p3 (IIRout_p3[4] ), + .IIRout_p4 (IIRout_p4[4] ), + .IIRout_p5 (IIRout_p5[4] ), + .IIRout_p6 (IIRout_p6[4] ), + .IIRout_p7 (IIRout_p7[4] ) ); -IIR_top inst_iir_top_5 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1]), - .IIRin_p1_r4 (IIRin_p1_r[3]), - .IIRin_p2_r6 (IIRin_p2_r[5]), - .IIRin_p3_r8 (IIRin_p3_r[7]), - .IIRin_p4_r10 (IIRin_p4_r[9]), - .IIRin_p5_r12 (IIRin_p5_r[11]), - .IIRin_p6_r14 (IIRin_p6_r[13]), - .a_re (a_re5 ), - .a_im (a_im5 ), - .b_re (b_re5 ), - .b_im (b_im5 ), - .ab_re (ab_re5 ), - .ab_im (ab_im5 ), - .abb_re (abb_re5 ), - .abb_im (abb_im5 ), - .ab_pow3_re (ab_pow3_re5 ), - .ab_pow3_im (ab_pow3_im5 ), - .ab_pow4_re (ab_pow4_re5 ), - .ab_pow4_im (ab_pow4_im5 ), - .ab_pow5_re (ab_pow5_re5 ), - .ab_pow5_im (ab_pow5_im5 ), - .ab_pow6_re (ab_pow6_re5 ), - .ab_pow6_im (ab_pow6_im5 ), - .ab_pow7_re (ab_pow7_re5 ), - .ab_pow7_im (ab_pow7_im5 ), - .b_pow8_re (b_pow8_re5 ), - .b_pow8_im (b_pow8_im5 ), - .IIRout_p0 (IIRout_p0[5] ), - .IIRout_p1 (IIRout_p1[5] ), - .IIRout_p2 (IIRout_p2[5] ), - .IIRout_p3 (IIRout_p3[5] ), - .IIRout_p4 (IIRout_p4[5] ), - .IIRout_p5 (IIRout_p5[5] ), - .IIRout_p6 (IIRout_p6[5] ), - .IIRout_p7 (IIRout_p7[5] ) +IIR_top #( + .data_out_width (temp_var_width ) +) inst_iir_top_5 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .IIRin_p0 (IIRin_p0 ), + .IIRin_p1 (IIRin_p1 ), + .IIRin_p2 (IIRin_p2 ), + .IIRin_p3 (IIRin_p3 ), + .IIRin_p4 (IIRin_p4 ), + .IIRin_p5 (IIRin_p5 ), + .IIRin_p6 (IIRin_p6 ), + .IIRin_p7 (IIRin_p7 ), + .IIRin_p0_r2 (IIRin_p0_r[1] ), + .IIRin_p1_r4 (IIRin_p1_r[3] ), + .IIRin_p2_r6 (IIRin_p2_r[5] ), + .IIRin_p3_r8 (IIRin_p3_r[7] ), + .IIRin_p4_r10 (IIRin_p4_r[9] ), + .IIRin_p5_r12 (IIRin_p5_r[11] ), + .IIRin_p6_r14 (IIRin_p6_r[13] ), + .a_re (a_re5 ), + .a_im (a_im5 ), + .b_re (b_re5 ), + .b_im (b_im5 ), + .ab_re (ab_re5 ), + .ab_im (ab_im5 ), + .abb_re (abb_re5 ), + .abb_im (abb_im5 ), + .ab_pow3_re (ab_pow3_re5 ), + .ab_pow3_im (ab_pow3_im5 ), + .ab_pow4_re (ab_pow4_re5 ), + .ab_pow4_im (ab_pow4_im5 ), + .ab_pow5_re (ab_pow5_re5 ), + .ab_pow5_im (ab_pow5_im5 ), + .ab_pow6_re (ab_pow6_re5 ), + .ab_pow6_im (ab_pow6_im5 ), + .ab_pow7_re (ab_pow7_re5 ), + .ab_pow7_im (ab_pow7_im5 ), + .b_pow8_re (b_pow8_re5 ), + .b_pow8_im (b_pow8_im5 ), + .IIRout_p0 (IIRout_p0[5] ), + .IIRout_p1 (IIRout_p1[5] ), + .IIRout_p2 (IIRout_p2[5] ), + .IIRout_p3 (IIRout_p3[5] ), + .IIRout_p4 (IIRout_p4[5] ), + .IIRout_p5 (IIRout_p5[5] ), + .IIRout_p6 (IIRout_p6[5] ), + .IIRout_p7 (IIRout_p7[5] ) ); assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] +IIRout_p0[2] +IIRout_p0[3] +IIRout_p0[4] +IIRout_p0[5]; From 6e386a27436e98570e4040365931c186c7ddc629 Mon Sep 17 00:00:00 2001 From: futh0403 Date: Thu, 13 Mar 2025 21:02:23 +0800 Subject: [PATCH 5/5] =?UTF-8?q?=E5=90=88=E5=B9=B6main=E5=88=86=E6=94=AF?= =?UTF-8?q?=E7=9A=84=E9=83=A8=E5=88=86=E4=BF=AE=E6=94=B9=20-=E5=B0=BD?= =?UTF-8?q?=E9=87=8F=E9=81=BF=E5=85=8D=E4=BD=BF=E7=94=A8for=E5=BE=AA?= =?UTF-8?q?=E7=8E=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- rtl/z_dsp/IIR_Filter_p8.v | 66 +++---- rtl/z_dsp/IIR_top.v | 32 ---- rtl/z_dsp/TailCorr_top.v | 184 +++++++++++++------ rtl/z_dsp/diff_p.v | 247 +++++++++++++------------ rtl/z_dsp/s2p_2.v | 85 +++------ rtl/z_dsp/sirv_gnrl_dffs.v | 326 +++++++++++++++++++++++++++++++++ script_m/TailCorr_Test_Verdi.m | 10 +- sim/files.f | 1 + 8 files changed, 648 insertions(+), 303 deletions(-) create mode 100644 rtl/z_dsp/sirv_gnrl_dffs.v diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index 762f219..fd2d49a 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -1,36 +1,3 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : IIR_Filter.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.4 2024-05-28 thfu -//2024-05-28 10:22:49 -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module IIR_Filter_p8 #( parameter coef_width = 32 ,parameter data_in_width = 16 @@ -74,9 +41,36 @@ module IIR_Filter_p8 #( ,output signed [data_out_width-1:0] dout_im // Im(y(8n-8)) ); -wire signed [data_in_width-1 :0] dinp [7:0] = {dinp7 , dinp6 , dinp5 ,dinp4 , dinp3 , dinp2 , dinp1, dinp0}; -wire signed [coef_width-1 :0] ab_pow_re [7:0] = {ab_pow7_re, ab_pow6_re, ab_pow5_re ,ab_pow4_re, ab_pow3_re, abb_re, ab_re, a_re }; -wire signed [coef_width-1 :0] ab_pow_im [7:0] = {ab_pow7_im, ab_pow6_im, ab_pow5_im ,ab_pow4_im, ab_pow3_im, abb_im, ab_im, a_im }; +wire signed [data_in_width-1 :0] dinp [7:0]; +assign dinp[7] = dinp7; +assign dinp[6] = dinp6; +assign dinp[5] = dinp5; +assign dinp[4] = dinp4; +assign dinp[3] = dinp3; +assign dinp[2] = dinp2; +assign dinp[1] = dinp1; +assign dinp[0] = dinp0; + +wire signed [coef_width-1 :0] ab_pow_re [7:0]; +assign ab_pow_re[7] = ab_pow7_re; +assign ab_pow_re[6] = ab_pow6_re; +assign ab_pow_re[5] = ab_pow5_re; +assign ab_pow_re[4] = ab_pow4_re; +assign ab_pow_re[3] = ab_pow3_re; +assign ab_pow_re[2] = abb_re; +assign ab_pow_re[1] = ab_re; +assign ab_pow_re[0] = a_re; + +wire signed [coef_width-1 :0] ab_pow_im [7:0]; +assign ab_pow_im[7] = ab_pow7_im; +assign ab_pow_im[6] = ab_pow6_im; +assign ab_pow_im[5] = ab_pow5_im; +assign ab_pow_im[4] = ab_pow4_im; +assign ab_pow_im[3] = ab_pow3_im; +assign ab_pow_im[2] = abb_im; +assign ab_pow_im[1] = ab_im; +assign ab_pow_im[0] = a_im; + wire signed [temp_var_width-1 :0] x_re [0:7]; wire signed [temp_var_width-1 :0] x_im [0:7]; diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index d9bcd91..049a24c 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -1,35 +1,3 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : TailCorr_top.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.3 2024-05-15 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module IIR_top #( parameter data_out_width = 23 diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index c7fd5d3..ca87ee0 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -1,35 +1,3 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : TailCorr_top.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.3 2025-02-28 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module TailCorr_top #( parameter temp_var_width = 22 @@ -207,14 +175,14 @@ wire signed [temp_var_width+2:0] sum_IIRout_p4; wire signed [temp_var_width+2:0] sum_IIRout_p5; wire signed [temp_var_width+2:0] sum_IIRout_p6; wire signed [temp_var_width+2:0] sum_IIRout_p7; -reg signed [15:0] din_p0_r [15:0]; -reg signed [15:0] din_p1_r [15:0]; -reg signed [15:0] din_p2_r [15:0]; -reg signed [15:0] din_p3_r [15:0]; -reg signed [15:0] din_p4_r [15:0]; -reg signed [15:0] din_p5_r [15:0]; -reg signed [15:0] din_p6_r [15:0]; -reg signed [15:0] din_p7_r [15:0]; +reg signed [15:0] din_p0_r [16:0]; +reg signed [15:0] din_p1_r [16:0]; +reg signed [15:0] din_p2_r [16:0]; +reg signed [15:0] din_p3_r [16:0]; +reg signed [15:0] din_p4_r [16:0]; +reg signed [15:0] din_p5_r [16:0]; +reg signed [15:0] din_p6_r [16:0]; +reg signed [15:0] din_p7_r [16:0]; reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7) reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22) reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37) @@ -270,7 +238,7 @@ diff_p inst_diff_p ( integer i; always @(posedge clk or negedge rstn) begin if (!rstn) begin - for (i = 0; i < 17; i = i + 1) begin + for (i = 0; i < 16; i = i + 1) begin din_p0_r[i] <= 'h0; din_p1_r[i] <= 'h0; din_p2_r[i] <= 'h0; @@ -290,7 +258,7 @@ always @(posedge clk or negedge rstn) begin din_p5_r[0] <= din_p5; din_p6_r[0] <= din_p6; din_p7_r[0] <= din_p7; - for (i = 0; i < 15; i = i + 1) begin + for (i = 0; i < 16; i = i + 1) begin din_p0_r[i+1] <= din_p0_r[i]; din_p1_r[i+1] <= din_p1_r[i]; din_p2_r[i+1] <= din_p2_r[i]; @@ -302,7 +270,121 @@ always @(posedge clk or negedge rstn) begin end end end +/* +wire signed [15:0] din_p0_r1; +wire signed [15:0] din_p1_r1; +wire signed [15:0] din_p2_r1; +wire signed [15:0] din_p3_r1; +wire signed [15:0] din_p4_r1; +wire signed [15:0] din_p5_r1; +wire signed [15:0] din_p6_r1; +wire signed [15:0] din_p7_r1; +wire signed [15:0] din_p0_r2; +wire signed [15:0] din_p1_r2; +wire signed [15:0] din_p2_r2; +wire signed [15:0] din_p3_r2; +wire signed [15:0] din_p4_r2; +wire signed [15:0] din_p5_r2; +wire signed [15:0] din_p6_r2; +wire signed [15:0] din_p7_r2; +wire signed [15:0] din_p0_r3; +wire signed [15:0] din_p1_r3; +wire signed [15:0] din_p2_r3; +wire signed [15:0] din_p3_r3; +wire signed [15:0] din_p4_r3; +wire signed [15:0] din_p5_r3; +wire signed [15:0] din_p6_r3; +wire signed [15:0] din_p7_r3; +wire signed [15:0] din_p0_r4; +wire signed [15:0] din_p1_r4; +wire signed [15:0] din_p2_r4; +wire signed [15:0] din_p3_r4; +wire signed [15:0] din_p4_r4; +wire signed [15:0] din_p5_r4; +wire signed [15:0] din_p6_r4; +wire signed [15:0] din_p7_r4; +wire signed [15:0] din_p0_r5; +wire signed [15:0] din_p1_r5; +wire signed [15:0] din_p2_r5; +wire signed [15:0] din_p3_r5; +wire signed [15:0] din_p4_r5; +wire signed [15:0] din_p5_r5; +wire signed [15:0] din_p6_r5; +wire signed [15:0] din_p7_r5; +wire signed [15:0] din_p0_r6; +wire signed [15:0] din_p1_r6; +wire signed [15:0] din_p2_r6; +wire signed [15:0] din_p3_r6; +wire signed [15:0] din_p4_r6; +wire signed [15:0] din_p5_r6; +wire signed [15:0] din_p6_r6; +wire signed [15:0] din_p7_r6; +wire signed [15:0] din_p0_r7; +wire signed [15:0] din_p1_r7; +wire signed [15:0] din_p2_r7; +wire signed [15:0] din_p3_r7; +wire signed [15:0] din_p4_r7; +wire signed [15:0] din_p5_r7; +wire signed [15:0] din_p6_r7; +wire signed [15:0] din_p7_r7; +sirv_gnrl_dfflr #(16) dff_din_p0_1(en,din_p0, din_p0_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_1(en,din_p1, din_p1_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_1(en,din_p2, din_p2_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_1(en,din_p3, din_p3_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_1(en,din_p4, din_p4_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_1(en,din_p5, din_p5_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_1(en,din_p6, din_p6_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_1(en,din_p7, din_p7_r1 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_2(en,din_p0_r1, din_p0_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_2(en,din_p1_r1, din_p1_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_2(en,din_p2_r1, din_p2_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_2(en,din_p3_r1, din_p3_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_2(en,din_p4_r1, din_p4_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_2(en,din_p5_r1, din_p5_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_2(en,din_p6_r1, din_p6_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_2(en,din_p7_r1, din_p7_r2 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_3(en,din_p0_r2, din_p0_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_3(en,din_p1_r2, din_p1_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_3(en,din_p2_r2, din_p2_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_3(en,din_p3_r2, din_p3_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_3(en,din_p4_r2, din_p4_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_3(en,din_p5_r2, din_p5_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_3(en,din_p6_r2, din_p6_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_3(en,din_p7_r2, din_p7_r3 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_4(en,din_p0_r3, din_p0_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_4(en,din_p1_r3, din_p1_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_4(en,din_p2_r3, din_p2_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_4(en,din_p3_r3, din_p3_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_4(en,din_p4_r3, din_p4_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_4(en,din_p5_r3, din_p5_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_4(en,din_p6_r3, din_p6_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_4(en,din_p7_r3, din_p7_r4 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_5(en,din_p0_r4, din_p0_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_5(en,din_p1_r4, din_p1_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_5(en,din_p2_r4, din_p2_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_5(en,din_p3_r4, din_p3_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_5(en,din_p4_r4, din_p4_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_5(en,din_p5_r4, din_p5_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_5(en,din_p6_r4, din_p6_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_5(en,din_p7_r4, din_p7_r5 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_6(en,din_p0_r5, din_p0_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_6(en,din_p1_r5, din_p1_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_6(en,din_p2_r5, din_p2_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_6(en,din_p3_r5, din_p3_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_6(en,din_p4_r5, din_p4_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_6(en,din_p5_r5, din_p5_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_6(en,din_p6_r5, din_p6_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_6(en,din_p7_r5, din_p7_r6 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p0_7(en,din_p0_r6, din_p0_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p1_7(en,din_p1_r6, din_p1_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p2_7(en,din_p2_r6, din_p2_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p3_7(en,din_p3_r6, din_p3_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p4_7(en,din_p4_r6, din_p4_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p5_7(en,din_p5_r6, din_p5_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p6_7(en,din_p6_r6, din_p6_r7 ,clk,rstn); +sirv_gnrl_dfflr #(16) dff_din_p7_7(en,din_p7_r6, din_p7_r7 ,clk,rstn); +*/ always @(posedge clk or negedge rstn) begin if (!rstn) begin @@ -745,14 +827,14 @@ always @(posedge clk or negedge rstn) begin end end -assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) -assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) -assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) -assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) -assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115) -assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) -assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) -assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) +assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) +assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) +assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) +assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) +assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-116) +assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) +assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) +assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); @@ -828,7 +910,7 @@ always @(posedge clk or negedge rstn)begin end end assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); -assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ; +assign vldo_r0_h = vldo_diff_r[16] == 0 && vldo_diff_r[15] == 1 ; assign vldo = vldo_r0; endmodule diff --git a/rtl/z_dsp/diff_p.v b/rtl/z_dsp/diff_p.v index b21aea1..d76bdbc 100644 --- a/rtl/z_dsp/diff_p.v +++ b/rtl/z_dsp/diff_p.v @@ -1,48 +1,16 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : TailCorr_top.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.3 2024-05-15 thfu -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- module diff_p ( - input rstn -,input clk -,input en -,input vldi -,input signed [15:0] din0 -,input signed [15:0] din1 -,input signed [15:0] din2 -,input signed [15:0] din3 -,output vldo + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,output vldo ,output signed [15:0] dout_p0 ,output signed [15:0] dout_p1 ,output signed [15:0] dout_p2 @@ -62,89 +30,130 @@ module diff_p ); - -wire [15:0] din_wire [0:3]; - -assign din_wire[0] = din0; -assign din_wire[1] = din1; -assign din_wire[2] = din2; -assign din_wire[3] = din3; +wire signed [15:0] din_p0_r0; +wire signed [15:0] din_p1_r0; +wire signed [15:0] din_p2_r0; +wire signed [15:0] din_p3_r0; +wire signed [15:0] din_p4_r0; +wire signed [15:0] din_p5_r0; +wire signed [15:0] din_p6_r0; +wire signed [15:0] din_p7_r0; +wire vldo_0; +wire vldo_1; +wire vldo_2; +wire vldo_3; +wire vldo_r0; +assign vldo_r0 = vldo_0 || vldo_1 || vldo_2 || vldo_3; +sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn); +s2p_2 inst1_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din0), + .en (vldi), + .dout0 (din_p0_r0), + .dout1 (din_p4_r0) + ,.vldo( vldo_0) + ); +s2p_2 inst2_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din1), + .en (vldi), + .dout0 (din_p1_r0), + .dout1 (din_p5_r0) + ,.vldo( vldo_1) + ); +s2p_2 inst3_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din2), + .en (vldi), + .dout0 (din_p2_r0), + .dout1 (din_p6_r0) + ,.vldo( vldo_2) + ); +s2p_2 inst4_s2p_2 ( + .clk (clk), + .rst_n (rstn), + .din (din3), + .en (vldi), + .dout0 (din_p3_r0), + .dout1 (din_p7_r0) + ,.vldo( vldo_3) + ); -wire [3:0] vldo_temp; -wire signed [15:0] dinp_r0 [7:0]; -genvar i; -generate - for (i = 0; i < 4; i = i + 1) begin: s2p_inst - s2p_2 inst_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din_wire[i]), - .en (vldi), - .dout0 (dinp_r0[i]), - .dout1 (dinp_r0[i+4]), - .vldo (vldo_temp[i]) - ); - end -endgenerate -assign vldo = vldo_temp[0]; +wire signed [15:0] din_p0_r1; +wire signed [15:0] din_p1_r1; +wire signed [15:0] din_p2_r1; +wire signed [15:0] din_p3_r1; +wire signed [15:0] din_p4_r1; +wire signed [15:0] din_p5_r1; +wire signed [15:0] din_p6_r1; +wire signed [15:0] din_p7_r1; -reg signed [15:0] dinp_r1 [0:7]; -integer j; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (j = 0; j < 8; j = j + 1) begin - dinp_r1[j] <= 'h0; - end - end - else if (en) begin - for (j = 0; j < 8; j = j + 1) begin - dinp_r1[j] <= dinp_r0[j]; - end - end +sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn); + +assign dout_p0 = din_p0_r0; +assign dout_p1 = din_p1_r0; +assign dout_p2 = din_p2_r0; +assign dout_p3 = din_p3_r0; +assign dout_p4 = din_p4_r0; +assign dout_p5 = din_p5_r0; +assign dout_p6 = din_p6_r0; +assign dout_p7 = din_p7_r0; + +reg signed [15:0] diff_p0_r1; +reg signed [15:0] diff_p1_r1; +reg signed [15:0] diff_p2_r1; +reg signed [15:0] diff_p3_r1; +reg signed [15:0] diff_p4_r1; +reg signed [15:0] diff_p5_r1; +reg signed [15:0] diff_p6_r1; +reg signed [15:0] diff_p7_r1; + +always @(posedge clk or negedge rstn)begin +if(rstn==1'b0)begin + diff_p0_r1 <= 0; + diff_p1_r1 <= 0; + diff_p2_r1 <= 0; + diff_p3_r1 <= 0; + diff_p4_r1 <= 0; + diff_p5_r1 <= 0; + diff_p6_r1 <= 0; + diff_p7_r1 <= 0; + +end +else if(en)begin + diff_p0_r1 <= din_p0_r0 - din_p7_r1; + diff_p1_r1 <= din_p1_r0 - din_p0_r0; + diff_p2_r1 <= din_p2_r0 - din_p1_r0; + diff_p3_r1 <= din_p3_r0 - din_p2_r0; + diff_p4_r1 <= din_p4_r0 - din_p3_r0; + diff_p5_r1 <= din_p5_r0 - din_p4_r0; + diff_p6_r1 <= din_p6_r0 - din_p5_r0; + diff_p7_r1 <= din_p7_r0 - din_p6_r0; +end +else begin + diff_p0_r1 <= diff_p0_r1; + diff_p1_r1 <= diff_p1_r1; + diff_p2_r1 <= diff_p2_r1; + diff_p3_r1 <= diff_p3_r1; + diff_p4_r1 <= diff_p4_r1; + diff_p5_r1 <= diff_p5_r1; + diff_p6_r1 <= diff_p6_r1; + diff_p7_r1 <= diff_p7_r1; +end end -wire signed [15:0] diffp_r0 [0:7]; -generate - for (i = 0; i < 8; i = i + 1) begin: diff_assign - if (i == 0) - assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7]; - else - assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1]; - end -endgenerate - -assign dout_p0 = dinp_r1[0]; -assign dout_p1 = dinp_r1[1]; -assign dout_p2 = dinp_r1[2]; -assign dout_p3 = dinp_r1[3]; -assign dout_p4 = dinp_r1[4]; -assign dout_p5 = dinp_r1[5]; -assign dout_p6 = dinp_r1[6]; -assign dout_p7 = dinp_r1[7]; - -reg signed [15:0] diffp_r1 [0:7]; -always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (j = 0; j < 8; j = j + 1) begin - diffp_r1[j] <= 0; - end - end - else if (en) begin - for (j = 0; j < 8; j = j + 1) begin - diffp_r1[j] <= diffp_r0[j]; - end - end -end - -assign diff_p0 = diffp_r1[0]; -assign diff_p1 = diffp_r1[1]; -assign diff_p2 = diffp_r1[2]; -assign diff_p3 = diffp_r1[3]; -assign diff_p4 = diffp_r1[4]; -assign diff_p5 = diffp_r1[5]; -assign diff_p6 = diffp_r1[6]; -assign diff_p7 = diffp_r1[7]; +assign diff_p0 = diff_p0_r1; +assign diff_p1 = diff_p1_r1; +assign diff_p2 = diff_p2_r1; +assign diff_p3 = diff_p3_r1; +assign diff_p4 = diff_p4_r1; +assign diff_p5 = diff_p5_r1; +assign diff_p6 = diff_p6_r1; +assign diff_p7 = diff_p7_r1; endmodule diff --git a/rtl/z_dsp/s2p_2.v b/rtl/z_dsp/s2p_2.v index a01e48e..afc6d95 100644 --- a/rtl/z_dsp/s2p_2.v +++ b/rtl/z_dsp/s2p_2.v @@ -8,21 +8,6 @@ module s2p_2 ( output vldo ); -reg en_r1; -reg en_r2; - -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - en_r1 <= 0; - en_r2 <= 0; - end - else begin - en_r1 <= en; - en_r2 <= en_r1; - end -end -assign vldo = en_r2; - reg cnt; wire add_cnt; wire end_cnt; @@ -45,7 +30,8 @@ end assign add_cnt = en == 1'b1; assign end_cnt = add_cnt && cnt== 2 - 1 ; - +wire en_r1; +wire en_r2; reg [ 15: 0] dout0_r0; reg [ 15: 0] dout1_r0; wire dout0_en; @@ -53,66 +39,45 @@ wire dout1_en; wire dout0_hold; wire dout1_hold; -always @(*)begin - if(rst_n==1'b0)begin - dout0_r0 = 16'd0; - dout1_r0 = 16'd0; +always @(posedge clk or negedge rst_n)begin + if(!rst_n)begin + dout0_r0 <= 16'b0; + dout1_r0 <= 16'b0; end else if(dout0_en)begin - dout0_r0 = din; + dout0_r0 <= din; end else if(dout1_en)begin - dout1_r0 = din; - end - else begin - dout0_r0 = 16'd0; - dout1_r0 = 16'd0; - - end -end -assign dout0_en = add_cnt && cnt == 0; -assign dout1_en = add_cnt && cnt == 1; - -reg [ 15: 0] dout0_r1; -reg [ 15: 0] dout1_r1; -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - dout0_r1 <= 16'd0; - dout1_r1 <= 16'd0; - end - else if(en)begin - dout0_r1 <= dout0_r0; - dout1_r1 <= dout1_r0; + dout1_r0 <= din; end else if(dout0_hold)begin - dout0_r1 <= dout0_r1; - dout1_r1 <= 16'd0; + dout0_r0 <= dout0_r0; + dout1_r0 <= 16'd0; end else if(dout1_hold)begin - dout0_r1 <= 16'd0; - dout1_r1 <= dout1_r1; + dout0_r0 <= 16'd0; + dout1_r0 <= dout1_r0; end else begin - dout0_r1 <= 16'd0; - dout1_r1 <= 16'd0; + dout0_r0 <= 16'd0; + dout1_r0 <= 16'd0; end - end + +assign dout0_en = add_cnt && cnt == 0; +assign dout1_en = add_cnt && cnt == 1; assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1; assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0; -reg [ 15: 0] dout0_r2; -always @(posedge clk or negedge rst_n)begin - if(rst_n==1'b0)begin - dout0_r2 <= 16'd0; - end - else begin - dout0_r2 <= dout0_r1; - end -end +sirv_gnrl_dffr #(1) dff_en_1(en , en_r1 ,clk,rst_n); +sirv_gnrl_dffr #(1) dff_en_2(en_r1, en_r2 ,clk,rst_n); +assign vldo = en_r2; -assign dout0 = dout0_r2; -assign dout1 = dout1_r1; +wire [ 15: 0] dout0_r1; +sirv_gnrl_dfflr #(16) dff_dout0_1(1'b1,dout0_r0, dout0_r1 ,clk,rst_n); + +assign dout0 = dout0_r1; +assign dout1 = dout1_r0; endmodule diff --git a/rtl/z_dsp/sirv_gnrl_dffs.v b/rtl/z_dsp/sirv_gnrl_dffs.v new file mode 100644 index 0000000..09e8ba1 --- /dev/null +++ b/rtl/z_dsp/sirv_gnrl_dffs.v @@ -0,0 +1,326 @@ + /* + Copyright 2018-2020 Nuclei System Technology, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + + + +//===================================================================== +// +// Designer : Bob Hu +// +// Description: +// All of the general DFF and Latch modules +// +// ==================================================================== + +// + + +// +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 1 +// +// =========================================================================== +`define DISABLE_SV_ASSERTION +`define dly #0.2 +module sirv_gnrl_dfflrs # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dfflr # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable and Reset +// Default reset value is input +// +// =========================================================================== + +module sirv_gnrl_dfflrd # ( + parameter DW = 32 +) ( + input [DW-1:0] init, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFLR_PROC + if (rst_n == 1'b0) + qout_r <= init; + else if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule + +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Load-enable, no reset +// +// =========================================================================== + +module sirv_gnrl_dffl # ( + parameter DW = 32 +) ( + + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk +); + +reg [DW-1:0] qout_r; + +always @(posedge clk) +begin : DFFL_PROC + if (lden == 1'b1) + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +sirv_gnrl_xchecker # ( + .DW(1) +) sirv_gnrl_xchecker( + .i_dat(lden), + .clk (clk) +); +//synopsys translate_on +`endif//} +`endif//} + + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 1 +// +// =========================================================================== + +module sirv_gnrl_dffrs # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFRS_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b1}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module sirv_gnrl DFF with Reset, no load-enable +// Default reset value is 0 +// +// =========================================================================== + +module sirv_gnrl_dffr # ( + parameter DW = 32 +) ( + + input [DW-1:0] dnxt, + output [DW-1:0] qout, + + input clk, + input rst_n +); + +reg [DW-1:0] qout_r; + +always @(posedge clk or negedge rst_n) +begin : DFFR_PROC + if (rst_n == 1'b0) + qout_r <= {DW{1'b0}}; + else + qout_r <= `dly dnxt; +end + +assign qout = qout_r; + +endmodule +// =========================================================================== +// +// Description: +// Verilog module for general latch +// +// =========================================================================== + +module sirv_gnrl_ltch # ( + parameter DW = 32 +) ( + + //input test_mode, + input lden, + input [DW-1:0] dnxt, + output [DW-1:0] qout +); + +reg [DW-1:0] qout_r; + +always @ * +begin : LTCH_PROC + if (lden == 1'b1) + qout_r <= dnxt; +end + +//assign qout = test_mode ? dnxt : qout_r; +assign qout = qout_r; + +`ifndef FPGA_SOURCE//{ +`ifndef DISABLE_SV_ASSERTION//{ +//synopsys translate_off +always_comb +begin + CHECK_THE_X_VALUE: + assert (lden !== 1'bx) + else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n"); +end + +//synopsys translate_on +`endif//} +`endif//} + + +endmodule diff --git a/script_m/TailCorr_Test_Verdi.m b/script_m/TailCorr_Test_Verdi.m index 37385f5..ad98fe6 100644 --- a/script_m/TailCorr_Test_Verdi.m +++ b/script_m/TailCorr_Test_Verdi.m @@ -2,11 +2,11 @@ clc;clear;close all % addpath("/data/work/thfu/TailCorr/script_m"); data_source = 'matlab'; -file_path = "/home/thfu/work/TailCorr/sim/z_dsp/"; +file_path = "/home/thfu/work/TailCorr/sim/"; rng('shuffle'); if strcmp(data_source, 'matlab') - in = floor(cat(1,0,3000*randn(4*2579+4,1))); + in = floor(cat(1,0,30000*ones(4*2579+4,1))); for i = 0:3 filename = strcat(file_path, "in", num2str(i), "_matlab.dat"); subset = in(i+1:4:end); @@ -33,14 +33,14 @@ end cs_wave = []; -for i = 0:3 +for i = 0:7 filename = strcat(file_path, "dout", num2str(i), ".dat"); dout_data = importdata(filename); if isempty(cs_wave) N = length(dout_data); - cs_wave = zeros(4*N, 1); + cs_wave = zeros(8*N, 1); end - cs_wave(i+1:4:end) = dout_data; + cs_wave(i+1:8:end) = dout_data; end A = [0.025 0.015*1 0.0002*1 0]; diff --git a/sim/files.f b/sim/files.f index 3666571..b6473a6 100644 --- a/sim/files.f +++ b/sim/files.f @@ -7,6 +7,7 @@ ../rtl/z_dsp/s2p_2.v ../rtl/z_dsp/IIR_Filter_p8.v ../rtl/z_dsp/IIR_Filter_p1.v +../rtl/z_dsp/sirv_gnrl_dffs.v ../rtl/ref/mult_C.v ../rtl/ref/FixRound.v ../rtl/ref/TailCorr_top.v