Modify enable signal as clk divided by 2
使能口连时钟二分频； diff_plot.m使用最短的进行对比 Fit modification of enable signal as clk divided by 2 choose the min length to compare Enable of clk_div2 tested on FPGA
This commit is contained in:
futh0403
parent
08484e4771
commit
e058191d12
19
rtl/z_dsp.v
19
rtl/z_dsp.v
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@ -73,7 +73,8 @@ module z_dsp
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dout4,
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dout5,
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dout6,
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dout7
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dout7,
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vldo
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);
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input rstn;
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@ -117,10 +118,24 @@ output signed [15:0] dout4;
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output signed [15:0] dout5;
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output signed [15:0] dout6;
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output signed [15:0] dout7;
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output vldo;
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wire signed [15:0] IIR_out;
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reg [10:0] vldo_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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vldo_r <= 9'b0;
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end
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else
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begin
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vldo_r <= {vldo_r[10:0], en};
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end
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assign vldo = vldo_r[10];
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TailCorr_top inst_TailCorr_top
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(
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.clk (clk ),
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@ -0,0 +1,234 @@
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : Z_dsp_en_Test.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-11-04 thfu Test Enable signal using clk divided by 2
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module z_dsp_en_Test
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(
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clk,
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rstn,
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dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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tc_bypass,
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intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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din_re,
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din_im,
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a0_re, //a0's real part
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a0_im, //a0's image part
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b0_re,
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b0_im,
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a1_re,
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a1_im,
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b1_re,
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b1_im,
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a2_re,
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a2_im,
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b2_re,
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b2_im,
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a3_re,
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a3_im,
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b3_re,
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b3_im,
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a4_re,
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a4_im,
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b4_re,
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b4_im,
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a5_re,
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a5_im,
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b5_re,
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b5_im,
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dout0,
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dout1,
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dout2,
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dout3,
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dout4,
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dout5,
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dout6,
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dout7,
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vldo
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);
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input rstn;
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input clk;
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input tc_bypass;
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input [1:0] intp_mode;
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input [1:0] dac_mode_sel;
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input signed [15:0] din_re;
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input signed [15:0] din_im;
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input signed [36:0] a0_re;
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input signed [36:0] a0_im;
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input signed [20:0] b0_re;
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input signed [20:0] b0_im;
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input signed [36:0] a1_re;
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input signed [36:0] a1_im;
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input signed [20:0] b1_re;
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input signed [20:0] b1_im;
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input signed [36:0] a2_re;
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input signed [36:0] a2_im;
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input signed [20:0] b2_re;
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input signed [20:0] b2_im;
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input signed [36:0] a3_re;
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input signed [36:0] a3_im;
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input signed [20:0] b3_re;
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input signed [20:0] b3_im;
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input signed [36:0] a4_re;
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input signed [36:0] a4_im;
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input signed [20:0] b4_re;
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input signed [20:0] b4_im;
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input signed [36:0] a5_re;
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input signed [36:0] a5_im;
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input signed [20:0] b5_re;
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input signed [20:0] b5_im;
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output signed [15:0] dout0;
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output signed [15:0] dout1;
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output signed [15:0] dout2;
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output signed [15:0] dout3;
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output signed [15:0] dout4;
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output signed [15:0] dout5;
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output signed [15:0] dout6;
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output signed [15:0] dout7;
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output vldo;
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wire signed [15:0] IIR_out;
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reg en;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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en <= 0;
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else
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en <= ~en;
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reg [13:0] vldo_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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vldo_r <= 9'b0;
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end
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else
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begin
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vldo_r <= {vldo_r[13:0], en};
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end
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assign vldo = vldo_r[13];
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TailCorr_top inst_TailCorr_top
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(
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.tc_bypass (tc_bypass ),
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.din_re (din_re ),
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.din_im (din_im ),
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.a0_re (a0_re ),
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.a0_im (a0_im ),
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.b0_re (b0_re ),
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.b0_im (b0_im ),
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.a1_re (a1_re ),
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.a1_im (a1_im ),
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.b1_re (b1_re ),
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.b1_im (b1_im ),
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.a2_re (a2_re ),
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.a2_im (a2_im ),
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.b2_re (b2_re ),
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.b2_im (b2_im ),
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.a3_re (a3_re ),
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.a3_im (a3_im ),
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.b3_re (b3_re ),
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.b3_im (b3_im ),
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.a4_re (a4_re ),
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.a4_im (a4_im ),
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.b4_re (b4_re ),
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.b4_im (b4_im ),
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.a5_re (a5_re ),
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.a5_im (a5_im ),
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.b5_re (b5_re ),
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.b5_im (b5_im ),
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.dout (IIR_out )
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);
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wire signed [15:0] dout_0;
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wire signed [15:0] dout_1;
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wire signed [15:0] dout_2;
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wire signed [15:0] dout_3;
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wire signed [15:0] dout_4;
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wire signed [15:0] dout_5;
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wire signed [15:0] dout_6;
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wire signed [15:0] dout_7;
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MeanIntp_8 inst_MeanIntp_8
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(
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.intp_mode (intp_mode ),
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.din (IIR_out ),
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.dout_0 (dout_0 ),
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.dout_1 (dout_1 ),
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.dout_2 (dout_2 ),
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.dout_3 (dout_3 ),
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.dout_4 (dout_4 ),
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.dout_5 (dout_5 ),
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.dout_6 (dout_6 ),
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.dout_7 (dout_7 )
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);
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lsdacif inst_lsdacif
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(
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.clk (clk ),
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.rstn (rstn ),
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.dac_mode_sel (dac_mode_sel ),
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.intp_mode (intp_mode ),
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.din0 (dout_0 ),
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.din1 (dout_1 ),
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.din2 (dout_2 ),
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.din3 (dout_3 ),
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.din4 (dout_4 ),
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.din5 (dout_5 ),
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.din6 (dout_6 ),
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.din7 (dout_7 ),
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.dout0 (dout0 ),
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.dout1 (dout1 ),
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.dout2 (dout2 ),
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.dout3 (dout3 ),
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.dout4 (dout4 ),
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.dout5 (dout5 ),
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.dout6 (dout6 ),
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.dout7 (dout7 )
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);
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endmodule
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@ -1,6 +1,8 @@
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function diff_plot(iir_out, Script_out,leg1,leg2,a)
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N = length(iir_out);
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N = min(length(iir_out),length(Script_out));
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iir_out = iir_out(1:N);
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Script_out = Script_out(1:N);
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n = 0:1:N-1;
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diff = iir_out-Script_out;
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@ -14,9 +14,10 @@
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../rtl/lsdacif.v
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../rtl/TailCorr_top.v
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../rtl/z_dsp.v
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../rtl/z_dsp_en_Test.v
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../rtl/MeanIntp_8.v
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../rtl/DW02_mult.v
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../rtl/IIR_Filter.v
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../tb/clk_gen.v
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../tb/tb_top.v
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../tb/tb_z_dsp_en_Test.v
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@ -0,0 +1,675 @@
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module TB();
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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end
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reg rstn;
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reg [15:0] din_im;
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reg [31:0] a0_re;
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reg [31:0] a0_im;
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reg [31:0] b0_re;
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reg [31:0] b0_im;
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reg [31:0] a1_re;
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reg [31:0] a1_im;
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reg [31:0] b1_re;
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reg [31:0] b1_im;
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reg [31:0] a2_re;
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reg [31:0] a2_im;
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reg [31:0] b2_re;
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reg [31:0] b2_im;
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reg [31:0] a3_re;
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reg [31:0] a3_im;
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reg [31:0] b3_re;
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reg [31:0] b3_im;
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reg [31:0] a4_re;
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reg [31:0] a4_im;
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reg [31:0] b4_re;
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reg [31:0] b4_im;
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reg [31:0] a5_re;
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reg [31:0] a5_im;
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reg [31:0] b5_re;
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reg [31:0] b5_im;
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reg [47:0] fcw;
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reg [21:0] cnt;
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reg [15:0] din_imp;
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reg [15:0] din_rect;
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reg [15:0] din_cos;
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reg [15:0] iir_in;
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wire [1 :0] source_mode;
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wire [15:0] cos;
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wire [15:0] sin;
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wire [15:0] dout_p0;
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reg en;
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reg clk;
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reg clk_div2;
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reg clk_div4;
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initial
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begin
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#0;
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rstn = 1'b0;
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clk = 1'b0;
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clk_div2 = 1'b0;
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clk_div4 = 1'b0;
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en = 1'b0;
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din_im = 16'd0;
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a0_re = 32'd1757225200;
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a0_im = 32'd0;
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b0_re = -32'd1042856;
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b0_im = 32'd0;
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a1_re = 32'd1045400392;
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a1_im = 32'd0;
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b1_re = -32'd1046395;
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b1_im = 32'd0;
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a2_re = 32'd13740916;
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a2_im = 32'd0;
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b2_re = -32'd1047703;
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b2_im = 32'd0;
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a3_re = 32'd0;
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a3_im = 32'd0;
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b3_re = -32'd0;
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b3_im = 32'd0;
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a4_re = 32'd0;
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a4_im = 32'd0;
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b4_re = -32'd0;
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b4_im = 32'd0;
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a5_re = 32'd0;
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a5_im = 32'd0;
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b5_re = -32'd0;
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b5_im = 32'd0;
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fcw = 48'h0840_0000_0000;
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din_imp = 16'd0;
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din_rect = 16'd0;
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din_cos = 16'd0;
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#300;
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rstn = 1'b1;
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#16600300;
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// din_imp = 16'd30000;
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// din_rect = 16'd30000;
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// en = 1'b1;
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#6400;
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// din_imp = 16'd0;
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#64000;
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// din_rect = 16'd0;
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end
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always #200 clk = ~clk;
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always #400 clk_div2 = ~clk_div2;
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always #800 clk_div4 = ~clk_div4;
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wire clk_div16_0;
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wire clk_div16_1;
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wire clk_div16_2;
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wire clk_div16_3;
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wire clk_div16_4;
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wire clk_div16_5;
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wire clk_div16_6;
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wire clk_div16_7;
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wire clk_div16_8;
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wire clk_div16_9;
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wire clk_div16_a;
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wire clk_div16_b;
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wire clk_div16_c;
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wire clk_div16_d;
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wire clk_div16_e;
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wire clk_div16_f;
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wire clk_l;
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wire clk_h;
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clk_gen inst_clk_gen(
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.rstn (rstn ),
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.clk (clk ),
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.clk_div16_0 (clk_div16_0 ),
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.clk_div16_1 (clk_div16_1 ),
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.clk_div16_2 (clk_div16_2 ),
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.clk_div16_3 (clk_div16_3 ),
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.clk_div16_4 (clk_div16_4 ),
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.clk_div16_5 (clk_div16_5 ),
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.clk_div16_6 (clk_div16_6 ),
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.clk_div16_7 (clk_div16_7 ),
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.clk_div16_8 (clk_div16_8 ),
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.clk_div16_9 (clk_div16_9 ),
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.clk_div16_a (clk_div16_a ),
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.clk_div16_b (clk_div16_b ),
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.clk_div16_c (clk_div16_c ),
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.clk_div16_d (clk_div16_d ),
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.clk_div16_e (clk_div16_e ),
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.clk_div16_f (clk_div16_f ),
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.clk_h (clk_h ),
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.clk_l (clk_l )
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);
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wire clk_div32_0;
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wire clk_div32_1;
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wire clk_div32_2;
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wire clk_div32_3;
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wire clk_div32_4;
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wire clk_div32_5;
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wire clk_div32_6;
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wire clk_div32_7;
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wire clk_div32_8;
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wire clk_div32_9;
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wire clk_div32_a;
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wire clk_div32_b;
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wire clk_div32_c;
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wire clk_div32_d;
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wire clk_div32_e;
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wire clk_div32_f;
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wire clk_l1;
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wire clk_h1;
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clk_gen inst1_clk_gen(
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.rstn (rstn ),
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.clk (clk_div2 ),
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.clk_div16_0 (clk_div32_0 ),
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.clk_div16_1 (clk_div32_1 ),
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.clk_div16_2 (clk_div32_2 ),
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.clk_div16_3 (clk_div32_3 ),
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.clk_div16_4 (clk_div32_4 ),
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.clk_div16_5 (clk_div32_5 ),
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.clk_div16_6 (clk_div32_6 ),
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.clk_div16_7 (clk_div32_7 ),
|
||||
.clk_div16_8 (clk_div32_8 ),
|
||||
.clk_div16_9 (clk_div32_9 ),
|
||||
.clk_div16_a (clk_div32_a ),
|
||||
.clk_div16_b (clk_div32_b ),
|
||||
.clk_div16_c (clk_div32_c ),
|
||||
.clk_div16_d (clk_div32_d ),
|
||||
.clk_div16_e (clk_div32_e ),
|
||||
.clk_div16_f (clk_div32_f ),
|
||||
.clk_h (clk_h1 ),
|
||||
.clk_l (clk_l1 )
|
||||
);
|
||||
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_imp <= 22'd0;
|
||||
else if(cnt == 100)
|
||||
begin
|
||||
din_imp <= 16'd32767;
|
||||
//en <= 1'b1;
|
||||
end
|
||||
else
|
||||
din_imp <= 'h0;
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_rect <= 22'd0;
|
||||
else if(cnt >= 100 && cnt <=10100)
|
||||
begin
|
||||
din_rect <= 16'd30000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_rect <= 16'd0;
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
en <= 22'd0;
|
||||
else if(cnt >= 90 )
|
||||
begin
|
||||
en <= 1'b1;
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_cos <= 16'd0;
|
||||
iir_in <= 16'd0;
|
||||
end
|
||||
else
|
||||
din_cos <= {cos[15],cos[15:1]};
|
||||
|
||||
assign source_mode = 2'b01;
|
||||
|
||||
always @(*)
|
||||
|
||||
case(source_mode)
|
||||
2'b00 : iir_in = din_imp;
|
||||
2'b01 : iir_in = din_rect;
|
||||
2'b10 : iir_in = din_cos;
|
||||
endcase
|
||||
|
||||
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] dout_p0;
|
||||
wire [15:0] dout_p1;
|
||||
wire [15:0] dout_p2;
|
||||
wire [15:0] dout_p3;
|
||||
wire [15:0] dout_p4;
|
||||
wire [15:0] dout_p5;
|
||||
wire [15:0] dout_p6;
|
||||
wire [15:0] dout_p7;
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
assign intp_mode = 2'b11;
|
||||
|
||||
wire [1:0] dac_mode_sel;
|
||||
assign dac_mode_sel = 2'b00;
|
||||
|
||||
wire tc_bypass;
|
||||
assign tc_bypass = 1'b0;
|
||||
|
||||
z_dsp inst_Z_dsp
|
||||
(
|
||||
.clk (clk_h ),
|
||||
.rstn (rstn ),
|
||||
.en (clk_l ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout_p0 ),
|
||||
.dout1 (dout_p1 ),
|
||||
.dout2 (dout_p2 ),
|
||||
.dout3 (dout_p3 ),
|
||||
.dout4 (dout_p4 ),
|
||||
.dout5 (dout_p5 ),
|
||||
.dout6 (dout_p6 ),
|
||||
.dout7 (dout_p7 )
|
||||
|
||||
);
|
||||
|
||||
wire [15:0] dout_clkl_p0;
|
||||
wire [15:0] dout_clkl_p1;
|
||||
wire [15:0] dout_clkl_p2;
|
||||
wire [15:0] dout_clkl_p3;
|
||||
wire [15:0] dout_clkl_p4;
|
||||
wire [15:0] dout_clkl_p5;
|
||||
wire [15:0] dout_clkl_p6;
|
||||
wire [15:0] dout_clkl_p7;
|
||||
|
||||
|
||||
z_dsp inst1_Z_dsp
|
||||
(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout_clkl_p0 ),
|
||||
.dout1 (dout_clkl_p1 ),
|
||||
.dout2 (dout_clkl_p2 ),
|
||||
.dout3 (dout_clkl_p3 ),
|
||||
.dout4 (dout_clkl_p4 ),
|
||||
.dout5 (dout_clkl_p5 ),
|
||||
.dout6 (dout_clkl_p6 ),
|
||||
.dout7 (dout_clkl_p7 )
|
||||
|
||||
);
|
||||
|
||||
reg [15:0] dout_p0_r1 = 0;
|
||||
reg [15:0] dout_p1_r1 = 0;
|
||||
reg [15:0] dout_p2_r1 = 0;
|
||||
reg [15:0] dout_p3_r1 = 0;
|
||||
reg [15:0] dout_p4_r1 = 0;
|
||||
reg [15:0] dout_p5_r1 = 0;
|
||||
reg [15:0] dout_p6_r1 = 0;
|
||||
reg [15:0] dout_p7_r1 = 0;
|
||||
reg [15:0] dout_p0_r2 = 0;
|
||||
reg [15:0] dout_p1_r2 = 0;
|
||||
reg [15:0] dout_p2_r2 = 0;
|
||||
reg [15:0] dout_p3_r2 = 0;
|
||||
reg [15:0] dout_p4_r2 = 0;
|
||||
reg [15:0] dout_p5_r2 = 0;
|
||||
reg [15:0] dout_p6_r2 = 0;
|
||||
reg [15:0] dout_p7_r2 = 0;
|
||||
reg [15:0] dout_p0_r3 = 0;
|
||||
reg [15:0] dout_p1_r3 = 0;
|
||||
reg [15:0] dout_p2_r3 = 0;
|
||||
reg [15:0] dout_p3_r3 = 0;
|
||||
reg [15:0] dout_p4_r3 = 0;
|
||||
reg [15:0] dout_p5_r3 = 0;
|
||||
reg [15:0] dout_p6_r3 = 0;
|
||||
reg [15:0] dout_p7_r3 = 0;
|
||||
|
||||
|
||||
always @(posedge clk_h or negedge rstn ) begin
|
||||
if(!rstn) begin
|
||||
dout_p0_r1 <= 0;
|
||||
dout_p1_r1 <= 0;
|
||||
dout_p2_r1 <= 0;
|
||||
dout_p3_r1 <= 0;
|
||||
dout_p4_r1 <= 0;
|
||||
dout_p5_r1 <= 0;
|
||||
dout_p6_r1 <= 0;
|
||||
dout_p7_r1 <= 0;
|
||||
dout_p0_r2 <= 0;
|
||||
dout_p1_r2 <= 0;
|
||||
dout_p2_r2 <= 0;
|
||||
dout_p3_r2 <= 0;
|
||||
dout_p4_r2 <= 0;
|
||||
dout_p5_r2 <= 0;
|
||||
dout_p6_r2 <= 0;
|
||||
dout_p7_r2 <= 0;
|
||||
dout_p0_r3 <= 0;
|
||||
dout_p1_r3 <= 0;
|
||||
dout_p2_r3 <= 0;
|
||||
dout_p3_r3 <= 0;
|
||||
dout_p4_r3 <= 0;
|
||||
dout_p5_r3 <= 0;
|
||||
dout_p6_r3 <= 0;
|
||||
dout_p7_r3 <= 0;
|
||||
end
|
||||
else begin
|
||||
dout_p0_r1 <= dout_p0;
|
||||
dout_p1_r1 <= dout_p1;
|
||||
dout_p2_r1 <= dout_p2;
|
||||
dout_p3_r1 <= dout_p3;
|
||||
dout_p4_r1 <= dout_p4;
|
||||
dout_p5_r1 <= dout_p5;
|
||||
dout_p6_r1 <= dout_p6;
|
||||
dout_p7_r1 <= dout_p7;
|
||||
dout_p0_r2 <= dout_p0_r1;
|
||||
dout_p1_r2 <= dout_p1_r1;
|
||||
dout_p2_r2 <= dout_p2_r1;
|
||||
dout_p3_r2 <= dout_p3_r1;
|
||||
dout_p4_r2 <= dout_p4_r1;
|
||||
dout_p5_r2 <= dout_p5_r1;
|
||||
dout_p6_r2 <= dout_p6_r1;
|
||||
dout_p7_r2 <= dout_p7_r1;
|
||||
dout_p0_r3 <= dout_p0_r2;
|
||||
dout_p1_r3 <= dout_p1_r2;
|
||||
dout_p2_r3 <= dout_p2_r2;
|
||||
dout_p3_r3 <= dout_p3_r2;
|
||||
dout_p4_r3 <= dout_p4_r2;
|
||||
dout_p5_r3 <= dout_p5_r2;
|
||||
dout_p6_r3 <= dout_p6_r2;
|
||||
dout_p7_r3 <= dout_p7_r2;
|
||||
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] cs_wave = 0;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave = dout_p3;
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
|
||||
@(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
|
||||
@(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
|
||||
@(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
|
||||
@(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
|
||||
@(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
|
||||
@(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
|
||||
@(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
reg [15:0] cs_wave1 = 0;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave1 = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave1 = dout_p3;
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
|
||||
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
|
||||
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
|
||||
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
|
||||
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
|
||||
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
|
||||
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
|
||||
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
wire [15:0] diff;
|
||||
assign diff = cs_wave1 - cs_wave;
|
||||
integer signed In_fid;
|
||||
integer X1_fid;
|
||||
integer X2_fid;
|
||||
integer X4_fid;
|
||||
integer X8_fid;
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
In_fid = $fopen("./in.dat");
|
||||
case (intp_mode)
|
||||
2'b00 : X1_fid = $fopen("./X1_data.dat");
|
||||
2'b01 : X2_fid = $fopen("./X2_data.dat");
|
||||
2'b10 : X4_fid = $fopen("./X4_data.dat");
|
||||
2'b11 : X8_fid = $fopen("./X8_data.dat");
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk_div16_f)
|
||||
if(cnt >= 90)
|
||||
$fwrite(In_fid,"%d\n",{{{~iir_in[15]}},iir_in[14:0]});
|
||||
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
@(posedge clk_div16_a)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
||||
@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
|
||||
@(posedge clk_div16_2)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_f)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
@(posedge clk_div32_d)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
||||
@(posedge clk_div32_b)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
|
||||
@(posedge clk_div32_9)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
|
||||
@(posedge clk_div32_7)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
|
||||
@(posedge clk_div32_5)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
|
||||
@(posedge clk_div32_3)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
|
||||
@(posedge clk_div32_1)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
|
||||
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
/*
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
|
||||
always@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
|
||||
always@(posedge clk_div16_a)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
|
||||
always@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
|
||||
always@(posedge clk_div16_2)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
*/
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -7,7 +7,6 @@ begin
|
|||
end
|
||||
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg [15:0] din_im;
|
||||
|
||||
|
|
@ -51,11 +50,17 @@ wire [15:0] dout_p0;
|
|||
|
||||
reg en;
|
||||
|
||||
reg clk;
|
||||
reg clk_div2;
|
||||
reg clk_div4;
|
||||
|
||||
initial
|
||||
begin
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
clk_div2 = 1'b0;
|
||||
clk_div4 = 1'b0;
|
||||
en = 1'b0;
|
||||
|
||||
din_im = 16'd0;
|
||||
|
|
@ -104,6 +109,8 @@ begin
|
|||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
always #400 clk_div2 = ~clk_div2;
|
||||
always #800 clk_div4 = ~clk_div4;
|
||||
|
||||
wire clk_div16_0;
|
||||
wire clk_div16_1;
|
||||
|
|
@ -121,7 +128,8 @@ wire clk_div16_c;
|
|||
wire clk_div16_d;
|
||||
wire clk_div16_e;
|
||||
wire clk_div16_f;
|
||||
|
||||
wire clk_l;
|
||||
wire clk_h;
|
||||
|
||||
clk_gen inst_clk_gen(
|
||||
.rstn (rstn ),
|
||||
|
|
@ -146,7 +154,50 @@ clk_gen inst_clk_gen(
|
|||
.clk_l (clk_l )
|
||||
);
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
wire clk_div32_0;
|
||||
wire clk_div32_1;
|
||||
wire clk_div32_2;
|
||||
wire clk_div32_3;
|
||||
wire clk_div32_4;
|
||||
wire clk_div32_5;
|
||||
wire clk_div32_6;
|
||||
wire clk_div32_7;
|
||||
wire clk_div32_8;
|
||||
wire clk_div32_9;
|
||||
wire clk_div32_a;
|
||||
wire clk_div32_b;
|
||||
wire clk_div32_c;
|
||||
wire clk_div32_d;
|
||||
wire clk_div32_e;
|
||||
wire clk_div32_f;
|
||||
wire clk_l1;
|
||||
wire clk_h1;
|
||||
|
||||
clk_gen inst1_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk_div2 ),
|
||||
.clk_div16_0 (clk_div32_0 ),
|
||||
.clk_div16_1 (clk_div32_1 ),
|
||||
.clk_div16_2 (clk_div32_2 ),
|
||||
.clk_div16_3 (clk_div32_3 ),
|
||||
.clk_div16_4 (clk_div32_4 ),
|
||||
.clk_div16_5 (clk_div32_5 ),
|
||||
.clk_div16_6 (clk_div32_6 ),
|
||||
.clk_div16_7 (clk_div32_7 ),
|
||||
.clk_div16_8 (clk_div32_8 ),
|
||||
.clk_div16_9 (clk_div32_9 ),
|
||||
.clk_div16_a (clk_div32_a ),
|
||||
.clk_div16_b (clk_div32_b ),
|
||||
.clk_div16_c (clk_div32_c ),
|
||||
.clk_div16_d (clk_div32_d ),
|
||||
.clk_div16_e (clk_div32_e ),
|
||||
.clk_div16_f (clk_div32_f ),
|
||||
.clk_h (clk_h1 ),
|
||||
.clk_l (clk_l1 )
|
||||
);
|
||||
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
|
|
@ -158,7 +209,7 @@ begin
|
|||
$finish(0);
|
||||
end
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_imp <= 22'd0;
|
||||
else if(cnt == 100)
|
||||
|
|
@ -169,7 +220,7 @@ always@(posedge clk_div16_f or negedge rstn)
|
|||
else
|
||||
din_imp <= 'h0;
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_rect <= 22'd0;
|
||||
else if(cnt >= 100 && cnt <=10100)
|
||||
|
|
@ -181,7 +232,7 @@ always@(posedge clk_div16_f or negedge rstn)
|
|||
din_rect <= 16'd0;
|
||||
end
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
en <= 22'd0;
|
||||
else if(cnt >= 90 )
|
||||
|
|
@ -189,7 +240,7 @@ always@(posedge clk_div16_f or negedge rstn)
|
|||
en <= 1'b1;
|
||||
end
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_cos <= 16'd0;
|
||||
|
|
@ -198,7 +249,7 @@ always@(posedge clk_div16_f or negedge rstn)
|
|||
else
|
||||
din_cos <= {cos[15],cos[15:1]};
|
||||
|
||||
assign source_mode = 2'b10;
|
||||
assign source_mode = 2'b01;
|
||||
|
||||
always @(*)
|
||||
|
||||
|
|
@ -212,7 +263,7 @@ always @(*)
|
|||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk_div16_f ),
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
|
|
@ -241,11 +292,10 @@ assign dac_mode_sel = 2'b00;
|
|||
wire tc_bypass;
|
||||
assign tc_bypass = 1'b0;
|
||||
|
||||
z_dsp inst_Z_dsp
|
||||
z_dsp_en_Test inst_Z_dsp_en_Test
|
||||
(
|
||||
.clk (clk_div16_f ),
|
||||
.clk (clk_h ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
|
|
@ -286,6 +336,143 @@ z_dsp inst_Z_dsp
|
|||
|
||||
);
|
||||
|
||||
wire [15:0] dout_clkl_p0;
|
||||
wire [15:0] dout_clkl_p1;
|
||||
wire [15:0] dout_clkl_p2;
|
||||
wire [15:0] dout_clkl_p3;
|
||||
wire [15:0] dout_clkl_p4;
|
||||
wire [15:0] dout_clkl_p5;
|
||||
wire [15:0] dout_clkl_p6;
|
||||
wire [15:0] dout_clkl_p7;
|
||||
|
||||
|
||||
z_dsp inst1_Z_dsp
|
||||
(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout_clkl_p0 ),
|
||||
.dout1 (dout_clkl_p1 ),
|
||||
.dout2 (dout_clkl_p2 ),
|
||||
.dout3 (dout_clkl_p3 ),
|
||||
.dout4 (dout_clkl_p4 ),
|
||||
.dout5 (dout_clkl_p5 ),
|
||||
.dout6 (dout_clkl_p6 ),
|
||||
.dout7 (dout_clkl_p7 )
|
||||
|
||||
);
|
||||
|
||||
reg [15:0] dout_p0_r1 = 0;
|
||||
reg [15:0] dout_p1_r1 = 0;
|
||||
reg [15:0] dout_p2_r1 = 0;
|
||||
reg [15:0] dout_p3_r1 = 0;
|
||||
reg [15:0] dout_p4_r1 = 0;
|
||||
reg [15:0] dout_p5_r1 = 0;
|
||||
reg [15:0] dout_p6_r1 = 0;
|
||||
reg [15:0] dout_p7_r1 = 0;
|
||||
reg [15:0] dout_p0_r2 = 0;
|
||||
reg [15:0] dout_p1_r2 = 0;
|
||||
reg [15:0] dout_p2_r2 = 0;
|
||||
reg [15:0] dout_p3_r2 = 0;
|
||||
reg [15:0] dout_p4_r2 = 0;
|
||||
reg [15:0] dout_p5_r2 = 0;
|
||||
reg [15:0] dout_p6_r2 = 0;
|
||||
reg [15:0] dout_p7_r2 = 0;
|
||||
reg [15:0] dout_p0_r3 = 0;
|
||||
reg [15:0] dout_p1_r3 = 0;
|
||||
reg [15:0] dout_p2_r3 = 0;
|
||||
reg [15:0] dout_p3_r3 = 0;
|
||||
reg [15:0] dout_p4_r3 = 0;
|
||||
reg [15:0] dout_p5_r3 = 0;
|
||||
reg [15:0] dout_p6_r3 = 0;
|
||||
reg [15:0] dout_p7_r3 = 0;
|
||||
|
||||
|
||||
always @(posedge clk_h or negedge rstn ) begin
|
||||
if(!rstn) begin
|
||||
dout_p0_r1 <= 0;
|
||||
dout_p1_r1 <= 0;
|
||||
dout_p2_r1 <= 0;
|
||||
dout_p3_r1 <= 0;
|
||||
dout_p4_r1 <= 0;
|
||||
dout_p5_r1 <= 0;
|
||||
dout_p6_r1 <= 0;
|
||||
dout_p7_r1 <= 0;
|
||||
dout_p0_r2 <= 0;
|
||||
dout_p1_r2 <= 0;
|
||||
dout_p2_r2 <= 0;
|
||||
dout_p3_r2 <= 0;
|
||||
dout_p4_r2 <= 0;
|
||||
dout_p5_r2 <= 0;
|
||||
dout_p6_r2 <= 0;
|
||||
dout_p7_r2 <= 0;
|
||||
dout_p0_r3 <= 0;
|
||||
dout_p1_r3 <= 0;
|
||||
dout_p2_r3 <= 0;
|
||||
dout_p3_r3 <= 0;
|
||||
dout_p4_r3 <= 0;
|
||||
dout_p5_r3 <= 0;
|
||||
dout_p6_r3 <= 0;
|
||||
dout_p7_r3 <= 0;
|
||||
end
|
||||
else begin
|
||||
dout_p0_r1 <= dout_p0;
|
||||
dout_p1_r1 <= dout_p1;
|
||||
dout_p2_r1 <= dout_p2;
|
||||
dout_p3_r1 <= dout_p3;
|
||||
dout_p4_r1 <= dout_p4;
|
||||
dout_p5_r1 <= dout_p5;
|
||||
dout_p6_r1 <= dout_p6;
|
||||
dout_p7_r1 <= dout_p7;
|
||||
dout_p0_r2 <= dout_p0_r1;
|
||||
dout_p1_r2 <= dout_p1_r1;
|
||||
dout_p2_r2 <= dout_p2_r1;
|
||||
dout_p3_r2 <= dout_p3_r1;
|
||||
dout_p4_r2 <= dout_p4_r1;
|
||||
dout_p5_r2 <= dout_p5_r1;
|
||||
dout_p6_r2 <= dout_p6_r1;
|
||||
dout_p7_r2 <= dout_p7_r1;
|
||||
dout_p0_r3 <= dout_p0_r2;
|
||||
dout_p1_r3 <= dout_p1_r2;
|
||||
dout_p2_r3 <= dout_p2_r2;
|
||||
dout_p3_r3 <= dout_p3_r2;
|
||||
dout_p4_r3 <= dout_p4_r2;
|
||||
dout_p5_r3 <= dout_p5_r2;
|
||||
dout_p6_r3 <= dout_p6_r2;
|
||||
dout_p7_r3 <= dout_p7_r2;
|
||||
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] cs_wave = 0;
|
||||
|
||||
|
|
@ -310,19 +497,59 @@ always@(*)
|
|||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_c) cs_wave = dout_p1;
|
||||
@(posedge clk_div16_a) cs_wave = dout_p2;
|
||||
@(posedge clk_div16_8) cs_wave = dout_p3;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p4;
|
||||
@(posedge clk_div16_4) cs_wave = dout_p5;
|
||||
@(posedge clk_div16_2) cs_wave = dout_p6;
|
||||
@(posedge clk_div16_0) cs_wave = dout_p7;
|
||||
@(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
|
||||
@(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
|
||||
@(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
|
||||
@(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
|
||||
@(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
|
||||
@(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
|
||||
@(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
|
||||
@(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
reg [15:0] cs_wave1 = 0;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave1 = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave1 = dout_p3;
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
|
||||
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
|
||||
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
|
||||
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
|
||||
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
|
||||
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
|
||||
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
|
||||
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
wire [15:0] diff;
|
||||
assign diff = cs_wave1 - cs_wave;
|
||||
integer signed In_fid;
|
||||
integer X1_fid;
|
||||
integer X2_fid;
|
||||
|
|
@ -382,28 +609,28 @@ always@(*)
|
|||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div16_e)
|
||||
@(posedge clk_div32_f)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
@(posedge clk_div16_c)
|
||||
@(posedge clk_div32_d)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
||||
@(posedge clk_div16_a)
|
||||
@(posedge clk_div32_b)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
|
||||
@(posedge clk_div16_8)
|
||||
@(posedge clk_div32_9)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
|
||||
@(posedge clk_div16_6)
|
||||
@(posedge clk_div32_7)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
|
||||
@(posedge clk_div16_4)
|
||||
@(posedge clk_div32_5)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
|
||||
@(posedge clk_div16_2)
|
||||
@(posedge clk_div32_3)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
|
||||
@(posedge clk_div16_0)
|
||||
@(posedge clk_div32_1)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
|
||||
|
||||
|
|
@ -441,7 +668,6 @@ always@(posedge clk_div16_2)
|
|||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
*/
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
Loading…
Reference in New Issue