init
This commit is contained in:
commit
dcd8166010
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////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: KB WSFDB June 30, 1994
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: 714fe7a9
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Multiplier
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// A_width-Bits * B_width-Bits => A_width+B_width Bits
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// Operands A and B can be either both signed (two's complement) or
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// both unsigned numbers. TC determines the coding of the input operands.
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// ie. TC = '1' => signed multiplication
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// TC = '0' => unsigned multiplication
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//
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// FIXED: by replacement with A tested working version
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// that not only doesn't multiplies right it does it
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// two times faster!
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// RPH 07/17/2002
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// Rewrote to comply with the new guidelines
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//------------------------------------------------------------------------------
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module DW02_mult(A,B,TC,PRODUCT);
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parameter integer A_width = 8;
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parameter integer B_width = 8;
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input [A_width-1:0] A;
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input [B_width-1:0] B;
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input TC;
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output [A_width+B_width-1:0] PRODUCT;
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wire [A_width+B_width-1:0] PRODUCT;
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wire [A_width-1:0] temp_a;
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wire [B_width-1:0] temp_b;
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wire [A_width+B_width-2:0] long_temp1,long_temp2;
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (A_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)",
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A_width );
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end
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if (B_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)",
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B_width );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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assign temp_a = (A[A_width-1])? (~A + 1'b1) : A;
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assign temp_b = (B[B_width-1])? (~B + 1'b1) : B;
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assign long_temp1 = temp_a * temp_b;
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assign long_temp2 = ~(long_temp1 - 1'b1);
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assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} :
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(TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))?
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{1'b1,long_temp2} : {1'b0,long_temp1})
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: A * B;
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endmodule
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@ -0,0 +1,103 @@
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module IIR_Filter (
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clk,
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rstn,
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din_re,
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din_im,
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a_re,
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a_im,
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b_re,
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b_im,
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dout
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);
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input rstn;
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input clk;
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input signed [15:0] din_re;
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input signed [15:0] din_im;
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input signed [31:0] a_re;
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input signed [31:0] a_im;
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input signed [31:0] b_re;
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input signed [31:0] b_im;
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output signed [15:0] dout;
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wire signed [48:0] mult_x_re;
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wire signed [48:0] mult_x_im;
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wire signed [54:0] mult_y_re;
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wire signed [54:0] mult_y_im;
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wire signed [15:0] dout_t;
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wire signed [50:0] Ysum_re;
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wire signed [50:0] Ysum_im;
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reg signed [15:0] dout_r1;
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reg signed [50:0] YsumR_re;
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reg signed [50:0] YsumR_im;
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reg signed [50:0] YsumR1_re;
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reg signed [50:0] YsumR1_im;
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mult_C #(16,16,32,32) inst_c1 ( .a (din_re ),
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.b (din_im ),
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.c (a_re ),
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.d (a_im ),
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.Re (mult_x_re ),
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.Im (mult_x_im )
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);
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mult_C #(32,32,32,32) inst_c2 ( .a (YsumR_re ),
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.b (YsumR_im ),
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.c (b_re ),
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.d (b_im ),
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.Re (mult_y_re ),
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.Im (mult_y_im )
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);
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assign Ysum_re = mult_x_re - mult_y_re;
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assign Ysum_im = mult_x_im - mult_y_im;
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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YsumR_re <= 'h0;
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YsumR_im <= 'h0;
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end
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else
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begin
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YsumR_re <= {{20{Ysum_re[50]}},Ysum_re[50:20]} + Ysum_re[50];
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YsumR_im <= {{20{Ysum_im[50]}},Ysum_im[50:20]} + Ysum_im[50];
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end
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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YsumR1_re <= 'h0;
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end
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else
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begin
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YsumR1_re <= {{16{YsumR_re[50]}},YsumR_re[50:16]};
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end
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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dout_r1 <= 'h0;
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end
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else
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begin
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if(YsumR1_re[16:15]==2'b01)
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dout_r1 <= 16'd32767;
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else if(YsumR1_re[16:15]==2'b10)
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dout_r1 <= -16'd32768;
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else
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dout_r1 <= YsumR1_re[15:0];
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end
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assign dout = dout_r1;
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endmodule
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@ -0,0 +1,209 @@
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module TailCorr_top
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(
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clk,
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rstn,
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din_re,
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din_im,
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a0_re,
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a0_im,
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b0_re,
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b0_im,
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a1_re,
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a1_im,
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b1_re,
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b1_im,
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a2_re,
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a2_im,
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b2_re,
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b2_im,
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a3_re,
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a3_im,
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b3_re,
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b3_im,
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a4_re,
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a4_im,
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b4_re,
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b4_im,
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a5_re,
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a5_im,
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b5_re,
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b5_im,
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dout
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);
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input rstn;
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input clk;
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input signed [15:0] din_re;
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input signed [15:0] din_im;
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input signed [31:0] a0_re;
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input signed [31:0] a0_im;
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input signed [31:0] b0_re;
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input signed [31:0] b0_im;
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input signed [31:0] a1_re;
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input signed [31:0] a1_im;
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input signed [31:0] b1_re;
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input signed [31:0] b1_im;
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input signed [31:0] a2_re;
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input signed [31:0] a2_im;
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input signed [31:0] b2_re;
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input signed [31:0] b2_im;
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input signed [31:0] a3_re;
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input signed [31:0] a3_im;
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input signed [31:0] b3_re;
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input signed [31:0] b3_im;
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input signed [31:0] a4_re;
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input signed [31:0] a4_im;
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input signed [31:0] b4_re;
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input signed [31:0] b4_im;
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input signed [31:0] a5_re;
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input signed [31:0] a5_im;
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input signed [31:0] b5_re;
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input signed [31:0] b5_im;
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output signed [15:0] dout;
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wire signed [15:0] IIRin_re;
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wire signed [15:0] IIRin_im;
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wire signed [15:0] dout_0;
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wire signed [15:0] dout_1;
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wire signed [15:0] dout_2;
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wire signed [15:0] dout_3;
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wire signed [15:0] dout_4;
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wire signed [15:0] dout_5;
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wire signed [18:0] Ysum;
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reg signed [15:0] din_r0;
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reg signed [15:0] din_r1;
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reg signed [15:0] din_r2;
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reg signed [15:0] din_r3;
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reg signed [15:0] din_r4;
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reg signed [15:0] dout_r;
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diff inst_diffRe
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(
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.clk (clk ),
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.rstn (rstn ),
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.din (din_re ),
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.dout (IIRin_re )
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);
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diff inst_diffIm
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(
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.clk (clk ),
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.rstn (rstn ),
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.din (din_im ),
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.dout (IIRin_im )
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);
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IIR_Filter inst_iir_0 (
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.clk (clk ),
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.rstn (rstn ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a0_re ),
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.a_im (a0_im ),
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.b_re (b0_re ),
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.b_im (b0_im ),
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.dout (dout_0 )
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);
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IIR_Filter inst_iir_1 (
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.clk (clk ),
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.rstn (rstn ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a1_re ),
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.a_im (a1_im ),
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.b_re (b1_re ),
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.b_im (b1_im ),
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.dout (dout_1 )
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);
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IIR_Filter inst_iir_2 (
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.clk (clk ),
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.rstn (rstn ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a2_re ),
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.a_im (a2_im ),
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.b_re (b2_re ),
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.b_im (b2_im ),
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.dout (dout_2 )
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);
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IIR_Filter inst_iir_3 (
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.clk (clk ),
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.rstn (rstn ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a3_re ),
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.a_im (a3_im ),
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.b_re (b3_re ),
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.b_im (b3_im ),
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.dout (dout_3 )
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);
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IIR_Filter inst_iir_4 (
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.clk (clk ),
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.rstn (rstn ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a4_re ),
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.a_im (a4_im ),
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.b_re (b4_re ),
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.b_im (b4_im ),
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.dout (dout_4 )
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);
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IIR_Filter inst_iir_5 (
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.clk (clk ),
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.rstn (rstn ),
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.din_re (IIRin_re ),
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.din_im (IIRin_im ),
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.a_re (a5_re ),
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.a_im (a5_im ),
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.b_re (b5_re ),
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.b_im (b5_im ),
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.dout (dout_5 )
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);
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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din_r0 <= 'h0;
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din_r1 <= 'h0;
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din_r2 <= 'h0;
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din_r3 <= 'h0;
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din_r4 <= 'h0;
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end
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else
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begin
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din_r0 <= din_re;
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din_r1 <= din_r0;
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din_r2 <= din_r1;
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din_r3 <= din_r2;
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din_r4 <= din_r3;
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end
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assign Ysum = dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4;
|
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|
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always@(posedge clk or negedge rstn)
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if (!rstn)
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begin
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dout_r <= 'h0;
|
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end
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else
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begin
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if(Ysum[16:15]==2'b01)
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dout_r <= 16'd32767;
|
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else if(Ysum[16:15]==2'b10)
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dout_r <= -16'd32768;
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else
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dout_r <= Ysum[15:0];
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end
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assign dout = dout_r;
|
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endmodule
|
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|
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@ -0,0 +1,37 @@
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module diff(
|
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clk,
|
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rstn,
|
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din,
|
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dout
|
||||
);
|
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|
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|
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input rstn;
|
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input clk;
|
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input signed [15:0] din;
|
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|
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output signed [15:0] dout;
|
||||
|
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|
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reg [15:0] din_r;
|
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reg [15:0] din_r1;
|
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reg [15:0] out_r;
|
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|
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always@(posedge clk or negedge rstn)
|
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if(!rstn)
|
||||
begin
|
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din_r <= 16'd0;
|
||||
din_r1 <= 16'd0;
|
||||
|
||||
out_r <= 16'd0;
|
||||
end
|
||||
else
|
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begin
|
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din_r <= din;
|
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din_r1 <= din_r;
|
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|
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out_r <= din_r - din_r1;
|
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end
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assign dout = out_r;
|
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|
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endmodule
|
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|
|
@ -0,0 +1,53 @@
|
|||
module mult_C(
|
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a,
|
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b,
|
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c,
|
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d,
|
||||
Re,
|
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Im
|
||||
);
|
||||
|
||||
parameter integer A_width = 8;
|
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parameter integer B_width = 8;
|
||||
parameter integer C_width = 8;
|
||||
parameter integer D_width = 8;
|
||||
|
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input signed [A_width-1:0] a;
|
||||
input signed [B_width-1:0] b;
|
||||
input signed [C_width-1:0] c;
|
||||
input signed [D_width-1:0] d;
|
||||
|
||||
output signed [A_width+C_width:0] Re;
|
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output signed [A_width+D_width:0] Im;
|
||||
|
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wire signed [A_width+C_width-1:0] ac;
|
||||
wire signed [B_width+D_width-1:0] bd;
|
||||
wire signed [A_width+D_width-1:0] ad;
|
||||
wire signed [B_width+C_width-1:0] bc;
|
||||
|
||||
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ac )
|
||||
);
|
||||
|
||||
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bd )
|
||||
);
|
||||
|
||||
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ad )
|
||||
);
|
||||
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bc )
|
||||
);
|
||||
assign Re = ac - bd;
|
||||
assign Im = ad + bc;
|
||||
|
||||
endmodule
|
||||
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