From dabe5478db391831927ff998d98abb0b312a39a7 Mon Sep 17 00:00:00 2001 From: thfu <2779155576@qq.com> Date: Mon, 17 Mar 2025 14:31:37 +0800 Subject: [PATCH] Real --- rtl/z_dsp/CoefGen.sv | 280 ++------------------------------------ rtl/z_dsp/IIR_Filter_p1.v | 51 ++----- rtl/z_dsp/IIR_Filter_p8.v | 68 ++------- rtl/z_dsp/IIR_top.v | 176 ++++++++---------------- rtl/z_dsp/TailCorr_top.v | 120 ---------------- rtl/z_dsp/mult_C.v | 117 ---------------- rtl/z_dsp/mult_real.v | 39 ++++++ rtl/z_dsp/mult_x.v | 99 -------------- rtl/z_dsp/z_dsp.v | 156 +-------------------- sim/z_dsp/files.f | 5 +- sim/z_dsp/tb_z_dsp.v | 34 +---- 11 files changed, 137 insertions(+), 1008 deletions(-) delete mode 100644 rtl/z_dsp/mult_C.v create mode 100644 rtl/z_dsp/mult_real.v delete mode 100644 rtl/z_dsp/mult_x.v diff --git a/rtl/z_dsp/CoefGen.sv b/rtl/z_dsp/CoefGen.sv index 62fe8e8..a31dcf4 100644 --- a/rtl/z_dsp/CoefGen.sv +++ b/rtl/z_dsp/CoefGen.sv @@ -9,149 +9,77 @@ module CoefGen #( ,input clk ,input [5:0] vldi ,input signed [31:0] a0_re -,input signed [31:0] a0_im ,input signed [31:0] b0_re -,input signed [31:0] b0_im ,input signed [31:0] a1_re -,input signed [31:0] a1_im ,input signed [31:0] b1_re -,input signed [31:0] b1_im ,input signed [31:0] a2_re -,input signed [31:0] a2_im ,input signed [31:0] b2_re -,input signed [31:0] b2_im ,input signed [31:0] a3_re -,input signed [31:0] a3_im ,input signed [31:0] b3_re -,input signed [31:0] b3_im ,input signed [31:0] a4_re -,input signed [31:0] a4_im ,input signed [31:0] b4_re -,input signed [31:0] b4_im ,input signed [31:0] a5_re -,input signed [31:0] a5_im ,input signed [31:0] b5_re -,input signed [31:0] b5_im ,output reg signed [31:0] a_re0 -,output reg signed [31:0] a_im0 ,output reg signed [31:0] b_re0 -,output reg signed [31:0] b_im0 ,output reg signed [31:0] ab_re0 -,output reg signed [31:0] ab_im0 ,output reg signed [31:0] abb_re0 -,output reg signed [31:0] abb_im0 ,output reg signed [31:0] ab_pow3_re0 -,output reg signed [31:0] ab_pow3_im0 ,output reg signed [31:0] ab_pow4_re0 -,output reg signed [31:0] ab_pow4_im0 ,output reg signed [31:0] ab_pow5_re0 -,output reg signed [31:0] ab_pow5_im0 ,output reg signed [31:0] ab_pow6_re0 -,output reg signed [31:0] ab_pow6_im0 ,output reg signed [31:0] ab_pow7_re0 -,output reg signed [31:0] ab_pow7_im0 ,output reg signed [31:0] b_pow8_re0 -,output reg signed [31:0] b_pow8_im0 ,output reg signed [31:0] a_re1 -,output reg signed [31:0] a_im1 ,output reg signed [31:0] b_re1 -,output reg signed [31:0] b_im1 ,output reg signed [31:0] ab_re1 -,output reg signed [31:0] ab_im1 ,output reg signed [31:0] abb_re1 -,output reg signed [31:0] abb_im1 ,output reg signed [31:0] ab_pow3_re1 -,output reg signed [31:0] ab_pow3_im1 ,output reg signed [31:0] ab_pow4_re1 -,output reg signed [31:0] ab_pow4_im1 ,output reg signed [31:0] ab_pow5_re1 -,output reg signed [31:0] ab_pow5_im1 ,output reg signed [31:0] ab_pow6_re1 -,output reg signed [31:0] ab_pow6_im1 ,output reg signed [31:0] ab_pow7_re1 -,output reg signed [31:0] ab_pow7_im1 ,output reg signed [31:0] b_pow8_re1 -,output reg signed [31:0] b_pow8_im1 ,output reg signed [31:0] a_re2 -,output reg signed [31:0] a_im2 ,output reg signed [31:0] b_re2 -,output reg signed [31:0] b_im2 ,output reg signed [31:0] ab_re2 -,output reg signed [31:0] ab_im2 ,output reg signed [31:0] abb_re2 -,output reg signed [31:0] abb_im2 ,output reg signed [31:0] ab_pow3_re2 -,output reg signed [31:0] ab_pow3_im2 ,output reg signed [31:0] ab_pow4_re2 -,output reg signed [31:0] ab_pow4_im2 ,output reg signed [31:0] ab_pow5_re2 -,output reg signed [31:0] ab_pow5_im2 ,output reg signed [31:0] ab_pow6_re2 -,output reg signed [31:0] ab_pow6_im2 ,output reg signed [31:0] ab_pow7_re2 -,output reg signed [31:0] ab_pow7_im2 ,output reg signed [31:0] b_pow8_re2 -,output reg signed [31:0] b_pow8_im2 ,output reg signed [31:0] a_re3 -,output reg signed [31:0] a_im3 ,output reg signed [31:0] b_re3 -,output reg signed [31:0] b_im3 ,output reg signed [31:0] ab_re3 -,output reg signed [31:0] ab_im3 ,output reg signed [31:0] abb_re3 -,output reg signed [31:0] abb_im3 ,output reg signed [31:0] ab_pow3_re3 -,output reg signed [31:0] ab_pow3_im3 ,output reg signed [31:0] ab_pow4_re3 -,output reg signed [31:0] ab_pow4_im3 ,output reg signed [31:0] ab_pow5_re3 -,output reg signed [31:0] ab_pow5_im3 ,output reg signed [31:0] ab_pow6_re3 -,output reg signed [31:0] ab_pow6_im3 ,output reg signed [31:0] ab_pow7_re3 -,output reg signed [31:0] ab_pow7_im3 ,output reg signed [31:0] b_pow8_re3 -,output reg signed [31:0] b_pow8_im3 ,output reg signed [31:0] a_re4 -,output reg signed [31:0] a_im4 ,output reg signed [31:0] b_re4 -,output reg signed [31:0] b_im4 ,output reg signed [31:0] ab_re4 -,output reg signed [31:0] ab_im4 ,output reg signed [31:0] abb_re4 -,output reg signed [31:0] abb_im4 ,output reg signed [31:0] ab_pow3_re4 -,output reg signed [31:0] ab_pow3_im4 ,output reg signed [31:0] ab_pow4_re4 -,output reg signed [31:0] ab_pow4_im4 ,output reg signed [31:0] ab_pow5_re4 -,output reg signed [31:0] ab_pow5_im4 ,output reg signed [31:0] ab_pow6_re4 -,output reg signed [31:0] ab_pow6_im4 ,output reg signed [31:0] ab_pow7_re4 -,output reg signed [31:0] ab_pow7_im4 ,output reg signed [31:0] b_pow8_re4 -,output reg signed [31:0] b_pow8_im4 ,output reg signed [31:0] a_re5 -,output reg signed [31:0] a_im5 ,output reg signed [31:0] b_re5 -,output reg signed [31:0] b_im5 ,output reg signed [31:0] ab_re5 -,output reg signed [31:0] ab_im5 ,output reg signed [31:0] abb_re5 -,output reg signed [31:0] abb_im5 ,output reg signed [31:0] ab_pow3_re5 -,output reg signed [31:0] ab_pow3_im5 ,output reg signed [31:0] ab_pow4_re5 -,output reg signed [31:0] ab_pow4_im5 ,output reg signed [31:0] ab_pow5_re5 -,output reg signed [31:0] ab_pow5_im5 ,output reg signed [31:0] ab_pow6_re5 -,output reg signed [31:0] ab_pow6_im5 ,output reg signed [31:0] ab_pow7_re5 -,output reg signed [31:0] ab_pow7_im5 ,output reg signed [31:0] b_pow8_re5 -,output reg signed [31:0] b_pow8_im5 ); @@ -160,60 +88,42 @@ wire vldi_or = | vldi; sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn); reg signed [data_in_width-1:0] a_re_r1; -reg signed [data_in_width-1:0] a_im_r1; reg signed [data_in_width-1:0] b_re_r1; -reg signed [data_in_width-1:0] b_im_r1; always @(posedge clk or negedge rstn) begin if(rstn == 1'b0) begin a_re_r1 <= 'h0; - a_im_r1 <= 'h0; b_re_r1 <= 'h0; - b_im_r1 <= 'h0; end else if(|vldi) begin case(1'b1) vldi[0]: begin a_re_r1 <= a0_re; - a_im_r1 <= a0_im; b_re_r1 <= b0_re; - b_im_r1 <= b0_im; end vldi[1]: begin a_re_r1 <= a1_re; - a_im_r1 <= a1_im; b_re_r1 <= b1_re; - b_im_r1 <= b1_im; end vldi[2]: begin a_re_r1 <= a2_re; - a_im_r1 <= a2_im; b_re_r1 <= b2_re; - b_im_r1 <= b2_im; end vldi[3]: begin a_re_r1 <= a3_re; - a_im_r1 <= a3_im; b_re_r1 <= b3_re; - b_im_r1 <= b3_im; end vldi[4]: begin a_re_r1 <= a4_re; - a_im_r1 <= a4_im; b_re_r1 <= b4_re; - b_im_r1 <= b4_im; end vldi[5]: begin a_re_r1 <= a5_re; - a_im_r1 <= a5_im; b_re_r1 <= b5_re; - b_im_r1 <= b5_im; end // default: begin // a_re_r1 <= a_re[0]; -// a_im_r1 <= a_im[0]; // b_re_r1 <= b_re[0]; -// b_im_r1 <= b_im[0]; // end endcase end @@ -259,142 +169,97 @@ assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0; assign en_l = end_cnt0; reg signed [data_in_width-1:0] bin_re; -reg signed [data_in_width-1:0] bin_im; wire signed [data_in_width-1:0] bout_re; -wire signed [data_in_width-1:0] bout_im; always @(*)begin if(en_r1) begin bin_re <= bout_re; - bin_im <= bout_im; end else begin bin_re <= 32'd2147483647; - bin_im <= 0; end end -mult_C +mult_real #( .A_width(data_in_width) -,.B_width(data_in_width) ,.C_width(coef_width) -,.D_width(coef_width) ,.o_width(data_in_width) ) inst_c1 ( .clk (clk ), .rstn (rstn ), .en (en ), - .a (bin_re ), - .b (bin_im ), - .c (b_re_r1 ), - .d (b_im_r1 ), - .Re (bout_re ), - .Im (bout_im ) + .din (bin_re ), + .coef (b_re_r1 ), + .dout (bout_re ) ); wire signed [data_in_width-1:0] abo_re; -wire signed [data_in_width-1:0] abo_im; -mult_C +mult_real #( .A_width(data_in_width) -,.B_width(data_in_width) ,.C_width(coef_width) -,.D_width(coef_width) ,.o_width(data_in_width) ) inst_c2 ( .clk (clk ), .rstn (rstn ), .en (en ), - .a (bin_re ), - .b (bin_im ), - .c (a_re_r1 ), - .d (a_im_r1 ), - .Re (abo_re ), - .Im (abo_im ) + .din (bin_re ), + .coef (a_re_r1 ), + .dout (abo_re ) ); reg signed [coef_width-1 :0] ao_re_r1 ; -reg signed [coef_width-1 :0] ao_im_r1 ; reg signed [coef_width-1 :0] ab_re_r1 ; -reg signed [coef_width-1 :0] ab_im_r1 ; reg signed [coef_width-1 :0] abb_re_r1 ; -reg signed [coef_width-1 :0] abb_im_r1 ; reg signed [coef_width-1 :0] ab_pow3_re_r1 ; -reg signed [coef_width-1 :0] ab_pow3_im_r1 ; reg signed [coef_width-1 :0] ab_pow4_re_r1 ; -reg signed [coef_width-1 :0] ab_pow4_im_r1 ; reg signed [coef_width-1 :0] ab_pow5_re_r1 ; -reg signed [coef_width-1 :0] ab_pow5_im_r1 ; reg signed [coef_width-1 :0] ab_pow6_re_r1 ; -reg signed [coef_width-1 :0] ab_pow6_im_r1 ; reg signed [coef_width-1 :0] ab_pow7_re_r1 ; -reg signed [coef_width-1 :0] ab_pow7_im_r1 ; reg signed [coef_width-1 :0] bo_re_r1 ; -reg signed [coef_width-1 :0] bo_im_r1 ; reg signed [coef_width-1 :0] b_pow8_re_r1 ; -reg signed [coef_width-1 :0] b_pow8_im_r1 ; always @(posedge clk or negedge rstn)begin if(!rstn)begin ao_re_r1 <= 0; - ao_im_r1 <= 0; ab_re_r1 <= 0; - ab_im_r1 <= 0; abb_re_r1 <= 0; - abb_im_r1 <= 0; ab_pow3_re_r1 <= 0; - ab_pow3_im_r1 <= 0; ab_pow4_re_r1 <= 0; - ab_pow4_im_r1 <= 0; ab_pow5_re_r1 <= 0; - ab_pow5_im_r1 <= 0; ab_pow6_re_r1 <= 0; - ab_pow6_im_r1 <= 0; ab_pow7_re_r1 <= 0; - ab_pow7_im_r1 <= 0; bo_re_r1 <= 0; - bo_im_r1 <= 0; b_pow8_re_r1 <= 0; - b_pow8_im_r1 <= 0; end else if(add_cnt0 && cnt0 == 1 && en_r1)begin ao_re_r1 <= abo_re; - ao_im_r1 <= abo_im; bo_re_r1 <= bin_re; - bo_im_r1 <= bin_im; end else if(add_cnt0 && cnt0 == 2 && en_r1)begin ab_re_r1 <= abo_re; - ab_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 3 && en_r1)begin abb_re_r1 <= abo_re; - abb_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 4 && en_r1)begin ab_pow3_re_r1 <= abo_re; - ab_pow3_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 5 && en_r1)begin ab_pow4_re_r1 <= abo_re; - ab_pow4_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 6 && en_r1)begin ab_pow5_re_r1 <= abo_re; - ab_pow5_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 7 && en_r1)begin ab_pow6_re_r1 <= abo_re; - ab_pow6_im_r1 <= abo_im; end else if(cnt0 == 0 && en_r1)begin ab_pow7_re_r1 <= abo_re; - ab_pow7_im_r1 <= abo_im; b_pow8_re_r1 <= bin_re; - b_pow8_im_r1 <= bin_im; end // else begin // end @@ -424,279 +289,150 @@ sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn); always @(posedge clk or negedge rstn) begin if(!rstn) begin a_re0 <= 0; - a_im0 <= 0; b_re0 <= 0; - b_im0 <= 0; ab_re0 <= 0; - ab_im0 <= 0; abb_re0 <= 0; - abb_im0 <= 0; ab_pow3_re0 <= 0; - ab_pow3_im0 <= 0; ab_pow4_re0 <= 0; - ab_pow4_im0 <= 0; ab_pow5_re0 <= 0; - ab_pow5_im0 <= 0; ab_pow6_re0 <= 0; - ab_pow6_im0 <= 0; ab_pow7_re0 <= 0; - ab_pow7_im0 <= 0; b_pow8_re0 <= 0; - b_pow8_im0 <= 0; a_re1 <= 0; - a_im1 <= 0; b_re1 <= 0; - b_im1 <= 0; ab_re1 <= 0; - ab_im1 <= 0; abb_re1 <= 0; - abb_im1 <= 0; ab_pow3_re1 <= 0; - ab_pow3_im1 <= 0; ab_pow4_re1 <= 0; - ab_pow4_im1 <= 0; ab_pow5_re1 <= 0; - ab_pow5_im1 <= 0; ab_pow6_re1 <= 0; - ab_pow6_im1 <= 0; ab_pow7_re1 <= 0; - ab_pow7_im1 <= 0; b_pow8_re1 <= 0; - b_pow8_im1 <= 0; a_re2 <= 0; - a_im2 <= 0; b_re2 <= 0; - b_im2 <= 0; ab_re2 <= 0; - ab_im2 <= 0; abb_re2 <= 0; - abb_im2 <= 0; ab_pow3_re2 <= 0; - ab_pow3_im2 <= 0; ab_pow4_re2 <= 0; - ab_pow4_im2 <= 0; ab_pow5_re2 <= 0; - ab_pow5_im2 <= 0; ab_pow6_re2 <= 0; - ab_pow6_im2 <= 0; ab_pow7_re2 <= 0; - ab_pow7_im2 <= 0; b_pow8_re2 <= 0; - b_pow8_im2 <= 0; a_re3 <= 0; - a_im3 <= 0; b_re3 <= 0; - b_im3 <= 0; ab_re3 <= 0; - ab_im3 <= 0; abb_re3 <= 0; - abb_im3 <= 0; ab_pow3_re3 <= 0; - ab_pow3_im3 <= 0; ab_pow4_re3 <= 0; - ab_pow4_im3 <= 0; ab_pow5_re3 <= 0; - ab_pow5_im3 <= 0; ab_pow6_re3 <= 0; - ab_pow6_im3 <= 0; ab_pow7_re3 <= 0; - ab_pow7_im3 <= 0; b_pow8_re3 <= 0; - b_pow8_im3 <= 0; a_re4 <= 0; - a_im4 <= 0; b_re4 <= 0; - b_im4 <= 0; ab_re4 <= 0; - ab_im4 <= 0; abb_re4 <= 0; - abb_im4 <= 0; ab_pow3_re4 <= 0; - ab_pow3_im4 <= 0; ab_pow4_re4 <= 0; - ab_pow4_im4 <= 0; ab_pow5_re4 <= 0; - ab_pow5_im4 <= 0; ab_pow6_re4 <= 0; - ab_pow6_im4 <= 0; ab_pow7_re4 <= 0; - ab_pow7_im4 <= 0; b_pow8_re4 <= 0; - b_pow8_im4 <= 0; a_re5 <= 0; - a_im5 <= 0; b_re5 <= 0; - b_im5 <= 0; ab_re5 <= 0; - ab_im5 <= 0; abb_re5 <= 0; - abb_im5 <= 0; ab_pow3_re5 <= 0; - ab_pow3_im5 <= 0; ab_pow4_re5 <= 0; - ab_pow4_im5 <= 0; ab_pow5_re5 <= 0; - ab_pow5_im5 <= 0; ab_pow6_re5 <= 0; - ab_pow6_im5 <= 0; ab_pow7_re5 <= 0; - ab_pow7_im5 <= 0; b_pow8_re5 <= 0; - b_pow8_im5 <= 0; end else if(|vldi_r10) begin case(1'b1) vldi_r10[0]: begin a_re0 <= ao_re_r1 ; - a_im0 <= ao_im_r1 ; b_re0 <= bo_re_r1 ; - b_im0 <= bo_im_r1 ; ab_re0 <= ab_re_r1 ; - ab_im0 <= ab_im_r1 ; abb_re0 <= abb_re_r1 ; - abb_im0 <= abb_im_r1 ; ab_pow3_re0 <= ab_pow3_re_r1; - ab_pow3_im0 <= ab_pow3_im_r1; ab_pow4_re0 <= ab_pow4_re_r1; - ab_pow4_im0 <= ab_pow4_im_r1; ab_pow5_re0 <= ab_pow5_re_r1; - ab_pow5_im0 <= ab_pow5_im_r1; ab_pow6_re0 <= ab_pow6_re_r1; - ab_pow6_im0 <= ab_pow6_im_r1; ab_pow7_re0 <= ab_pow7_re_r1; - ab_pow7_im0 <= ab_pow7_im_r1; b_pow8_re0 <= b_pow8_re_r1 ; - b_pow8_im0 <= b_pow8_im_r1 ; end vldi_r10[1]: begin a_re1 <= ao_re_r1 ; - a_im1 <= ao_im_r1 ; b_re1 <= bo_re_r1 ; - b_im1 <= bo_im_r1 ; ab_re1 <= ab_re_r1 ; - ab_im1 <= ab_im_r1 ; abb_re1 <= abb_re_r1 ; - abb_im1 <= abb_im_r1 ; ab_pow3_re1 <= ab_pow3_re_r1; - ab_pow3_im1 <= ab_pow3_im_r1; ab_pow4_re1 <= ab_pow4_re_r1; - ab_pow4_im1 <= ab_pow4_im_r1; ab_pow5_re1 <= ab_pow5_re_r1; - ab_pow5_im1 <= ab_pow5_im_r1; ab_pow6_re1 <= ab_pow6_re_r1; - ab_pow6_im1 <= ab_pow6_im_r1; ab_pow7_re1 <= ab_pow7_re_r1; - ab_pow7_im1 <= ab_pow7_im_r1; b_pow8_re1 <= b_pow8_re_r1 ; - b_pow8_im1 <= b_pow8_im_r1 ; end vldi_r10[2]: begin a_re2 <= ao_re_r1 ; - a_im2 <= ao_im_r1 ; b_re2 <= bo_re_r1 ; - b_im2 <= bo_im_r1 ; ab_re2 <= ab_re_r1 ; - ab_im2 <= ab_im_r1 ; abb_re2 <= abb_re_r1 ; - abb_im2 <= abb_im_r1 ; ab_pow3_re2 <= ab_pow3_re_r1; - ab_pow3_im2 <= ab_pow3_im_r1; ab_pow4_re2 <= ab_pow4_re_r1; - ab_pow4_im2 <= ab_pow4_im_r1; ab_pow5_re2 <= ab_pow5_re_r1; - ab_pow5_im2 <= ab_pow5_im_r1; ab_pow6_re2 <= ab_pow6_re_r1; - ab_pow6_im2 <= ab_pow6_im_r1; ab_pow7_re2 <= ab_pow7_re_r1; - ab_pow7_im2 <= ab_pow7_im_r1; b_pow8_re2 <= b_pow8_re_r1 ; - b_pow8_im2 <= b_pow8_im_r1 ; end vldi_r10[3]: begin a_re3 <= ao_re_r1 ; - a_im3 <= ao_im_r1 ; b_re3 <= bo_re_r1 ; - b_im3 <= bo_im_r1 ; ab_re3 <= ab_re_r1 ; - ab_im3 <= ab_im_r1 ; abb_re3 <= abb_re_r1 ; - abb_im3 <= abb_im_r1 ; ab_pow3_re3 <= ab_pow3_re_r1; - ab_pow3_im3 <= ab_pow3_im_r1; ab_pow4_re3 <= ab_pow4_re_r1; - ab_pow4_im3 <= ab_pow4_im_r1; ab_pow5_re3 <= ab_pow5_re_r1; - ab_pow5_im3 <= ab_pow5_im_r1; ab_pow6_re3 <= ab_pow6_re_r1; - ab_pow6_im3 <= ab_pow6_im_r1; ab_pow7_re3 <= ab_pow7_re_r1; - ab_pow7_im3 <= ab_pow7_im_r1; b_pow8_re3 <= b_pow8_re_r1 ; - b_pow8_im3 <= b_pow8_im_r1 ; end vldi_r10[4]: begin a_re4 <= ao_re_r1 ; - a_im4 <= ao_im_r1 ; b_re4 <= bo_re_r1 ; - b_im4 <= bo_im_r1 ; ab_re4 <= ab_re_r1 ; - ab_im4 <= ab_im_r1 ; abb_re4 <= abb_re_r1 ; - abb_im4 <= abb_im_r1 ; ab_pow3_re4 <= ab_pow3_re_r1; - ab_pow3_im4 <= ab_pow3_im_r1; ab_pow4_re4 <= ab_pow4_re_r1; - ab_pow4_im4 <= ab_pow4_im_r1; ab_pow5_re4 <= ab_pow5_re_r1; - ab_pow5_im4 <= ab_pow5_im_r1; ab_pow6_re4 <= ab_pow6_re_r1; - ab_pow6_im4 <= ab_pow6_im_r1; ab_pow7_re4 <= ab_pow7_re_r1; - ab_pow7_im4 <= ab_pow7_im_r1; b_pow8_re4 <= b_pow8_re_r1 ; - b_pow8_im4 <= b_pow8_im_r1 ; end vldi_r10[5]: begin a_re5 <= ao_re_r1 ; - a_im5 <= ao_im_r1 ; b_re5 <= bo_re_r1 ; - b_im5 <= bo_im_r1 ; ab_re5 <= ab_re_r1 ; - ab_im5 <= ab_im_r1 ; abb_re5 <= abb_re_r1 ; - abb_im5 <= abb_im_r1 ; ab_pow3_re5 <= ab_pow3_re_r1; - ab_pow3_im5 <= ab_pow3_im_r1; ab_pow4_re5 <= ab_pow4_re_r1; - ab_pow4_im5 <= ab_pow4_im_r1; ab_pow5_re5 <= ab_pow5_re_r1; - ab_pow5_im5 <= ab_pow5_im_r1; ab_pow6_re5 <= ab_pow6_re_r1; - ab_pow6_im5 <= ab_pow6_im_r1; ab_pow7_re5 <= ab_pow7_re_r1; - ab_pow7_im5 <= ab_pow7_im_r1; b_pow8_re5 <= b_pow8_re_r1 ; - b_pow8_im5 <= b_pow8_im_r1 ; end // default: begin // ao_re[0] <= 'h0; -// ao_im[0] <= 'h0; // ab_re[0] <= 'h0; -// ab_im[0] <= 'h0; // abb_re[0] <= 'h0; -// abb_im[0] <= 'h0; // ab_pow3_re[0] <= 'h0; -// ab_pow3_im[0] <= 'h0; // ab_pow4_re[0] <= 'h0; -// ab_pow4_im[0] <= 'h0; // ab_pow5_re[0] <= 'h0; -// ab_pow5_im[0] <= 'h0; // ab_pow6_re[0] <= 'h0; -// ab_pow6_im[0] <= 'h0; // ab_pow7_re[0] <= 'h0; -// ab_pow7_im[0] <= 'h0; // b_pow8_re[0] <= 'h0; -// b_pow8_im[0] <= 'h0; // end endcase end diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v index e6c6f01..6528097 100644 --- a/rtl/z_dsp/IIR_Filter_p1.v +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -45,73 +45,56 @@ module IIR_Filter_p1 #( ,input en ,input signed [data_in_width-1 :0] din_re // Re(x(t)) ,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1)) -,input signed [cascade_in_width-1:0] dout_r1_im // Im(y(t-1)) ,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] a_im ,input signed [coef_width-1 :0] b_re -,input signed [coef_width-1 :0] b_im ,output signed [data_out_width-1:0] dout_re // Re(y(t-16)) -,output signed [data_out_width-1:0] dout_im // Im(y(t-16)) ); wire signed [temp_var_width-1 :0] x1_re; -wire signed [temp_var_width-1 :0] x1_im; wire signed [temp_var_width-1 :0] y1_re; -wire signed [temp_var_width-1 :0] y1_im; wire signed [temp_var_width :0] y_re; -wire signed [temp_var_width :0] y_im; wire signed [data_out_width-1:0] y_re_trunc; -wire signed [data_out_width-1:0] y_im_trunc; // x1 = a * din delay M = a*x(t-8) -mult_x +mult_real #( .A_width (data_in_width ) - ,.C_width (coef_width ) - ,.D_width (coef_width ) + ,.C_width (coef_width ) ,.o_width (temp_var_width ) ) inst_c1 ( - .clk (clk ), + .clk (clk ), .rstn (rstn ), .en (en ), - .a (din_re ), - .c (a_re ), - .d (a_im ), - .Re (x1_re ), - .Im (x1_im ) + .din (din_re ), + .coef (a_re ), + .dout (x1_re ) ); // y1 = b * dout_r1 delay M = b*y(t-9) // y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) -mult_C +mult_real #( - .A_width (cascade_in_width ) - ,.B_width (cascade_in_width ) - ,.C_width (coef_width ) - ,.D_width (coef_width ) - ,.o_width (temp_var_width ) + .A_width (cascade_in_width ) + ,.C_width (coef_width ) + ,.o_width (temp_var_width ) ) -inst_c3 ( +inst_c2 ( .clk (clk ), .rstn (rstn ), .en (en ), - .a (dout_r1_re ), - .b (dout_r1_im ), - .c (b_re ), - .d (b_im ), - .Re (y1_re ), - .Im (y1_im ) + .din (dout_r1_re ), + .coef (b_re ), + .dout (y1_re ) ); assign y_re = x1_re + y1_re; -assign y_im = x1_im + y1_im; // dout = round(y) delay M = round(y(t-16)) @@ -120,13 +103,7 @@ trunc #( ,.msb (temp_var_width-1 ) ,.lsb (temp_var_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); -trunc #( - .diw (temp_var_width+1 ) - ,.msb (temp_var_width-1 ) - ,.lsb (temp_var_width-data_out_width ) -) round_u2 (clk, rstn, en, y_im, y_im_trunc); assign dout_re = y_re_trunc; -assign dout_im = y_im_trunc; endmodule diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v index 46738a1..46afcf2 100644 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ b/rtl/z_dsp/IIR_Filter_p8.v @@ -19,26 +19,16 @@ module IIR_Filter_p8 #( ,input signed [data_in_width-1 :0] dinp7 //x(8n+9) ,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] a_im ,input signed [coef_width-1 :0] ab_re -,input signed [coef_width-1 :0] ab_im ,input signed [coef_width-1 :0] abb_re -,input signed [coef_width-1 :0] abb_im ,input signed [coef_width-1 :0] ab_pow3_re -,input signed [coef_width-1 :0] ab_pow3_im ,input signed [coef_width-1 :0] ab_pow4_re -,input signed [coef_width-1 :0] ab_pow4_im ,input signed [coef_width-1 :0] ab_pow5_re -,input signed [coef_width-1 :0] ab_pow5_im ,input signed [coef_width-1 :0] ab_pow6_re -,input signed [coef_width-1 :0] ab_pow6_im ,input signed [coef_width-1 :0] ab_pow7_re -,input signed [coef_width-1 :0] ab_pow7_im ,input signed [coef_width-1 :0] b_pow8_re -,input signed [coef_width-1 :0] b_pow8_im ,output signed [data_out_width-1:0] dout_re // Re(y(8n-8)) -,output signed [data_out_width-1:0] dout_im // Im(y(8n-8)) ); wire signed [data_in_width-1 :0] dinp [7:0]; @@ -61,32 +51,17 @@ assign ab_pow_re[2] = abb_re; assign ab_pow_re[1] = ab_re; assign ab_pow_re[0] = a_re; -wire signed [coef_width-1 :0] ab_pow_im [7:0]; -assign ab_pow_im[7] = ab_pow7_im; -assign ab_pow_im[6] = ab_pow6_im; -assign ab_pow_im[5] = ab_pow5_im; -assign ab_pow_im[4] = ab_pow4_im; -assign ab_pow_im[3] = ab_pow3_im; -assign ab_pow_im[2] = abb_im; -assign ab_pow_im[1] = ab_im; -assign ab_pow_im[0] = a_im; wire signed [temp_var_width-1 :0] x_re [0:7]; -wire signed [temp_var_width-1 :0] x_im [0:7]; wire signed [temp_var_width+3 :0] v_re; -wire signed [temp_var_width+3 :0] v_im; reg signed [temp_var_width+3 :0] v1_re; -reg signed [temp_var_width+3 :0] v1_im; wire signed [temp_var_width+3 :0] y_re; -wire signed [temp_var_width+3 :0] y_im; wire signed [temp_var_width+3 :0] y1_re; -wire signed [temp_var_width+3 :0] y1_im; wire signed [data_out_width-1:0] y_re_trunc; -wire signed [data_out_width-1:0] y_im_trunc; // x[0] = (dinp0 * a_re) delay M = a*x(8n+8) // x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7) @@ -99,20 +74,17 @@ wire signed [data_out_width-1:0] y_im_trunc; genvar i; generate for (i = 0; i < 8; i = i + 1) begin: mult_c_inst - mult_x #( + mult_real #( .A_width (data_in_width ), .C_width (coef_width ), - .D_width (coef_width ), .o_width (temp_var_width ) ) inst_c ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .a (dinp[i] ), - .c (ab_pow_re[i] ), - .d (ab_pow_im[i] ), - .Re (x_re[i] ), - .Im (x_im[i] ) + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din (dinp[i] ), + .coef (ab_pow_re[i]), + .dout (x_re[i] ) ); end endgenerate @@ -120,50 +92,40 @@ endgenerate // v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7]; -assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7]; always @(posedge clk or negedge rstn) if (!rstn) begin v1_re <= 'h0; - v1_im <= 'h0; end else if(en) begin v1_re <= v_re; - v1_im <= v_im; end else begin v1_re <= v1_re; - v1_im <= v1_im; end // y1 = (b^8 * y) delay M = b^8*y(8n-8) // y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) -mult_C +mult_real #( .A_width (temp_var_width+4 ) - ,.B_width (temp_var_width+4 ) - ,.C_width (coef_width ) - ,.D_width (coef_width ) + ,.C_width (coef_width ) ,.o_width (temp_var_width+4 ) ) inst_c9 ( .clk (clk ), .rstn (rstn ), .en (en ), - .a (y_re ), - .b (y_im ), - .c (b_pow8_re ), - .d (b_pow8_im ), - .Re (y1_re ), - .Im (y1_im ) + .din (y_re ), + .coef (b_pow8_re ), + .dout (y1_re ) ); assign y_re = v1_re + y1_re; -assign y_im = v1_im + y1_im; // dout = round(y) delay M = round(y(8n-8)) trunc #( @@ -171,15 +133,9 @@ trunc #( ,.msb (temp_var_width-1 ) ,.lsb (temp_var_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); -trunc #( - .diw (temp_var_width+4 ) - ,.msb (temp_var_width-1 ) - ,.lsb (temp_var_width-data_out_width ) -) round_u2 (clk, rstn, en, y_im, y_im_trunc); assign dout_re = y_re_trunc; -assign dout_im = y_im_trunc; endmodule diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index 049a24c..a4d3b36 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -7,41 +7,31 @@ module IIR_top #( input rstn ,input clk ,input en -,input signed [15 :0] IIRin_p0 // x(8n+9) -,input signed [15 :0] IIRin_p1 // x(8n+10) -,input signed [15 :0] IIRin_p2 // x(8n+11) -,input signed [15 :0] IIRin_p3 // x(8n+12) -,input signed [15 :0] IIRin_p4 // x(8n+13) -,input signed [15 :0] IIRin_p5 // x(8n+14) -,input signed [15 :0] IIRin_p6 // x(8n+15) -,input signed [15 :0] IIRin_p7 // x(8n+16) -,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) -,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) -,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) -,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) -,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) -,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) -,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) +,input signed [15 :0] IIRin_p0 // x(8n+9) +,input signed [15 :0] IIRin_p1 // x(8n+10) +,input signed [15 :0] IIRin_p2 // x(8n+11) +,input signed [15 :0] IIRin_p3 // x(8n+12) +,input signed [15 :0] IIRin_p4 // x(8n+13) +,input signed [15 :0] IIRin_p5 // x(8n+14) +,input signed [15 :0] IIRin_p6 // x(8n+15) +,input signed [15 :0] IIRin_p7 // x(8n+16) +,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) +,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) +,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) +,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) +,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) +,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) +,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) ,input signed [31 :0] a_re -,input signed [31 :0] a_im ,input signed [31 :0] b_re -,input signed [31 :0] b_im ,input signed [31 :0] ab_re -,input signed [31 :0] ab_im ,input signed [31 :0] abb_re -,input signed [31 :0] abb_im ,input signed [31 :0] ab_pow3_re -,input signed [31 :0] ab_pow3_im ,input signed [31 :0] ab_pow4_re -,input signed [31 :0] ab_pow4_im ,input signed [31 :0] ab_pow5_re -,input signed [31 :0] ab_pow5_im ,input signed [31 :0] ab_pow6_re -,input signed [31 :0] ab_pow6_im ,input signed [31 :0] ab_pow7_re -,input signed [31 :0] ab_pow7_im ,input signed [31 :0] b_pow8_re -,input signed [31 :0] b_pow8_im ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) @@ -61,21 +51,13 @@ wire signed [temp_var_width- 9:0] IIRout_p4_re; wire signed [temp_var_width-11:0] IIRout_p5_re; wire signed [temp_var_width-13:0] IIRout_p6_re; wire signed [temp_var_width-15:0] IIRout_p7_re; -wire signed [temp_var_width- 1:0] IIRout_p0_im; -wire signed [temp_var_width- 3:0] IIRout_p1_im; -wire signed [temp_var_width- 5:0] IIRout_p2_im; -wire signed [temp_var_width- 7:0] IIRout_p3_im; -wire signed [temp_var_width- 9:0] IIRout_p4_im; -wire signed [temp_var_width-11:0] IIRout_p5_im; -wire signed [temp_var_width-13:0] IIRout_p6_im; -wire signed [temp_var_width-15:0] IIRout_p7_im; IIR_Filter_p8 #( .data_out_width (temp_var_width ) ) inst_iir_p0 ( - .clk (clk ), + .clk (clk ), .rstn (rstn ), .en (en ), .dinp0 (IIRin_p7 ), // x(8n+16) @@ -87,148 +69,110 @@ IIR_Filter_p8 #( .dinp6 (IIRin_p1 ), // x(8n+10) .dinp7 (IIRin_p0 ), // x(8n+9) .a_re (a_re ), - .a_im (a_im ), .ab_re (ab_re ), - .ab_im (ab_im ), .abb_re (abb_re ), - .abb_im (abb_im ), .ab_pow3_re (ab_pow3_re ), - .ab_pow3_im (ab_pow3_im ), .ab_pow4_re (ab_pow4_re ), - .ab_pow4_im (ab_pow4_im ), .ab_pow5_re (ab_pow5_re ), - .ab_pow5_im (ab_pow5_im ), .ab_pow6_re (ab_pow6_re ), - .ab_pow6_im (ab_pow6_im ), .ab_pow7_re (ab_pow7_re ), - .ab_pow7_im (ab_pow7_im ), .b_pow8_re (b_pow8_re ), - .b_pow8_im (b_pow8_im ), - .dout_re (IIRout_p0_re ), // Re(y(8n-8)) - .dout_im (IIRout_p0_im ) // Im(y(8n-8)) + .dout_re (IIRout_p0_re ) // Re(y(8n-8)) ); IIR_Filter_p1 #( .cascade_in_width (temp_var_width ) ) inst_iir_p1( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p0_r2 ), // x(8n-7) .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) - .dout_r1_im (IIRout_p0_im ), // Im(y(8n-8)) - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .dout_re (IIRout_p1_re ), // Re(y(8n-23)) - .dout_im (IIRout_p1_im ) // Im(y(8n-23)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p1_re ) // Re(y(8n-23)) ); IIR_Filter_p1 #( .cascade_in_width (temp_var_width-2 ) ) inst_iir_p2 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p1_r4 ), // x(8n-22) .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) - .dout_r1_im (IIRout_p1_im ), // Im(y(8n-23)) - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .dout_re (IIRout_p2_re ), // Re(y(8n-38)) - .dout_im (IIRout_p2_im ) // Im(y(8n-38)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p2_re ) // Re(y(8n-38)) ); IIR_Filter_p1 #( .cascade_in_width (temp_var_width-4 ) ) inst_iir_p3 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p2_r6 ), // x(8n-37) .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) - .dout_r1_im (IIRout_p2_im ), // Im(y(8n-38)) - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .dout_re (IIRout_p3_re ), // Re(y(8n-53)) - .dout_im (IIRout_p3_im ) // Im(y(8n-53)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p3_re ) // Re(y(8n-53)) ); IIR_Filter_p1 #( .cascade_in_width (temp_var_width-6 ) ) inst_iir_p4 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p3_r8 ), // x(8n-52) .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) - .dout_r1_im (IIRout_p3_im ), // Im(y(8n-53)) - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .dout_re (IIRout_p4_re ), // Re(y(8n-68)) - .dout_im (IIRout_p4_im ) // Im(y(8n-68)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p4_re ) // Re(y(8n-68)) ); IIR_Filter_p1 #( .cascade_in_width (temp_var_width-8 ) ) inst_iir_p5 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p4_r10 ), // x(8n-67) .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) - .dout_r1_im (IIRout_p4_im ), // Im(y(8n-68)) - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .dout_re (IIRout_p5_re ), // Re(y(8n-83)) - .dout_im (IIRout_p5_im ) // Im(y(8n-83)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p5_re ) // Re(y(8n-83)) ); IIR_Filter_p1 #( .cascade_in_width (temp_var_width-10 ) ) inst_iir_p6 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p5_r12 ), // x(8n-82) .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) - .dout_r1_im (IIRout_p5_im ), // Im(y(8n-83)) - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .dout_re (IIRout_p6_re ), // Re(y(8n-98)) - .dout_im (IIRout_p6_im ) // Im(y(8n-98)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p6_re ) // Re(y(8n-98)) ); IIR_Filter_p1 #( .cascade_in_width (temp_var_width-12 ) ) inst_iir_p7 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p6_r14 ), // x(8n-97) .dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) - .dout_r1_im (IIRout_p6_im ), // Im(y(8n-98)) - .a_re (a_re ), - .a_im (a_im ), - .b_re (b_re ), - .b_im (b_im ), - .dout_re (IIRout_p7_re ), // Re(y(8n-113)) - .dout_im (IIRout_p7_im ) // Im(y(8n-113)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p7_re ) // Re(y(8n-113)) ); -assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8) -assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23) -assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38) -assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53) -assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68) -assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83) -assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98) -assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113) +assign IIRout_p0 = IIRout_p0_re[temp_var_width- 0-1 : temp_var_width- 0-data_out_width]; // y(8n-8) +assign IIRout_p1 = IIRout_p1_re[temp_var_width- 2-1 : temp_var_width- 2-data_out_width]; // y(8n-23) +assign IIRout_p2 = IIRout_p2_re[temp_var_width- 4-1 : temp_var_width- 4-data_out_width]; // y(8n-38) +assign IIRout_p3 = IIRout_p3_re[temp_var_width- 6-1 : temp_var_width- 6-data_out_width]; // y(8n-53) +assign IIRout_p4 = IIRout_p4_re[temp_var_width- 8-1 : temp_var_width- 8-data_out_width]; // y(8n-68) +assign IIRout_p5 = IIRout_p5_re[temp_var_width-10-1 : temp_var_width-10-data_out_width]; // y(8n-83) +assign IIRout_p6 = IIRout_p6_re[temp_var_width-12-1 : temp_var_width-12-data_out_width]; // y(8n-98) +assign IIRout_p7 = IIRout_p7_re[temp_var_width-14-1 : temp_var_width-14-data_out_width]; // y(8n-113) endmodule diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index 1be0a8a..df242ab 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -12,125 +12,65 @@ module TailCorr_top #( ,input signed [15:0] din2 ,input signed [15:0] din3 ,input signed [31:0] a_re0 -,input signed [31:0] a_im0 ,input signed [31:0] b_re0 -,input signed [31:0] b_im0 ,input signed [31:0] ab_re0 -,input signed [31:0] ab_im0 ,input signed [31:0] abb_re0 -,input signed [31:0] abb_im0 ,input signed [31:0] ab_pow3_re0 -,input signed [31:0] ab_pow3_im0 ,input signed [31:0] ab_pow4_re0 -,input signed [31:0] ab_pow4_im0 ,input signed [31:0] ab_pow5_re0 -,input signed [31:0] ab_pow5_im0 ,input signed [31:0] ab_pow6_re0 -,input signed [31:0] ab_pow6_im0 ,input signed [31:0] ab_pow7_re0 -,input signed [31:0] ab_pow7_im0 ,input signed [31:0] b_pow8_re0 -,input signed [31:0] b_pow8_im0 ,input signed [31:0] a_re1 -,input signed [31:0] a_im1 ,input signed [31:0] b_re1 -,input signed [31:0] b_im1 ,input signed [31:0] ab_re1 -,input signed [31:0] ab_im1 ,input signed [31:0] abb_re1 -,input signed [31:0] abb_im1 ,input signed [31:0] ab_pow3_re1 -,input signed [31:0] ab_pow3_im1 ,input signed [31:0] ab_pow4_re1 -,input signed [31:0] ab_pow4_im1 ,input signed [31:0] ab_pow5_re1 -,input signed [31:0] ab_pow5_im1 ,input signed [31:0] ab_pow6_re1 -,input signed [31:0] ab_pow6_im1 ,input signed [31:0] ab_pow7_re1 -,input signed [31:0] ab_pow7_im1 ,input signed [31:0] b_pow8_re1 -,input signed [31:0] b_pow8_im1 ,input signed [31:0] a_re2 -,input signed [31:0] a_im2 ,input signed [31:0] b_re2 -,input signed [31:0] b_im2 ,input signed [31:0] ab_re2 -,input signed [31:0] ab_im2 ,input signed [31:0] abb_re2 -,input signed [31:0] abb_im2 ,input signed [31:0] ab_pow3_re2 -,input signed [31:0] ab_pow3_im2 ,input signed [31:0] ab_pow4_re2 -,input signed [31:0] ab_pow4_im2 ,input signed [31:0] ab_pow5_re2 -,input signed [31:0] ab_pow5_im2 ,input signed [31:0] ab_pow6_re2 -,input signed [31:0] ab_pow6_im2 ,input signed [31:0] ab_pow7_re2 -,input signed [31:0] ab_pow7_im2 ,input signed [31:0] b_pow8_re2 -,input signed [31:0] b_pow8_im2 ,input signed [31:0] a_re3 -,input signed [31:0] a_im3 ,input signed [31:0] b_re3 -,input signed [31:0] b_im3 ,input signed [31:0] ab_re3 -,input signed [31:0] ab_im3 ,input signed [31:0] abb_re3 -,input signed [31:0] abb_im3 ,input signed [31:0] ab_pow3_re3 -,input signed [31:0] ab_pow3_im3 ,input signed [31:0] ab_pow4_re3 -,input signed [31:0] ab_pow4_im3 ,input signed [31:0] ab_pow5_re3 -,input signed [31:0] ab_pow5_im3 ,input signed [31:0] ab_pow6_re3 -,input signed [31:0] ab_pow6_im3 ,input signed [31:0] ab_pow7_re3 -,input signed [31:0] ab_pow7_im3 ,input signed [31:0] b_pow8_re3 -,input signed [31:0] b_pow8_im3 ,input signed [31:0] a_re4 -,input signed [31:0] a_im4 ,input signed [31:0] b_re4 -,input signed [31:0] b_im4 ,input signed [31:0] ab_re4 -,input signed [31:0] ab_im4 ,input signed [31:0] abb_re4 -,input signed [31:0] abb_im4 ,input signed [31:0] ab_pow3_re4 -,input signed [31:0] ab_pow3_im4 ,input signed [31:0] ab_pow4_re4 -,input signed [31:0] ab_pow4_im4 ,input signed [31:0] ab_pow5_re4 -,input signed [31:0] ab_pow5_im4 ,input signed [31:0] ab_pow6_re4 -,input signed [31:0] ab_pow6_im4 ,input signed [31:0] ab_pow7_re4 -,input signed [31:0] ab_pow7_im4 ,input signed [31:0] b_pow8_re4 -,input signed [31:0] b_pow8_im4 ,input signed [31:0] a_re5 -,input signed [31:0] a_im5 ,input signed [31:0] b_re5 -,input signed [31:0] b_im5 ,input signed [31:0] ab_re5 -,input signed [31:0] ab_im5 ,input signed [31:0] abb_re5 -,input signed [31:0] abb_im5 ,input signed [31:0] ab_pow3_re5 -,input signed [31:0] ab_pow3_im5 ,input signed [31:0] ab_pow4_re5 -,input signed [31:0] ab_pow4_im5 ,input signed [31:0] ab_pow5_re5 -,input signed [31:0] ab_pow5_im5 ,input signed [31:0] ab_pow6_re5 -,input signed [31:0] ab_pow6_im5 ,input signed [31:0] ab_pow7_re5 -,input signed [31:0] ab_pow7_im5 ,input signed [31:0] b_pow8_re5 -,input signed [31:0] b_pow8_im5 ,output signed [15:0] dout_p0 ,output signed [15:0] dout_p1 @@ -468,25 +408,15 @@ IIR_top #( .IIRin_p5_r12 (IIRin_p5_r[11] ), .IIRin_p6_r14 (IIRin_p6_r[13] ), .a_re (a_re0 ), - .a_im (a_im0 ), .b_re (b_re0 ), - .b_im (b_im0 ), .ab_re (ab_re0 ), - .ab_im (ab_im0 ), .abb_re (abb_re0 ), - .abb_im (abb_im0 ), .ab_pow3_re (ab_pow3_re0 ), - .ab_pow3_im (ab_pow3_im0 ), .ab_pow4_re (ab_pow4_re0 ), - .ab_pow4_im (ab_pow4_im0 ), .ab_pow5_re (ab_pow5_re0 ), - .ab_pow5_im (ab_pow5_im0 ), .ab_pow6_re (ab_pow6_re0 ), - .ab_pow6_im (ab_pow6_im0 ), .ab_pow7_re (ab_pow7_re0 ), - .ab_pow7_im (ab_pow7_im0 ), .b_pow8_re (b_pow8_re0 ), - .b_pow8_im (b_pow8_im0 ), .IIRout_p0 (IIRout_p0[0] ), .IIRout_p1 (IIRout_p1[0] ), .IIRout_p2 (IIRout_p2[0] ), @@ -519,25 +449,15 @@ IIR_top #( .IIRin_p5_r12 (IIRin_p5_r[11] ), .IIRin_p6_r14 (IIRin_p6_r[13] ), .a_re (a_re1 ), - .a_im (a_im1 ), .b_re (b_re1 ), - .b_im (b_im1 ), .ab_re (ab_re1 ), - .ab_im (ab_im1 ), .abb_re (abb_re1 ), - .abb_im (abb_im1 ), .ab_pow3_re (ab_pow3_re1 ), - .ab_pow3_im (ab_pow3_im1 ), .ab_pow4_re (ab_pow4_re1 ), - .ab_pow4_im (ab_pow4_im1 ), .ab_pow5_re (ab_pow5_re1 ), - .ab_pow5_im (ab_pow5_im1 ), .ab_pow6_re (ab_pow6_re1 ), - .ab_pow6_im (ab_pow6_im1 ), .ab_pow7_re (ab_pow7_re1 ), - .ab_pow7_im (ab_pow7_im1 ), .b_pow8_re (b_pow8_re1 ), - .b_pow8_im (b_pow8_im1 ), .IIRout_p0 (IIRout_p0[1] ), .IIRout_p1 (IIRout_p1[1] ), .IIRout_p2 (IIRout_p2[1] ), @@ -570,25 +490,15 @@ IIR_top #( .IIRin_p5_r12 (IIRin_p5_r[11] ), .IIRin_p6_r14 (IIRin_p6_r[13] ), .a_re (a_re2 ), - .a_im (a_im2 ), .b_re (b_re2 ), - .b_im (b_im2 ), .ab_re (ab_re2 ), - .ab_im (ab_im2 ), .abb_re (abb_re2 ), - .abb_im (abb_im2 ), .ab_pow3_re (ab_pow3_re2 ), - .ab_pow3_im (ab_pow3_im2 ), .ab_pow4_re (ab_pow4_re2 ), - .ab_pow4_im (ab_pow4_im2 ), .ab_pow5_re (ab_pow5_re2 ), - .ab_pow5_im (ab_pow5_im2 ), .ab_pow6_re (ab_pow6_re2 ), - .ab_pow6_im (ab_pow6_im2 ), .ab_pow7_re (ab_pow7_re2 ), - .ab_pow7_im (ab_pow7_im2 ), .b_pow8_re (b_pow8_re2 ), - .b_pow8_im (b_pow8_im2 ), .IIRout_p0 (IIRout_p0[2] ), .IIRout_p1 (IIRout_p1[2] ), .IIRout_p2 (IIRout_p2[2] ), @@ -621,25 +531,15 @@ IIR_top #( .IIRin_p5_r12 (IIRin_p5_r[11] ), .IIRin_p6_r14 (IIRin_p6_r[13] ), .a_re (a_re3 ), - .a_im (a_im3 ), .b_re (b_re3 ), - .b_im (b_im3 ), .ab_re (ab_re3 ), - .ab_im (ab_im3 ), .abb_re (abb_re3 ), - .abb_im (abb_im3 ), .ab_pow3_re (ab_pow3_re3 ), - .ab_pow3_im (ab_pow3_im3 ), .ab_pow4_re (ab_pow4_re3 ), - .ab_pow4_im (ab_pow4_im3 ), .ab_pow5_re (ab_pow5_re3 ), - .ab_pow5_im (ab_pow5_im3 ), .ab_pow6_re (ab_pow6_re3 ), - .ab_pow6_im (ab_pow6_im3 ), .ab_pow7_re (ab_pow7_re3 ), - .ab_pow7_im (ab_pow7_im3 ), .b_pow8_re (b_pow8_re3 ), - .b_pow8_im (b_pow8_im3 ), .IIRout_p0 (IIRout_p0[3] ), .IIRout_p1 (IIRout_p1[3] ), .IIRout_p2 (IIRout_p2[3] ), @@ -672,25 +572,15 @@ IIR_top #( .IIRin_p5_r12 (IIRin_p5_r[11] ), .IIRin_p6_r14 (IIRin_p6_r[13] ), .a_re (a_re4 ), - .a_im (a_im4 ), .b_re (b_re4 ), - .b_im (b_im4 ), .ab_re (ab_re4 ), - .ab_im (ab_im4 ), .abb_re (abb_re4 ), - .abb_im (abb_im4 ), .ab_pow3_re (ab_pow3_re4 ), - .ab_pow3_im (ab_pow3_im4 ), .ab_pow4_re (ab_pow4_re4 ), - .ab_pow4_im (ab_pow4_im4 ), .ab_pow5_re (ab_pow5_re4 ), - .ab_pow5_im (ab_pow5_im4 ), .ab_pow6_re (ab_pow6_re4 ), - .ab_pow6_im (ab_pow6_im4 ), .ab_pow7_re (ab_pow7_re4 ), - .ab_pow7_im (ab_pow7_im4 ), .b_pow8_re (b_pow8_re4 ), - .b_pow8_im (b_pow8_im4 ), .IIRout_p0 (IIRout_p0[4] ), .IIRout_p1 (IIRout_p1[4] ), .IIRout_p2 (IIRout_p2[4] ), @@ -723,25 +613,15 @@ IIR_top #( .IIRin_p5_r12 (IIRin_p5_r[11] ), .IIRin_p6_r14 (IIRin_p6_r[13] ), .a_re (a_re5 ), - .a_im (a_im5 ), .b_re (b_re5 ), - .b_im (b_im5 ), .ab_re (ab_re5 ), - .ab_im (ab_im5 ), .abb_re (abb_re5 ), - .abb_im (abb_im5 ), .ab_pow3_re (ab_pow3_re5 ), - .ab_pow3_im (ab_pow3_im5 ), .ab_pow4_re (ab_pow4_re5 ), - .ab_pow4_im (ab_pow4_im5 ), .ab_pow5_re (ab_pow5_re5 ), - .ab_pow5_im (ab_pow5_im5 ), .ab_pow6_re (ab_pow6_re5 ), - .ab_pow6_im (ab_pow6_im5 ), .ab_pow7_re (ab_pow7_re5 ), - .ab_pow7_im (ab_pow7_im5 ), .b_pow8_re (b_pow8_re5 ), - .b_pow8_im (b_pow8_im5 ), .IIRout_p0 (IIRout_p0[5] ), .IIRout_p1 (IIRout_p1[5] ), .IIRout_p2 (IIRout_p2[5] ), diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v deleted file mode 100644 index d386159..0000000 --- a/rtl/z_dsp/mult_C.v +++ /dev/null @@ -1,117 +0,0 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : mult_C.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.1 2024-05-28 thfu -//2024-05-28 10:22:18 -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- -module mult_C #( - parameter integer A_width = 8 -,parameter integer B_width = 8 -,parameter integer C_width = 8 -,parameter integer D_width = 8 -,parameter integer o_width = 31//division - -) - -( - clk, - rstn, - en, - a, - b, - c, - d, - Re, - Im -); - -input rstn; -input clk; -input en; -input signed [A_width-1 :0] a; -input signed [B_width-1 :0] b; -input signed [C_width-1 :0] c; -input signed [D_width-1 :0] d; - -output signed [o_width-1 :0] Re; -output signed [o_width-1 :0] Im; - -wire signed [A_width+C_width-1:0] ac; -wire signed [B_width+D_width-1:0] bd; -wire signed [A_width+D_width-1:0] ad; -wire signed [B_width+C_width-1:0] bc; -wire signed [A_width+C_width :0] Re_tmp; -wire signed [A_width+D_width :0] Im_tmp; -wire signed [o_width-1 :0] Re_trunc; -wire signed [o_width-1 :0] Im_trunc; - - -DW02_mult #(A_width,C_width) inst_c1( .A (a ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (ac ) - ); - -DW02_mult #(B_width,D_width) inst_c2( .A (b ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (bd ) - ); - -DW02_mult #(A_width,D_width) inst_c3( .A (a ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (ad ) - ); -DW02_mult #(B_width,C_width) inst_c4( .A (b ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (bc ) - ); - -assign Re_tmp = ac - bd; -assign Im_tmp = ad + bc; - -trunc #( - .diw (A_width+C_width+1 ) - ,.msb (A_width+C_width-2 ) - ,.lsb (A_width+C_width-o_width-1 ) -) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); -trunc #( - .diw (A_width+D_width+1 ) - ,.msb (A_width+D_width-2 ) - ,.lsb (A_width+C_width-o_width-1 ) -) u_round2 (clk, rstn, en, Im_tmp, Im_trunc); - -// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. -assign Re = Re_trunc; -assign Im = Im_trunc; - -endmodule diff --git a/rtl/z_dsp/mult_real.v b/rtl/z_dsp/mult_real.v new file mode 100644 index 0000000..5ad989e --- /dev/null +++ b/rtl/z_dsp/mult_real.v @@ -0,0 +1,39 @@ + +module mult_real #( + parameter integer A_width = 8 +,parameter integer C_width = 8 +,parameter integer o_width = 31//division + +) + +( + input rstn +,input clk +,input en +,input signed [A_width-1 :0] din +,input signed [C_width-1 :0] coef +,output signed [o_width-1 :0] dout + +); + +wire signed [A_width+C_width-1:0] ac; +wire signed [o_width-1 :0] Re_trunc; + + + +DW02_mult #(A_width,C_width) inst_c1 ( + .A (din ), + .B (coef ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); + +trunc #( + .diw (A_width+C_width ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round1 (clk, rstn, en, ac, Re_trunc); + +assign dout = Re_trunc; + +endmodule diff --git a/rtl/z_dsp/mult_x.v b/rtl/z_dsp/mult_x.v deleted file mode 100644 index 7a65101..0000000 --- a/rtl/z_dsp/mult_x.v +++ /dev/null @@ -1,99 +0,0 @@ -//+FHDR-------------------------------------------------------------------------------------------------------- -// Company: -//----------------------------------------------------------------------------------------------------------------- -// File Name : mult_C.v -// Department : -// Author : thfu -// Author's Tel : -//----------------------------------------------------------------------------------------------------------------- -// Relese History -// Version Date Author Description -// 0.1 2024-05-28 thfu -//2024-05-28 10:22:18 -//----------------------------------------------------------------------------------------------------------------- -// Keywords : -// -//----------------------------------------------------------------------------------------------------------------- -// Parameter -// -//----------------------------------------------------------------------------------------------------------------- -// Purpose : -// -//----------------------------------------------------------------------------------------------------------------- -// Target Device: -// Tool versions: -//----------------------------------------------------------------------------------------------------------------- -// Reuse Issues -// Reset Strategy: -// Clock Domains: -// Critical Timing: -// Asynchronous I/F: -// Synthesizable (y/n): -// Other: -//-FHDR-------------------------------------------------------------------------------------------------------- -module mult_x #( - parameter integer A_width = 8 -,parameter integer C_width = 8 -,parameter integer D_width = 8 -,parameter integer o_width = 31//division - -) - -( - clk, - rstn, - en, - a, - c, - d, - Re, - Im -); - -input rstn; -input clk; -input en; -input signed [A_width-1 :0] a; -input signed [C_width-1 :0] c; -input signed [D_width-1 :0] d; - -output signed [o_width-1 :0] Re; -output signed [o_width-1 :0] Im; - -wire signed [A_width+C_width-1:0] ac; -wire signed [A_width+D_width-1:0] ad; -wire signed [o_width-1 :0] Re_trunc; -wire signed [o_width-1 :0] Im_trunc; - - - -DW02_mult #(A_width,C_width) inst_c1( .A (a ), - .B (c ), - .TC (1'b1 ), - .PRODUCT (ac ) - ); - -DW02_mult #(A_width,D_width) inst_c3( .A (a ), - .B (d ), - .TC (1'b1 ), - .PRODUCT (ad ) - ); - - - -trunc #( - .diw (A_width+C_width ) - ,.msb (A_width+C_width-2 ) - ,.lsb (A_width+C_width-o_width-1 ) -) u_round1 (clk, rstn, en, ac, Re_trunc); -trunc #( - .diw (A_width+D_width ) - ,.msb (A_width+D_width-2 ) - ,.lsb (A_width+D_width-o_width-1 ) -) u_round2 (clk, rstn, en, ad, Im_trunc); - -// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. -assign Re = Re_trunc; -assign Im = Im_trunc; - -endmodule diff --git a/rtl/z_dsp/z_dsp.v b/rtl/z_dsp/z_dsp.v index 6c243a5..680390b 100644 --- a/rtl/z_dsp/z_dsp.v +++ b/rtl/z_dsp/z_dsp.v @@ -14,29 +14,17 @@ module z_dsp ,input signed [15:0] din2 ,input signed [15:0] din3 ,input signed [31:0] a0_re -,input signed [31:0] a0_im ,input signed [31:0] b0_re -,input signed [31:0] b0_im ,input signed [31:0] a1_re -,input signed [31:0] a1_im ,input signed [31:0] b1_re -,input signed [31:0] b1_im ,input signed [31:0] a2_re -,input signed [31:0] a2_im ,input signed [31:0] b2_re -,input signed [31:0] b2_im ,input signed [31:0] a3_re -,input signed [31:0] a3_im ,input signed [31:0] b3_re -,input signed [31:0] b3_im ,input signed [31:0] a4_re -,input signed [31:0] a4_im ,input signed [31:0] b4_re -,input signed [31:0] b4_im ,input signed [31:0] a5_re -,input signed [31:0] a5_im ,input signed [31:0] b5_re -,input signed [31:0] b5_im ,output signed [15:0] dout0 ,output signed [15:0] dout1 ,output signed [15:0] dout2 @@ -49,174 +37,92 @@ wire signed [15:0] IIR_out; wire signed [31:0] ao_re [5:0]; -wire signed [31:0] ao_im [5:0]; wire signed [31:0] ab_re [5:0]; -wire signed [31:0] ab_im [5:0]; wire signed [31:0] abb_re [5:0]; -wire signed [31:0] abb_im [5:0]; wire signed [31:0] ab_pow3_re [5:0]; -wire signed [31:0] ab_pow3_im [5:0]; wire signed [31:0] ab_pow4_re [5:0]; -wire signed [31:0] ab_pow4_im [5:0]; wire signed [31:0] ab_pow5_re [5:0]; -wire signed [31:0] ab_pow5_im [5:0]; wire signed [31:0] ab_pow6_re [5:0]; -wire signed [31:0] ab_pow6_im [5:0]; wire signed [31:0] ab_pow7_re [5:0]; -wire signed [31:0] ab_pow7_im [5:0]; wire signed [31:0] bo_re [5:0]; -wire signed [31:0] bo_im [5:0]; wire signed [31:0] b_pow8_re [5:0]; -wire signed [31:0] b_pow8_im [5:0]; CoefGen inst_CoefGen( .clk (clk ), .rstn (rstn ), .vldi (vldi_coef ), .a0_re (a0_re ), - .a0_im (a0_im ), .b0_re (b0_re ), - .b0_im (b0_im ), .a1_re (a1_re ), - .a1_im (a1_im ), .b1_re (b1_re ), - .b1_im (b1_im ), .a2_re (a2_re ), - .a2_im (a2_im ), .b2_re (b2_re ), - .b2_im (b2_im ), .a3_re (a3_re ), - .a3_im (a3_im ), .b3_re (b3_re ), - .b3_im (b3_im ), .a4_re (a4_re ), - .a4_im (a4_im ), .b4_re (b4_re ), - .b4_im (b4_im ), .a5_re (a5_re ), - .a5_im (a5_im ), .b5_re (b5_re ), - .b5_im (b5_im ), .a_re0 (ao_re[0] ), - .a_im0 (ao_im[0] ), .b_re0 (bo_re[0] ), - .b_im0 (bo_im[0] ), .ab_re0 (ab_re[0] ), - .ab_im0 (ab_im[0] ), .abb_re0 (abb_re[0] ), - .abb_im0 (abb_im[0] ), .ab_pow3_re0 (ab_pow3_re[0]), - .ab_pow3_im0 (ab_pow3_im[0]), .ab_pow4_re0 (ab_pow4_re[0]), - .ab_pow4_im0 (ab_pow4_im[0]), .ab_pow5_re0 (ab_pow5_re[0]), - .ab_pow5_im0 (ab_pow5_im[0]), .ab_pow6_re0 (ab_pow6_re[0]), - .ab_pow6_im0 (ab_pow6_im[0]), .ab_pow7_re0 (ab_pow7_re[0]), - .ab_pow7_im0 (ab_pow7_im[0]), .b_pow8_re0 (b_pow8_re[0] ), - .b_pow8_im0 (b_pow8_im[0] ), .a_re1 (ao_re[1] ), - .a_im1 (ao_im[1] ), .b_re1 (bo_re[1] ), - .b_im1 (bo_im[1] ), .ab_re1 (ab_re[1] ), - .ab_im1 (ab_im[1] ), .abb_re1 (abb_re[1] ), - .abb_im1 (abb_im[1] ), .ab_pow3_re1 (ab_pow3_re[1]), - .ab_pow3_im1 (ab_pow3_im[1]), .ab_pow4_re1 (ab_pow4_re[1]), - .ab_pow4_im1 (ab_pow4_im[1]), .ab_pow5_re1 (ab_pow5_re[1]), - .ab_pow5_im1 (ab_pow5_im[1]), .ab_pow6_re1 (ab_pow6_re[1]), - .ab_pow6_im1 (ab_pow6_im[1]), .ab_pow7_re1 (ab_pow7_re[1]), - .ab_pow7_im1 (ab_pow7_im[1]), .b_pow8_re1 (b_pow8_re[1] ), - .b_pow8_im1 (b_pow8_im[1] ), .a_re2 (ao_re[2] ), - .a_im2 (ao_im[2] ), .b_re2 (bo_re[2] ), - .b_im2 (bo_im[2] ), .ab_re2 (ab_re[2] ), - .ab_im2 (ab_im[2] ), .abb_re2 (abb_re[2] ), - .abb_im2 (abb_im[2] ), .ab_pow3_re2 (ab_pow3_re[2]), - .ab_pow3_im2 (ab_pow3_im[2]), .ab_pow4_re2 (ab_pow4_re[2]), - .ab_pow4_im2 (ab_pow4_im[2]), .ab_pow5_re2 (ab_pow5_re[2]), - .ab_pow5_im2 (ab_pow5_im[2]), .ab_pow6_re2 (ab_pow6_re[2]), - .ab_pow6_im2 (ab_pow6_im[2]), .ab_pow7_re2 (ab_pow7_re[2]), - .ab_pow7_im2 (ab_pow7_im[2]), .b_pow8_re2 (b_pow8_re[2] ), - .b_pow8_im2 (b_pow8_im[2] ), .a_re3 (ao_re[3] ), - .a_im3 (ao_im[3] ), .b_re3 (bo_re[3] ), - .b_im3 (bo_im[3] ), .ab_re3 (ab_re[3] ), - .ab_im3 (ab_im[3] ), .abb_re3 (abb_re[3] ), - .abb_im3 (abb_im[3] ), .ab_pow3_re3 (ab_pow3_re[3]), - .ab_pow3_im3 (ab_pow3_im[3]), .ab_pow4_re3 (ab_pow4_re[3]), - .ab_pow4_im3 (ab_pow4_im[3]), .ab_pow5_re3 (ab_pow5_re[3]), - .ab_pow5_im3 (ab_pow5_im[3]), .ab_pow6_re3 (ab_pow6_re[3]), - .ab_pow6_im3 (ab_pow6_im[3]), .ab_pow7_re3 (ab_pow7_re[3]), - .ab_pow7_im3 (ab_pow7_im[3]), .b_pow8_re3 (b_pow8_re[3] ), - .b_pow8_im3 (b_pow8_im[3] ), .a_re4 (ao_re[4] ), - .a_im4 (ao_im[4] ), .b_re4 (bo_re[4] ), - .b_im4 (bo_im[4] ), .ab_re4 (ab_re[4] ), - .ab_im4 (ab_im[4] ), .abb_re4 (abb_re[4] ), - .abb_im4 (abb_im[4] ), .ab_pow3_re4 (ab_pow3_re[4]), - .ab_pow3_im4 (ab_pow3_im[4]), .ab_pow4_re4 (ab_pow4_re[4]), - .ab_pow4_im4 (ab_pow4_im[4]), .ab_pow5_re4 (ab_pow5_re[4]), - .ab_pow5_im4 (ab_pow5_im[4]), .ab_pow6_re4 (ab_pow6_re[4]), - .ab_pow6_im4 (ab_pow6_im[4]), .ab_pow7_re4 (ab_pow7_re[4]), - .ab_pow7_im4 (ab_pow7_im[4]), .b_pow8_re4 (b_pow8_re[4] ), - .b_pow8_im4 (b_pow8_im[4] ), .a_re5 (ao_re[5] ), - .a_im5 (ao_im[5] ), .b_re5 (bo_re[5] ), - .b_im5 (bo_im[5] ), .ab_re5 (ab_re[5] ), - .ab_im5 (ab_im[5] ), .abb_re5 (abb_re[5] ), - .abb_im5 (abb_im[5] ), .ab_pow3_re5 (ab_pow3_re[5]), - .ab_pow3_im5 (ab_pow3_im[5]), .ab_pow4_re5 (ab_pow4_re[5]), - .ab_pow4_im5 (ab_pow4_im[5]), .ab_pow5_re5 (ab_pow5_re[5]), - .ab_pow5_im5 (ab_pow5_im[5]), .ab_pow6_re5 (ab_pow6_re[5]), - .ab_pow6_im5 (ab_pow6_im[5]), .ab_pow7_re5 (ab_pow7_re[5]), - .ab_pow7_im5 (ab_pow7_im[5]), - .b_pow8_re5 (b_pow8_re[5] ), - .b_pow8_im5 (b_pow8_im[5] ) + .b_pow8_re5 (b_pow8_re[5] ) ); wire signed [15:0] dout_0; @@ -241,125 +147,65 @@ TailCorr_top inst_TailCorr_top .din2 (din2 ), .din3 (din3 ), .a_re0 (ao_re[0] ), - .a_im0 (ao_im[0] ), .b_re0 (bo_re[0] ), - .b_im0 (bo_im[0] ), .ab_re0 (ab_re[0] ), - .ab_im0 (ab_im[0] ), .abb_re0 (abb_re[0] ), - .abb_im0 (abb_im[0] ), .ab_pow3_re0 (ab_pow3_re[0]), - .ab_pow3_im0 (ab_pow3_im[0]), .ab_pow4_re0 (ab_pow4_re[0]), - .ab_pow4_im0 (ab_pow4_im[0]), .ab_pow5_re0 (ab_pow5_re[0]), - .ab_pow5_im0 (ab_pow5_im[0]), .ab_pow6_re0 (ab_pow6_re[0]), - .ab_pow6_im0 (ab_pow6_im[0]), .ab_pow7_re0 (ab_pow7_re[0]), - .ab_pow7_im0 (ab_pow7_im[0]), .b_pow8_re0 (b_pow8_re[0] ), - .b_pow8_im0 (b_pow8_im[0] ), .a_re1 (ao_re[1] ), - .a_im1 (ao_im[1] ), .b_re1 (bo_re[1] ), - .b_im1 (bo_im[1] ), .ab_re1 (ab_re[1] ), - .ab_im1 (ab_im[1] ), .abb_re1 (abb_re[1] ), - .abb_im1 (abb_im[1] ), .ab_pow3_re1 (ab_pow3_re[1]), - .ab_pow3_im1 (ab_pow3_im[1]), .ab_pow4_re1 (ab_pow4_re[1]), - .ab_pow4_im1 (ab_pow4_im[1]), .ab_pow5_re1 (ab_pow5_re[1]), - .ab_pow5_im1 (ab_pow5_im[1]), .ab_pow6_re1 (ab_pow6_re[1]), - .ab_pow6_im1 (ab_pow6_im[1]), .ab_pow7_re1 (ab_pow7_re[1]), - .ab_pow7_im1 (ab_pow7_im[1]), .b_pow8_re1 (b_pow8_re[1] ), - .b_pow8_im1 (b_pow8_im[1] ), .a_re2 (ao_re[2] ), - .a_im2 (ao_im[2] ), .b_re2 (bo_re[2] ), - .b_im2 (bo_im[2] ), .ab_re2 (ab_re[2] ), - .ab_im2 (ab_im[2] ), .abb_re2 (abb_re[2] ), - .abb_im2 (abb_im[2] ), .ab_pow3_re2 (ab_pow3_re[2]), - .ab_pow3_im2 (ab_pow3_im[2]), .ab_pow4_re2 (ab_pow4_re[2]), - .ab_pow4_im2 (ab_pow4_im[2]), .ab_pow5_re2 (ab_pow5_re[2]), - .ab_pow5_im2 (ab_pow5_im[2]), .ab_pow6_re2 (ab_pow6_re[2]), - .ab_pow6_im2 (ab_pow6_im[2]), .ab_pow7_re2 (ab_pow7_re[2]), - .ab_pow7_im2 (ab_pow7_im[2]), .b_pow8_re2 (b_pow8_re[2] ), - .b_pow8_im2 (b_pow8_im[2] ), .a_re3 (ao_re[3] ), - .a_im3 (ao_im[3] ), .b_re3 (bo_re[3] ), - .b_im3 (bo_im[3] ), .ab_re3 (ab_re[3] ), - .ab_im3 (ab_im[3] ), .abb_re3 (abb_re[3] ), - .abb_im3 (abb_im[3] ), .ab_pow3_re3 (ab_pow3_re[3]), - .ab_pow3_im3 (ab_pow3_im[3]), .ab_pow4_re3 (ab_pow4_re[3]), - .ab_pow4_im3 (ab_pow4_im[3]), .ab_pow5_re3 (ab_pow5_re[3]), - .ab_pow5_im3 (ab_pow5_im[3]), .ab_pow6_re3 (ab_pow6_re[3]), - .ab_pow6_im3 (ab_pow6_im[3]), .ab_pow7_re3 (ab_pow7_re[3]), - .ab_pow7_im3 (ab_pow7_im[3]), .b_pow8_re3 (b_pow8_re[3] ), - .b_pow8_im3 (b_pow8_im[3] ), .a_re4 (ao_re[4] ), - .a_im4 (ao_im[4] ), .b_re4 (bo_re[4] ), - .b_im4 (bo_im[4] ), .ab_re4 (ab_re[4] ), - .ab_im4 (ab_im[4] ), .abb_re4 (abb_re[4] ), - .abb_im4 (abb_im[4] ), .ab_pow3_re4 (ab_pow3_re[4]), - .ab_pow3_im4 (ab_pow3_im[4]), .ab_pow4_re4 (ab_pow4_re[4]), - .ab_pow4_im4 (ab_pow4_im[4]), .ab_pow5_re4 (ab_pow5_re[4]), - .ab_pow5_im4 (ab_pow5_im[4]), .ab_pow6_re4 (ab_pow6_re[4]), - .ab_pow6_im4 (ab_pow6_im[4]), .ab_pow7_re4 (ab_pow7_re[4]), - .ab_pow7_im4 (ab_pow7_im[4]), .b_pow8_re4 (b_pow8_re[4] ), - .b_pow8_im4 (b_pow8_im[4] ), .a_re5 (ao_re[5] ), - .a_im5 (ao_im[5] ), .b_re5 (bo_re[5] ), - .b_im5 (bo_im[5] ), .ab_re5 (ab_re[5] ), - .ab_im5 (ab_im[5] ), .abb_re5 (abb_re[5] ), - .abb_im5 (abb_im[5] ), .ab_pow3_re5 (ab_pow3_re[5]), - .ab_pow3_im5 (ab_pow3_im[5]), .ab_pow4_re5 (ab_pow4_re[5]), - .ab_pow4_im5 (ab_pow4_im[5]), .ab_pow5_re5 (ab_pow5_re[5]), - .ab_pow5_im5 (ab_pow5_im[5]), .ab_pow6_re5 (ab_pow6_re[5]), - .ab_pow6_im5 (ab_pow6_im[5]), .ab_pow7_re5 (ab_pow7_re[5]), - .ab_pow7_im5 (ab_pow7_im[5]), .b_pow8_re5 (b_pow8_re[5] ), - .b_pow8_im5 (b_pow8_im[5] ), .dout_p0 (dout_0 ), .dout_p1 (dout_1 ), .dout_p2 (dout_2 ), diff --git a/sim/z_dsp/files.f b/sim/z_dsp/files.f index 031c99f..c4b94f2 100644 --- a/sim/z_dsp/files.f +++ b/sim/z_dsp/files.f @@ -1,4 +1,4 @@ -../../rtl/z_dsp/z_dsp.sv +../../rtl/z_dsp/z_dsp.v ../../rtl/z_dsp/TailCorr_top.v ../../rtl/z_dsp/rate_adapter.v ../../rtl/z_dsp/IIR_top.v @@ -8,8 +8,7 @@ ../../rtl/z_dsp/diff_p.v ../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/Trunc.v -../../rtl/z_dsp/mult_C.v -../../rtl/z_dsp/mult_x.v +../../rtl/z_dsp/mult_real.v ../../rtl/z_dsp/syncer.v ../../rtl/z_dsp/sirv_gnrl_dffs.v ../../rtl/model/DW02_mult.v diff --git a/sim/z_dsp/tb_z_dsp.v b/sim/z_dsp/tb_z_dsp.v index 3db53da..0a47e34 100644 --- a/sim/z_dsp/tb_z_dsp.v +++ b/sim/z_dsp/tb_z_dsp.v @@ -10,7 +10,7 @@ begin $fsdbDumpvars(0, TB); $fsdbDumpMDA(); // $srandom(417492050); - source_mode = 2'd3; //1 for rect;2 for random;3 from matlab + source_mode = 2'd2; //1 for rect;2 for random;3 from matlab end reg rstn; @@ -31,9 +31,7 @@ end reg signed [31:0] a_re [5:0]; -reg signed [31:0] a_im [5:0]; reg signed [31:0] b_re [5:0]; -reg signed [31:0] b_im [5:0]; initial begin rstn = 0; @@ -41,56 +39,38 @@ initial begin vldi_coef <= 0; din_rect = 16'd0; a_re[3] <= 0; - a_im[3] <= 0; b_re[3] <= 0; - b_im[3] <= 0; a_re[4] <= 0; - a_im[4] <= 0; b_re[4] <= 0; - b_im[4] <= 0; a_re[5] <= 0; - a_im[5] <= 0; b_re[5] <= 0; - b_im[5] <= 0; repeat(3) @(posedge clk); vldi_coef[0] <= 1; rstn = 1; a_re[0] <= 55007237; - a_im[0] <= 0; b_re[0] <= 2143083068; - b_im[0] <= 0; @(posedge clk); vldi_coef[0] <= 0; a_re[0] <= 0; - a_im[0] <= 0; b_re[0] <= 0; - b_im[0] <= 0; repeat(8) @(posedge clk); vldi_coef[1] <= 1; rstn = 1; a_re[1] <= 32690030; - a_im[1] <= 0; b_re[1] <= 2145807236; - b_im[1] <= 0; @(posedge clk); vldi_coef[1] <= 0; a_re[1] <= 0; - a_im[1] <= 0; b_re[1] <= 0; - b_im[1] <= 0; repeat(8) @(posedge clk); vldi_coef[2] <= 1; rstn = 1; a_re[2] <= 429516; - a_im[2] <= 0; b_re[2] <= 2146812530; - b_im[2] <= 0; @(posedge clk); vldi_coef[2] <= 0; a_re[2] <= 0; - a_im[2] <= 0; b_re[2] <= 0; - b_im[2] <= 0; repeat(108) @(posedge clk); vldi_data <= 1; // repeat(10000) @(posedge clk); @@ -247,29 +227,17 @@ z_dsp inst_z_dsp( .din2 (iir_in[2] ), .din3 (iir_in[3] ), .a0_re (a_re[0] ), - .a0_im (a_im[0] ), .b0_re (b_re[0] ), - .b0_im (b_im[0] ), .a1_re (a_re[1] ), - .a1_im (a_im[1] ), .b1_re (b_re[1] ), - .b1_im (b_im[1] ), .a2_re (a_re[2] ), - .a2_im (a_im[2] ), .b2_re (b_re[2] ), - .b2_im (b_im[2] ), .a3_re (a_re[3] ), - .a3_im (a_im[3] ), .b3_re (b_re[3] ), - .b3_im (b_im[3] ), .a4_re (a_re[4] ), - .a4_im (a_im[4] ), .b4_re (b_re[4] ), - .b4_im (b_im[4] ), .a5_re (a_re[5] ), - .a5_im (a_im[5] ), .b5_re (b_re[5] ), - .b5_im (b_im[5] ), .dout0 (dout_p[0] ), .dout1 (dout_p[1] ), .dout2 (dout_p[2] ),