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v04-enable of clk_div2

This commit is contained in:
thfu 2024-11-12 17:35:22 +08:00
parent e9dbf0564e
commit d6eb195dde
7 changed files with 92754 additions and 313 deletions
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244
rtl/TailCorr_top.v
View File

@ -47,32 +47,32 @@ input clk,
input rstn, input rstn,
input en, input en,
input tc_bypass, input tc_bypass,
input signed [15:0] din_re, input signed [data_in_width-1:0] din_re,
input signed [15:0] din_im, input signed [data_in_width-1:0] din_im,
input signed [31:0] a0_re, input signed [frac_coef_width:0] a0_re,
input signed [31:0] a0_im, input signed [frac_coef_width:0] a0_im,
input signed [31:0] b0_re, input signed [frac_coef_width:0] b0_re,
input signed [31:0] b0_im, input signed [frac_coef_width:0] b0_im,
input signed [31:0] a1_re, input signed [frac_coef_width:0] a1_re,
input signed [31:0] a1_im, input signed [frac_coef_width:0] a1_im,
input signed [31:0] b1_re, input signed [frac_coef_width:0] b1_re,
input signed [31:0] b1_im, input signed [frac_coef_width:0] b1_im,
input signed [31:0] a2_re, input signed [frac_coef_width:0] a2_re,
input signed [31:0] a2_im, input signed [frac_coef_width:0] a2_im,
input signed [31:0] b2_re, input signed [frac_coef_width:0] b2_re,
input signed [31:0] b2_im, input signed [frac_coef_width:0] b2_im,
input signed [31:0] a3_re, input signed [frac_coef_width:0] a3_re,
input signed [31:0] a3_im, input signed [frac_coef_width:0] a3_im,
input signed [31:0] b3_re, input signed [frac_coef_width:0] b3_re,
input signed [31:0] b3_im, input signed [frac_coef_width:0] b3_im,
input signed [31:0] a4_re, input signed [frac_coef_width:0] a4_re,
input signed [31:0] a4_im, input signed [frac_coef_width:0] a4_im,
input signed [31:0] b4_re, input signed [frac_coef_width:0] b4_re,
input signed [31:0] b4_im, input signed [frac_coef_width:0] b4_im,
input signed [31:0] a5_re, input signed [frac_coef_width:0] a5_re,
input signed [31:0] a5_im, input signed [frac_coef_width:0] a5_im,
input signed [31:0] b5_re, input signed [frac_coef_width:0] b5_re,
input signed [31:0] b5_im, input signed [frac_coef_width:0] b5_im,
output signed [15:0] dout, output signed [15:0] dout,
output saturation_0, output saturation_0,
output saturation_1, output saturation_1,
@ -82,14 +82,14 @@ output saturation_4,
output saturation_5 output saturation_5
); );
wire signed [15:0] IIRin_re; wire signed [data_in_width-1:0] IIRin_re;
wire signed [15:0] IIRin_im; wire signed [data_in_width-1:0] IIRin_im;
wire signed [35:0] dout_0; wire signed [data_out_width-1:0] dout_0;
wire signed [35:0] dout_1; wire signed [data_out_width-1:0] dout_1;
wire signed [35:0] dout_2; wire signed [data_out_width-1:0] dout_2;
wire signed [35:0] dout_3; wire signed [data_out_width-1:0] dout_3;
wire signed [35:0] dout_4; wire signed [data_out_width-1:0] dout_4;
wire signed [35:0] dout_5; wire signed [data_out_width-1:0] dout_5;
wire signed [18:0] Ysum; wire signed [18:0] Ysum;
reg signed [15:0] dout_r; reg signed [15:0] dout_r;
@ -274,96 +274,126 @@ inst_iir_5
.saturation (saturation_5 ) .saturation (saturation_5 )
); );
reg signed [35:0] dout_round_0; reg signed [data_out_width-1:0] dout_round_0;
reg signed [35:0] dout_round_1; reg signed [data_out_width-1:0] dout_round_1;
reg signed [35:0] dout_round_2; reg signed [data_out_width-1:0] dout_round_2;
reg signed [35:0] dout_round_3; reg signed [data_out_width-1:0] dout_round_3;
reg signed [35:0] dout_round_4; reg signed [data_out_width-1:0] dout_round_4;
reg signed [35:0] dout_round_5; reg signed [data_out_width-1:0] dout_round_5;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
dout_round_0 <= 'h0; dout_round_0 <= 'h0;
end end
else if(dout_0[35] == 1'b0) else if(en) begin
begin if(dout_0[35] == 1'b0)
dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; begin
end dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
else if (dout_0[35] == 1'b1) end
begin else if (dout_0[35] == 1'b1)
dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; begin
end dout_round_0 <= dout_0 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
end
else begin
dout_round_0 <= dout_round_0;
end
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
dout_round_1 <= 'h0; dout_round_1 <= 'h0;
end end
else if(dout_1[35] == 1'b0) else if(en) begin
begin if(dout_1[35] == 1'b0)
dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; begin
end dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
else if (dout_1[35] == 1'b1) end
begin else if (dout_1[35] == 1'b1)
dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; begin
end dout_round_1 <= dout_1 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
end
else begin
dout_round_1 <= dout_round_1;
end
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
dout_round_2 <= 'h0; dout_round_2 <= 'h0;
end end
else if(dout_2[35] == 1'b0) else if(en) begin
begin if(dout_2[35] == 1'b0)
dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; begin
end dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
else if (dout_2[35] == 1'b1) end
begin else if (dout_2[35] == 1'b1)
dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; begin
end dout_round_2 <= dout_2 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
end
else begin
dout_round_2 <= dout_round_2;
end
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
dout_round_3 <= 'h0; dout_round_3 <= 'h0;
end end
else if(dout_3[35] == 1'b0) else if(en) begin
begin if(dout_3[35] == 1'b0)
dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; begin
end dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
else if (dout_3[35] == 1'b1) end
begin else if (dout_3[35] == 1'b1)
dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; begin
end dout_round_3 <= dout_3 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
end
else begin
dout_round_3 <= dout_round_3;
end
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
dout_round_4 <= 'h0; dout_round_4 <= 'h0;
end end
else if(dout_4[35] == 1'b0) else if(en) begin
begin if(dout_4[35] == 1'b0)
dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; begin
end dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
else if (dout_4[35] == 1'b1) end
begin else if (dout_4[35] == 1'b1)
dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; begin
end dout_round_4 <= dout_4 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
end
else begin
dout_round_4 <= dout_round_4;
end
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if(!rstn) if(!rstn)
begin begin
dout_round_5 <= 'h0; dout_round_5 <= 'h0;
end end
else if(dout_5[35] == 1'b0) else if(en) begin
begin if(dout_5[35] == 1'b0)
dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}}; begin
end dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}};
else if (dout_5[35] == 1'b1) end
begin else if (dout_5[35] == 1'b1)
dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1; begin
end dout_round_5 <= dout_5 + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
end
end
else begin
dout_round_5 <= dout_round_5;
end
wire signed [15:0] dout_cut_0; wire signed [15:0] dout_cut_0;
@ -380,10 +410,44 @@ assign dout_cut_3 = dout_round_3[35:20];
assign dout_cut_4 = dout_round_4[35:20]; assign dout_cut_4 = dout_round_4[35:20];
assign dout_cut_5 = dout_round_5[35:20]; assign dout_cut_5 = dout_round_5[35:20];
reg signed [15:0] dout_cut0_r0;
reg signed [15:0] dout_cut1_r0;
reg signed [15:0] dout_cut2_r0;
reg signed [15:0] dout_cut3_r0;
reg signed [15:0] dout_cut4_r0;
reg signed [15:0] dout_cut5_r0;
always @(posedge clk or negedge rstn)
if(!rstn) begin
dout_cut0_r0 <= 'h0;
dout_cut1_r0 <= 'h0;
dout_cut2_r0 <= 'h0;
dout_cut3_r0 <= 'h0;
dout_cut4_r0 <= 'h0;
dout_cut5_r0 <= 'h0;
end
else if(en) begin
dout_cut0_r0 <= dout_cut_0;
dout_cut1_r0 <= dout_cut_1;
dout_cut2_r0 <= dout_cut_2;
dout_cut3_r0 <= dout_cut_3;
dout_cut4_r0 <= dout_cut_4;
dout_cut5_r0 <= dout_cut_5;
end
else begin
dout_cut0_r0 <= dout_cut0_r0;
dout_cut1_r0 <= dout_cut1_r0;
dout_cut2_r0 <= dout_cut2_r0;
dout_cut3_r0 <= dout_cut3_r0;
dout_cut4_r0 <= dout_cut4_r0;
dout_cut5_r0 <= dout_cut5_r0;
end
reg signed [15:0] din_r0; reg signed [15:0] din_r0;
reg signed [15:0] din_r1; reg signed [15:0] din_r1;
reg signed [15:0] din_r2; reg signed [15:0] din_r2;
reg signed [15:0] din_r3; reg signed [15:0] din_r3;
reg signed [15:0] din_r4;
always @(posedge clk or negedge rstn) always @(posedge clk or negedge rstn)
if (!rstn) if (!rstn)
@ -399,6 +463,7 @@ always @(posedge clk or negedge rstn)
din_r1 <= din_r0; din_r1 <= din_r0;
din_r2 <= din_r1; din_r2 <= din_r1;
din_r3 <= din_r2; din_r3 <= din_r2;
din_r4 <= din_r3;
end end
else else
begin begin
@ -406,9 +471,10 @@ always @(posedge clk or negedge rstn)
din_r1 <= din_r1; din_r1 <= din_r1;
din_r2 <= din_r2; din_r2 <= din_r2;
din_r3 <= din_r3; din_r3 <= din_r3;
din_r4 <= din_r4;
end end
assign Ysum = din_r3 + dout_cut_0 + dout_cut_1 + dout_cut_2 + dout_cut_3 + dout_cut_4 + dout_cut_5; assign Ysum = din_r4 + dout_cut0_r0 + dout_cut1_r0 + dout_cut2_r0 + dout_cut3_r0 + dout_cut4_r0 + dout_cut5_r0;
always@(posedge clk or negedge rstn) always@(posedge clk or negedge rstn)
if (!rstn)begin if (!rstn)begin

1
rtl/diff.v
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@ -70,6 +70,7 @@ always@(posedge clk or negedge rstn)
din_r1 <= din_r1; din_r1 <= din_r1;
out_r <= out_r; out_r <= out_r;
end end
assign dout = out_r; assign dout = out_r;
endmodule endmodule

1
rtl/z_dsp.v
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@ -83,6 +83,7 @@ output saturation_4,
output saturation_5 output saturation_5
); );
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;
reg [10:0] vldo_r; reg [10:0] vldo_r;

92417
rtl/z_dsp_en_Test.edf Normal file
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File diff suppressed because it is too large Load Diff

217
rtl/z_dsp_en_Test.v
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@ -8,7 +8,7 @@
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Relese History // Relese History
// Version Date Author Description // Version Date Author Description
// 0.1 2024-11-04 thfu Test Enable signal using clk divided by 2 // 0.1 2024-11-12 thfu Test Enable signal using clk divided by 2
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
// Keywords : // Keywords :
// //
@ -33,92 +33,55 @@
module z_dsp_en_Test module z_dsp_en_Test
( (
clk, input clk,
input rstn,
rstn, input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve; //2'b10:Double Double data mode;2'b11:reserve;
tc_bypass, input tc_bypass,
intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve; input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
din_re, input signed [15:0] din_re,
din_im, input signed [15:0] din_im,
a0_re, //a0's real part input signed [31:0] a0_re, //a0's real part
a0_im, //a0's image part input signed [31:0] a0_im, //a0's image part
b0_re, input signed [31:0] b0_re,
b0_im, input signed [31:0] b0_im,
a1_re, input signed [31:0] a1_re,
a1_im, input signed [31:0] a1_im,
b1_re, input signed [31:0] b1_re,
b1_im, input signed [31:0] b1_im,
a2_re, input signed [31:0] a2_re,
a2_im, input signed [31:0] a2_im,
b2_re, input signed [31:0] b2_re,
b2_im, input signed [31:0] b2_im,
a3_re, input signed [31:0] a3_re,
a3_im, input signed [31:0] a3_im,
b3_re, input signed [31:0] b3_re,
b3_im, input signed [31:0] b3_im,
a4_re, input signed [31:0] a4_re,
a4_im, input signed [31:0] a4_im,
b4_re, input signed [31:0] b4_re,
b4_im, input signed [31:0] b4_im,
a5_re, input signed [31:0] a5_re,
a5_im, input signed [31:0] a5_im,
b5_re, input signed [31:0] b5_re,
b5_im, input signed [31:0] b5_im,
dout0, output signed [15:0] dout0,
dout1, output signed [15:0] dout1,
dout2, output signed [15:0] dout2,
dout3, output signed [15:0] dout3,
dout4, output signed [15:0] dout4,
dout5, output signed [15:0] dout5,
dout6, output signed [15:0] dout6,
dout7, output signed [15:0] dout7,
vldo output vldo,
output saturation_0,
output saturation_1,
output saturation_2,
output saturation_3,
output saturation_4,
output saturation_5
); );
input rstn;
input clk;
input tc_bypass;
input [1:0] intp_mode;
input [1:0] dac_mode_sel;
input signed [15:0] din_re;
input signed [15:0] din_im;
input signed [36:0] a0_re;
input signed [36:0] a0_im;
input signed [20:0] b0_re;
input signed [20:0] b0_im;
input signed [36:0] a1_re;
input signed [36:0] a1_im;
input signed [20:0] b1_re;
input signed [20:0] b1_im;
input signed [36:0] a2_re;
input signed [36:0] a2_im;
input signed [20:0] b2_re;
input signed [20:0] b2_im;
input signed [36:0] a3_re;
input signed [36:0] a3_im;
input signed [20:0] b3_re;
input signed [20:0] b3_im;
input signed [36:0] a4_re;
input signed [36:0] a4_im;
input signed [20:0] b4_re;
input signed [20:0] b4_im;
input signed [36:0] a5_re;
input signed [36:0] a5_im;
input signed [20:0] b5_re;
input signed [20:0] b5_im;
output signed [15:0] dout0;
output signed [15:0] dout1;
output signed [15:0] dout2;
output signed [15:0] dout3;
output signed [15:0] dout4;
output signed [15:0] dout5;
output signed [15:0] dout6;
output signed [15:0] dout7;
output vldo;
wire signed [15:0] IIR_out; wire signed [15:0] IIR_out;
reg en; reg en;
@ -129,26 +92,14 @@ always@(posedge clk or negedge rstn)
else else
en <= ~en; en <= ~en;
reg [13:0] vldo_r; z_dsp inst_z_dsp
always@(posedge clk or negedge rstn)
if(!rstn)
begin
vldo_r <= 9'b0;
end
else
begin
vldo_r <= {vldo_r[13:0], en};
end
assign vldo = vldo_r[13];
TailCorr_top inst_TailCorr_top
( (
.clk (clk ), .clk (clk ),
.rstn (rstn ), .rstn (rstn ),
.en (en ), .en (en ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (din_re ), .din_re (din_re ),
.din_im (din_im ), .din_im (din_im ),
.a0_re (a0_re ), .a0_re (a0_re ),
@ -175,60 +126,22 @@ TailCorr_top inst_TailCorr_top
.a5_im (a5_im ), .a5_im (a5_im ),
.b5_re (b5_re ), .b5_re (b5_re ),
.b5_im (b5_im ), .b5_im (b5_im ),
.dout (IIR_out ) .dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.dout4 (dout4 ),
.dout5 (dout5 ),
.dout6 (dout6 ),
.dout7 (dout7 ),
.vldo (vldo ),
.saturation_0 (saturation_0 ),
.saturation_1 (saturation_1 ),
.saturation_2 (saturation_2 ),
.saturation_3 (saturation_3 ),
.saturation_4 (saturation_4 ),
.saturation_5 (saturation_5 )
); );
wire signed [15:0] dout_0;
wire signed [15:0] dout_1;
wire signed [15:0] dout_2;
wire signed [15:0] dout_3;
wire signed [15:0] dout_4;
wire signed [15:0] dout_5;
wire signed [15:0] dout_6;
wire signed [15:0] dout_7;
MeanIntp_8 inst_MeanIntp_8
(
.clk (clk ),
.rstn (rstn ),
.en (en ),
.intp_mode (intp_mode ),
.din (IIR_out ),
.dout_0 (dout_0 ),
.dout_1 (dout_1 ),
.dout_2 (dout_2 ),
.dout_3 (dout_3 ),
.dout_4 (dout_4 ),
.dout_5 (dout_5 ),
.dout_6 (dout_6 ),
.dout_7 (dout_7 )
);
lsdacif inst_lsdacif
(
.clk (clk ),
.rstn (rstn ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din0 (dout_0 ),
.din1 (dout_1 ),
.din2 (dout_2 ),
.din3 (dout_3 ),
.din4 (dout_4 ),
.din5 (dout_5 ),
.din6 (dout_6 ),
.din7 (dout_7 ),
.dout0 (dout0 ),
.dout1 (dout1 ),
.dout2 (dout2 ),
.dout3 (dout3 ),
.dout4 (dout4 ),
.dout5 (dout5 ),
.dout6 (dout6 ),
.dout7 (dout7 )
);
endmodule endmodule

1
sim/files.f
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@ -13,6 +13,7 @@
../rtl/lsdacif.v ../rtl/lsdacif.v
../rtl/TailCorr_top.v ../rtl/TailCorr_top.v
../rtl/z_dsp.v ../rtl/z_dsp.v
../rtl/z_dsp_en_Test.v
../rtl/MeanIntp_8.v ../rtl/MeanIntp_8.v
../rtl/DW02_mult.v ../rtl/DW02_mult.v
../rtl/DW_iir_dc.v ../rtl/DW_iir_dc.v

182
tb/tb_z_dsp.v
View File

@ -273,6 +273,75 @@ NCO inst_nco_0(
.sin (sin ) .sin (sin )
); );
wire [1:0] intp_mode;
assign intp_mode = 2'b11;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
assign tc_bypass = 1'b0;
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
wire [15:0] dout_clkl_p3;
wire [15:0] dout_clkl_p4;
wire [15:0] dout_clkl_p5;
wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7;
z_dsp inst_Z_dsp
(
.clk (clk_l ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_clkl_p0 ),
.dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ),
.dout4 (dout_clkl_p4 ),
.dout5 (dout_clkl_p5 ),
.dout6 (dout_clkl_p6 ),
.dout7 (dout_clkl_p7 ),
.vldo ( ),
.saturation_0 ( ),
.saturation_1 ( ),
.saturation_2 ( ),
.saturation_3 ( ),
.saturation_4 ( ),
.saturation_5 ( )
);
wire [15:0] dout_p0; wire [15:0] dout_p0;
wire [15:0] dout_p1; wire [15:0] dout_p1;
@ -283,20 +352,10 @@ wire [15:0] dout_p5;
wire [15:0] dout_p6; wire [15:0] dout_p6;
wire [15:0] dout_p7; wire [15:0] dout_p7;
wire [1:0] intp_mode; z_dsp_en_Test inst_z_dsp_en_Test
assign intp_mode = 2'b11;
wire [1:0] dac_mode_sel;
assign dac_mode_sel = 2'b00;
wire tc_bypass;
assign tc_bypass = 1'b0;
z_dsp inst_Z_dsp
( (
.clk (clk_l ), .clk (clk_h ),
.rstn (rstn ), .rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ), .tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ), .dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ), .intp_mode (intp_mode ),
@ -341,65 +400,9 @@ z_dsp inst_Z_dsp
.saturation_3 ( ), .saturation_3 ( ),
.saturation_4 ( ), .saturation_4 ( ),
.saturation_5 ( ) .saturation_5 ( )
); );
/*
wire [15:0] dout_clkl_p0;
wire [15:0] dout_clkl_p1;
wire [15:0] dout_clkl_p2;
wire [15:0] dout_clkl_p3;
wire [15:0] dout_clkl_p4;
wire [15:0] dout_clkl_p5;
wire [15:0] dout_clkl_p6;
wire [15:0] dout_clkl_p7;
z_dsp inst1_Z_dsp
(
.clk (clk_l ),
.rstn (rstn ),
.en (en ),
.tc_bypass (tc_bypass ),
.dac_mode_sel (dac_mode_sel ),
.intp_mode (intp_mode ),
.din_re (iir_in ),
.din_im (din_im ),
.a0_re (a0_re ),
.a0_im (a0_im ),
.b0_re (b0_re ),
.b0_im (b0_im ),
.a1_re (a1_re ),
.a1_im (a1_im ),
.b1_re (b1_re ),
.b1_im (b1_im ),
.a2_re (a2_re ),
.a2_im (a2_im ),
.b2_re (b2_re ),
.b2_im (b2_im ),
.a3_re (a3_re ),
.a3_im (a3_im ),
.b3_re (b3_re ),
.b3_im (b3_im ),
.a4_re (a4_re ),
.a4_im (a4_im ),
.b4_re (b4_re ),
.b4_im (b4_im ),
.a5_re (a5_re ),
.a5_im (a5_im ),
.b5_re (b5_re ),
.b5_im (b5_im ),
.dout0 (dout_clkl_p0 ),
.dout1 (dout_clkl_p1 ),
.dout2 (dout_clkl_p2 ),
.dout3 (dout_clkl_p3 ),
.dout4 (dout_clkl_p4 ),
.dout5 (dout_clkl_p5 ),
.dout6 (dout_clkl_p6 ),
.dout7 (dout_clkl_p7 )
);
*/
reg [15:0] dout_p0_r1 = 0; reg [15:0] dout_p0_r1 = 0;
reg [15:0] dout_p1_r1 = 0; reg [15:0] dout_p1_r1 = 0;
reg [15:0] dout_p2_r1 = 0; reg [15:0] dout_p2_r1 = 0;
@ -408,6 +411,7 @@ reg [15:0] dout_p4_r1 = 0;
reg [15:0] dout_p5_r1 = 0; reg [15:0] dout_p5_r1 = 0;
reg [15:0] dout_p6_r1 = 0; reg [15:0] dout_p6_r1 = 0;
reg [15:0] dout_p7_r1 = 0; reg [15:0] dout_p7_r1 = 0;
reg [15:0] dout_p0_r2 = 0; reg [15:0] dout_p0_r2 = 0;
reg [15:0] dout_p1_r2 = 0; reg [15:0] dout_p1_r2 = 0;
reg [15:0] dout_p2_r2 = 0; reg [15:0] dout_p2_r2 = 0;
@ -416,6 +420,7 @@ reg [15:0] dout_p4_r2 = 0;
reg [15:0] dout_p5_r2 = 0; reg [15:0] dout_p5_r2 = 0;
reg [15:0] dout_p6_r2 = 0; reg [15:0] dout_p6_r2 = 0;
reg [15:0] dout_p7_r2 = 0; reg [15:0] dout_p7_r2 = 0;
reg [15:0] dout_p0_r3 = 0; reg [15:0] dout_p0_r3 = 0;
reg [15:0] dout_p1_r3 = 0; reg [15:0] dout_p1_r3 = 0;
reg [15:0] dout_p2_r3 = 0; reg [15:0] dout_p2_r3 = 0;
@ -425,6 +430,24 @@ reg [15:0] dout_p5_r3 = 0;
reg [15:0] dout_p6_r3 = 0; reg [15:0] dout_p6_r3 = 0;
reg [15:0] dout_p7_r3 = 0; reg [15:0] dout_p7_r3 = 0;
reg [15:0] dout_p0_r4 = 0;
reg [15:0] dout_p1_r4 = 0;
reg [15:0] dout_p2_r4 = 0;
reg [15:0] dout_p3_r4 = 0;
reg [15:0] dout_p4_r4 = 0;
reg [15:0] dout_p5_r4 = 0;
reg [15:0] dout_p6_r4 = 0;
reg [15:0] dout_p7_r4 = 0;
reg [15:0] dout_p0_r5 = 0;
reg [15:0] dout_p1_r5 = 0;
reg [15:0] dout_p2_r5 = 0;
reg [15:0] dout_p3_r5 = 0;
reg [15:0] dout_p4_r5 = 0;
reg [15:0] dout_p5_r5 = 0;
reg [15:0] dout_p6_r5 = 0;
reg [15:0] dout_p7_r5 = 0;
always @(posedge clk_h or negedge rstn ) begin always @(posedge clk_h or negedge rstn ) begin
if(!rstn) begin if(!rstn) begin
@ -462,6 +485,7 @@ always @(posedge clk_h or negedge rstn ) begin
dout_p5_r1 <= dout_p5; dout_p5_r1 <= dout_p5;
dout_p6_r1 <= dout_p6; dout_p6_r1 <= dout_p6;
dout_p7_r1 <= dout_p7; dout_p7_r1 <= dout_p7;
dout_p0_r2 <= dout_p0_r1; dout_p0_r2 <= dout_p0_r1;
dout_p1_r2 <= dout_p1_r1; dout_p1_r2 <= dout_p1_r1;
dout_p2_r2 <= dout_p2_r1; dout_p2_r2 <= dout_p2_r1;
@ -470,6 +494,7 @@ always @(posedge clk_h or negedge rstn ) begin
dout_p5_r2 <= dout_p5_r1; dout_p5_r2 <= dout_p5_r1;
dout_p6_r2 <= dout_p6_r1; dout_p6_r2 <= dout_p6_r1;
dout_p7_r2 <= dout_p7_r1; dout_p7_r2 <= dout_p7_r1;
dout_p0_r3 <= dout_p0_r2; dout_p0_r3 <= dout_p0_r2;
dout_p1_r3 <= dout_p1_r2; dout_p1_r3 <= dout_p1_r2;
dout_p2_r3 <= dout_p2_r2; dout_p2_r3 <= dout_p2_r2;
@ -479,6 +504,23 @@ always @(posedge clk_h or negedge rstn ) begin
dout_p6_r3 <= dout_p6_r2; dout_p6_r3 <= dout_p6_r2;
dout_p7_r3 <= dout_p7_r2; dout_p7_r3 <= dout_p7_r2;
dout_p0_r4 <= dout_p0_r3;
dout_p1_r4 <= dout_p1_r3;
dout_p2_r4 <= dout_p2_r3;
dout_p3_r4 <= dout_p3_r3;
dout_p4_r4 <= dout_p4_r3;
dout_p5_r4 <= dout_p5_r3;
dout_p6_r4 <= dout_p6_r3;
dout_p7_r4 <= dout_p7_r3;
dout_p0_r5 <= dout_p0_r4;
dout_p1_r5 <= dout_p1_r4;
dout_p2_r5 <= dout_p2_r4;
dout_p3_r5 <= dout_p3_r4;
dout_p4_r5 <= dout_p4_r4;
dout_p5_r5 <= dout_p5_r4;
dout_p6_r5 <= dout_p6_r4;
dout_p7_r5 <= dout_p7_r4;
end end
end end
@ -519,7 +561,7 @@ always@(*)
endcase endcase
join join
/*
reg [15:0] cs_wave1 = 0; reg [15:0] cs_wave1 = 0;
always@(*) always@(*)
@ -559,7 +601,7 @@ always@(*)
wire [15:0] diff; wire [15:0] diff;
assign diff = cs_wave1 - cs_wave; assign diff = cs_wave1 - cs_wave;
*/
integer signed In_fid; integer signed In_fid;
integer signed diff_fid; integer signed diff_fid;
integer signed OrgOut_fid; integer signed OrgOut_fid;