与基于IP核的分支合并
This commit is contained in:
futh0403
commit
d4d76dc68a
89041
edfFile/z_dsp.edf
89041
edfFile/z_dsp.edf
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@ -1,84 +0,0 @@
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : Z_dsp.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.3 2024-11-09 thfu to fit the addition of IP core
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module z_dsp
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(
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input clk,
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input rstn,
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input en, //enable
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input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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input tc_bypass,
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input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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input vldi,
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input signed [15:0] din_re,
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input signed [15:0] din_im,
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input signed [31:0] a0_re, //a0's real part
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input signed [31:0] a0_im, //a0's image part
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input signed [31:0] b0_re,
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input signed [31:0] b0_im,
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input signed [31:0] a1_re,
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input signed [31:0] a1_im,
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input signed [31:0] b1_re,
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input signed [31:0] b1_im,
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input signed [31:0] a2_re,
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input signed [31:0] a2_im,
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input signed [31:0] b2_re,
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input signed [31:0] b2_im,
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input signed [31:0] a3_re,
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input signed [31:0] a3_im,
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input signed [31:0] b3_re,
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input signed [31:0] b3_im,
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input signed [31:0] a4_re,
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input signed [31:0] a4_im,
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input signed [31:0] b4_re,
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input signed [31:0] b4_im,
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input signed [31:0] a5_re,
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input signed [31:0] a5_im,
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input signed [31:0] b5_re,
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input signed [31:0] b5_im,
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output signed [15:0] dout0,
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output signed [15:0] dout1,
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output signed [15:0] dout2,
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output signed [15:0] dout3,
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output vldo,
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output saturation_0,
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output saturation_1,
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output saturation_2,
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output saturation_3,
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output saturation_4,
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output saturation_5
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);
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endmodule
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90520
edfFile/z_dsp_en.edf
90520
edfFile/z_dsp_en.edf
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////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1994 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: KB WSFDB June 30, 1994
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: 714fe7a9
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// DesignWare_release: O-2018.06-DWBB_201806.3
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Multiplier
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// A_width-Bits * B_width-Bits => A_width+B_width Bits
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// Operands A and B can be either both signed (two's complement) or
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// both unsigned numbers. TC determines the coding of the input operands.
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// ie. TC = '1' => signed multiplication
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// TC = '0' => unsigned multiplication
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//
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// FIXED: by replacement with A tested working version
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// that not only doesn't multiplies right it does it
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// two times faster!
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// RPH 07/17/2002
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// Rewrote to comply with the new guidelines
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//------------------------------------------------------------------------------
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module DW02_mult(A,B,TC,PRODUCT);
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parameter integer A_width = 8;
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parameter integer B_width = 8;
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input [A_width-1:0] A;
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input [B_width-1:0] B;
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input TC;
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output [A_width+B_width-1:0] PRODUCT;
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wire [A_width+B_width-1:0] PRODUCT;
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wire [A_width-1:0] temp_a;
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wire [B_width-1:0] temp_b;
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wire [A_width+B_width-2:0] long_temp1,long_temp2;
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (A_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter A_width (lower bound: 1)",
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A_width );
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end
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if (B_width < 1) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter B_width (lower bound: 1)",
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B_width );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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assign temp_a = (A[A_width-1])? (~A + 1'b1) : A;
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assign temp_b = (B[B_width-1])? (~B + 1'b1) : B;
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assign long_temp1 = temp_a * temp_b;
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assign long_temp2 = ~(long_temp1 - 1'b1);
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assign PRODUCT = ((^(A ^ A) !== 1'b0) || (^(B ^ B) !== 1'b0) || (^(TC ^ TC) !== 1'b0) ) ? {A_width+B_width{1'bX}} :
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(TC)? (((A[A_width-1] ^ B[B_width-1]) && (|long_temp1))?
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{1'b1,long_temp2} : {1'b0,long_temp1})
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: A * B;
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endmodule
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150
rtl/nco/coef_c.v
150
rtl/nco/coef_c.v
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@ -1,150 +0,0 @@
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module COEF_C(
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index ,
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C0_C ,
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C1_C ,
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C2_C
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);
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input [4:0] index;
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output [17:0] C0_C;
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output [11:0] C1_C;
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output [5:0] C2_C;
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reg [17:0] C0_C;
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reg [11:0] C1_C;
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reg [5:0] C2_C;
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//------------------------
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//----C0_C OK
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always@(*)
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begin
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case(index)
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5'd 0 : C0_C =18'h3ffff;
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5'd 1 : C0_C =18'h3ffb1;
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5'd 2 : C0_C =18'h3fec4;
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5'd 3 : C0_C =18'h3fd3a;
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5'd 4 : C0_C =18'h3fb12;
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5'd 5 : C0_C =18'h3f84d;
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5'd 6 : C0_C =18'h3f4eb;
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5'd 7 : C0_C =18'h3f0ed;
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5'd 8 : C0_C =18'h3ec53;
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5'd 9 : C0_C =18'h3e71e;
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5'd10 : C0_C =18'h3e150;
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5'd11 : C0_C =18'h3dae8;
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5'd12 : C0_C =18'h3d3e8;
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5'd13 : C0_C =18'h3cc51;
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5'd14 : C0_C =18'h3c424;
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5'd15 : C0_C =18'h3bb62;
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5'd16 : C0_C =18'h3b20d;
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5'd17 : C0_C =18'h3a827;
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5'd18 : C0_C =18'h39daf;
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5'd19 : C0_C =18'h392a9;
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5'd20 : C0_C =18'h38716;
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5'd21 : C0_C =18'h37af8;
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5'd22 : C0_C =18'h36e50;
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5'd23 : C0_C =18'h36121;
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5'd24 : C0_C =18'h3536d;
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5'd25 : C0_C =18'h34535;
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5'd26 : C0_C =18'h3367c;
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5'd27 : C0_C =18'h32744;
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5'd28 : C0_C =18'h31790;
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5'd29 : C0_C =18'h30762;
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5'd30 : C0_C =18'h2f6bc;
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5'd31 : C0_C =18'h2e5a1;
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// default : C0_C = C0_C;
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endcase
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end
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//------------------------
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//----C1_C OK
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always@(*)
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begin
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case(index)
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5'd 0 : C1_C =12'd 0;
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5'd 1 : C1_C =12'd 79;
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5'd 2 : C1_C =12'd 158;
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5'd 3 : C1_C =12'd 237;
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5'd 4 : C1_C =12'd 315;
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5'd 5 : C1_C =12'd 394;
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5'd 6 : C1_C =12'd 472;
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5'd 7 : C1_C =12'd 550;
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5'd 8 : C1_C =12'd 628;
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5'd 9 : C1_C =12'd 705;
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5'd10 : C1_C =12'd 782;
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5'd11 : C1_C =12'd 858;
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5'd12 : C1_C =12'd 934;
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5'd13 : C1_C =12'd1009;
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5'd14 : C1_C =12'd1084;
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5'd15 : C1_C =12'd1158;
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5'd16 : C1_C =12'd1231;
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5'd17 : C1_C =12'd1304;
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5'd18 : C1_C =12'd1376;
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5'd19 : C1_C =12'd1446;
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5'd20 : C1_C =12'd1517;
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5'd21 : C1_C =12'd1586;
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5'd22 : C1_C =12'd1654;
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5'd23 : C1_C =12'd1721;
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5'd24 : C1_C =12'd1787;
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5'd25 : C1_C =12'd1852;
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5'd26 : C1_C =12'd1916;
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5'd27 : C1_C =12'd1979;
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5'd28 : C1_C =12'd2041;
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5'd29 : C1_C =12'd2101;
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5'd30 : C1_C =12'd2161;
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5'd31 : C1_C =12'd2218;
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// default : C1_C = C1_C;
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endcase
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end
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//------------------------
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//----C2_C
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always@(*)
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begin
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case(index)
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5'd 0 : C2_C =6'd39;
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5'd 1 : C2_C =6'd39;
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5'd 2 : C2_C =6'd39;
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5'd 3 : C2_C =6'd39;
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5'd 4 : C2_C =6'd39;
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5'd 5 : C2_C =6'd39;
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5'd 6 : C2_C =6'd39;
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5'd 7 : C2_C =6'd39;
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5'd 8 : C2_C =6'd39;
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5'd 9 : C2_C =6'd38;
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5'd10 : C2_C =6'd38;
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5'd11 : C2_C =6'd38;
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5'd12 : C2_C =6'd38;
|
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5'd13 : C2_C =6'd37;
|
||||
5'd14 : C2_C =6'd37;
|
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5'd15 : C2_C =6'd37;
|
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5'd16 : C2_C =6'd36;
|
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5'd17 : C2_C =6'd36;
|
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5'd18 : C2_C =6'd35;
|
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5'd19 : C2_C =6'd35;
|
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5'd20 : C2_C =6'd35;
|
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5'd21 : C2_C =6'd34;
|
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5'd22 : C2_C =6'd34;
|
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5'd23 : C2_C =6'd33;
|
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5'd24 : C2_C =6'd33;
|
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5'd25 : C2_C =6'd32;
|
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5'd26 : C2_C =6'd31;
|
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5'd27 : C2_C =6'd31;
|
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5'd28 : C2_C =6'd30;
|
||||
5'd29 : C2_C =6'd30;
|
||||
5'd30 : C2_C =6'd29;
|
||||
5'd31 : C2_C =6'd28;
|
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// default : C2_C = C2_C;
|
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endcase
|
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|
||||
|
||||
end
|
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endmodule
|
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|
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|
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155
rtl/nco/coef_s.v
155
rtl/nco/coef_s.v
|
|
@ -1,155 +0,0 @@
|
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module COEF_S(
|
||||
|
||||
index ,
|
||||
C0_S ,
|
||||
C1_S ,
|
||||
C2_S
|
||||
|
||||
);
|
||||
|
||||
input [4:0] index;
|
||||
|
||||
output [17:0] C0_S;
|
||||
output [11:0] C1_S;
|
||||
output [4:0] C2_S;
|
||||
|
||||
|
||||
reg [17:0] C0_S;
|
||||
reg [11:0] C1_S;
|
||||
reg [4:0] C2_S;
|
||||
|
||||
//------------------------
|
||||
//----C0_S
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C0_S =18'd 0;
|
||||
5'd 1 : C0_S =18'd 6433;
|
||||
5'd 2 : C0_S =18'd 12863;
|
||||
5'd 3 : C0_S =18'd 19284;
|
||||
5'd 4 : C0_S =18'd 25695;
|
||||
5'd 5 : C0_S =18'd 32089;
|
||||
5'd 6 : C0_S =18'd 38464;
|
||||
5'd 7 : C0_S =18'd 44817;
|
||||
5'd 8 : C0_S =18'd 51142;
|
||||
5'd 9 : C0_S =18'd 57436;
|
||||
5'd10 : C0_S =18'd 63696;
|
||||
5'd11 : C0_S =18'd 69917;
|
||||
5'd12 : C0_S =18'd 76096;
|
||||
5'd13 : C0_S =18'd 82230;
|
||||
5'd14 : C0_S =18'd 88314;
|
||||
5'd15 : C0_S =18'd 94344;
|
||||
5'd16 : C0_S =18'd100318;
|
||||
5'd17 : C0_S =18'd106232;
|
||||
5'd18 : C0_S =18'd112081;
|
||||
5'd19 : C0_S =18'd117863;
|
||||
5'd20 : C0_S =18'd123574;
|
||||
5'd21 : C0_S =18'd129210;
|
||||
5'd22 : C0_S =18'd134769;
|
||||
5'd23 : C0_S =18'd140246;
|
||||
5'd24 : C0_S =18'd145639;
|
||||
5'd25 : C0_S =18'd150945;
|
||||
5'd26 : C0_S =18'd156159;
|
||||
5'd27 : C0_S =18'd161279;
|
||||
5'd28 : C0_S =18'd166302;
|
||||
5'd29 : C0_S =18'd171225;
|
||||
5'd30 : C0_S =18'd176045;
|
||||
5'd31 : C0_S =18'd180759;
|
||||
// default : C0_S = C0_S;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
//------------------------
|
||||
|
||||
|
||||
//------------------------
|
||||
//----C1_S OK
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C1_S =12'd3217;
|
||||
5'd 1 : C1_S =12'd3216;
|
||||
5'd 2 : C1_S =12'd3213;
|
||||
5'd 3 : C1_S =12'd3208;
|
||||
5'd 4 : C1_S =12'd3202;
|
||||
5'd 5 : C1_S =12'd3193;
|
||||
5'd 6 : C1_S =12'd3182;
|
||||
5'd 7 : C1_S =12'd3170;
|
||||
5'd 8 : C1_S =12'd3155;
|
||||
5'd 9 : C1_S =12'd3139;
|
||||
5'd10 : C1_S =12'd3121;
|
||||
5'd11 : C1_S =12'd3101;
|
||||
5'd12 : C1_S =12'd3079;
|
||||
5'd13 : C1_S =12'd3055;
|
||||
5'd14 : C1_S =12'd3029;
|
||||
5'd15 : C1_S =12'd3002;
|
||||
5'd16 : C1_S =12'd2972;
|
||||
5'd17 : C1_S =12'd2941;
|
||||
5'd18 : C1_S =12'd2908;
|
||||
5'd19 : C1_S =12'd2874;
|
||||
5'd20 : C1_S =12'd2837;
|
||||
5'd21 : C1_S =12'd2799;
|
||||
5'd22 : C1_S =12'd2759;
|
||||
5'd23 : C1_S =12'd2718;
|
||||
5'd24 : C1_S =12'd2675;
|
||||
5'd25 : C1_S =12'd2630;
|
||||
5'd26 : C1_S =12'd2584;
|
||||
5'd27 : C1_S =12'd2536;
|
||||
5'd28 : C1_S =12'd2487;
|
||||
5'd29 : C1_S =12'd2436;
|
||||
5'd30 : C1_S =12'd2384;
|
||||
5'd31 : C1_S =12'd2330;
|
||||
// default : C1_S = C1_S;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
//------------------------
|
||||
//----C2_S
|
||||
always@(*)
|
||||
begin
|
||||
|
||||
case(index)
|
||||
5'd 0 : C2_S =5'd 0;
|
||||
5'd 1 : C2_S =5'd 1;
|
||||
5'd 2 : C2_S =5'd 2;
|
||||
5'd 3 : C2_S =5'd 3;
|
||||
5'd 4 : C2_S =5'd 4;
|
||||
5'd 5 : C2_S =5'd 5;
|
||||
5'd 6 : C2_S =5'd 6;
|
||||
5'd 7 : C2_S =5'd 7;
|
||||
5'd 8 : C2_S =5'd 8;
|
||||
5'd 9 : C2_S =5'd 9;
|
||||
5'd10 : C2_S =5'd10;
|
||||
5'd11 : C2_S =5'd11;
|
||||
5'd12 : C2_S =5'd12;
|
||||
5'd13 : C2_S =5'd13;
|
||||
5'd14 : C2_S =5'd14;
|
||||
5'd15 : C2_S =5'd15;
|
||||
5'd16 : C2_S =5'd16;
|
||||
5'd17 : C2_S =5'd16;
|
||||
5'd18 : C2_S =5'd17;
|
||||
5'd19 : C2_S =5'd18;
|
||||
5'd20 : C2_S =5'd19;
|
||||
5'd21 : C2_S =5'd20;
|
||||
5'd22 : C2_S =5'd21;
|
||||
5'd23 : C2_S =5'd22;
|
||||
5'd24 : C2_S =5'd22;
|
||||
5'd25 : C2_S =5'd23;
|
||||
5'd26 : C2_S =5'd24;
|
||||
5'd27 : C2_S =5'd25;
|
||||
5'd28 : C2_S =5'd25;
|
||||
5'd29 : C2_S =5'd26;
|
||||
5'd30 : C2_S =5'd27;
|
||||
5'd31 : C2_S =5'd28;
|
||||
// default : C2_S = C2_S;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
144
rtl/nco/cos_op.v
144
rtl/nco/cos_op.v
|
|
@ -1,144 +0,0 @@
|
|||
module COS_OP(
|
||||
clk ,
|
||||
rstn ,
|
||||
pha_map ,
|
||||
pha_indx_msb ,
|
||||
cos_op_o
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input [18:0] pha_map;
|
||||
output [2:0] pha_indx_msb;
|
||||
output [14:0] cos_op_o;
|
||||
|
||||
wire [2:0] pha_indx_msb_w;
|
||||
assign pha_indx_msb_w=pha_map[18:16];
|
||||
|
||||
wire [15:0] pha_indx_lsb;
|
||||
assign pha_indx_lsb=pha_map[15:0];
|
||||
wire [15:0] pha_op;
|
||||
assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb;
|
||||
|
||||
wire [4:0] indx;
|
||||
assign indx=pha_op[15:11];
|
||||
wire [10:0] x_w;
|
||||
assign x_w=pha_op[10:0];
|
||||
wire [17:0] c0;
|
||||
wire [11:0] c1;
|
||||
wire [5:0] c2;
|
||||
|
||||
|
||||
COEF_C coef_c_inst1(
|
||||
.index(indx) ,
|
||||
.C0_C(c0) ,
|
||||
.C1_C(c1) ,
|
||||
.C2_C(c2)
|
||||
);
|
||||
|
||||
reg[17:0] c0_r1;
|
||||
reg[17:0] c0_r2;
|
||||
reg[17:0] c0_r3;
|
||||
reg[17:0] c0_r4;
|
||||
reg[17:0] c0_r5;
|
||||
reg[17:0] c0_r6;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c0_r1<=c0;
|
||||
c0_r2<=c0_r1;
|
||||
c0_r3<=c0_r2;
|
||||
c0_r4<=c0_r3;
|
||||
c0_r5<=c0_r4;
|
||||
c0_r6<=c0_r5;
|
||||
end
|
||||
reg [11:0] c1_r1;
|
||||
reg [11:0] c1_r2;
|
||||
reg [11:0] c1_r3;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c1_r1<=c1;
|
||||
c1_r2<=c1_r1;
|
||||
c1_r3<=c1_r2;
|
||||
end
|
||||
reg [5:0] c2_r1;
|
||||
always@(posedge clk)
|
||||
c2_r1<=c2;
|
||||
reg[10:0] x_r1;
|
||||
reg[10:0] x_r2;
|
||||
reg[10:0] x_r3;
|
||||
reg[10:0] x_r4;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
x_r1<=x_w;
|
||||
x_r2<=x_r1;
|
||||
x_r3<=x_r2;
|
||||
x_r4<=x_r3;
|
||||
end
|
||||
|
||||
wire [16:0] c2x;
|
||||
|
||||
DW_mult_pipe #(11,6,2,0,1) inst_mult_0(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r1 ),
|
||||
.b (c2_r1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2x )
|
||||
);
|
||||
|
||||
wire [5:0] c2x_w;
|
||||
assign c2x_w=c2x[10]?(c2x[16:11]+6'd1):c2x[16:11];
|
||||
|
||||
reg [11:0] c2xc1;
|
||||
always@(posedge clk)
|
||||
c2xc1<=c1_r2+c2x_w;
|
||||
wire [22:0] c2xc1x;
|
||||
DW_mult_pipe #(11,12,3,0,1) inst_mult_1(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r3 ),
|
||||
.b (c2xc1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2xc1x )
|
||||
);
|
||||
|
||||
|
||||
wire [12:0] c2xc1x_w;
|
||||
assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10];
|
||||
reg [12:0] c2xc1x_r;
|
||||
always@(posedge clk)
|
||||
c2xc1x_r<=c2xc1x_w;
|
||||
wire [17:0] c2xc1xc0;
|
||||
assign c2xc1xc0 =c0_r6-c2xc1x_r;
|
||||
|
||||
wire[15:0] c2xc1xc0_w1;
|
||||
assign c2xc1xc0_w1=c2xc1xc0[2]?({1'b0,c2xc1xc0[17:3]}+15'd1):{1'b0,c2xc1xc0[17:3]};
|
||||
|
||||
wire[14:0] c2xc1xc0_w;
|
||||
assign c2xc1xc0_w=(c2xc1xc0_w1>=15'd32767)?15'd32767:c2xc1xc0_w1[14:0];
|
||||
reg [14:0] c2xc1xc0_r;
|
||||
always@(posedge clk)
|
||||
c2xc1xc0_r<=c2xc1xc0_w;
|
||||
assign cos_op_o=c2xc1xc0_r;
|
||||
reg[2:0] pha_indx_msb_r1;
|
||||
reg[2:0] pha_indx_msb_r2;
|
||||
reg[2:0] pha_indx_msb_r3;
|
||||
reg[2:0] pha_indx_msb_r4;
|
||||
reg[2:0] pha_indx_msb_r5;
|
||||
reg[2:0] pha_indx_msb_r6;
|
||||
reg[2:0] pha_indx_msb_r7;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
pha_indx_msb_r1<=pha_indx_msb_w;
|
||||
pha_indx_msb_r2<=pha_indx_msb_r1;
|
||||
pha_indx_msb_r3<=pha_indx_msb_r2;
|
||||
pha_indx_msb_r4<=pha_indx_msb_r3;
|
||||
pha_indx_msb_r5<=pha_indx_msb_r4;
|
||||
pha_indx_msb_r6<=pha_indx_msb_r5;
|
||||
pha_indx_msb_r7<=pha_indx_msb_r6;
|
||||
end
|
||||
|
||||
assign pha_indx_msb=pha_indx_msb_r7;
|
||||
endmodule
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
module NCO(
|
||||
clk,
|
||||
rstn,
|
||||
phase_manual_clr,
|
||||
phase_auto_clr,
|
||||
fcw,
|
||||
pha,
|
||||
|
||||
cos,
|
||||
|
||||
sin
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input phase_manual_clr;
|
||||
input phase_auto_clr;
|
||||
input [47:0] fcw;
|
||||
input [15:0] pha;
|
||||
|
||||
output [15:0] cos;
|
||||
output [15:0] sin;
|
||||
|
||||
|
||||
wire clr_acc;
|
||||
wire clr_fix;
|
||||
assign clr_acc = phase_auto_clr | phase_manual_clr;
|
||||
assign clr_fix = phase_manual_clr;
|
||||
|
||||
wire [15:0] s1_i_o;
|
||||
wire [15:0] s2_i_o;
|
||||
wire [15:0] s3_i_o;
|
||||
|
||||
P_NCO inst_p_nco(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.clr (clr_fix ),
|
||||
.clr_acc (clr_acc ),
|
||||
.pha (pha ),
|
||||
.s1 (s1_i_o ),
|
||||
.s2 (s2_i_o ),
|
||||
.s3 (s3_i_o ),
|
||||
.s1_o (s1_i_o ),
|
||||
.s2_o (s2_i_o ),
|
||||
.s3_o (s3_i_o ),
|
||||
.fcw (fcw ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
module P_NCO(
|
||||
clk,
|
||||
rstn,
|
||||
clr,
|
||||
clr_acc,
|
||||
pha,
|
||||
|
||||
s1,
|
||||
s2,
|
||||
s3,
|
||||
|
||||
s1_o,
|
||||
s2_o,
|
||||
s3_o,
|
||||
|
||||
fcw,
|
||||
|
||||
cos,
|
||||
sin
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input clr;
|
||||
input clr_acc;
|
||||
input [15:0] pha;
|
||||
|
||||
input [15:0] s1;
|
||||
input [15:0] s2;
|
||||
input [15:0] s3;
|
||||
|
||||
output [15:0] s1_o;
|
||||
output [15:0] s2_o;
|
||||
output [15:0] s3_o;
|
||||
|
||||
output [15:0] cos;
|
||||
output [15:0] sin;
|
||||
|
||||
|
||||
input [47:0] fcw;
|
||||
|
||||
|
||||
reg [15:0] pha_r;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
pha_r <= 16'd0;
|
||||
else
|
||||
pha_r <= pha;
|
||||
|
||||
wire [18:0] pha0;
|
||||
|
||||
PIPE3_ACC_48BIT inst_pipe(.clk(clk),.rstn(rstn),.in(fcw),.clr(clr_acc),.ptw(pha),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha0));
|
||||
|
||||
PH2AMP inst_ph2amp_0(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha0) ,
|
||||
.sin_o(sin) ,
|
||||
.cos_o(cos)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
module PH2AMP(
|
||||
clk ,
|
||||
rstn ,
|
||||
pha_map ,
|
||||
sin_o ,
|
||||
cos_o
|
||||
);
|
||||
input clk;
|
||||
input rstn;
|
||||
input [18:0] pha_map;
|
||||
|
||||
output [15:0] sin_o;
|
||||
output [15:0] cos_o;
|
||||
|
||||
//wire [2:0] pha_indx_msb_s;
|
||||
wire [14:0] sin_w;
|
||||
SIN_OP inst_sin_op(
|
||||
.clk(clk),
|
||||
.rstn(rstn),
|
||||
.pha_map(pha_map),
|
||||
// .pha_indx_msb(pha_indx_msb_s),
|
||||
.sin_op_o(sin_w)
|
||||
);
|
||||
wire [2:0] pha_indx_msb_c;
|
||||
wire [14:0] cos_w;
|
||||
COS_OP inst_cos_op(
|
||||
.clk(clk) ,
|
||||
.rstn(rstn) ,
|
||||
.pha_map(pha_map) ,
|
||||
.pha_indx_msb(pha_indx_msb_c),
|
||||
.cos_op_o(cos_w)
|
||||
);
|
||||
wire[15:0] cos_w_1;
|
||||
wire[15:0] sin_w_1;
|
||||
wire[15:0] cos_w_0;
|
||||
wire[15:0] sin_w_0;//0:-,1:+
|
||||
|
||||
assign cos_w_1={1'b0,cos_w};
|
||||
assign sin_w_1={1'b0,sin_w};
|
||||
assign cos_w_0=(cos_w_1==16'd0)?16'd0:~cos_w_1+16'd1;
|
||||
assign sin_w_0=(sin_w_1==16'd0)?16'd0:~sin_w_1+16'd1;
|
||||
|
||||
reg[15:0] cos_tmp;
|
||||
reg[15:0] sin_tmp;
|
||||
always@(posedge clk)
|
||||
case(pha_indx_msb_c)//synopsys parallel_case
|
||||
3'b000:begin
|
||||
cos_tmp<=cos_w_1;
|
||||
sin_tmp<=sin_w_1;
|
||||
end
|
||||
3'b001:begin
|
||||
cos_tmp<=sin_w_1;
|
||||
sin_tmp<=cos_w_1;
|
||||
end
|
||||
3'b010:begin
|
||||
cos_tmp<=sin_w_0;
|
||||
sin_tmp<=cos_w_1;
|
||||
end
|
||||
3'b011:begin
|
||||
cos_tmp<=cos_w_0;
|
||||
sin_tmp<=sin_w_1;
|
||||
end
|
||||
3'b100:begin
|
||||
cos_tmp<=cos_w_0;
|
||||
sin_tmp<=sin_w_0;
|
||||
end
|
||||
3'b101:begin
|
||||
cos_tmp<=sin_w_0;
|
||||
sin_tmp<=cos_w_0;
|
||||
end
|
||||
3'b110:begin
|
||||
cos_tmp<=sin_w_1;
|
||||
sin_tmp<=cos_w_0;
|
||||
end
|
||||
3'b111:begin
|
||||
cos_tmp<=cos_w_1;
|
||||
sin_tmp<=sin_w_0;
|
||||
end
|
||||
endcase
|
||||
|
||||
assign sin_o=sin_tmp;
|
||||
assign cos_o=cos_tmp;
|
||||
endmodule
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
|
||||
|
||||
module PIPE3_ACC_48BIT(
|
||||
clk,
|
||||
rstn,
|
||||
in,
|
||||
clr,
|
||||
ptw,
|
||||
s_i_1,
|
||||
s_i_2,
|
||||
s_i_3,
|
||||
s_o_1,
|
||||
s_o_2,
|
||||
s_o_3,
|
||||
out
|
||||
);
|
||||
|
||||
//---
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input [47:0] in;
|
||||
input clr;
|
||||
input [15:0] ptw;
|
||||
|
||||
input [15:0] s_i_1;
|
||||
input [15:0] s_i_2;
|
||||
input [15:0] s_i_3;
|
||||
|
||||
output [15:0] s_o_1;
|
||||
output [15:0] s_o_2;
|
||||
output [15:0] s_o_3;
|
||||
output [18:0] out;
|
||||
|
||||
//----------------------------------------------------------------------------------------------------
|
||||
|
||||
reg [47:0] acc;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
acc<=48'h0;
|
||||
else if(clr)
|
||||
acc<=48'h0;
|
||||
else
|
||||
acc<={s_i_1,s_i_2,s_i_3}+in;
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------------------------------
|
||||
wire [15:0] s1;
|
||||
wire [15:0] s2;
|
||||
wire [15:0] s3;
|
||||
|
||||
assign s_o_1 = acc[47:32];
|
||||
assign s_o_2 = acc[31:16];
|
||||
assign s_o_3 = acc[15:0];
|
||||
|
||||
wire[18:0] pha_w;
|
||||
assign pha_w=acc[47:29];
|
||||
reg[18:0] pha_r;
|
||||
always@(posedge clk)
|
||||
pha_r<=pha_w+{ptw,3'b0};
|
||||
|
||||
assign out=pha_r;
|
||||
//END
|
||||
endmodule
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
|
||||
|
||||
module PIPE3_ADD_48BIT(
|
||||
clk,
|
||||
rstn,
|
||||
in,
|
||||
clr,
|
||||
ptw,
|
||||
s1,
|
||||
s2,
|
||||
s3,
|
||||
out
|
||||
);
|
||||
|
||||
//---
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input [47:0] in;
|
||||
input clr;
|
||||
input [15:0] ptw;
|
||||
|
||||
input [15:0] s1;
|
||||
input [15:0] s2;
|
||||
input [15:0] s3;
|
||||
output [18:0] out;
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------------------------------
|
||||
|
||||
reg [47:0] acc;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
acc<=48'h0;
|
||||
else if(clr)
|
||||
acc<=48'h0;
|
||||
else
|
||||
acc<={s1,s2,s3}+in;
|
||||
//---
|
||||
|
||||
wire[18:0] pha_w;
|
||||
assign pha_w=acc[47:29];
|
||||
reg[18:0] pha_r;
|
||||
always@(posedge clk)
|
||||
pha_r<=pha_w+{ptw,3'b0};
|
||||
|
||||
|
||||
assign out=pha_r;
|
||||
//END
|
||||
endmodule
|
||||
144
rtl/nco/sin_op.v
144
rtl/nco/sin_op.v
|
|
@ -1,144 +0,0 @@
|
|||
module SIN_OP(
|
||||
clk,
|
||||
rstn,
|
||||
pha_map,
|
||||
// pha_indx_msb,
|
||||
sin_op_o
|
||||
);
|
||||
|
||||
input clk;
|
||||
input rstn;
|
||||
input[18:0] pha_map;
|
||||
//output [2:0] pha_indx_msb;
|
||||
output [14:0] sin_op_o;
|
||||
|
||||
wire [2:0] pha_indx_msb_w;
|
||||
assign pha_indx_msb_w=pha_map[18:16];
|
||||
|
||||
wire [15:0] pha_indx_lsb;
|
||||
assign pha_indx_lsb=pha_map[15:0];
|
||||
wire [15:0] pha_op;
|
||||
assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb;
|
||||
|
||||
wire [4:0] indx;
|
||||
assign indx=pha_op[15:11];
|
||||
wire [10:0] x_w;
|
||||
assign x_w=pha_op[10:0];
|
||||
wire [17:0] c0;
|
||||
wire [11:0] c1;
|
||||
wire [4:0] c2;
|
||||
|
||||
COEF_S coef_s_inst1(
|
||||
.index(indx) ,
|
||||
.C0_S(c0) ,
|
||||
.C1_S(c1) ,
|
||||
.C2_S(c2)
|
||||
);
|
||||
|
||||
reg[17:0] c0_r1;
|
||||
reg[17:0] c0_r2;
|
||||
reg[17:0] c0_r3;
|
||||
reg[17:0] c0_r4;
|
||||
reg[17:0] c0_r5;
|
||||
reg[17:0] c0_r6;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c0_r1<=c0;
|
||||
c0_r2<=c0_r1;
|
||||
c0_r3<=c0_r2;
|
||||
c0_r4<=c0_r3;
|
||||
c0_r5<=c0_r4;
|
||||
c0_r6<=c0_r5;
|
||||
end
|
||||
reg [11:0] c1_r1;
|
||||
reg [11:0] c1_r2;
|
||||
reg [11:0] c1_r3;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
c1_r1<=c1;
|
||||
c1_r2<=c1_r1;
|
||||
c1_r3<=c1_r2;
|
||||
end
|
||||
reg [4:0] c2_r1;
|
||||
always@(posedge clk)
|
||||
c2_r1<=c2;
|
||||
reg[10:0] x_r1;
|
||||
reg[10:0] x_r2;
|
||||
reg[10:0] x_r3;
|
||||
reg[10:0] x_r4;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
x_r1<=x_w;
|
||||
x_r2<=x_r1;
|
||||
x_r3<=x_r2;
|
||||
x_r4<=x_r3;
|
||||
end
|
||||
|
||||
wire [15:0] c2x;
|
||||
|
||||
DW_mult_pipe #(11,5,2,0,1) inst_mult_0(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r1 ),
|
||||
.b (c2_r1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2x )
|
||||
);
|
||||
|
||||
|
||||
wire [4:0] c2x_w;
|
||||
assign c2x_w=c2x[10]?(c2x[15:11]+5'd1):c2x[15:11];
|
||||
reg [11:0] c2xc1;
|
||||
always@(posedge clk)
|
||||
c2xc1<=c1_r2-c2x_w;
|
||||
|
||||
wire [22:0] c2xc1x;
|
||||
|
||||
DW_mult_pipe #(11,12,3,0,1) inst_mult_1(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.en (1'b1 ),
|
||||
.a (x_r3 ),
|
||||
.b (c2xc1 ),
|
||||
.tc (1'b0 ),
|
||||
.product (c2xc1x )
|
||||
);
|
||||
|
||||
wire [12:0] c2xc1x_w;
|
||||
assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10];
|
||||
reg [12:0] c2xc1x_r;
|
||||
always@(posedge clk)
|
||||
c2xc1x_r<=c2xc1x_w;
|
||||
wire[17:0] c2xc1xc0;
|
||||
assign c2xc1xc0=c0_r6+c2xc1x_r;
|
||||
wire [14:0] c2xc1xc0_w;
|
||||
assign c2xc1xc0_w=c2xc1xc0[2]?(c2xc1xc0[17:3]+13'd1):c2xc1xc0[17:3];
|
||||
reg [14:0] c2xc1xc0_r;
|
||||
always@(posedge clk)
|
||||
c2xc1xc0_r<=c2xc1xc0_w;
|
||||
|
||||
assign sin_op_o=c2xc1xc0_r;
|
||||
/*
|
||||
reg[2:0] pha_indx_msb_r1;
|
||||
reg[2:0] pha_indx_msb_r2;
|
||||
reg[2:0] pha_indx_msb_r3;
|
||||
reg[2:0] pha_indx_msb_r4;
|
||||
reg[2:0] pha_indx_msb_r5;
|
||||
reg[2:0] pha_indx_msb_r6;
|
||||
reg[2:0] pha_indx_msb_r7;
|
||||
always@(posedge clk)
|
||||
begin
|
||||
pha_indx_msb_r1<=pha_indx_msb_w;
|
||||
pha_indx_msb_r2<=pha_indx_msb_r1;
|
||||
pha_indx_msb_r3<=pha_indx_msb_r2;
|
||||
pha_indx_msb_r4<=pha_indx_msb_r3;
|
||||
pha_indx_msb_r5<=pha_indx_msb_r4;
|
||||
pha_indx_msb_r6<=pha_indx_msb_r5;
|
||||
pha_indx_msb_r7<=pha_indx_msb_r6;
|
||||
end
|
||||
|
||||
end
|
||||
assign pha_indx_msb=pha_indx_msb_r7;
|
||||
*/
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,695 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : IIR_Filter.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.4 2024-05-28 thfu
|
||||
//2024-05-28 10:22:49
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module CoefGen #(
|
||||
parameter data_in_width = 32
|
||||
,parameter coef_width = 32
|
||||
,parameter frac_data_out_width = 20//X for in,5
|
||||
,parameter frac_coef_width = 31//division
|
||||
)
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input [5:0] vldi
|
||||
,input signed [31:0] a0_re
|
||||
,input signed [31:0] a0_im
|
||||
,input signed [31:0] b0_re
|
||||
,input signed [31:0] b0_im
|
||||
,input signed [31:0] a1_re
|
||||
,input signed [31:0] a1_im
|
||||
,input signed [31:0] b1_re
|
||||
,input signed [31:0] b1_im
|
||||
,input signed [31:0] a2_re
|
||||
,input signed [31:0] a2_im
|
||||
,input signed [31:0] b2_re
|
||||
,input signed [31:0] b2_im
|
||||
,input signed [31:0] a3_re
|
||||
,input signed [31:0] a3_im
|
||||
,input signed [31:0] b3_re
|
||||
,input signed [31:0] b3_im
|
||||
,input signed [31:0] a4_re
|
||||
,input signed [31:0] a4_im
|
||||
,input signed [31:0] b4_re
|
||||
,input signed [31:0] b4_im
|
||||
,input signed [31:0] a5_re
|
||||
,input signed [31:0] a5_im
|
||||
,input signed [31:0] b5_re
|
||||
,input signed [31:0] b5_im
|
||||
,output reg signed [31:0] a_re0
|
||||
,output reg signed [31:0] a_im0
|
||||
,output reg signed [31:0] ab_re0
|
||||
,output reg signed [31:0] ab_im0
|
||||
,output reg signed [31:0] abb_re0
|
||||
,output reg signed [31:0] abb_im0
|
||||
,output reg signed [31:0] ab_pow3_re0
|
||||
,output reg signed [31:0] ab_pow3_im0
|
||||
,output reg signed [31:0] ab_pow4_re0
|
||||
,output reg signed [31:0] ab_pow4_im0
|
||||
,output reg signed [31:0] ab_pow5_re0
|
||||
,output reg signed [31:0] ab_pow5_im0
|
||||
,output reg signed [31:0] ab_pow6_re0
|
||||
,output reg signed [31:0] ab_pow6_im0
|
||||
,output reg signed [31:0] ab_pow7_re0
|
||||
,output reg signed [31:0] ab_pow7_im0
|
||||
,output reg signed [31:0] b_pow8_re0
|
||||
,output reg signed [31:0] b_pow8_im0
|
||||
,output reg signed [31:0] a_re1
|
||||
,output reg signed [31:0] a_im1
|
||||
,output reg signed [31:0] ab_re1
|
||||
,output reg signed [31:0] ab_im1
|
||||
,output reg signed [31:0] abb_re1
|
||||
,output reg signed [31:0] abb_im1
|
||||
,output reg signed [31:0] ab_pow3_re1
|
||||
,output reg signed [31:0] ab_pow3_im1
|
||||
,output reg signed [31:0] ab_pow4_re1
|
||||
,output reg signed [31:0] ab_pow4_im1
|
||||
,output reg signed [31:0] ab_pow5_re1
|
||||
,output reg signed [31:0] ab_pow5_im1
|
||||
,output reg signed [31:0] ab_pow6_re1
|
||||
,output reg signed [31:0] ab_pow6_im1
|
||||
,output reg signed [31:0] ab_pow7_re1
|
||||
,output reg signed [31:0] ab_pow7_im1
|
||||
,output reg signed [31:0] b_pow8_re1
|
||||
,output reg signed [31:0] b_pow8_im1
|
||||
,output reg signed [31:0] a_re2
|
||||
,output reg signed [31:0] a_im2
|
||||
,output reg signed [31:0] ab_re2
|
||||
,output reg signed [31:0] ab_im2
|
||||
,output reg signed [31:0] abb_re2
|
||||
,output reg signed [31:0] abb_im2
|
||||
,output reg signed [31:0] ab_pow3_re2
|
||||
,output reg signed [31:0] ab_pow3_im2
|
||||
,output reg signed [31:0] ab_pow4_re2
|
||||
,output reg signed [31:0] ab_pow4_im2
|
||||
,output reg signed [31:0] ab_pow5_re2
|
||||
,output reg signed [31:0] ab_pow5_im2
|
||||
,output reg signed [31:0] ab_pow6_re2
|
||||
,output reg signed [31:0] ab_pow6_im2
|
||||
,output reg signed [31:0] ab_pow7_re2
|
||||
,output reg signed [31:0] ab_pow7_im2
|
||||
,output reg signed [31:0] b_pow8_re2
|
||||
,output reg signed [31:0] b_pow8_im2
|
||||
,output reg signed [31:0] a_re3
|
||||
,output reg signed [31:0] a_im3
|
||||
,output reg signed [31:0] ab_re3
|
||||
,output reg signed [31:0] ab_im3
|
||||
,output reg signed [31:0] abb_re3
|
||||
,output reg signed [31:0] abb_im3
|
||||
,output reg signed [31:0] ab_pow3_re3
|
||||
,output reg signed [31:0] ab_pow3_im3
|
||||
,output reg signed [31:0] ab_pow4_re3
|
||||
,output reg signed [31:0] ab_pow4_im3
|
||||
,output reg signed [31:0] ab_pow5_re3
|
||||
,output reg signed [31:0] ab_pow5_im3
|
||||
,output reg signed [31:0] ab_pow6_re3
|
||||
,output reg signed [31:0] ab_pow6_im3
|
||||
,output reg signed [31:0] ab_pow7_re3
|
||||
,output reg signed [31:0] ab_pow7_im3
|
||||
,output reg signed [31:0] b_pow8_re3
|
||||
,output reg signed [31:0] b_pow8_im3
|
||||
,output reg signed [31:0] a_re4
|
||||
,output reg signed [31:0] a_im4
|
||||
,output reg signed [31:0] ab_re4
|
||||
,output reg signed [31:0] ab_im4
|
||||
,output reg signed [31:0] abb_re4
|
||||
,output reg signed [31:0] abb_im4
|
||||
,output reg signed [31:0] ab_pow3_re4
|
||||
,output reg signed [31:0] ab_pow3_im4
|
||||
,output reg signed [31:0] ab_pow4_re4
|
||||
,output reg signed [31:0] ab_pow4_im4
|
||||
,output reg signed [31:0] ab_pow5_re4
|
||||
,output reg signed [31:0] ab_pow5_im4
|
||||
,output reg signed [31:0] ab_pow6_re4
|
||||
,output reg signed [31:0] ab_pow6_im4
|
||||
,output reg signed [31:0] ab_pow7_re4
|
||||
,output reg signed [31:0] ab_pow7_im4
|
||||
,output reg signed [31:0] b_pow8_re4
|
||||
,output reg signed [31:0] b_pow8_im4
|
||||
,output reg signed [31:0] a_re5
|
||||
,output reg signed [31:0] a_im5
|
||||
,output reg signed [31:0] ab_re5
|
||||
,output reg signed [31:0] ab_im5
|
||||
,output reg signed [31:0] abb_re5
|
||||
,output reg signed [31:0] abb_im5
|
||||
,output reg signed [31:0] ab_pow3_re5
|
||||
,output reg signed [31:0] ab_pow3_im5
|
||||
,output reg signed [31:0] ab_pow4_re5
|
||||
,output reg signed [31:0] ab_pow4_im5
|
||||
,output reg signed [31:0] ab_pow5_re5
|
||||
,output reg signed [31:0] ab_pow5_im5
|
||||
,output reg signed [31:0] ab_pow6_re5
|
||||
,output reg signed [31:0] ab_pow6_im5
|
||||
,output reg signed [31:0] ab_pow7_re5
|
||||
,output reg signed [31:0] ab_pow7_im5
|
||||
,output reg signed [31:0] b_pow8_re5
|
||||
,output reg signed [31:0] b_pow8_im5
|
||||
);
|
||||
|
||||
|
||||
reg vldi_or_r1;
|
||||
wire vldi_or = | vldi;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
vldi_or_r1 <= 'h0;
|
||||
end
|
||||
else begin
|
||||
vldi_or_r1 <= vldi_or;
|
||||
end
|
||||
end
|
||||
|
||||
reg signed [data_in_width-1:0] a_re_r1;
|
||||
reg signed [data_in_width-1:0] a_im_r1;
|
||||
reg signed [data_in_width-1:0] b_re_r1;
|
||||
reg signed [data_in_width-1:0] b_im_r1;
|
||||
|
||||
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(rstn == 1'b0) begin
|
||||
a_re_r1 <= 'h0;
|
||||
a_im_r1 <= 'h0;
|
||||
b_re_r1 <= 'h0;
|
||||
b_im_r1 <= 'h0;
|
||||
end
|
||||
else if(|vldi) begin
|
||||
case(1'b1)
|
||||
vldi[0]: begin
|
||||
a_re_r1 <= a0_re;
|
||||
a_im_r1 <= a0_im;
|
||||
b_re_r1 <= b0_re;
|
||||
b_im_r1 <= b0_im;
|
||||
end
|
||||
vldi[1]: begin
|
||||
a_re_r1 <= a1_re;
|
||||
a_im_r1 <= a1_im;
|
||||
b_re_r1 <= b1_re;
|
||||
b_im_r1 <= b1_im;
|
||||
end
|
||||
vldi[2]: begin
|
||||
a_re_r1 <= a2_re;
|
||||
a_im_r1 <= a2_im;
|
||||
b_re_r1 <= b2_re;
|
||||
b_im_r1 <= b2_im;
|
||||
end
|
||||
vldi[3]: begin
|
||||
a_re_r1 <= a3_re;
|
||||
a_im_r1 <= a3_im;
|
||||
b_re_r1 <= b3_re;
|
||||
b_im_r1 <= b3_im;
|
||||
end
|
||||
vldi[4]: begin
|
||||
a_re_r1 <= a4_re;
|
||||
a_im_r1 <= a4_im;
|
||||
b_re_r1 <= b4_re;
|
||||
b_im_r1 <= b4_im;
|
||||
end
|
||||
vldi[5]: begin
|
||||
a_re_r1 <= a5_re;
|
||||
a_im_r1 <= a5_im;
|
||||
b_re_r1 <= b5_re;
|
||||
b_im_r1 <= b5_im;
|
||||
end
|
||||
// default: begin
|
||||
// a_re_r1 <= a_re[0];
|
||||
// a_im_r1 <= a_im[0];
|
||||
// b_re_r1 <= b_re[0];
|
||||
// b_im_r1 <= b_im[0];
|
||||
// end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg en;
|
||||
reg en_r1;
|
||||
reg [3:0] cnt0;
|
||||
wire add_cnt0;
|
||||
wire end_cnt0;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(!rstn)begin
|
||||
cnt0 <= 0;
|
||||
end
|
||||
else if(add_cnt0)begin
|
||||
if(end_cnt0)
|
||||
cnt0 <= 0;
|
||||
else
|
||||
cnt0 <= cnt0 + 1;
|
||||
end
|
||||
end
|
||||
|
||||
assign add_cnt0 = en;
|
||||
assign end_cnt0 = add_cnt0 && cnt0== 8-1;
|
||||
|
||||
wire en_l;
|
||||
wire en_h;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
en <= 0;
|
||||
end
|
||||
else if(en_h)begin
|
||||
en <= 1;
|
||||
end
|
||||
else if(en_l)begin
|
||||
en <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
|
||||
assign en_l = end_cnt0;
|
||||
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
en_r1 <= 'h0;
|
||||
end
|
||||
else begin
|
||||
en_r1 <= en;
|
||||
end
|
||||
end
|
||||
|
||||
reg signed [data_in_width-1:0] bin_re;
|
||||
reg signed [data_in_width-1:0] bin_im;
|
||||
wire signed [data_in_width-1:0] bout_re;
|
||||
wire signed [data_in_width-1:0] bout_im;
|
||||
always @(*)begin
|
||||
if(en_r1) begin
|
||||
bin_re <= bout_re;
|
||||
bin_im <= bout_im;
|
||||
end
|
||||
else begin
|
||||
bin_re <= 32'd2147483647;
|
||||
bin_im <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
mult_C
|
||||
#(
|
||||
.A_width(data_in_width)
|
||||
,.B_width(data_in_width)
|
||||
,.C_width(coef_width)
|
||||
,.D_width(coef_width)
|
||||
,.frac_coef_width(frac_coef_width)
|
||||
)
|
||||
inst_c1 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (bin_re ),
|
||||
.b (bin_im ),
|
||||
.c (b_re_r1 ),
|
||||
.d (b_im_r1 ),
|
||||
.Re (bout_re ),
|
||||
.Im (bout_im )
|
||||
);
|
||||
|
||||
|
||||
wire signed [data_in_width-1:0] abo_re;
|
||||
wire signed [data_in_width-1:0] abo_im;
|
||||
mult_C
|
||||
#(
|
||||
.A_width(data_in_width)
|
||||
,.B_width(data_in_width)
|
||||
,.C_width(coef_width)
|
||||
,.D_width(coef_width)
|
||||
,.frac_coef_width(frac_coef_width)
|
||||
)
|
||||
inst_c2 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (bin_re ),
|
||||
.b (bin_im ),
|
||||
.c (a_re_r1 ),
|
||||
.d (a_im_r1 ),
|
||||
.Re (abo_re ),
|
||||
.Im (abo_im )
|
||||
);
|
||||
|
||||
reg signed [coef_width-1 :0] ao_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ao_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_im_r1 ;
|
||||
reg signed [coef_width-1 :0] abb_re_r1 ;
|
||||
reg signed [coef_width-1 :0] abb_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow3_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow3_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow4_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow4_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow5_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow5_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow6_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow6_im_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow7_re_r1 ;
|
||||
reg signed [coef_width-1 :0] ab_pow7_im_r1 ;
|
||||
reg signed [coef_width-1 :0] b_pow8_re_r1 ;
|
||||
reg signed [coef_width-1 :0] b_pow8_im_r1 ;
|
||||
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
ao_re_r1 <= 0;
|
||||
ao_im_r1 <= 0;
|
||||
ab_re_r1 <= 0;
|
||||
ab_im_r1 <= 0;
|
||||
abb_re_r1 <= 0;
|
||||
abb_im_r1 <= 0;
|
||||
ab_pow3_re_r1 <= 0;
|
||||
ab_pow3_im_r1 <= 0;
|
||||
ab_pow4_re_r1 <= 0;
|
||||
ab_pow4_im_r1 <= 0;
|
||||
ab_pow5_re_r1 <= 0;
|
||||
ab_pow5_im_r1 <= 0;
|
||||
ab_pow6_re_r1 <= 0;
|
||||
ab_pow6_im_r1 <= 0;
|
||||
ab_pow7_re_r1 <= 0;
|
||||
ab_pow7_im_r1 <= 0;
|
||||
b_pow8_re_r1 <= 0;
|
||||
b_pow8_im_r1 <= 0;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 1 && en_r1)begin
|
||||
ao_re_r1 <= abo_re;
|
||||
ao_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 2 && en_r1)begin
|
||||
ab_re_r1 <= abo_re;
|
||||
ab_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 3 && en_r1)begin
|
||||
abb_re_r1 <= abo_re;
|
||||
abb_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 4 && en_r1)begin
|
||||
ab_pow3_re_r1 <= abo_re;
|
||||
ab_pow3_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 5 && en_r1)begin
|
||||
ab_pow4_re_r1 <= abo_re;
|
||||
ab_pow4_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 6 && en_r1)begin
|
||||
ab_pow5_re_r1 <= abo_re;
|
||||
ab_pow5_im_r1 <= abo_im;
|
||||
end
|
||||
else if(add_cnt0 && cnt0 == 7 && en_r1)begin
|
||||
ab_pow6_re_r1 <= abo_re;
|
||||
ab_pow6_im_r1 <= abo_im;
|
||||
end
|
||||
else if(cnt0 == 0 && en_r1)begin
|
||||
ab_pow7_re_r1 <= abo_re;
|
||||
ab_pow7_im_r1 <= abo_im;
|
||||
b_pow8_re_r1 <= bin_re;
|
||||
b_pow8_im_r1 <= bin_im;
|
||||
end
|
||||
// else begin
|
||||
// end
|
||||
end
|
||||
|
||||
reg [5:0] vldi_r10;
|
||||
syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if(rstn == 1'b0) begin
|
||||
a_re0 <= 0;
|
||||
a_im0 <= 0;
|
||||
ab_re0 <= 0;
|
||||
ab_im0 <= 0;
|
||||
abb_re0 <= 0;
|
||||
abb_im0 <= 0;
|
||||
ab_pow3_re0 <= 0;
|
||||
ab_pow3_im0 <= 0;
|
||||
ab_pow4_re0 <= 0;
|
||||
ab_pow4_im0 <= 0;
|
||||
ab_pow5_re0 <= 0;
|
||||
ab_pow5_im0 <= 0;
|
||||
ab_pow6_re0 <= 0;
|
||||
ab_pow6_im0 <= 0;
|
||||
ab_pow7_re0 <= 0;
|
||||
ab_pow7_im0 <= 0;
|
||||
b_pow8_re0 <= 0;
|
||||
b_pow8_im0 <= 0;
|
||||
a_re1 <= 0;
|
||||
a_im1 <= 0;
|
||||
ab_re1 <= 0;
|
||||
ab_im1 <= 0;
|
||||
abb_re1 <= 0;
|
||||
abb_im1 <= 0;
|
||||
ab_pow3_re1 <= 0;
|
||||
ab_pow3_im1 <= 0;
|
||||
ab_pow4_re1 <= 0;
|
||||
ab_pow4_im1 <= 0;
|
||||
ab_pow5_re1 <= 0;
|
||||
ab_pow5_im1 <= 0;
|
||||
ab_pow6_re1 <= 0;
|
||||
ab_pow6_im1 <= 0;
|
||||
ab_pow7_re1 <= 0;
|
||||
ab_pow7_im1 <= 0;
|
||||
b_pow8_re1 <= 0;
|
||||
b_pow8_im1 <= 0;
|
||||
a_re2 <= 0;
|
||||
a_im2 <= 0;
|
||||
ab_re2 <= 0;
|
||||
ab_im2 <= 0;
|
||||
abb_re2 <= 0;
|
||||
abb_im2 <= 0;
|
||||
ab_pow3_re2 <= 0;
|
||||
ab_pow3_im2 <= 0;
|
||||
ab_pow4_re2 <= 0;
|
||||
ab_pow4_im2 <= 0;
|
||||
ab_pow5_re2 <= 0;
|
||||
ab_pow5_im2 <= 0;
|
||||
ab_pow6_re2 <= 0;
|
||||
ab_pow6_im2 <= 0;
|
||||
ab_pow7_re2 <= 0;
|
||||
ab_pow7_im2 <= 0;
|
||||
b_pow8_re2 <= 0;
|
||||
b_pow8_im2 <= 0;
|
||||
a_re3 <= 0;
|
||||
a_im3 <= 0;
|
||||
ab_re3 <= 0;
|
||||
ab_im3 <= 0;
|
||||
abb_re3 <= 0;
|
||||
abb_im3 <= 0;
|
||||
ab_pow3_re3 <= 0;
|
||||
ab_pow3_im3 <= 0;
|
||||
ab_pow4_re3 <= 0;
|
||||
ab_pow4_im3 <= 0;
|
||||
ab_pow5_re3 <= 0;
|
||||
ab_pow5_im3 <= 0;
|
||||
ab_pow6_re3 <= 0;
|
||||
ab_pow6_im3 <= 0;
|
||||
ab_pow7_re3 <= 0;
|
||||
ab_pow7_im3 <= 0;
|
||||
b_pow8_re3 <= 0;
|
||||
b_pow8_im3 <= 0;
|
||||
a_re4 <= 0;
|
||||
a_im4 <= 0;
|
||||
ab_re4 <= 0;
|
||||
ab_im4 <= 0;
|
||||
abb_re4 <= 0;
|
||||
abb_im4 <= 0;
|
||||
ab_pow3_re4 <= 0;
|
||||
ab_pow3_im4 <= 0;
|
||||
ab_pow4_re4 <= 0;
|
||||
ab_pow4_im4 <= 0;
|
||||
ab_pow5_re4 <= 0;
|
||||
ab_pow5_im4 <= 0;
|
||||
ab_pow6_re4 <= 0;
|
||||
ab_pow6_im4 <= 0;
|
||||
ab_pow7_re4 <= 0;
|
||||
ab_pow7_im4 <= 0;
|
||||
b_pow8_re4 <= 0;
|
||||
b_pow8_im4 <= 0;
|
||||
a_re5 <= 0;
|
||||
a_im5 <= 0;
|
||||
ab_re5 <= 0;
|
||||
ab_im5 <= 0;
|
||||
abb_re5 <= 0;
|
||||
abb_im5 <= 0;
|
||||
ab_pow3_re5 <= 0;
|
||||
ab_pow3_im5 <= 0;
|
||||
ab_pow4_re5 <= 0;
|
||||
ab_pow4_im5 <= 0;
|
||||
ab_pow5_re5 <= 0;
|
||||
ab_pow5_im5 <= 0;
|
||||
ab_pow6_re5 <= 0;
|
||||
ab_pow6_im5 <= 0;
|
||||
ab_pow7_re5 <= 0;
|
||||
ab_pow7_im5 <= 0;
|
||||
b_pow8_re5 <= 0;
|
||||
b_pow8_im5 <= 0;
|
||||
end
|
||||
else if(|vldi_r10) begin
|
||||
case(1'b1)
|
||||
vldi_r10[0]: begin
|
||||
a_re0 <= ao_re_r1 ;
|
||||
a_im0 <= ao_im_r1 ;
|
||||
ab_re0 <= ab_re_r1 ;
|
||||
ab_im0 <= ab_im_r1 ;
|
||||
abb_re0 <= abb_re_r1 ;
|
||||
abb_im0 <= abb_im_r1 ;
|
||||
ab_pow3_re0 <= ab_pow3_re_r1;
|
||||
ab_pow3_im0 <= ab_pow3_im_r1;
|
||||
ab_pow4_re0 <= ab_pow4_re_r1;
|
||||
ab_pow4_im0 <= ab_pow4_im_r1;
|
||||
ab_pow5_re0 <= ab_pow5_re_r1;
|
||||
ab_pow5_im0 <= ab_pow5_im_r1;
|
||||
ab_pow6_re0 <= ab_pow6_re_r1;
|
||||
ab_pow6_im0 <= ab_pow6_im_r1;
|
||||
ab_pow7_re0 <= ab_pow7_re_r1;
|
||||
ab_pow7_im0 <= ab_pow7_im_r1;
|
||||
b_pow8_re0 <= b_pow8_re_r1 ;
|
||||
b_pow8_im0 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[1]: begin
|
||||
a_re1 <= ao_re_r1 ;
|
||||
a_im1 <= ao_im_r1 ;
|
||||
ab_re1 <= ab_re_r1 ;
|
||||
ab_im1 <= ab_im_r1 ;
|
||||
abb_re1 <= abb_re_r1 ;
|
||||
abb_im1 <= abb_im_r1 ;
|
||||
ab_pow3_re1 <= ab_pow3_re_r1;
|
||||
ab_pow3_im1 <= ab_pow3_im_r1;
|
||||
ab_pow4_re1 <= ab_pow4_re_r1;
|
||||
ab_pow4_im1 <= ab_pow4_im_r1;
|
||||
ab_pow5_re1 <= ab_pow5_re_r1;
|
||||
ab_pow5_im1 <= ab_pow5_im_r1;
|
||||
ab_pow6_re1 <= ab_pow6_re_r1;
|
||||
ab_pow6_im1 <= ab_pow6_im_r1;
|
||||
ab_pow7_re1 <= ab_pow7_re_r1;
|
||||
ab_pow7_im1 <= ab_pow7_im_r1;
|
||||
b_pow8_re1 <= b_pow8_re_r1 ;
|
||||
b_pow8_im1 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[2]: begin
|
||||
a_re2 <= ao_re_r1 ;
|
||||
a_im2 <= ao_im_r1 ;
|
||||
ab_re2 <= ab_re_r1 ;
|
||||
ab_im2 <= ab_im_r1 ;
|
||||
abb_re2 <= abb_re_r1 ;
|
||||
abb_im2 <= abb_im_r1 ;
|
||||
ab_pow3_re2 <= ab_pow3_re_r1;
|
||||
ab_pow3_im2 <= ab_pow3_im_r1;
|
||||
ab_pow4_re2 <= ab_pow4_re_r1;
|
||||
ab_pow4_im2 <= ab_pow4_im_r1;
|
||||
ab_pow5_re2 <= ab_pow5_re_r1;
|
||||
ab_pow5_im2 <= ab_pow5_im_r1;
|
||||
ab_pow6_re2 <= ab_pow6_re_r1;
|
||||
ab_pow6_im2 <= ab_pow6_im_r1;
|
||||
ab_pow7_re2 <= ab_pow7_re_r1;
|
||||
ab_pow7_im2 <= ab_pow7_im_r1;
|
||||
b_pow8_re2 <= b_pow8_re_r1 ;
|
||||
b_pow8_im2 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[3]: begin
|
||||
a_re3 <= ao_re_r1 ;
|
||||
a_im3 <= ao_im_r1 ;
|
||||
ab_re3 <= ab_re_r1 ;
|
||||
ab_im3 <= ab_im_r1 ;
|
||||
abb_re3 <= abb_re_r1 ;
|
||||
abb_im3 <= abb_im_r1 ;
|
||||
ab_pow3_re3 <= ab_pow3_re_r1;
|
||||
ab_pow3_im3 <= ab_pow3_im_r1;
|
||||
ab_pow4_re3 <= ab_pow4_re_r1;
|
||||
ab_pow4_im3 <= ab_pow4_im_r1;
|
||||
ab_pow5_re3 <= ab_pow5_re_r1;
|
||||
ab_pow5_im3 <= ab_pow5_im_r1;
|
||||
ab_pow6_re3 <= ab_pow6_re_r1;
|
||||
ab_pow6_im3 <= ab_pow6_im_r1;
|
||||
ab_pow7_re3 <= ab_pow7_re_r1;
|
||||
ab_pow7_im3 <= ab_pow7_im_r1;
|
||||
b_pow8_re3 <= b_pow8_re_r1 ;
|
||||
b_pow8_im3 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[4]: begin
|
||||
a_re4 <= ao_re_r1 ;
|
||||
a_im4 <= ao_im_r1 ;
|
||||
ab_re4 <= ab_re_r1 ;
|
||||
ab_im4 <= ab_im_r1 ;
|
||||
abb_re4 <= abb_re_r1 ;
|
||||
abb_im4 <= abb_im_r1 ;
|
||||
ab_pow3_re4 <= ab_pow3_re_r1;
|
||||
ab_pow3_im4 <= ab_pow3_im_r1;
|
||||
ab_pow4_re4 <= ab_pow4_re_r1;
|
||||
ab_pow4_im4 <= ab_pow4_im_r1;
|
||||
ab_pow5_re4 <= ab_pow5_re_r1;
|
||||
ab_pow5_im4 <= ab_pow5_im_r1;
|
||||
ab_pow6_re4 <= ab_pow6_re_r1;
|
||||
ab_pow6_im4 <= ab_pow6_im_r1;
|
||||
ab_pow7_re4 <= ab_pow7_re_r1;
|
||||
ab_pow7_im4 <= ab_pow7_im_r1;
|
||||
b_pow8_re4 <= b_pow8_re_r1 ;
|
||||
b_pow8_im4 <= b_pow8_im_r1 ;
|
||||
end
|
||||
vldi_r10[5]: begin
|
||||
a_re5 <= ao_re_r1 ;
|
||||
a_im5 <= ao_im_r1 ;
|
||||
ab_re5 <= ab_re_r1 ;
|
||||
ab_im5 <= ab_im_r1 ;
|
||||
abb_re5 <= abb_re_r1 ;
|
||||
abb_im5 <= abb_im_r1 ;
|
||||
ab_pow3_re5 <= ab_pow3_re_r1;
|
||||
ab_pow3_im5 <= ab_pow3_im_r1;
|
||||
ab_pow4_re5 <= ab_pow4_re_r1;
|
||||
ab_pow4_im5 <= ab_pow4_im_r1;
|
||||
ab_pow5_re5 <= ab_pow5_re_r1;
|
||||
ab_pow5_im5 <= ab_pow5_im_r1;
|
||||
ab_pow6_re5 <= ab_pow6_re_r1;
|
||||
ab_pow6_im5 <= ab_pow6_im_r1;
|
||||
ab_pow7_re5 <= ab_pow7_re_r1;
|
||||
ab_pow7_im5 <= ab_pow7_im_r1;
|
||||
b_pow8_re5 <= b_pow8_re_r1 ;
|
||||
b_pow8_im5 <= b_pow8_im_r1 ;
|
||||
end
|
||||
// default: begin
|
||||
// ao_re[0] <= 'h0;
|
||||
// ao_im[0] <= 'h0;
|
||||
// ab_re[0] <= 'h0;
|
||||
// ab_im[0] <= 'h0;
|
||||
// abb_re[0] <= 'h0;
|
||||
// abb_im[0] <= 'h0;
|
||||
// ab_pow3_re[0] <= 'h0;
|
||||
// ab_pow3_im[0] <= 'h0;
|
||||
// ab_pow4_re[0] <= 'h0;
|
||||
// ab_pow4_im[0] <= 'h0;
|
||||
// ab_pow5_re[0] <= 'h0;
|
||||
// ab_pow5_im[0] <= 'h0;
|
||||
// ab_pow6_re[0] <= 'h0;
|
||||
// ab_pow6_im[0] <= 'h0;
|
||||
// ab_pow7_re[0] <= 'h0;
|
||||
// ab_pow7_im[0] <= 'h0;
|
||||
// b_pow8_re[0] <= 'h0;
|
||||
// b_pow8_im[0] <= 'h0;
|
||||
// end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,380 +0,0 @@
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This confidential and proprietary software may be used only
|
||||
// as authorized by a licensing agreement from Synopsys Inc.
|
||||
// In the event of publication, the following notice is applicable:
|
||||
//
|
||||
// (C) COPYRIGHT 1995 - 2018 SYNOPSYS INC.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// The entire notice above must be reproduced on all authorized
|
||||
// copies.
|
||||
//
|
||||
// AUTHOR: KB May 20, 1995
|
||||
//
|
||||
// VERSION: Verilog Simulation Model for DW_iir_dc
|
||||
//
|
||||
// DesignWare_version: 10b10551
|
||||
// DesignWare_release: O-2018.06-DWBB_201806.1
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//-----------------------------------------------------------------------------------
|
||||
//
|
||||
// ABSTRACT: Verilog simulation model for IIR filter with dynamic coefficients
|
||||
//
|
||||
// MODIFIED:
|
||||
// Doug Lee 06/02/2008
|
||||
// Fix for STAR#9000245949
|
||||
// data_out and saturation results were wrong
|
||||
// compared to synthetic and VHDL simulation
|
||||
// models in a specific negative number
|
||||
// boundary case. Re-wrote rounding/saturation
|
||||
// function to resemble VHDL simulation model
|
||||
// approach.
|
||||
//
|
||||
// Zhijun (Jerry) Huang 02/12/2004
|
||||
// Changed interface names
|
||||
// Added parameter legality check
|
||||
// Added asynchronous reset signal rst_n
|
||||
// Added optional output register controlled by parameter out_reg
|
||||
// Added X-processing
|
||||
// Fixed verilog analysis warning about zero multiconcat multiplier
|
||||
// Fixed verilog analysis error about negative array index
|
||||
// Fixed logic errors with saturation and negative/positive handling
|
||||
// Fixed logic errors with feedback_data when feedback_width > data_out_width
|
||||
//
|
||||
//-----------------------------------------------------------------------------------
|
||||
|
||||
module DW_iir_dc_m(clk,rst_n,init_n,enable,
|
||||
A1_coef,A2_coef,B0_coef,B1_coef,B2_coef,
|
||||
data_in,data_out,saturation);
|
||||
parameter integer data_in_width = 8;
|
||||
parameter integer data_out_width = 16;
|
||||
parameter integer frac_data_out_width = 4;
|
||||
parameter integer feedback_width = 12;
|
||||
parameter integer max_coef_width = 8;
|
||||
parameter integer frac_coef_width = 4;
|
||||
parameter integer saturation_mode = 0;
|
||||
parameter integer out_reg = 1;
|
||||
input clk,rst_n,init_n,enable;
|
||||
input [max_coef_width-1:0] A1_coef,A2_coef,B0_coef,B1_coef,B2_coef;
|
||||
input [data_in_width-1:0] data_in;
|
||||
output [data_out_width-1:0] data_out;
|
||||
output saturation;
|
||||
|
||||
parameter integer psum_width = (feedback_width-frac_data_out_width > data_in_width)?
|
||||
feedback_width+max_coef_width+3
|
||||
: data_in_width+frac_data_out_width+max_coef_width+3;
|
||||
|
||||
|
||||
|
||||
function [feedback_width+data_out_width:0] rnd_sat;
|
||||
input [psum_width-1:0] psum0;
|
||||
|
||||
reg signed [psum_width:0] psum0_shiftedby1;
|
||||
reg signed [data_out_width-1:0] data_out_noreg;
|
||||
reg signed [feedback_width-1:0] feedback_data;
|
||||
reg signed [frac_coef_width:0] round_limit;
|
||||
reg signed [frac_coef_width-1:0] psum0_frac_part;
|
||||
reg signed [data_out_width-1:0] max_pos_output;
|
||||
reg signed [data_out_width-1:0] max_neg_output;
|
||||
reg signed [feedback_width-1:0] max_pos_feedback;
|
||||
reg signed [feedback_width-1:0] max_neg_feedback;
|
||||
reg signed [data_out_width-1:0] output_inc_data;
|
||||
reg signed [feedback_width-1:0] feedback_inc_data;
|
||||
reg output_to_big;
|
||||
reg feedback_to_big;
|
||||
reg saturation_internal;
|
||||
|
||||
integer i, j, k, l;
|
||||
|
||||
begin
|
||||
for (i=0; i<data_out_width; i=i+1) begin
|
||||
if (i == data_out_width-1)
|
||||
max_pos_output[i] = 0;
|
||||
else
|
||||
max_pos_output[i] = 1;
|
||||
end
|
||||
|
||||
for (j=0; j<data_out_width; j=j+1) begin
|
||||
if (j == data_out_width-1)
|
||||
max_neg_output[j] = 1;
|
||||
else if (j == 0)
|
||||
if (saturation_mode == 0)
|
||||
max_neg_output[j] = 0;
|
||||
else
|
||||
max_neg_output[j] = 1;
|
||||
else
|
||||
max_neg_output[j] = 0;
|
||||
end
|
||||
|
||||
for (k=0; k<feedback_width; k=k+1) begin
|
||||
if (k == feedback_width-1)
|
||||
max_pos_feedback[k] = 0;
|
||||
else
|
||||
max_pos_feedback[k] = 1;
|
||||
end
|
||||
|
||||
for (l=0; l<feedback_width; l=l+1) begin
|
||||
if (l == feedback_width-1)
|
||||
max_neg_feedback[l] = 1;
|
||||
else if (l == 0)
|
||||
if (saturation_mode == 0)
|
||||
max_neg_feedback[l] = 0;
|
||||
else
|
||||
max_neg_feedback[l] = 1;
|
||||
else
|
||||
max_neg_feedback[l] = 0;
|
||||
end
|
||||
|
||||
// round_limit = -2^(frac_coef_width-1)
|
||||
for (i=0; i<=frac_coef_width; i=i+1) begin
|
||||
if (i == frac_coef_width)
|
||||
round_limit[i] = 1;
|
||||
else if (i == frac_coef_width-1)
|
||||
round_limit[i] = 1;
|
||||
else
|
||||
round_limit[i] = 0;
|
||||
end
|
||||
|
||||
|
||||
if (frac_coef_width > 0) begin
|
||||
psum0_shiftedby1 = psum0 << 1;
|
||||
|
||||
// Break out the frac_coef portion of psum0
|
||||
for (i=0; i<frac_coef_width; i=i+1) begin
|
||||
psum0_frac_part[i] = psum0[i];
|
||||
end
|
||||
|
||||
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_output, 1'b1})) begin
|
||||
data_out_noreg = max_pos_output;
|
||||
output_to_big = 1;
|
||||
end else begin
|
||||
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_output)) begin
|
||||
data_out_noreg = max_neg_output;
|
||||
output_to_big = 1;
|
||||
end else begin
|
||||
if (psum0_shiftedby1[frac_coef_width] &&
|
||||
(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
|
||||
output_inc_data = psum0[data_out_width+frac_coef_width-1:frac_coef_width] + 1;
|
||||
data_out_noreg = output_inc_data;
|
||||
output_to_big = 0;
|
||||
end else begin
|
||||
data_out_noreg = psum0[data_out_width+frac_coef_width-1:frac_coef_width];
|
||||
output_to_big = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_feedback, 1'b1})) begin
|
||||
feedback_data = max_pos_feedback;
|
||||
feedback_to_big = 1;
|
||||
end else begin
|
||||
if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_feedback)) begin
|
||||
feedback_data = max_neg_feedback;
|
||||
feedback_to_big = 1;
|
||||
end else begin
|
||||
if (psum0_shiftedby1[frac_coef_width] &&
|
||||
(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
|
||||
feedback_inc_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width] + 1;
|
||||
feedback_data = feedback_inc_data;
|
||||
feedback_to_big = 0;
|
||||
end else begin
|
||||
feedback_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width];
|
||||
feedback_to_big = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
if ($signed(psum0) > $signed(max_pos_output)) begin
|
||||
data_out_noreg = max_pos_output;
|
||||
output_to_big = 1;
|
||||
end else begin
|
||||
if ($signed(psum0) < $signed(max_neg_output)) begin
|
||||
data_out_noreg = max_neg_output;
|
||||
output_to_big = 1;
|
||||
end else begin
|
||||
data_out_noreg = psum0[data_out_width-1:0];
|
||||
output_to_big = 0;
|
||||
end
|
||||
end
|
||||
if ($signed(psum0) > $signed(max_pos_feedback)) begin
|
||||
feedback_data = max_pos_feedback;
|
||||
feedback_to_big = 1;
|
||||
end else begin
|
||||
if ($signed(psum0) < $signed(max_neg_feedback)) begin
|
||||
feedback_data = max_neg_feedback;
|
||||
feedback_to_big = 1;
|
||||
end else begin
|
||||
feedback_data = psum0[feedback_width-1:0];
|
||||
feedback_to_big = 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
saturation_internal = output_to_big || feedback_to_big;
|
||||
|
||||
rnd_sat = {saturation_internal, feedback_data, data_out_noreg};
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire [data_in_width-1:0] gated_data_in;
|
||||
wire [feedback_width-1:0] feedback_data;
|
||||
wire [max_coef_width-1:0] A1_coef_wire,A2_coef_wire,
|
||||
B0_coef_wire,B1_coef_wire,B2_coef_wire;
|
||||
wire [data_in_width+max_coef_width-1:0] B0_product,B1_product,B2_product;
|
||||
wire [feedback_width+max_coef_width-1:0] A1_product,A2_product;
|
||||
wire [psum_width-3:0] psum2;
|
||||
reg [psum_width-3:0] psum2_saved;
|
||||
wire [psum_width-1:0] psum1,psum0;
|
||||
reg [psum_width-1:0] psum1_saved;
|
||||
wire [data_out_width-1:0] data_out_internal;
|
||||
wire saturation_internal;
|
||||
reg [data_out_width-1:0] data_out_reg;
|
||||
reg saturation_reg;
|
||||
|
||||
assign A1_coef_wire = A1_coef;
|
||||
assign A2_coef_wire = A2_coef;
|
||||
assign B0_coef_wire = B0_coef;
|
||||
assign B1_coef_wire = B1_coef;
|
||||
assign B2_coef_wire = B2_coef;
|
||||
assign gated_data_in = (init_n == 1'b0) ? {data_in_width{1'b0}} : data_in;
|
||||
|
||||
|
||||
DW02_mult #(data_in_width,max_coef_width) B0_mult(gated_data_in,B0_coef_wire,1'b1,B0_product);
|
||||
|
||||
DW02_mult #(feedback_width,max_coef_width) A1_mult(feedback_data,A1_coef_wire,1'b1,A1_product);
|
||||
|
||||
|
||||
assign psum1 = {{psum_width{A1_product[feedback_width+max_coef_width-1]}},
|
||||
A1_product[feedback_width+max_coef_width-2:0]};
|
||||
|
||||
assign psum0 = ({{psum_width{B0_product[data_in_width+max_coef_width-1]}},
|
||||
B0_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
|
||||
+ psum1_saved;
|
||||
|
||||
assign {saturation_internal,feedback_data,data_out_internal} = rnd_sat(psum0);
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if (rst_n == 1'b0) begin
|
||||
psum1_saved <= {psum_width{1'b0}};
|
||||
data_out_reg <= {data_out_width{1'b0}};
|
||||
saturation_reg <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
|
||||
if (init_n == 1'b0)
|
||||
psum1_saved <= {psum_width{1'b0}};
|
||||
else if (enable == 1'b1)
|
||||
psum1_saved <= psum1;
|
||||
else
|
||||
psum1_saved <= psum1_saved;
|
||||
|
||||
if (init_n == 1'b0) begin
|
||||
data_out_reg <= {data_out_width{1'b0}};
|
||||
saturation_reg <= 1'b0;
|
||||
end
|
||||
else if (enable == 1'b1) begin
|
||||
data_out_reg <= data_out_internal;
|
||||
saturation_reg <= saturation_internal;
|
||||
end
|
||||
else begin
|
||||
data_out_reg <= data_out_reg;
|
||||
saturation_reg <= saturation_reg;
|
||||
end
|
||||
end
|
||||
|
||||
assign data_out = (out_reg == 0) ? data_out_internal : data_out_reg;
|
||||
assign saturation = (out_reg == 0) ? saturation_internal : saturation_reg;
|
||||
|
||||
// synopsys translate_off
|
||||
//-------------------------------------------------------------------------
|
||||
// Parameter legality check
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
initial begin : parameter_check
|
||||
integer param_err_flg;
|
||||
|
||||
param_err_flg = 0;
|
||||
|
||||
|
||||
if (data_in_width < 2) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter data_in_width (lower bound: 2)",
|
||||
data_in_width );
|
||||
end
|
||||
|
||||
if ( (data_out_width < 2) || (data_out_width > psum_width-frac_coef_width) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter data_out_width (legal range: 2 to psum_width-frac_coef_width)",
|
||||
data_out_width );
|
||||
end
|
||||
|
||||
if ( (frac_data_out_width < 0) || (frac_data_out_width > data_out_width-1) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter frac_data_out_width (legal range: 0 to data_out_width-1)",
|
||||
frac_data_out_width );
|
||||
end
|
||||
|
||||
if (feedback_width < 2) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter feedback_width (lower bound: 2)",
|
||||
feedback_width );
|
||||
end
|
||||
|
||||
if (max_coef_width < 2) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter max_coef_width (lower bound: 2)",
|
||||
max_coef_width );
|
||||
end
|
||||
|
||||
if ( (frac_coef_width < 0) || (frac_coef_width > max_coef_width-1) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter frac_coef_width (legal range: 0 to max_coef_width-1)",
|
||||
frac_coef_width );
|
||||
end
|
||||
|
||||
if ( (saturation_mode < 0) || (saturation_mode > 1) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter saturation_mode (legal range: 0 to 1)",
|
||||
saturation_mode );
|
||||
end
|
||||
|
||||
if ( (out_reg < 0) || (out_reg > 1) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter out_reg (legal range: 0 to 1)",
|
||||
out_reg );
|
||||
end
|
||||
|
||||
if ( param_err_flg == 1) begin
|
||||
$display(
|
||||
"%m :\n Simulation aborted due to invalid parameter value(s)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
end // parameter_check
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Report unknown clock inputs
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
always @ (clk) begin : clk_monitor
|
||||
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
|
||||
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
|
||||
$time, clk );
|
||||
end // clk_monitor
|
||||
|
||||
// synopsys translate_on
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : IIR_Filter.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.4 2024-05-28 thfu
|
||||
//2024-05-28 10:22:49
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module IIR_Filter_p8 #(
|
||||
parameter data_in_width = 16
|
||||
,parameter coef_width = 32
|
||||
,parameter frac_data_out_width = 20//X for in,5
|
||||
,parameter frac_coef_width = 31//division
|
||||
)
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input signed [data_in_width-1:0] dinp0
|
||||
,input signed [data_in_width-1:0] dinp1
|
||||
,input signed [data_in_width-1:0] dinp2
|
||||
,input signed [data_in_width-1:0] dinp3
|
||||
,input signed [data_in_width-1:0] dinp4
|
||||
,input signed [data_in_width-1:0] dinp5
|
||||
,input signed [data_in_width-1:0] dinp6
|
||||
,input signed [data_in_width-1:0] dinp7
|
||||
|
||||
,input signed [coef_width-1 :0] a_re
|
||||
,input signed [coef_width-1 :0] a_im
|
||||
,input signed [coef_width-1 :0] ab_re
|
||||
,input signed [coef_width-1 :0] ab_im
|
||||
,input signed [coef_width-1 :0] abb_re
|
||||
,input signed [coef_width-1 :0] abb_im
|
||||
,input signed [coef_width-1 :0] ab_pow3_re
|
||||
,input signed [coef_width-1 :0] ab_pow3_im
|
||||
,input signed [coef_width-1 :0] ab_pow4_re
|
||||
,input signed [coef_width-1 :0] ab_pow4_im
|
||||
,input signed [coef_width-1 :0] ab_pow5_re
|
||||
,input signed [coef_width-1 :0] ab_pow5_im
|
||||
,input signed [coef_width-1 :0] ab_pow6_re
|
||||
,input signed [coef_width-1 :0] ab_pow6_im
|
||||
,input signed [coef_width-1 :0] ab_pow7_re
|
||||
,input signed [coef_width-1 :0] ab_pow7_im
|
||||
|
||||
,input signed [coef_width-1 :0] b_pow8_re
|
||||
,input signed [coef_width-1 :0] b_pow8_im
|
||||
,output signed [data_in_width-1:0] dout
|
||||
);
|
||||
|
||||
wire signed [data_in_width-1 :0] dinp [7:0];
|
||||
assign dinp[7] = dinp7;
|
||||
assign dinp[6] = dinp6;
|
||||
assign dinp[5] = dinp5;
|
||||
assign dinp[4] = dinp4;
|
||||
assign dinp[3] = dinp3;
|
||||
assign dinp[2] = dinp2;
|
||||
assign dinp[1] = dinp1;
|
||||
assign dinp[0] = dinp0;
|
||||
|
||||
wire signed [coef_width-1 :0] ab_pow_re [7:0];
|
||||
assign ab_pow_re[7] = ab_pow7_re;
|
||||
assign ab_pow_re[6] = ab_pow6_re;
|
||||
assign ab_pow_re[5] = ab_pow5_re;
|
||||
assign ab_pow_re[4] = ab_pow4_re;
|
||||
assign ab_pow_re[3] = ab_pow3_re;
|
||||
assign ab_pow_re[2] = abb_re;
|
||||
assign ab_pow_re[1] = ab_re;
|
||||
assign ab_pow_re[0] = a_re;
|
||||
|
||||
wire signed [coef_width-1 :0] ab_pow_im [7:0];
|
||||
assign ab_pow_im[7] = ab_pow7_im;
|
||||
assign ab_pow_im[6] = ab_pow6_im;
|
||||
assign ab_pow_im[5] = ab_pow5_im;
|
||||
assign ab_pow_im[4] = ab_pow4_im;
|
||||
assign ab_pow_im[3] = ab_pow3_im;
|
||||
assign ab_pow_im[2] = abb_im;
|
||||
assign ab_pow_im[1] = ab_im;
|
||||
assign ab_pow_im[0] = a_im;
|
||||
|
||||
wire signed [data_in_width+frac_data_out_width-1:0] x_re [0:7];
|
||||
wire signed [data_in_width+frac_data_out_width-1:0] x_im [0:7];
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 8; i = i + 1) begin: mult_x_inst
|
||||
mult_x #(
|
||||
.A_width(data_in_width),
|
||||
.C_width(coef_width+frac_data_out_width),
|
||||
.D_width(coef_width+frac_data_out_width),
|
||||
.frac_coef_width(frac_coef_width)
|
||||
) inst_mult_x (
|
||||
.clk (clk),
|
||||
.rstn (rstn),
|
||||
.en (en),
|
||||
.a (dinp[i]),
|
||||
.c ({ab_pow_re[i],{frac_data_out_width{1'b0}}}),
|
||||
.d ({ab_pow_im[i],{frac_data_out_width{1'b0}}}),
|
||||
.Re (x_re[i]),
|
||||
.Im (x_im[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire signed [data_in_width+frac_data_out_width+3:0] v_re;
|
||||
wire signed [data_in_width+frac_data_out_width+3:0] v_im;
|
||||
|
||||
assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7];
|
||||
assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7];
|
||||
|
||||
reg signed [data_in_width+frac_data_out_width+3:0] v1_re;
|
||||
reg signed [data_in_width+frac_data_out_width+3:0] v1_im;
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
v1_re <= 'h0;
|
||||
v1_im <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
v1_re <= v_re;
|
||||
v1_im <= v_im;
|
||||
end
|
||||
else
|
||||
begin
|
||||
v1_re <= v1_re;
|
||||
v1_im <= v1_im;
|
||||
end
|
||||
|
||||
wire signed [data_in_width+frac_data_out_width+3:0] y_re;
|
||||
wire signed [data_in_width+frac_data_out_width+3:0] y_im;
|
||||
wire signed [data_in_width+frac_data_out_width+3:0] y1_re;
|
||||
wire signed [data_in_width+frac_data_out_width+3:0] y1_im;
|
||||
|
||||
reg signed [data_in_width-1:0] dout_re;
|
||||
|
||||
mult_C
|
||||
#(
|
||||
.A_width(data_in_width+frac_data_out_width+4)
|
||||
,.B_width(data_in_width+frac_data_out_width+4)
|
||||
,.C_width(coef_width)
|
||||
,.D_width(coef_width)
|
||||
,.frac_coef_width(frac_coef_width)
|
||||
)
|
||||
inst_c9 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.a (y_re ),
|
||||
.b (y_im ),
|
||||
.c (b_pow8_re ),
|
||||
.d (b_pow8_im ),
|
||||
.Re (y1_re ),//b^8*y(n-1)
|
||||
.Im (y1_im )
|
||||
);
|
||||
|
||||
assign y_re = v1_re + y1_re;
|
||||
assign y_im = v1_im + y1_im;
|
||||
|
||||
wire signed [data_in_width+frac_data_out_width+3:0] dout_round;
|
||||
|
||||
FixRound #(data_in_width+frac_data_out_width+4,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
dout_re <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_re <= dout_re;
|
||||
end
|
||||
|
||||
reg signed [data_in_width-1:0] dout_clip;
|
||||
|
||||
always @(posedge clk or negedge rstn)
|
||||
if (!rstn)
|
||||
begin
|
||||
dout_clip <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
|
||||
dout_clip <= 16'd32767;
|
||||
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
|
||||
dout_clip <= -16'd32768;
|
||||
else
|
||||
dout_clip <= dout_re;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_clip <= dout_clip;
|
||||
end
|
||||
|
||||
assign dout = dout_clip;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,360 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : TailCorr_top.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.3 2024-05-15 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module IIR_top
|
||||
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
,input signed [15 :0] IIRin_p0
|
||||
,input signed [15 :0] IIRin_p1
|
||||
,input signed [15 :0] IIRin_p2
|
||||
,input signed [15 :0] IIRin_p3
|
||||
,input signed [15 :0] IIRin_p4
|
||||
,input signed [15 :0] IIRin_p5
|
||||
,input signed [15 :0] IIRin_p6
|
||||
,input signed [15 :0] IIRin_p7
|
||||
,input signed [31 :0] a_re
|
||||
,input signed [31 :0] a_im
|
||||
,input signed [31 :0] ab_re
|
||||
,input signed [31 :0] ab_im
|
||||
,input signed [31 :0] abb_re
|
||||
,input signed [31 :0] abb_im
|
||||
,input signed [31 :0] ab_pow3_re
|
||||
,input signed [31 :0] ab_pow3_im
|
||||
,input signed [31 :0] ab_pow4_re
|
||||
,input signed [31 :0] ab_pow4_im
|
||||
,input signed [31 :0] ab_pow5_re
|
||||
,input signed [31 :0] ab_pow5_im
|
||||
,input signed [31 :0] ab_pow6_re
|
||||
,input signed [31 :0] ab_pow6_im
|
||||
,input signed [31 :0] ab_pow7_re
|
||||
,input signed [31 :0] ab_pow7_im
|
||||
,input signed [31 :0] b_pow8_re
|
||||
,input signed [31 :0] b_pow8_im
|
||||
|
||||
,output signed [15 :0] IIRout_p0
|
||||
,output signed [15 :0] IIRout_p1
|
||||
,output signed [15 :0] IIRout_p2
|
||||
,output signed [15 :0] IIRout_p3
|
||||
,output signed [15 :0] IIRout_p4
|
||||
,output signed [15 :0] IIRout_p5
|
||||
,output signed [15 :0] IIRout_p6
|
||||
,output signed [15 :0] IIRout_p7
|
||||
);
|
||||
reg signed [15:0] IIRin_p_r1 [7:1];
|
||||
wire signed [15 : 0] IIRin_p [7:0];
|
||||
assign IIRin_p[7] = IIRin_p7;
|
||||
assign IIRin_p[6] = IIRin_p6;
|
||||
assign IIRin_p[5] = IIRin_p5;
|
||||
assign IIRin_p[4] = IIRin_p4;
|
||||
assign IIRin_p[3] = IIRin_p3;
|
||||
assign IIRin_p[2] = IIRin_p2;
|
||||
assign IIRin_p[1] = IIRin_p1;
|
||||
assign IIRin_p[0] = IIRin_p0;
|
||||
integer i;
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (i = 1; i < 8; i = i + 1) begin
|
||||
IIRin_p_r1[i] <= 'h0;
|
||||
end
|
||||
end
|
||||
else if (en) begin
|
||||
for (i = 1; i < 8; i = i + 1) begin
|
||||
IIRin_p_r1[i] <= IIRin_p[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
IIR_Filter_p8 inst_iir_p0 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[0] ),
|
||||
.dinp1 (IIRin_p_r1[7] ),
|
||||
.dinp2 (IIRin_p_r1[6] ),
|
||||
.dinp3 (IIRin_p_r1[5] ),
|
||||
.dinp4 (IIRin_p_r1[4] ),
|
||||
.dinp5 (IIRin_p_r1[3] ),
|
||||
.dinp6 (IIRin_p_r1[2] ),
|
||||
.dinp7 (IIRin_p_r1[1] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p0 )
|
||||
);
|
||||
|
||||
IIR_Filter_p8 inst_iir_p1 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[1] ),
|
||||
.dinp1 (IIRin_p[0] ),
|
||||
.dinp2 (IIRin_p_r1[7] ),
|
||||
.dinp3 (IIRin_p_r1[6] ),
|
||||
.dinp4 (IIRin_p_r1[5] ),
|
||||
.dinp5 (IIRin_p_r1[4] ),
|
||||
.dinp6 (IIRin_p_r1[3] ),
|
||||
.dinp7 (IIRin_p_r1[2] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p1 )
|
||||
);
|
||||
IIR_Filter_p8 inst_iir_p2 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[2] ),
|
||||
.dinp1 (IIRin_p[1] ),
|
||||
.dinp2 (IIRin_p[0] ),
|
||||
.dinp3 (IIRin_p_r1[7] ),
|
||||
.dinp4 (IIRin_p_r1[6] ),
|
||||
.dinp5 (IIRin_p_r1[5] ),
|
||||
.dinp6 (IIRin_p_r1[4] ),
|
||||
.dinp7 (IIRin_p_r1[3] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p2 )
|
||||
);
|
||||
IIR_Filter_p8 inst_iir_p3 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[3] ),
|
||||
.dinp1 (IIRin_p[2] ),
|
||||
.dinp2 (IIRin_p[1] ),
|
||||
.dinp3 (IIRin_p[0] ),
|
||||
.dinp4 (IIRin_p_r1[7] ),
|
||||
.dinp5 (IIRin_p_r1[6] ),
|
||||
.dinp6 (IIRin_p_r1[5] ),
|
||||
.dinp7 (IIRin_p_r1[4] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p3 )
|
||||
);
|
||||
IIR_Filter_p8 inst_iir_p4 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[4] ),
|
||||
.dinp1 (IIRin_p[3] ),
|
||||
.dinp2 (IIRin_p[2] ),
|
||||
.dinp3 (IIRin_p[1] ),
|
||||
.dinp4 (IIRin_p[0] ),
|
||||
.dinp5 (IIRin_p_r1[7] ),
|
||||
.dinp6 (IIRin_p_r1[6] ),
|
||||
.dinp7 (IIRin_p_r1[5] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p4 )
|
||||
);
|
||||
IIR_Filter_p8 inst_iir_p5 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[5] ),
|
||||
.dinp1 (IIRin_p[4] ),
|
||||
.dinp2 (IIRin_p[3] ),
|
||||
.dinp3 (IIRin_p[2] ),
|
||||
.dinp4 (IIRin_p[1] ),
|
||||
.dinp5 (IIRin_p[0] ),
|
||||
.dinp6 (IIRin_p_r1[7] ),
|
||||
.dinp7 (IIRin_p_r1[6] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p5 )
|
||||
);
|
||||
IIR_Filter_p8 inst_iir_p6 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[6] ),
|
||||
.dinp1 (IIRin_p[5] ),
|
||||
.dinp2 (IIRin_p[4] ),
|
||||
.dinp3 (IIRin_p[3] ),
|
||||
.dinp4 (IIRin_p[2] ),
|
||||
.dinp5 (IIRin_p[1] ),
|
||||
.dinp6 (IIRin_p[0] ),
|
||||
.dinp7 (IIRin_p_r1[7] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p6 )
|
||||
);
|
||||
IIR_Filter_p8 inst_iir_p7 (
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.dinp0 (IIRin_p[7] ),
|
||||
.dinp1 (IIRin_p[6] ),
|
||||
.dinp2 (IIRin_p[5] ),
|
||||
.dinp3 (IIRin_p[4] ),
|
||||
.dinp4 (IIRin_p[3] ),
|
||||
.dinp5 (IIRin_p[2] ),
|
||||
.dinp6 (IIRin_p[1] ),
|
||||
.dinp7 (IIRin_p[0] ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im ),
|
||||
.dout (IIRout_p7 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,229 +0,0 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : MeanIntp_8.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-09-27 thfu top module of 8 mean interpolation
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module MeanIntp_8(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
intp_mode,
|
||||
din, //input
|
||||
dout_0,//output
|
||||
dout_1,
|
||||
dout_2,
|
||||
dout_3,
|
||||
dout_4,
|
||||
dout_5,
|
||||
dout_6,
|
||||
dout_7
|
||||
);
|
||||
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input [1:0] intp_mode;
|
||||
input signed [15:0] din;
|
||||
|
||||
output signed [15:0] dout_0;
|
||||
output signed [15:0] dout_1;
|
||||
output signed [15:0] dout_2;
|
||||
output signed [15:0] dout_3;
|
||||
output signed [15:0] dout_4;
|
||||
output signed [15:0] dout_5;
|
||||
output signed [15:0] dout_6;
|
||||
output signed [15:0] dout_7;
|
||||
|
||||
reg [15:0] din_r1;
|
||||
reg [15:0] din_r2;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_r1 <= 'h0;
|
||||
din_r2 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_r1 <= din;
|
||||
din_r2 <= din_r1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r1 <= din_r1;
|
||||
din_r2 <= din_r2;
|
||||
end
|
||||
|
||||
wire [16:0] sum_0_1;
|
||||
wire [16:0] sum_0_1_round0;
|
||||
wire [16:0] sum_0_1_round1;
|
||||
wire [16:0] sum_0_1_round2;
|
||||
|
||||
assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
|
||||
|
||||
FixRound #(17,1) u_round1 (clk, rstn, en, sum_0_1, sum_0_1_round0);
|
||||
FixRound #(17,2) u_round2 (clk, rstn, en, sum_0_1, sum_0_1_round1);
|
||||
FixRound #(17,3) u_round3 (clk, rstn, en, sum_0_1, sum_0_1_round2);
|
||||
|
||||
wire signed [16:0] diff_1_2;//(din-din_r1)/2
|
||||
wire signed [16:0] diff_1_4;//(din-din_r1)/4
|
||||
wire signed [16:0] diff_1_8;//(din-din_r1)/8
|
||||
|
||||
assign diff_1_2 = {{1 {sum_0_1_round0[16]}},sum_0_1_round0[16:1]};
|
||||
assign diff_1_4 = {{2 {sum_0_1_round1[16]}},sum_0_1_round1[16:2]};
|
||||
assign diff_1_8 = {{3 {sum_0_1_round2[16]}},sum_0_1_round2[16:3]};
|
||||
|
||||
reg signed [16:0] dout_r0;
|
||||
reg signed [16:0] dout_r1;
|
||||
reg signed [16:0] dout_r2;
|
||||
reg signed [16:0] dout_r3;
|
||||
reg signed [16:0] dout_r4;
|
||||
reg signed [16:0] dout_r5;
|
||||
reg signed [16:0] dout_r6;
|
||||
reg signed [16:0] dout_r7;
|
||||
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
dout_r0 <= 'h0;
|
||||
dout_r1 <= 'h0;
|
||||
dout_r2 <= 'h0;
|
||||
dout_r3 <= 'h0;
|
||||
dout_r4 <= 'h0;
|
||||
dout_r5 <= 'h0;
|
||||
dout_r6 <= 'h0;
|
||||
dout_r7 <= 'h0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
dout_r0 <= din_r2;
|
||||
dout_r1 <= din_r2 + diff_1_8;
|
||||
dout_r2 <= din_r2 + diff_1_4;
|
||||
dout_r3 <= din_r2 + diff_1_4 + diff_1_8;
|
||||
dout_r4 <= din_r2 + diff_1_2;
|
||||
dout_r5 <= din_r2 + diff_1_2 + diff_1_8;
|
||||
dout_r6 <= din_r2 + diff_1_2 + diff_1_4;
|
||||
dout_r7 <= din_r2 + diff_1_2 + diff_1_4 + diff_1_8;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout_r0 <= dout_r0;
|
||||
dout_r1 <= dout_r1;
|
||||
dout_r2 <= dout_r2;
|
||||
dout_r3 <= dout_r3;
|
||||
dout_r4 <= dout_r4;
|
||||
dout_r5 <= dout_r5;
|
||||
dout_r6 <= dout_r6;
|
||||
dout_r7 <= dout_r7;
|
||||
end
|
||||
|
||||
reg signed [15:0] mux_p_0;
|
||||
reg signed [15:0] mux_p_1;
|
||||
reg signed [15:0] mux_p_2;
|
||||
reg signed [15:0] mux_p_3;
|
||||
reg signed [15:0] mux_p_4;
|
||||
reg signed [15:0] mux_p_5;
|
||||
reg signed [15:0] mux_p_6;
|
||||
reg signed [15:0] mux_p_7;
|
||||
|
||||
always@(posedge clk) begin
|
||||
case(intp_mode)
|
||||
2'b00:
|
||||
begin
|
||||
mux_p_0 <= dout_r0;
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= 16'h0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
end
|
||||
2'b01:
|
||||
begin
|
||||
mux_p_0 <= dout_r0;
|
||||
mux_p_1 <= dout_r4;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= 16'h0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
end
|
||||
2'b10:
|
||||
begin
|
||||
mux_p_0 <= dout_r0;
|
||||
mux_p_1 <= dout_r2;
|
||||
mux_p_2 <= dout_r4;
|
||||
mux_p_3 <= dout_r6;
|
||||
mux_p_4 <= 16'h0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
end
|
||||
2'b11:
|
||||
begin
|
||||
mux_p_0 <= dout_r0;
|
||||
mux_p_1 <= dout_r1;
|
||||
mux_p_2 <= dout_r2;
|
||||
mux_p_3 <= dout_r3;
|
||||
mux_p_4 <= dout_r4;
|
||||
mux_p_5 <= dout_r5;
|
||||
mux_p_6 <= dout_r6;
|
||||
mux_p_7 <= dout_r7;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
mux_p_0 <= 16'h0;
|
||||
mux_p_1 <= 16'h0;
|
||||
mux_p_2 <= 16'h0;
|
||||
mux_p_3 <= 16'h0;
|
||||
mux_p_4 <= 16'h0;
|
||||
mux_p_5 <= 16'h0;
|
||||
mux_p_6 <= 16'h0;
|
||||
mux_p_7 <= 16'h0;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
assign dout_0 = mux_p_0[15:0];
|
||||
assign dout_1 = mux_p_1[15:0];
|
||||
assign dout_2 = mux_p_2[15:0];
|
||||
assign dout_3 = mux_p_3[15:0];
|
||||
assign dout_4 = mux_p_4[15:0];
|
||||
assign dout_5 = mux_p_5[15:0];
|
||||
assign dout_6 = mux_p_6[15:0];
|
||||
assign dout_7 = mux_p_7[15:0];
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,111 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : mult_C.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-28 thfu
|
||||
//2024-05-28 10:22:18
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module mult_C #(
|
||||
parameter integer A_width = 8
|
||||
,parameter integer B_width = 8
|
||||
,parameter integer C_width = 8
|
||||
,parameter integer D_width = 8
|
||||
,parameter integer frac_coef_width = 31//division
|
||||
|
||||
)
|
||||
|
||||
(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
a,
|
||||
b,
|
||||
c,
|
||||
d,
|
||||
Re,
|
||||
Im
|
||||
);
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input signed [A_width-1:0] a;
|
||||
input signed [B_width-1:0] b;
|
||||
input signed [C_width-1:0] c;
|
||||
input signed [D_width-1:0] d;
|
||||
|
||||
output signed [A_width+C_width-frac_coef_width-2:0] Re;
|
||||
output signed [A_width+D_width-frac_coef_width-2:0] Im;
|
||||
|
||||
wire signed [A_width+C_width-1:0] ac;
|
||||
wire signed [B_width+D_width-1:0] bd;
|
||||
wire signed [A_width+D_width-1:0] ad;
|
||||
wire signed [B_width+C_width-1:0] bc;
|
||||
|
||||
|
||||
|
||||
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ac )
|
||||
);
|
||||
|
||||
DW02_mult #(B_width,D_width) inst_c2( .A (b ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bd )
|
||||
);
|
||||
|
||||
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ad )
|
||||
);
|
||||
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (bc )
|
||||
);
|
||||
wire signed [A_width+C_width:0] Re_tmp;
|
||||
wire signed [A_width+D_width:0] Im_tmp;
|
||||
|
||||
assign Re_tmp = ac - bd;
|
||||
assign Im_tmp = ad + bc;
|
||||
|
||||
wire signed [A_width+C_width:0] Re_round;
|
||||
wire signed [A_width+D_width:0] Im_round;
|
||||
|
||||
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
|
||||
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
|
||||
|
||||
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
|
||||
assign Re = Re_round[A_width+D_width-2:frac_coef_width];
|
||||
assign Im = Im_round[A_width+D_width-2:frac_coef_width];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : mult_C.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-28 thfu
|
||||
//2024-05-28 10:22:18
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module mult_x #(
|
||||
parameter integer A_width = 8
|
||||
,parameter integer C_width = 8
|
||||
,parameter integer D_width = 8
|
||||
,parameter integer frac_coef_width = 31//division
|
||||
|
||||
)
|
||||
|
||||
(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
a,
|
||||
c,
|
||||
d,
|
||||
Re,
|
||||
Im
|
||||
);
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input signed [A_width-1:0] a;
|
||||
input signed [C_width-1:0] c;
|
||||
input signed [D_width-1:0] d;
|
||||
|
||||
output signed [A_width+C_width-frac_coef_width-2:0] Re;
|
||||
output signed [A_width+D_width-frac_coef_width-2:0] Im;
|
||||
|
||||
wire signed [A_width+C_width-1:0] ac;
|
||||
wire signed [A_width+D_width-1:0] ad;
|
||||
|
||||
|
||||
|
||||
DW02_mult #(A_width,C_width) inst_c1( .A (a ),
|
||||
.B (c ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ac )
|
||||
);
|
||||
|
||||
|
||||
DW02_mult #(A_width,D_width) inst_c3( .A (a ),
|
||||
.B (d ),
|
||||
.TC (1'b1 ),
|
||||
.PRODUCT (ad )
|
||||
);
|
||||
|
||||
wire signed [A_width+C_width:0] Re_tmp;
|
||||
wire signed [A_width+D_width:0] Im_tmp;
|
||||
|
||||
assign Re_tmp = ac;
|
||||
assign Im_tmp = ad;
|
||||
|
||||
wire signed [A_width+C_width:0] Re_round;
|
||||
wire signed [A_width+D_width:0] Im_round;
|
||||
|
||||
FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
|
||||
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);
|
||||
|
||||
// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
|
||||
assign Re = Re_round[A_width+D_width-2:frac_coef_width];
|
||||
assign Im = Im_round[A_width+D_width-2:frac_coef_width];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
module s2p_2 (
|
||||
input clk,
|
||||
input rst_n,
|
||||
input [15:0] din,
|
||||
input en,
|
||||
output [15:0] dout0,
|
||||
output [15:0] dout1,
|
||||
output vldo
|
||||
);
|
||||
|
||||
reg en_r1;
|
||||
reg en_r2;
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
en_r1 <= 0;
|
||||
en_r2 <= 0;
|
||||
end
|
||||
else begin
|
||||
en_r1 <= en;
|
||||
en_r2 <= en_r1;
|
||||
end
|
||||
end
|
||||
assign vldo = en_r2;
|
||||
|
||||
reg cnt;
|
||||
wire add_cnt;
|
||||
wire end_cnt;
|
||||
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(!rst_n)begin
|
||||
cnt <= 0;
|
||||
end
|
||||
else if(add_cnt)begin
|
||||
if(end_cnt)
|
||||
cnt <= 0;
|
||||
else
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
else begin
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign add_cnt = en == 1'b1;
|
||||
assign end_cnt = add_cnt && cnt== 2 - 1 ;
|
||||
|
||||
|
||||
reg [ 15: 0] dout0_r0;
|
||||
reg [ 15: 0] dout1_r0;
|
||||
wire dout0_en;
|
||||
wire dout1_en;
|
||||
wire dout0_hold;
|
||||
wire dout1_hold;
|
||||
|
||||
always @(*)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
end
|
||||
else if(dout0_en)begin
|
||||
dout0_r0 = din;
|
||||
end
|
||||
else if(dout1_en)begin
|
||||
dout1_r0 = din;
|
||||
end
|
||||
else begin
|
||||
dout0_r0 = 16'd0;
|
||||
dout1_r0 = 16'd0;
|
||||
|
||||
end
|
||||
end
|
||||
assign dout0_en = add_cnt && cnt == 0;
|
||||
assign dout1_en = add_cnt && cnt == 1;
|
||||
|
||||
reg [ 15: 0] dout0_r1;
|
||||
reg [ 15: 0] dout1_r1;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
else if(en)begin
|
||||
dout0_r1 <= dout0_r0;
|
||||
dout1_r1 <= dout1_r0;
|
||||
end
|
||||
else if(dout0_hold)begin
|
||||
dout0_r1 <= dout0_r1;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
else if(dout1_hold)begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= dout1_r1;
|
||||
end
|
||||
else begin
|
||||
dout0_r1 <= 16'd0;
|
||||
dout1_r1 <= 16'd0;
|
||||
end
|
||||
|
||||
end
|
||||
assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
|
||||
assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;
|
||||
|
||||
reg [ 15: 0] dout0_r2;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout0_r2 <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
dout0_r2 <= dout0_r1;
|
||||
end
|
||||
end
|
||||
|
||||
assign dout0 = dout0_r2;
|
||||
assign dout1 = dout1_r1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,326 @@
|
|||
/*
|
||||
Copyright 2018-2020 Nuclei System Technology, Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//=====================================================================
|
||||
//
|
||||
// Designer : Bob Hu
|
||||
//
|
||||
// Description:
|
||||
// All of the general DFF and Latch modules
|
||||
//
|
||||
// ====================================================================
|
||||
|
||||
//
|
||||
|
||||
|
||||
//
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
`define DISABLE_SV_ASSERTION
|
||||
`define dly #0.2
|
||||
module sirv_gnrl_dfflrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable and Reset
|
||||
// Default reset value is input
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dfflrd # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
input [DW-1:0] init,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFLR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= init;
|
||||
else if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Load-enable, no reset
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffl # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk)
|
||||
begin : DFFL_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
sirv_gnrl_xchecker # (
|
||||
.DW(1)
|
||||
) sirv_gnrl_xchecker(
|
||||
.i_dat(lden),
|
||||
.clk (clk)
|
||||
);
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 1
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffrs # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFRS_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b1}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module sirv_gnrl DFF with Reset, no load-enable
|
||||
// Default reset value is 0
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_dffr # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout,
|
||||
|
||||
input clk,
|
||||
input rst_n
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin : DFFR_PROC
|
||||
if (rst_n == 1'b0)
|
||||
qout_r <= {DW{1'b0}};
|
||||
else
|
||||
qout_r <= `dly dnxt;
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
// ===========================================================================
|
||||
//
|
||||
// Description:
|
||||
// Verilog module for general latch
|
||||
//
|
||||
// ===========================================================================
|
||||
|
||||
module sirv_gnrl_ltch # (
|
||||
parameter DW = 32
|
||||
) (
|
||||
|
||||
//input test_mode,
|
||||
input lden,
|
||||
input [DW-1:0] dnxt,
|
||||
output [DW-1:0] qout
|
||||
);
|
||||
|
||||
reg [DW-1:0] qout_r;
|
||||
|
||||
always @ *
|
||||
begin : LTCH_PROC
|
||||
if (lden == 1'b1)
|
||||
qout_r <= dnxt;
|
||||
end
|
||||
|
||||
//assign qout = test_mode ? dnxt : qout_r;
|
||||
assign qout = qout_r;
|
||||
|
||||
`ifndef FPGA_SOURCE//{
|
||||
`ifndef DISABLE_SV_ASSERTION//{
|
||||
//synopsys translate_off
|
||||
always_comb
|
||||
begin
|
||||
CHECK_THE_X_VALUE:
|
||||
assert (lden !== 1'bx)
|
||||
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
|
||||
end
|
||||
|
||||
//synopsys translate_on
|
||||
`endif//}
|
||||
`endif//}
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,14 +1,15 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : diff.v
|
||||
// File Name : syncer.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author : PWY
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-05-11 thfu
|
||||
// 0.1 2024-03-13 PWY AWG dedicated register file
|
||||
// 0.2 2024-05-13 PWY
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
|
|
@ -30,47 +31,28 @@
|
|||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
module diff(
|
||||
clk,
|
||||
rstn,
|
||||
en,
|
||||
din,
|
||||
dout
|
||||
|
||||
|
||||
module syncer # (
|
||||
parameter width = 1
|
||||
,parameter stage = 2
|
||||
)
|
||||
(
|
||||
input clk_d
|
||||
,input rstn_d
|
||||
,input [width-1:0] data_s
|
||||
,output [width-1:0] data_d
|
||||
);
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
wire [width-1:0] data_temp[stage-1:0];
|
||||
sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
|
||||
for(i=1;i<stage;i=i+1) begin: SYNCER
|
||||
sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
input rstn;
|
||||
input clk;
|
||||
input en;
|
||||
input signed [15:0] din;
|
||||
|
||||
output signed [15:0] dout;
|
||||
|
||||
|
||||
reg [15:0] din_r;
|
||||
reg [15:0] din_r1;
|
||||
reg [15:0] out_r;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_r <= 16'd0;
|
||||
din_r1 <= 16'd0;
|
||||
out_r <= 16'd0;
|
||||
end
|
||||
else if(en)
|
||||
begin
|
||||
din_r <= din;
|
||||
din_r1 <= din_r;
|
||||
out_r <= din_r - din_r1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_r <= din_r;
|
||||
din_r1 <= din_r1;
|
||||
out_r <= out_r;
|
||||
end
|
||||
|
||||
assign dout = out_r;
|
||||
assign data_d = data_temp[stage-1];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,414 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : Z_dsp.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module z_dsp
|
||||
(
|
||||
input rstn
|
||||
,input clk
|
||||
,input en
|
||||
//,input tc_bypass
|
||||
,input [ 5:0] vldi_coef
|
||||
,input vldi_data
|
||||
//,input [1:0] intp_mode
|
||||
//,input [1:0] dac_mode_sel
|
||||
,input signed [15:0] din0
|
||||
,input signed [15:0] din1
|
||||
,input signed [15:0] din2
|
||||
,input signed [15:0] din3
|
||||
,input signed [31:0] a0_re
|
||||
,input signed [31:0] a0_im
|
||||
,input signed [31:0] b0_re
|
||||
,input signed [31:0] b0_im
|
||||
,input signed [31:0] a1_re
|
||||
,input signed [31:0] a1_im
|
||||
,input signed [31:0] b1_re
|
||||
,input signed [31:0] b1_im
|
||||
,input signed [31:0] a2_re
|
||||
,input signed [31:0] a2_im
|
||||
,input signed [31:0] b2_re
|
||||
,input signed [31:0] b2_im
|
||||
,input signed [31:0] a3_re
|
||||
,input signed [31:0] a3_im
|
||||
,input signed [31:0] b3_re
|
||||
,input signed [31:0] b3_im
|
||||
,input signed [31:0] a4_re
|
||||
,input signed [31:0] a4_im
|
||||
,input signed [31:0] b4_re
|
||||
,input signed [31:0] b4_im
|
||||
,input signed [31:0] a5_re
|
||||
,input signed [31:0] a5_im
|
||||
,input signed [31:0] b5_re
|
||||
,input signed [31:0] b5_im
|
||||
,output signed [15:0] dout0
|
||||
,output signed [15:0] dout1
|
||||
,output signed [15:0] dout2
|
||||
,output signed [15:0] dout3
|
||||
,output vldo
|
||||
);
|
||||
|
||||
|
||||
wire signed [15:0] IIR_out;
|
||||
|
||||
|
||||
reg signed [31:0] ao_re [5:0];
|
||||
reg signed [31:0] ao_im [5:0];
|
||||
reg signed [31:0] ab_re [5:0];
|
||||
reg signed [31:0] ab_im [5:0];
|
||||
reg signed [31:0] abb_re [5:0];
|
||||
reg signed [31:0] abb_im [5:0];
|
||||
reg signed [31:0] ab_pow3_re [5:0];
|
||||
reg signed [31:0] ab_pow3_im [5:0];
|
||||
reg signed [31:0] ab_pow4_re [5:0];
|
||||
reg signed [31:0] ab_pow4_im [5:0];
|
||||
reg signed [31:0] ab_pow5_re [5:0];
|
||||
reg signed [31:0] ab_pow5_im [5:0];
|
||||
reg signed [31:0] ab_pow6_re [5:0];
|
||||
reg signed [31:0] ab_pow6_im [5:0];
|
||||
reg signed [31:0] ab_pow7_re [5:0];
|
||||
reg signed [31:0] ab_pow7_im [5:0];
|
||||
reg signed [31:0] b_pow8_re [5:0];
|
||||
reg signed [31:0] b_pow8_im [5:0];
|
||||
|
||||
CoefGen inst_CoefGen(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.vldi (vldi_coef ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.a_re0 (ao_re[0] ),
|
||||
.a_im0 (ao_im[0] ),
|
||||
.ab_re0 (ab_re[0] ),
|
||||
.ab_im0 (ab_im[0] ),
|
||||
.abb_re0 (abb_re[0] ),
|
||||
.abb_im0 (abb_im[0] ),
|
||||
.ab_pow3_re0 (ab_pow3_re[0]),
|
||||
.ab_pow3_im0 (ab_pow3_im[0]),
|
||||
.ab_pow4_re0 (ab_pow4_re[0]),
|
||||
.ab_pow4_im0 (ab_pow4_im[0]),
|
||||
.ab_pow5_re0 (ab_pow5_re[0]),
|
||||
.ab_pow5_im0 (ab_pow5_im[0]),
|
||||
.ab_pow6_re0 (ab_pow6_re[0]),
|
||||
.ab_pow6_im0 (ab_pow6_im[0]),
|
||||
.ab_pow7_re0 (ab_pow7_re[0]),
|
||||
.ab_pow7_im0 (ab_pow7_im[0]),
|
||||
.b_pow8_re0 (b_pow8_re[0] ),
|
||||
.b_pow8_im0 (b_pow8_im[0] ),
|
||||
.a_re1 (ao_re[1] ),
|
||||
.a_im1 (ao_im[1] ),
|
||||
.ab_re1 (ab_re[1] ),
|
||||
.ab_im1 (ab_im[1] ),
|
||||
.abb_re1 (abb_re[1] ),
|
||||
.abb_im1 (abb_im[1] ),
|
||||
.ab_pow3_re1 (ab_pow3_re[1]),
|
||||
.ab_pow3_im1 (ab_pow3_im[1]),
|
||||
.ab_pow4_re1 (ab_pow4_re[1]),
|
||||
.ab_pow4_im1 (ab_pow4_im[1]),
|
||||
.ab_pow5_re1 (ab_pow5_re[1]),
|
||||
.ab_pow5_im1 (ab_pow5_im[1]),
|
||||
.ab_pow6_re1 (ab_pow6_re[1]),
|
||||
.ab_pow6_im1 (ab_pow6_im[1]),
|
||||
.ab_pow7_re1 (ab_pow7_re[1]),
|
||||
.ab_pow7_im1 (ab_pow7_im[1]),
|
||||
.b_pow8_re1 (b_pow8_re[1] ),
|
||||
.b_pow8_im1 (b_pow8_im[1] ),
|
||||
.a_re2 (ao_re[2] ),
|
||||
.a_im2 (ao_im[2] ),
|
||||
.ab_re2 (ab_re[2] ),
|
||||
.ab_im2 (ab_im[2] ),
|
||||
.abb_re2 (abb_re[2] ),
|
||||
.abb_im2 (abb_im[2] ),
|
||||
.ab_pow3_re2 (ab_pow3_re[2]),
|
||||
.ab_pow3_im2 (ab_pow3_im[2]),
|
||||
.ab_pow4_re2 (ab_pow4_re[2]),
|
||||
.ab_pow4_im2 (ab_pow4_im[2]),
|
||||
.ab_pow5_re2 (ab_pow5_re[2]),
|
||||
.ab_pow5_im2 (ab_pow5_im[2]),
|
||||
.ab_pow6_re2 (ab_pow6_re[2]),
|
||||
.ab_pow6_im2 (ab_pow6_im[2]),
|
||||
.ab_pow7_re2 (ab_pow7_re[2]),
|
||||
.ab_pow7_im2 (ab_pow7_im[2]),
|
||||
.b_pow8_re2 (b_pow8_re[2] ),
|
||||
.b_pow8_im2 (b_pow8_im[2] ),
|
||||
.a_re3 (ao_re[3] ),
|
||||
.a_im3 (ao_im[3] ),
|
||||
.ab_re3 (ab_re[3] ),
|
||||
.ab_im3 (ab_im[3] ),
|
||||
.abb_re3 (abb_re[3] ),
|
||||
.abb_im3 (abb_im[3] ),
|
||||
.ab_pow3_re3 (ab_pow3_re[3]),
|
||||
.ab_pow3_im3 (ab_pow3_im[3]),
|
||||
.ab_pow4_re3 (ab_pow4_re[3]),
|
||||
.ab_pow4_im3 (ab_pow4_im[3]),
|
||||
.ab_pow5_re3 (ab_pow5_re[3]),
|
||||
.ab_pow5_im3 (ab_pow5_im[3]),
|
||||
.ab_pow6_re3 (ab_pow6_re[3]),
|
||||
.ab_pow6_im3 (ab_pow6_im[3]),
|
||||
.ab_pow7_re3 (ab_pow7_re[3]),
|
||||
.ab_pow7_im3 (ab_pow7_im[3]),
|
||||
.b_pow8_re3 (b_pow8_re[3] ),
|
||||
.b_pow8_im3 (b_pow8_im[3] ),
|
||||
.a_re4 (ao_re[4] ),
|
||||
.a_im4 (ao_im[4] ),
|
||||
.ab_re4 (ab_re[4] ),
|
||||
.ab_im4 (ab_im[4] ),
|
||||
.abb_re4 (abb_re[4] ),
|
||||
.abb_im4 (abb_im[4] ),
|
||||
.ab_pow3_re4 (ab_pow3_re[4]),
|
||||
.ab_pow3_im4 (ab_pow3_im[4]),
|
||||
.ab_pow4_re4 (ab_pow4_re[4]),
|
||||
.ab_pow4_im4 (ab_pow4_im[4]),
|
||||
.ab_pow5_re4 (ab_pow5_re[4]),
|
||||
.ab_pow5_im4 (ab_pow5_im[4]),
|
||||
.ab_pow6_re4 (ab_pow6_re[4]),
|
||||
.ab_pow6_im4 (ab_pow6_im[4]),
|
||||
.ab_pow7_re4 (ab_pow7_re[4]),
|
||||
.ab_pow7_im4 (ab_pow7_im[4]),
|
||||
.b_pow8_re4 (b_pow8_re[4] ),
|
||||
.b_pow8_im4 (b_pow8_im[4] ),
|
||||
.a_re5 (ao_re[5] ),
|
||||
.a_im5 (ao_im[5] ),
|
||||
.ab_re5 (ab_re[5] ),
|
||||
.ab_im5 (ab_im[5] ),
|
||||
.abb_re5 (abb_re[5] ),
|
||||
.abb_im5 (abb_im[5] ),
|
||||
.ab_pow3_re5 (ab_pow3_re[5]),
|
||||
.ab_pow3_im5 (ab_pow3_im[5]),
|
||||
.ab_pow4_re5 (ab_pow4_re[5]),
|
||||
.ab_pow4_im5 (ab_pow4_im[5]),
|
||||
.ab_pow5_re5 (ab_pow5_re[5]),
|
||||
.ab_pow5_im5 (ab_pow5_im[5]),
|
||||
.ab_pow6_re5 (ab_pow6_re[5]),
|
||||
.ab_pow6_im5 (ab_pow6_im[5]),
|
||||
.ab_pow7_re5 (ab_pow7_re[5]),
|
||||
.ab_pow7_im5 (ab_pow7_im[5]),
|
||||
.b_pow8_re5 (b_pow8_re[5] ),
|
||||
.b_pow8_im5 (b_pow8_im[5] )
|
||||
);
|
||||
|
||||
wire signed [15:0] dout_0;
|
||||
wire signed [15:0] dout_1;
|
||||
wire signed [15:0] dout_2;
|
||||
wire signed [15:0] dout_3;
|
||||
wire signed [15:0] dout_4;
|
||||
wire signed [15:0] dout_5;
|
||||
wire signed [15:0] dout_6;
|
||||
wire signed [15:0] dout_7;
|
||||
reg vldo_TC;
|
||||
TailCorr_top inst_TailCorr_top
|
||||
(
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
.rstn (rstn ),
|
||||
.vldi (vldi_data ),
|
||||
// .dac_mode_sel (dac_mode_sel ),
|
||||
// .intp_mode (intp_mode ),
|
||||
.din0 (din0 ),
|
||||
.din1 (din1 ),
|
||||
.din2 (din2 ),
|
||||
.din3 (din3 ),
|
||||
.a_re0 (ao_re[0] ),
|
||||
.a_im0 (ao_im[0] ),
|
||||
.ab_re0 (ab_re[0] ),
|
||||
.ab_im0 (ab_im[0] ),
|
||||
.abb_re0 (abb_re[0] ),
|
||||
.abb_im0 (abb_im[0] ),
|
||||
.ab_pow3_re0 (ab_pow3_re[0]),
|
||||
.ab_pow3_im0 (ab_pow3_im[0]),
|
||||
.ab_pow4_re0 (ab_pow4_re[0]),
|
||||
.ab_pow4_im0 (ab_pow4_im[0]),
|
||||
.ab_pow5_re0 (ab_pow5_re[0]),
|
||||
.ab_pow5_im0 (ab_pow5_im[0]),
|
||||
.ab_pow6_re0 (ab_pow6_re[0]),
|
||||
.ab_pow6_im0 (ab_pow6_im[0]),
|
||||
.ab_pow7_re0 (ab_pow7_re[0]),
|
||||
.ab_pow7_im0 (ab_pow7_im[0]),
|
||||
.b_pow8_re0 (b_pow8_re[0] ),
|
||||
.b_pow8_im0 (b_pow8_im[0] ),
|
||||
.a_re1 (ao_re[1] ),
|
||||
.a_im1 (ao_im[1] ),
|
||||
.ab_re1 (ab_re[1] ),
|
||||
.ab_im1 (ab_im[1] ),
|
||||
.abb_re1 (abb_re[1] ),
|
||||
.abb_im1 (abb_im[1] ),
|
||||
.ab_pow3_re1 (ab_pow3_re[1]),
|
||||
.ab_pow3_im1 (ab_pow3_im[1]),
|
||||
.ab_pow4_re1 (ab_pow4_re[1]),
|
||||
.ab_pow4_im1 (ab_pow4_im[1]),
|
||||
.ab_pow5_re1 (ab_pow5_re[1]),
|
||||
.ab_pow5_im1 (ab_pow5_im[1]),
|
||||
.ab_pow6_re1 (ab_pow6_re[1]),
|
||||
.ab_pow6_im1 (ab_pow6_im[1]),
|
||||
.ab_pow7_re1 (ab_pow7_re[1]),
|
||||
.ab_pow7_im1 (ab_pow7_im[1]),
|
||||
.b_pow8_re1 (b_pow8_re[1] ),
|
||||
.b_pow8_im1 (b_pow8_im[1] ),
|
||||
.a_re2 (ao_re[2] ),
|
||||
.a_im2 (ao_im[2] ),
|
||||
.ab_re2 (ab_re[2] ),
|
||||
.ab_im2 (ab_im[2] ),
|
||||
.abb_re2 (abb_re[2] ),
|
||||
.abb_im2 (abb_im[2] ),
|
||||
.ab_pow3_re2 (ab_pow3_re[2]),
|
||||
.ab_pow3_im2 (ab_pow3_im[2]),
|
||||
.ab_pow4_re2 (ab_pow4_re[2]),
|
||||
.ab_pow4_im2 (ab_pow4_im[2]),
|
||||
.ab_pow5_re2 (ab_pow5_re[2]),
|
||||
.ab_pow5_im2 (ab_pow5_im[2]),
|
||||
.ab_pow6_re2 (ab_pow6_re[2]),
|
||||
.ab_pow6_im2 (ab_pow6_im[2]),
|
||||
.ab_pow7_re2 (ab_pow7_re[2]),
|
||||
.ab_pow7_im2 (ab_pow7_im[2]),
|
||||
.b_pow8_re2 (b_pow8_re[2] ),
|
||||
.b_pow8_im2 (b_pow8_im[2] ),
|
||||
.a_re3 (ao_re[3] ),
|
||||
.a_im3 (ao_im[3] ),
|
||||
.ab_re3 (ab_re[3] ),
|
||||
.ab_im3 (ab_im[3] ),
|
||||
.abb_re3 (abb_re[3] ),
|
||||
.abb_im3 (abb_im[3] ),
|
||||
.ab_pow3_re3 (ab_pow3_re[3]),
|
||||
.ab_pow3_im3 (ab_pow3_im[3]),
|
||||
.ab_pow4_re3 (ab_pow4_re[3]),
|
||||
.ab_pow4_im3 (ab_pow4_im[3]),
|
||||
.ab_pow5_re3 (ab_pow5_re[3]),
|
||||
.ab_pow5_im3 (ab_pow5_im[3]),
|
||||
.ab_pow6_re3 (ab_pow6_re[3]),
|
||||
.ab_pow6_im3 (ab_pow6_im[3]),
|
||||
.ab_pow7_re3 (ab_pow7_re[3]),
|
||||
.ab_pow7_im3 (ab_pow7_im[3]),
|
||||
.b_pow8_re3 (b_pow8_re[3] ),
|
||||
.b_pow8_im3 (b_pow8_im[3] ),
|
||||
.a_re4 (ao_re[4] ),
|
||||
.a_im4 (ao_im[4] ),
|
||||
.ab_re4 (ab_re[4] ),
|
||||
.ab_im4 (ab_im[4] ),
|
||||
.abb_re4 (abb_re[4] ),
|
||||
.abb_im4 (abb_im[4] ),
|
||||
.ab_pow3_re4 (ab_pow3_re[4]),
|
||||
.ab_pow3_im4 (ab_pow3_im[4]),
|
||||
.ab_pow4_re4 (ab_pow4_re[4]),
|
||||
.ab_pow4_im4 (ab_pow4_im[4]),
|
||||
.ab_pow5_re4 (ab_pow5_re[4]),
|
||||
.ab_pow5_im4 (ab_pow5_im[4]),
|
||||
.ab_pow6_re4 (ab_pow6_re[4]),
|
||||
.ab_pow6_im4 (ab_pow6_im[4]),
|
||||
.ab_pow7_re4 (ab_pow7_re[4]),
|
||||
.ab_pow7_im4 (ab_pow7_im[4]),
|
||||
.b_pow8_re4 (b_pow8_re[4] ),
|
||||
.b_pow8_im4 (b_pow8_im[4] ),
|
||||
.a_re5 (ao_re[5] ),
|
||||
.a_im5 (ao_im[5] ),
|
||||
.ab_re5 (ab_re[5] ),
|
||||
.ab_im5 (ab_im[5] ),
|
||||
.abb_re5 (abb_re[5] ),
|
||||
.abb_im5 (abb_im[5] ),
|
||||
.ab_pow3_re5 (ab_pow3_re[5]),
|
||||
.ab_pow3_im5 (ab_pow3_im[5]),
|
||||
.ab_pow4_re5 (ab_pow4_re[5]),
|
||||
.ab_pow4_im5 (ab_pow4_im[5]),
|
||||
.ab_pow5_re5 (ab_pow5_re[5]),
|
||||
.ab_pow5_im5 (ab_pow5_im[5]),
|
||||
.ab_pow6_re5 (ab_pow6_re[5]),
|
||||
.ab_pow6_im5 (ab_pow6_im[5]),
|
||||
.ab_pow7_re5 (ab_pow7_re[5]),
|
||||
.ab_pow7_im5 (ab_pow7_im[5]),
|
||||
.b_pow8_re5 (b_pow8_re[5] ),
|
||||
.b_pow8_im5 (b_pow8_im[5] ),
|
||||
.dout_p0 (dout_0 ),
|
||||
.dout_p1 (dout_1 ),
|
||||
.dout_p2 (dout_2 ),
|
||||
.dout_p3 (dout_3 ),
|
||||
.dout_p4 (dout_4 ),
|
||||
.dout_p5 (dout_5 ),
|
||||
.dout_p6 (dout_6 ),
|
||||
.dout_p7 (dout_7 ),
|
||||
|
||||
.vldo (vldo_TC )
|
||||
|
||||
);
|
||||
|
||||
assign vldo = vldo_TC;
|
||||
|
||||
reg signed [15:0] doutf_0;
|
||||
reg signed [15:0] doutf_1;
|
||||
reg signed [15:0] doutf_2;
|
||||
reg signed [15:0] doutf_3;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn) begin
|
||||
doutf_0 <= 0;
|
||||
doutf_1 <= 0;
|
||||
doutf_2 <= 0;
|
||||
doutf_3 <= 0;
|
||||
end
|
||||
else if(!en) begin
|
||||
doutf_0 <= dout_0;
|
||||
doutf_1 <= dout_1;
|
||||
doutf_2 <= dout_2;
|
||||
doutf_3 <= dout_3;
|
||||
end
|
||||
else begin
|
||||
doutf_0 <= dout_4;
|
||||
doutf_1 <= dout_5;
|
||||
doutf_2 <= dout_6;
|
||||
doutf_3 <= dout_7;
|
||||
end
|
||||
|
||||
assign dout0 = doutf_0;
|
||||
assign dout1 = doutf_1;
|
||||
assign dout2 = doutf_2;
|
||||
assign dout3 = doutf_3;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,140 +0,0 @@
|
|||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : Z_dsp_en_Test.v
|
||||
// Department :
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 0.1 2024-11-12 thfu Test Enable signal using clk divided by 2
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
module z_dsp_en_Test
|
||||
(
|
||||
input clk,
|
||||
input rstn,
|
||||
input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
|
||||
//2'b10:Double Double data mode;2'b11:reserve;
|
||||
input tc_bypass,
|
||||
input vldi,
|
||||
input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
|
||||
input signed [15:0] din_re,
|
||||
input signed [15:0] din_im,
|
||||
input signed [31:0] a0_re, //a0's real part
|
||||
input signed [31:0] a0_im, //a0's image part
|
||||
input signed [31:0] b0_re,
|
||||
input signed [31:0] b0_im,
|
||||
input signed [31:0] a1_re,
|
||||
input signed [31:0] a1_im,
|
||||
input signed [31:0] b1_re,
|
||||
input signed [31:0] b1_im,
|
||||
input signed [31:0] a2_re,
|
||||
input signed [31:0] a2_im,
|
||||
input signed [31:0] b2_re,
|
||||
input signed [31:0] b2_im,
|
||||
input signed [31:0] a3_re,
|
||||
input signed [31:0] a3_im,
|
||||
input signed [31:0] b3_re,
|
||||
input signed [31:0] b3_im,
|
||||
input signed [31:0] a4_re,
|
||||
input signed [31:0] a4_im,
|
||||
input signed [31:0] b4_re,
|
||||
input signed [31:0] b4_im,
|
||||
input signed [31:0] a5_re,
|
||||
input signed [31:0] a5_im,
|
||||
input signed [31:0] b5_re,
|
||||
input signed [31:0] b5_im,
|
||||
output signed [15:0] dout0,
|
||||
output signed [15:0] dout1,
|
||||
output signed [15:0] dout2,
|
||||
output signed [15:0] dout3,
|
||||
output vldo,
|
||||
output saturation_0,
|
||||
output saturation_1,
|
||||
output saturation_2,
|
||||
output saturation_3,
|
||||
output saturation_4,
|
||||
output saturation_5
|
||||
);
|
||||
|
||||
wire signed [15:0] IIR_out;
|
||||
|
||||
reg en;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
en <= 0;
|
||||
else
|
||||
en <= ~en;
|
||||
|
||||
z_dsp inst_z_dsp
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (~en ),
|
||||
.vldi (vldi ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din_re (din_re ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout0 ),
|
||||
.dout1 (dout1 ),
|
||||
.dout2 (dout2 ),
|
||||
.dout3 (dout3 ),
|
||||
.vldo (vldo ),
|
||||
.saturation_0 (saturation_0 ),
|
||||
.saturation_1 (saturation_1 ),
|
||||
.saturation_2 (saturation_2 ),
|
||||
.saturation_3 (saturation_3 ),
|
||||
.saturation_4 (saturation_4 ),
|
||||
.saturation_5 (saturation_5 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
%in+iir_out with 8 intp
|
||||
clc;clear;close all
|
||||
|
||||
in = importdata("/home/thfu/work/TailCorr/sim/in.dat");
|
||||
diff_in = importdata("/home/thfu/work/TailCorr/sim/diff_in.dat");
|
||||
wave_verdi = importdata("/home/thfu/work/TailCorr/sim/OrgOut.dat");
|
||||
|
||||
dout0 = importdata("/home/thfu/work/TailCorr/sim/dout0.dat");
|
||||
dout1 = importdata("/home/thfu/work/TailCorr/sim/dout1.dat");
|
||||
dout2 = importdata("/home/thfu/work/TailCorr/sim/dout2.dat");
|
||||
dout3 = importdata("/home/thfu/work/TailCorr/sim/dout3.dat");
|
||||
|
||||
N = length(dout0);
|
||||
cs_wave = zeros(4*N,1);
|
||||
cs_wave(1:4:4*N) = dout0;
|
||||
cs_wave(2:4:4*N) = dout1;
|
||||
cs_wave(3:4:4*N) = dout2;
|
||||
cs_wave(4:4:4*N) = dout3;
|
||||
|
||||
A = [0.025 0.015 0.0002 0];
|
||||
tau = -[1/250 1/650 1/1600 0];
|
||||
fs = 2e9;
|
||||
|
||||
coef_len = length(A);
|
||||
for i = 1:coef_len
|
||||
b(i) = exp(1e9/fs/(1-A(i))*tau(i));
|
||||
a(i) = A(i)/1/(1-A(i))*exp(1e9/fs/(1-A(i))/2*tau(i));
|
||||
h_ideal(:,i) = filter(a(i),[1 -b(i)],diff_in);
|
||||
end
|
||||
|
||||
wave_float = in+ sum(h_ideal,2);
|
||||
|
||||
wave_float_len = length(wave_float);
|
||||
wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')';
|
||||
|
||||
[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
|
||||
N = min(length(wave_float_8_A),length(cs_wave_A));
|
||||
figure()
|
||||
diff_plot(wave_float_8_A(90:end), cs_wave_A(162:end),'float','verdi',[0 N]);
|
||||
%%
|
||||
%Test of iir filter
|
||||
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
|
||||
N = min(length(wave_float_A),length(wave_verdi_A));
|
||||
figure()
|
||||
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
|
||||
%%
|
||||
signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
|
||||
%%
|
||||
fprintf("a is %.10f\n",a)
|
||||
fprintf("b is %.10f\n",b)
|
||||
|
||||
a_fix = round(a*2^31);
|
||||
b_fix = round(b*2^31);
|
||||
|
||||
a_hex = dec2hex(a_fix,8);
|
||||
b_hex = dec2hex(b_fix,8);
|
||||
|
||||
a_bin = dec2bin(a_fix,32);
|
||||
b_bin = dec2bin(b_fix,32);
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
%in+iir_out with 8 intp
|
||||
clc;clear;close all
|
||||
% addpath("/data/work/thfu/TailCorr/script_m");
|
||||
data_source = 'matlab';
|
||||
file_path = "/home/thfu/work/TailCorr/sim/z_dsp/";
|
||||
rng('shuffle');
|
||||
|
||||
if strcmp(data_source, 'matlab')
|
||||
in = floor(cat(1,0,3000*randn(4*2579+4,1)));
|
||||
for i = 0:3
|
||||
filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
|
||||
subset = in(i+1:4:end);
|
||||
fileID = fopen(filename, 'w');
|
||||
fprintf(fileID, '%d\n', subset);
|
||||
fclose(fileID);
|
||||
end
|
||||
in = [in; zeros(6e4,1)];
|
||||
system('make all');
|
||||
elseif strcmp(data_source, 'verdi')
|
||||
% system('make all');
|
||||
in = [];
|
||||
for i = 0:3
|
||||
filename = strcat(file_path, "in", num2str(i), ".dat");
|
||||
in_data = importdata(filename);
|
||||
if isempty(in)
|
||||
N = length(in_data);
|
||||
in = zeros(4*N, 1);
|
||||
end
|
||||
in(i+1:4:end) = in_data;
|
||||
end
|
||||
else
|
||||
end
|
||||
|
||||
|
||||
cs_wave = [];
|
||||
for i = 0:3
|
||||
filename = strcat(file_path, "dout", num2str(i), ".dat");
|
||||
dout_data = importdata(filename);
|
||||
if isempty(cs_wave)
|
||||
N = length(dout_data);
|
||||
cs_wave = zeros(4*N, 1);
|
||||
end
|
||||
cs_wave(i+1:4:end) = dout_data;
|
||||
end
|
||||
|
||||
A = [0.025 0.015*1 0.0002*1 0];
|
||||
tau = -[1/250 1/650 1/1600 0];
|
||||
fs = 2e9;
|
||||
|
||||
coef_len = length(A);
|
||||
for i = 1:coef_len
|
||||
b(i) = exp(1e9/fs/(1-A(i))*tau(i));
|
||||
a(i) = A(i)/1/(1-A(i))*exp(1e9/fs/(1-A(i))/2*tau(i));
|
||||
h_ideal(:,i) = filter(a(i),[1 -b(i)],diff(in));
|
||||
end
|
||||
len_in = length(in);
|
||||
len_h_ideal = length(h_ideal);
|
||||
in = [in; zeros(1, len_h_ideal - len_in + 1)'];
|
||||
wave_float = in(2:end)+ sum(h_ideal,2);
|
||||
|
||||
wave_float_len = length(wave_float);
|
||||
wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')';
|
||||
|
||||
[cs_wave_A,wave_float_A,Delay] = alignsignals(cs_wave,wave_float,Method="xcorr");
|
||||
N = min(length(wave_float),length(cs_wave_A));
|
||||
figure()
|
||||
diff_plot(wave_float_A, cs_wave_A,'float','verdi',[0 N]);
|
||||
|
||||
%% Test of iir filter with no intp
|
||||
|
||||
[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
|
||||
N = min(length(wave_float_A),length(wave_verdi_A));
|
||||
figure()
|
||||
diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
|
||||
%%
|
||||
signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
|
||||
%%
|
||||
|
||||
a_fix = round(a*2^31);
|
||||
b_fix = round(b*2^31);
|
||||
ab_fix = round(a.*b*2^31);
|
||||
ab2_fix = round(a.*b.^2*2^31);
|
||||
ab3_fix = round(a.*b.^3*2^31);
|
||||
ab4_fix = round(a.*b.^4*2^31);
|
||||
ab5_fix = round(a.*b.^5*2^31);
|
||||
ab6_fix = round(a.*b.^6*2^31);
|
||||
ab7_fix = round(a.*b.^7*2^31);
|
||||
b8_fix = round(b.^8*2^31);
|
||||
|
||||
a_hex = dec2hex(a_fix,8);
|
||||
|
||||
a_bin = dec2bin(a_fix,32);
|
||||
|
||||
fprintf('a_fix is %d\n',a_fix);
|
||||
fprintf('b_fix is %d\n',b_fix);
|
||||
fprintf('ab_fix is %d\n',ab_fix);
|
||||
fprintf('ab2_fix is %d\n', ab2_fix);
|
||||
fprintf('ab3_fix is %d\n', ab3_fix);
|
||||
fprintf('ab4_fix is %d\n', ab4_fix);
|
||||
fprintf('ab5_fix is %d\n', ab5_fix);
|
||||
fprintf('ab6_fix is %d\n', ab6_fix);
|
||||
fprintf('ab7_fix is %d\n', ab7_fix);
|
||||
fprintf('b8_fix is %d\n',b8_fix);
|
||||
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
%compare FIL with python script
|
||||
function diff_plot_py(fs,iir_out, Script_out,title1,title2,a,amp,edge,fileID)
|
||||
%输入数据长度不等时取其公共部分
|
||||
N = min(length(iir_out),length(Script_out));
|
||||
iir_out = iir_out(1:N);
|
||||
Script_out = Script_out(1:N);
|
||||
|
||||
diff = (iir_out - Script_out)/amp;%求差，并归一化
|
||||
|
||||
n = (0:1:N-1)/fs;
|
||||
%找出关心的数据点
|
||||
n_edge = find(n>=edge-1e-12);%edge代表下降沿
|
||||
n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
|
||||
n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
|
||||
n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
|
||||
n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
|
||||
|
||||
ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
|
||||
ne(1) = 1;
|
||||
|
||||
window_length = 100e-9*fs;
|
||||
diff_mean_window = movmean(diff,window_length);
|
||||
diff_std_window = movstd(diff,window_length);
|
||||
n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
|
||||
n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
|
||||
n_common = max(n_mean_window(end),n_std_window(end));
|
||||
%原始数据作图
|
||||
tiledlayout(2,1)
|
||||
ax1 = nexttile;
|
||||
plot(n,iir_out,n,Script_out)
|
||||
legend(title1,title2)
|
||||
xlabel('t/s')
|
||||
xlim(a)
|
||||
grid on
|
||||
hold on
|
||||
|
||||
%差值做图
|
||||
ax2 = nexttile;
|
||||
plot(n,diff)
|
||||
xlabel('t/s')
|
||||
title('diff')
|
||||
grid on
|
||||
hold on
|
||||
xlim(a)
|
||||
linkaxes([ax1,ax2],'x');
|
||||
|
||||
plot_p = @(x)[
|
||||
plot(n(x),diff(x),'r*');
|
||||
text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
|
||||
];
|
||||
|
||||
ne(1) = 1;
|
||||
|
||||
% [diff_max,R_mpos] = max(abs(diff));%误差最大值
|
||||
% plot_p(R_mpos);
|
||||
|
||||
if a(2) <= 5e-6
|
||||
plot_p(n_edge(1));%下降沿
|
||||
% plot_p(R_mpos);
|
||||
elseif a(2) == 20e-6
|
||||
plot_p(n50(1)); %下降沿20ns
|
||||
plot_p(n1000(1)); %下降沿1us
|
||||
plot_p(ne(end)); %误差小于万分之一
|
||||
fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
|
||||
fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100)));
|
||||
% fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
|
||||
% fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
|
||||
fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
|
||||
end
|
||||
|
||||
|
||||
|
||||
846
script_m/z_dsp.m
846
script_m/z_dsp.m
|
|
@ -1,305 +1,565 @@
|
|||
clc;clear;close all
|
||||
classdef z_dsp < handle
|
||||
properties
|
||||
%input
|
||||
fs_L;
|
||||
fs_H;
|
||||
TargetFrequency;
|
||||
G;
|
||||
simulink_time;
|
||||
intp_mode;
|
||||
dac_mode_sel;
|
||||
route_num;
|
||||
env_num;
|
||||
|
||||
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
|
||||
%%配置参数
|
||||
fs_L = 0.75e9; %硬件频率
|
||||
fs_H = 12e9; %以高频近似理想信号
|
||||
TargetFrequency = 3e9;
|
||||
G = 1;
|
||||
DownSample = 2;
|
||||
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
|
||||
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
|
||||
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
|
||||
route_num = 5;
|
||||
env_num = 7;
|
||||
|
||||
Ideal2Low = fs_H/(fs_L/2);
|
||||
Ideal2Target = fs_H/TargetFrequency;
|
||||
%% 添加路径、产生包络、配置S21参数、使用脚本计算
|
||||
|
||||
%%添加路径
|
||||
% addpath(genpath('D:\Work\EnvData'));
|
||||
% addpath(genpath('D:\Work\EnvData\data-v2'));
|
||||
% addpath(genpath('D:\Work\TailCorr_20241008_NoGit'));
|
||||
% addpath('D:\Work\TailCorr\script_m');
|
||||
cd("D:\Work\EnvData\acz");
|
||||
obj1 = py.importlib.import_module('acz');
|
||||
py.importlib.reload(obj1);
|
||||
cd("D:\Work\TailCorr_20241008_NoGit");
|
||||
obj2 = py.importlib.import_module('wave_calculation');
|
||||
py.importlib.reload(obj2);
|
||||
cd("D:\Work\TailCorr");
|
||||
%%产生包络
|
||||
%按点数产生理想方波
|
||||
% amp_rect = 1.5e4;
|
||||
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
|
||||
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
|
||||
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
|
||||
%
|
||||
% for i = 1:2
|
||||
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
|
||||
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
|
||||
% end
|
||||
|
||||
%flattop波
|
||||
A = 1.5e4;
|
||||
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
|
||||
[edge(2), length_flattop(2)] = deal(4,30);
|
||||
[edge(3), length_flattop(3)] = deal(4,50);
|
||||
[edge(4), length_flattop(4)] = deal(4,1000);
|
||||
[edge(5), length_flattop(5)] = deal(100,10000);
|
||||
for i = 1:5
|
||||
[edge_H(i), length_H(i)] = deal(edge(i)*fs_H/1e9,length_flattop(i)*fs_H/1e9);
|
||||
wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
|
||||
end
|
||||
|
||||
%acz波
|
||||
amplitude = 1.5e4;
|
||||
|
||||
carrierFreq = 0.000000;
|
||||
carrierPhase = 0.000000;
|
||||
dragAlpha = 0.000000;
|
||||
thf = 0.864;
|
||||
thi = 0.05;
|
||||
lam2 = -0.18;
|
||||
lam3 = 0.04;
|
||||
|
||||
length_acz(1) = 30;
|
||||
length_acz(2) = 50;
|
||||
|
||||
for i = 1:2
|
||||
length_acz_H(i) = int32(length_acz(i)*fs_H/1e9);
|
||||
wave_pre{i+5} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
|
||||
end
|
||||
|
||||
for i = 1:7
|
||||
wave_pre{i} = cat(2,wave_pre{i},zeros(1,floor(simulink_time*fs_H))); %校正前的高频信号
|
||||
wave_preL{i} = wave_pre{i}(1:Ideal2Low:end); %校正前的低频信号
|
||||
end
|
||||
|
||||
%%S21参数
|
||||
amp_real{1} = [0.025 0.015 0.0002 0.2 0 0];
|
||||
amp_imag{1} = [0 0 0 0 0 0];
|
||||
time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
time_imag{1} = [0 -1/300 -1/500 0 0 0];
|
||||
|
||||
amp_real{2} = [0.025 0.015 0.0002 0.2 0 0];
|
||||
amp_imag{2} = [0 0 0 0 0 0];
|
||||
time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
time_imag{2} = [0 -1/300 -1/500 0 0 0];
|
||||
|
||||
amp_real{3} = [0.025 0.009 0.0002 0.2 0 0];
|
||||
amp_imag{3} = [0 0.012 0 0 0 0];
|
||||
time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
time_imag{3} = [0 -1/300 -1/500 0 0 0];
|
||||
|
||||
|
||||
amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
|
||||
amp_imag{4}= [0 0 0 0 0 0];
|
||||
time_real{4}= [-1/250, -1/2000, -1/1600 -1/20 0 0];
|
||||
time_imag{4}= [0 -1/15 -1/50 0 0 0];
|
||||
|
||||
amp_real{5} = [0.025 0.009 0.0002 0.2 0 0];
|
||||
amp_imag{5} = [0 0.012 0 0 0 0];
|
||||
time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
|
||||
time_imag{5} = [0 -1/15 -1/50 0 0 0];
|
||||
|
||||
for i = 1:5
|
||||
amp_routing{i} = amp_real{1,i} + 1j*amp_imag{1,i};
|
||||
time_routing{i} = time_real{1,i} + 1j*time_imag{1,i};
|
||||
tau{i} = -1./time_routing{i};
|
||||
end
|
||||
|
||||
%%python脚本校正结果
|
||||
|
||||
convolve_bound = int8(3);
|
||||
calibration_time = int32(20e3);
|
||||
cal_method = int8(1);
|
||||
sampling_rateL = int64(fs_L/2);
|
||||
sampling_rate = int64(fs_H);
|
||||
|
||||
%校正后的高频信号
|
||||
for j = 1:route_num
|
||||
for i = 1:env_num
|
||||
wave_cal = cell(py.wave_calculation.wave_cal(wave_pre{1,i}, amp_real{1,j}, amp_imag{1,j}, time_real{1,j}, time_imag{1,j}, convolve_bound, calibration_time, cal_method, sampling_rate));
|
||||
wave_revised{j,i} = double(wave_cal{1,1});
|
||||
wave_calL = cell(py.wave_calculation.wave_cal(wave_preL{1,i}, amp_real{1,j}, amp_imag{1,j}, time_real{1,j}, time_imag{1,j}, convolve_bound, calibration_time, cal_method, sampling_rateL));
|
||||
wave_revisedL{j,i} = double(wave_calL{1,1});
|
||||
%output
|
||||
Ideal2Low;
|
||||
Ideal2Target;
|
||||
wave_pre;
|
||||
wave_preL;
|
||||
amp_real;
|
||||
amp_imag;
|
||||
time_real;
|
||||
time_imag;
|
||||
name;
|
||||
wave_revised;
|
||||
wave_revisedL;
|
||||
DownsamplingBy12GDataAlign;
|
||||
HardwareMeanIntpDataAlign;
|
||||
Delay;
|
||||
Delay_mode;
|
||||
pause_time;
|
||||
filename;
|
||||
rpt_num;
|
||||
FallingEdge;
|
||||
Amp;
|
||||
itv_time; %信号具有周期性时的间隔
|
||||
end
|
||||
alpha{j} = double(wave_calL{1,2});
|
||||
beta{j} = double(wave_calL{1,3});
|
||||
end
|
||||
% signalAnalyzer(wave_pre{1,1},'SampleRate',fs_H);
|
||||
|
||||
%校正后的低频信号
|
||||
methods
|
||||
|
||||
alpha_wideth=32;
|
||||
beta_width=32;
|
||||
%定点化系数
|
||||
for i = 1:route_num
|
||||
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
|
||||
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
|
||||
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
|
||||
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
|
||||
end
|
||||
%% 仿真
|
||||
for j = 1:route_num
|
||||
for i = 1:env_num
|
||||
options=simset('SrcWorkspace','current');
|
||||
sim('z_dsp',[0,simulink_time]);
|
||||
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
|
||||
dout0{j,i} = sim2m("dout0");
|
||||
dout1{j,i} = sim2m("dout1");
|
||||
dout2{j,i} = sim2m("dout2");
|
||||
dout3{j,i} = sim2m("dout3");
|
||||
function obj = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel)
|
||||
obj.fs_L = fs_L;
|
||||
obj.fs_H = fs_H;
|
||||
obj.TargetFrequency = TargetFrequency;
|
||||
obj.G = G;
|
||||
obj.simulink_time = simulink_time;
|
||||
obj.intp_mode = intp_mode;
|
||||
obj.dac_mode_sel = dac_mode_sel;
|
||||
obj.Ideal2Low = fs_H/(fs_L/2);
|
||||
obj.Ideal2Target = fs_H/TargetFrequency;
|
||||
obj.name = [
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第一组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第一组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第二组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第二组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第三组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第三组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第四组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第四组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿",...
|
||||
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿",...
|
||||
"第五组S21参数_acz_持续时间30ns_下降沿",...
|
||||
"第五组S21参数_acz_持续时间50ns_下降沿";
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第一组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第一组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第二组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第二组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第三组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第三组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第四组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第四组S21参数_acz_持续时间50ns_下降沿后";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后",...
|
||||
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后",...
|
||||
"第五组S21参数_acz_持续时间30ns_下降沿后",...
|
||||
"第五组S21参数_acz_持续时间50ns_下降沿后";
|
||||
];
|
||||
obj.pause_time = 0.5;
|
||||
obj.Amp = 1.5e4;
|
||||
end
|
||||
|
||||
function env(obj)
|
||||
|
||||
cd("D:\Work\EnvData\acz");
|
||||
obj1 = py.importlib.import_module('acz');
|
||||
py.importlib.reload(obj1);
|
||||
|
||||
%按点数产生理想方波
|
||||
% amp_rect = 1.5e4;
|
||||
% %单位是ns front是到达时间，flat是持续时间，lagging是后边还有多少个0，会影响脚本的修正时间
|
||||
% [front(1), flat(1), lagging(1)] = deal(50,100,7400);% 50,100,7400;100ns方波
|
||||
% [front(2), flat(2), lagging(2)] = deal(50,4000,11500);% 50,4000,11500；4us方波
|
||||
%
|
||||
% for i = 1:2
|
||||
% front_H(i) = front(i)*fs_H/1e9; flat_H(i) = flat(i)*fs_H/1e9; lagging_H(i) = lagging(i)*fs_H/1e9;
|
||||
% wave_pre{i} = amp_rect*cat(2,zeros(1,front_H(i)),ones(1,flat_H(i)),zeros(1,lagging_H(i)));%脚本的单位是点数
|
||||
% end
|
||||
%flattop波
|
||||
A = 1.5e4;
|
||||
[edge(1), length_flattop(1)] = deal(2,30);%ns，在fsn_L取1时是参数里的length
|
||||
[edge(2), length_flattop(2)] = deal(4,30);
|
||||
[edge(3), length_flattop(3)] = deal(4,50);
|
||||
[edge(4), length_flattop(4)] = deal(4,1000);
|
||||
[edge(5), length_flattop(5)] = deal(100,10000);
|
||||
|
||||
for i = 1:length(length_flattop)
|
||||
[edge_H(i), length_H(i)] = deal(edge(i)*obj.fs_H/1e9,length_flattop(i)*obj.fs_H/1e9);
|
||||
obj.wave_pre{i} = flattop(A, edge_H(i), length_H(i), 1);
|
||||
end
|
||||
|
||||
%acz波
|
||||
amplitude = 1.5e4;
|
||||
|
||||
carrierFreq = 0.000000;
|
||||
carrierPhase = 0.000000;
|
||||
dragAlpha = 0.000000;
|
||||
thf = 0.864;
|
||||
thi = 0.05;
|
||||
lam2 = -0.18;
|
||||
lam3 = 0.04;
|
||||
|
||||
length_acz(1) = 30;
|
||||
length_acz(2) = 50;
|
||||
|
||||
for i = 1:length(length_acz)
|
||||
length_acz_H(i) = int32(length_acz(i)*obj.fs_H/1e9);
|
||||
obj.wave_pre{i+length(length_flattop)} = real(double(py.acz.aczwave(amplitude, length_acz_H(i), carrierFreq,carrierPhase, dragAlpha,thf, thi, lam2, lam3)));
|
||||
end
|
||||
|
||||
obj.env_num = length(length_flattop) + length(length_acz);
|
||||
|
||||
for i = 1:obj.env_num
|
||||
obj.wave_pre{i} = cat(2,repmat(cat(2,obj.wave_pre{i},zeros(1,round(30e-9*obj.fs_H))),1,obj.rpt_num),zeros(1,floor(obj.simulink_time*obj.fs_H))); %校正前的高频信号
|
||||
obj.wave_preL{i} = obj.wave_pre{i}(1:obj.Ideal2Low:end); %校正前的低频信号
|
||||
end
|
||||
|
||||
assignin("base",'wave_preL',obj.wave_preL);
|
||||
obj.FallingEdge = [30e-9,30e-9,50e-9,1000e-9,10000e-9,30e-9,50e-9];
|
||||
|
||||
end
|
||||
|
||||
function route(obj)
|
||||
|
||||
obj.amp_real{1}= [0.025 0.015 0.0002 0.2 0 0];
|
||||
obj.amp_imag{1}= [0 0 0 0 0 0];
|
||||
obj.time_real{1} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{1} = [0 0 0 0 0 0];
|
||||
|
||||
obj.amp_real{2}= [0.025 0.015 0.0002 0.2 0 0];
|
||||
obj.amp_imag{2}= [0 0 0 0 0 0];
|
||||
obj.time_real{2} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{2} = [0 -1/300 -1/500 0 0 0];
|
||||
|
||||
obj.amp_real{3}= [0.025 0.009 0.0002 0.2 0 0];
|
||||
obj.amp_imag{3}= [0 0.012 0 0 0 0];
|
||||
obj.time_real{3} = [-1/250, -1/650, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{3} = [0 -1/300 -1/500 0 0 0];
|
||||
|
||||
obj.amp_real{4}= [0.025 0.015 0.0002 0.2 0 0];
|
||||
obj.amp_imag{4}= [0 0 0 0 0 0];
|
||||
obj.time_real{4} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{4} = [0 -1/15 -1/50 0 0 0];
|
||||
|
||||
obj.amp_real{5}= [0.025 0.009 0.0002 0.2 0 0];
|
||||
obj.amp_imag{5}= [0 0.012 0 0 0 0];
|
||||
obj.time_real{5} = [-1/250, -1/2000, -1/1600 -1/20 0 0];
|
||||
obj.time_imag{5} = [0 -1/15 -1/50 0 0 0];
|
||||
|
||||
[m,n] = size(obj.amp_real);
|
||||
obj.route_num = n;
|
||||
end
|
||||
|
||||
function py_cal(obj)
|
||||
|
||||
cd("D:\Work\TailCorr_20241008_NoGit");
|
||||
obj2 = py.importlib.import_module('wave_calculation');
|
||||
py.importlib.reload(obj2);
|
||||
cd("D:\Work\TailCorr");
|
||||
|
||||
convolve_bound = int8(3);
|
||||
calibration_time = int32(20e3);
|
||||
cal_method = int8(1);
|
||||
sampling_rateL = int64(obj.fs_L/2);
|
||||
sampling_rate = int64(obj.fs_H);
|
||||
|
||||
%校正后的高频信号
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:obj.env_num
|
||||
wave_cal = cell(py.wave_calculation.wave_cal(obj.wave_pre{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rate));
|
||||
obj.wave_revised{m,n} = double(wave_cal{1,1});
|
||||
wave_calL = cell(py.wave_calculation.wave_cal(obj.wave_preL{1,n}, obj.amp_real{1,m}, obj.amp_imag{1,m}, obj.time_real{1,m}, obj.time_imag{1,m}, convolve_bound, calibration_time, cal_method, sampling_rateL));
|
||||
obj.wave_revisedL{m,n} = double(wave_calL{1,1});
|
||||
end
|
||||
alpha{m} = double(wave_calL{1,2});
|
||||
beta{m} = double(wave_calL{1,3});
|
||||
end
|
||||
alpha_wideth=32;
|
||||
beta_width=32;
|
||||
%定点化系数
|
||||
for i = 1:obj.route_num
|
||||
alphaFixRe{i} = ceil((2^(alpha_wideth-1))*real(alpha{i}));
|
||||
alphaFixIm{i} = ceil((2^(alpha_wideth-1))*imag(alpha{i}));
|
||||
betaFixRe{i} = ceil((2^(beta_width-1))*real(beta{i}));
|
||||
betaFixIm{i} = ceil((2^(beta_width-1))*imag(beta{i}));
|
||||
end
|
||||
|
||||
assignin('base', 'alphaFixRe', alphaFixRe);
|
||||
assignin('base', 'alphaFixIm', alphaFixIm);
|
||||
assignin('base', 'betaFixRe' , betaFixRe);
|
||||
assignin('base', 'betaFixIm' , betaFixIm);
|
||||
end
|
||||
|
||||
function FIL(obj)
|
||||
|
||||
for m = 1:obj.route_num
|
||||
assignin('base', 'm', m);
|
||||
for n = 1:obj.env_num
|
||||
assignin('base', 'n', n);
|
||||
optnons=simset('SrcWorkspace','current');
|
||||
sim('z_dsp_FIL',[0,obj.simulink_time]);
|
||||
sim2m = @(x)reshape(logsout.get(x).Values.Data,[],1);
|
||||
dout0{m,n} = sim2m("dout0");
|
||||
dout1{m,n} = sim2m("dout1");
|
||||
dout2{m,n} = sim2m("dout2");
|
||||
dout3{m,n} = sim2m("dout3");
|
||||
|
||||
N = length(dout0{m,n});
|
||||
cs_wave{m,n} = zeros(4*N,1);
|
||||
|
||||
cs_wave{m,n}(1:4:4*N) = dout0{m,n};
|
||||
cs_wave{m,n}(2:4:4*N) = dout1{m,n};
|
||||
cs_wave{m,n}(3:4:4*N) = dout2{m,n};
|
||||
cs_wave{m,n}(4:4:4*N) = dout3{m,n};
|
||||
|
||||
HardwareMeanIntpData{m,n} = cs_wave{m,n};%硬件校正后内插
|
||||
DownsamplingBy12GData{m,n} = obj.wave_revised{m,n}(1:obj.Ideal2Target:end);
|
||||
[obj.DownsamplingBy12GDataAlign{m,n},obj.HardwareMeanIntpDataAlign{m,n},obj.Delay(m,n)] = ...
|
||||
alignsignals(DownsamplingBy12GData{m,n}(1:round(obj.TargetFrequency*20e-6)),HardwareMeanIntpData{m,n}(1:round(obj.TargetFrequency*20e-6)),"Method","xcorr");
|
||||
end
|
||||
end
|
||||
obj.Delay_mode = mode(obj.Delay,'all');
|
||||
fprintf('Delay_mode = %d\n',obj.Delay_mode);
|
||||
end
|
||||
|
||||
function DataShow(obj,save)
|
||||
|
||||
close all;
|
||||
|
||||
fileID = fopen(obj.filename, 'w');
|
||||
if fileID == -1
|
||||
disp('文件打开失败');
|
||||
else
|
||||
disp('文件打开成功');
|
||||
end
|
||||
|
||||
start_time = abs(obj.Delay_mode)/(obj.TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
|
||||
|
||||
if(obj.rpt_num == 1)
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:obj.env_num
|
||||
edge_Align(n) = obj.FallingEdge(n) + start_time;
|
||||
tmp(n) = edge_Align(n) + 10e-9;
|
||||
a{n} = [start_time-5e-9 tmp(n)];%[1/obj.fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
|
||||
b{n} = [tmp(n) 20e-6];
|
||||
|
||||
figure('Units','normalized','Position',[0.0004 0.5174 0.4992 0.4229]);
|
||||
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',a{n},obj.Amp,edge_Align(n),fileID);
|
||||
if(save == "save")
|
||||
savefig(obj.name(m,n));
|
||||
end
|
||||
|
||||
figure('Units','normalized','Position',[0.0004 0.0340 0.4992 0.4229]);
|
||||
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m+5,n),'硬件与脚本的差值',b{n},obj.Amp,edge_Align(n),fileID);
|
||||
if(save == "save")
|
||||
savefig(obj.name(m+5,n));
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:obj.env_num
|
||||
figure('Units','normalized','Position',[0 0.0333 1.0000 0.9125]);
|
||||
title(obj.name(m,n),Interpreter="none");
|
||||
tiledlayout('vertical','TileSpacing','tight')
|
||||
obj.diff_plot_py(obj.TargetFrequency,obj.HardwareMeanIntpDataAlign{m,n}', obj.DownsamplingBy12GDataAlign{m,n}(1:floor(obj.TargetFrequency*20e-6)),obj.name(m,n),'硬件与脚本的差值',obj.FallingEdge(n)+obj.itv_time,obj.Amp,start_time,fileID);
|
||||
if(save == "save")
|
||||
savefig(obj.name(m,n));
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
fclose(fileID);
|
||||
|
||||
end
|
||||
|
||||
function RouteShow(obj,save)
|
||||
|
||||
t = 0:1/(1e2):10000;
|
||||
for i = 1:5
|
||||
amp_routing{i} = obj.amp_real{1,i} + 1j*obj.amp_imag{1,i};
|
||||
time_routing{i} = obj.time_real{1,i} + 1j*obj.time_imag{1,i};
|
||||
tau{i} = -1./time_routing{i};
|
||||
end
|
||||
|
||||
figure()
|
||||
set(gcf,"Position",[1 49 2560 1314])
|
||||
tiledlayout('flow','TileSpacing','tight');
|
||||
title_name = ["第一组S_{21}参数","第二组S_{21}参数","第三组S_{21}参数","第四组S_{21}参数","第五组S_{21}参数"];
|
||||
for m = 1:obj.route_num
|
||||
for n = 1:1:length(amp_routing{1,m})
|
||||
S21_time{m}(:,n) = amp_routing{1,m}(n)*exp(time_routing{1,m}(n)*t);
|
||||
end
|
||||
nexttile
|
||||
plot(t*1e-9,real(sum(S21_time{m},2)));
|
||||
grid on
|
||||
title(title_name(m));
|
||||
end
|
||||
|
||||
if(save == "save")
|
||||
savefig("S21线路参数");
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
function FigDisplay(obj)
|
||||
if(obj.rpt_num == 1)
|
||||
for m = 1:obj.route_num*obj.env_num
|
||||
figure(2*m-1)
|
||||
figure(2*m)
|
||||
pause(obj.pause_time);
|
||||
end
|
||||
|
||||
else
|
||||
for m = 1:obj.route_num*obj.env_num
|
||||
figure(m)
|
||||
pause(obj.pause_time);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
function LoadFigAndDisplay(obj)
|
||||
for n = 1:obj.route_num
|
||||
for m = 1:obj.env_num
|
||||
open(strcat(obj.name(n,m),'.fig'));
|
||||
open(strcat(obj.name(n+5,m),'.fig'));
|
||||
pause(obj.pause_time);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
function ErrAny(obj,save)
|
||||
fid = fopen(obj.filename,'r');
|
||||
if(obj.rpt_num == 1)
|
||||
data = textscan(fid,'Falling edge of 20ns~40ns mean :%s std :%s Falling edge of 1us~1.1us mean :%s std :%s The mean and std stably less than 1e-4 is :%s s');
|
||||
fclose(fid);
|
||||
data{1} = cellfun(@str2num,data{1});
|
||||
data{2} = cellfun(@str2num,data{2});
|
||||
data{3} = cellfun(@str2num,data{3});
|
||||
data{4} = cellfun(@str2num,data{4});
|
||||
data{5} = cellfun(@str2num,data{5});
|
||||
title_name = ["下降沿后20ns~40ns误差的平均值","下降沿后20ns~40ns误差的标准差","下降沿后1us~1.1us误差的平均值","下降沿后1us~1.1us误差的标准差","加窗参数"];
|
||||
err_threshold = [1e-3 1e-3 1e-4 3e-4 5e-6];
|
||||
else
|
||||
data = textscan(fid,'每个周期拖尾误差均值的标准差 = %s s');
|
||||
fclose(fid);
|
||||
data{1} = cellfun(@str2num,data{1});
|
||||
title_name = ["多周期误差平均值的标准差"];
|
||||
err_threshold = [0.5e-3];
|
||||
end
|
||||
[h,v] = size(data);
|
||||
figure()
|
||||
tiledlayout('flow','TileSpacing','tight')
|
||||
colors = lines(obj.route_num);
|
||||
set(gcf,'Position', [1 49 2560 1314]);
|
||||
for m = 1:v
|
||||
nexttile
|
||||
hold on
|
||||
for i = 1:(obj.route_num)
|
||||
idx = (i-1)*(length(data{m})/obj.route_num) + 1 : i*(length(data{m})/obj.route_num);
|
||||
plot(idx,abs(data{m}(idx)),'-o','Color', colors(i, :));
|
||||
end
|
||||
yline(err_threshold(m),'--r');
|
||||
title(title_name(m));
|
||||
set(gca,'YScale','log');
|
||||
legend("第一组线路","第二组线路","第三组线路","第四组线路","第五组线路",'Location','northwest');
|
||||
end
|
||||
if(obj.rpt_num == 1)
|
||||
if(save == "save")
|
||||
savefig("单周期误差分析")
|
||||
end
|
||||
else
|
||||
if(save == "save")
|
||||
savefig("多周期误差分析")
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
%compare FIL with python script
|
||||
function diff_plot_py(obj,fs,iir_out, Script_out,title1,title2,a,amp,edge,fileID)
|
||||
|
||||
%输入数据长度不等时取其公共部分
|
||||
N = min(length(iir_out),length(Script_out));
|
||||
iir_out = iir_out(1:N);
|
||||
Script_out = Script_out(1:N);
|
||||
|
||||
diff = (iir_out - Script_out)/amp;%求差，并归一化
|
||||
|
||||
n = (0:1:N-1)/fs;
|
||||
%找出关心的数据点
|
||||
if(obj.rpt_num == 1)
|
||||
n_edge = find(n>=edge-1e-12);%edge代表下降沿
|
||||
n50 = find(n>=edge+20e-9-1e-12);%下降沿后20ns
|
||||
n20_40 = find((n>=edge+20e-9-1e-12) & (n<=edge+40e-9+1e-12));%下降沿后20ns到40ns
|
||||
n1000 = find(n>=edge+1000e-9-1e-12);%下降沿后1us
|
||||
n1000_1100 = find((n>=edge+1000e-9-1e-12) & (n<=edge+1100e-9+1e-12));%下降沿后1us到1.1us
|
||||
|
||||
ne = find((abs(diff)>=1e-4) & (abs(diff)<1));%误差小于万分之一的点
|
||||
ne(1) = 1;
|
||||
|
||||
window_length = 100e-9*fs;
|
||||
diff_mean_window = movmean(diff,window_length);
|
||||
diff_std_window = movstd(diff,window_length);
|
||||
n_mean_window = find((abs(diff_mean_window)>=1e-4) );%100ns窗，误差均值小于万分之一点
|
||||
n_std_window = find((abs(diff_std_window)>=1e-4) ); %100ns窗，误差方差小于万分之一点
|
||||
n_common = max(n_mean_window(end),n_std_window(end));
|
||||
%原始数据作图
|
||||
tiledlayout(2,1)
|
||||
ax1 = nexttile;
|
||||
plot(n,iir_out,n,Script_out)
|
||||
legend('硬件','软件');
|
||||
xlabel('t/s')
|
||||
xlim(a);
|
||||
title(title1,Interpreter="none");
|
||||
grid on
|
||||
hold on
|
||||
|
||||
%差值做图
|
||||
ax2 = nexttile;
|
||||
plot(n,diff)
|
||||
xlabel('t/s')
|
||||
title('diff')
|
||||
grid on
|
||||
hold on
|
||||
xlim(a)
|
||||
title('硬件与脚本的差值',Interpreter="none");
|
||||
linkaxes([ax1,ax2],'x');
|
||||
|
||||
plot_p = @(x)[
|
||||
plot(n(x),diff(x),'r*');
|
||||
text(n(x), diff(x)+diff(x)*0.1, ['(',num2str(n(x)),',',num2str(diff(x)),')'],'color','k');
|
||||
];
|
||||
|
||||
ne(1) = 1;
|
||||
|
||||
% [diff_max,R_mpos] = max(abs(diff));%误差最大值
|
||||
% plot_p(R_mpos);
|
||||
|
||||
if a(2) <= 5e-6
|
||||
plot_p(n_edge(1));%下降沿
|
||||
% plot_p(R_mpos);
|
||||
elseif a(2) == 20e-6
|
||||
plot_p(n50(1)); %下降沿20ns
|
||||
plot_p(n1000(1)); %下降沿1us
|
||||
plot_p(ne(end)); %误差小于万分之一
|
||||
fprintf(fileID,"Falling edge of 20ns~40ns mean :%.4e\t std :%.4e\t",mean(diff(n20_40)),std(diff(n20_40)));
|
||||
fprintf(fileID,"Falling edge of 1us~1.1us mean :%.4e\t std :%.4e\t",mean(diff(n1000_1100)),std(diff(n1000_1100)));
|
||||
% fprintf("The error after falling edge of 1us is:%.4e\t",diff(n1000(1)));
|
||||
% fprintf("The time of erroe less than 1e-4 is :%.4e us\n",(n(ne(end))-n(n_edge(1))));
|
||||
fprintf(fileID,"The mean and std stably less than 1e-4 is :%.4e s\n",(n(n_common)-n(n_edge(1))));
|
||||
end
|
||||
else
|
||||
n_start = find(n>=edge-1e-12);%edge代表下降沿
|
||||
|
||||
% 确定周期长度对应的采样点数量
|
||||
T = a; %在这种情况下，a这个参数用不到了，使用其传递周期，也就是说a这个参数有两种不同的涵义
|
||||
samples_per_period = round(T * fs); % 每个周期采样点数
|
||||
num_periods = obj.rpt_num; % 总周期数
|
||||
period_means = zeros(1, num_periods); % 存储每周期均值
|
||||
|
||||
for i = 1:num_periods
|
||||
% 提取当前周期的起止索引
|
||||
start_idx(i) = n_start(1) + (i - 1) * samples_per_period;
|
||||
end_idx(i) = n_start(1) + i * samples_per_period;
|
||||
|
||||
% 提取当前周期的数据
|
||||
period_data = diff(start_idx(i):end_idx(i));
|
||||
|
||||
% 计算当前周期的均值
|
||||
period_means(i) = mean(period_data);
|
||||
end
|
||||
fprintf(fileID,"每个周期拖尾误差均值的标准差 = %.4e s\n",std(period_means));
|
||||
ax1 = nexttile;
|
||||
plot(n,iir_out,n,Script_out);
|
||||
hold on
|
||||
plot(n(start_idx), Script_out(start_idx), 'r*'); % 标记每个周期的起始点
|
||||
plot(n(end_idx), Script_out(end_idx), 'g*'); % 标记每个周期的起始点
|
||||
legend('硬件','软件');
|
||||
xlabel('t/s');
|
||||
title(title1,Interpreter="none");
|
||||
ax2 = nexttile;
|
||||
hold on
|
||||
plot(n, diff); hold on; % 原始信号
|
||||
plot(n(end_idx), diff(end_idx), 'g*'); % 标记每个周期的起始点
|
||||
xlabel('t/s');
|
||||
ylabel('归一化误差');
|
||||
linkaxes([ax1,ax2],'x');
|
||||
xlim([0,n(end_idx(end)) + 5e-7]);
|
||||
title(title2,Interpreter="none");
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
N = length(dout0{j,i});
|
||||
cs_wave{j,i} = zeros(4*N,1);
|
||||
|
||||
cs_wave{j,i}(1:4:4*N) = dout0{j,i};
|
||||
cs_wave{j,i}(2:4:4*N) = dout1{j,i};
|
||||
cs_wave{j,i}(3:4:4*N) = dout2{j,i};
|
||||
cs_wave{j,i}(4:4:4*N) = dout3{j,i};
|
||||
|
||||
HardwareMeanIntpData{j,i} = cs_wave{j,i};%硬件校正后内插
|
||||
DownsamplingBy12GData{j,i} = wave_revised{j,i}(1:Ideal2Target:end);
|
||||
[DownsamplingBy12GDataAlign{j,i},HardwareMeanIntpDataAlign{j,i},Delay(j,i)] = ...
|
||||
alignsignals(DownsamplingBy12GData{j,i}(1:round(TargetFrequency*20e-6)),HardwareMeanIntpData{j,i}(1:round(TargetFrequency*20e-6)),"Method","xcorr");
|
||||
end
|
||||
end
|
||||
% signalAnalyzer(DownsamplingBy12GDataAlign{1},HardwareMeanIntpDataAlign{1},'SampleRate',3e9);
|
||||
%% 绘图并保存
|
||||
close all;
|
||||
|
||||
Amp = 1.5e4;
|
||||
FallingEdge = [
|
||||
% 150e-9,4050e-9,...%矩形波
|
||||
30e-9,30e-9,50e-9,1000e-9,10000e-9,...%flattop
|
||||
30e-9,50e-9%acz
|
||||
];
|
||||
|
||||
name = [
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
|
||||
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
|
||||
"第一组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
|
||||
"第一组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
|
||||
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
|
||||
"第二组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
|
||||
"第二组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
|
||||
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
|
||||
"第三组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
|
||||
"第三组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
|
||||
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
|
||||
"第四组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
|
||||
"第四组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后10ns",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后10ns",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后10ns",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后10ns",...
|
||||
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后10ns",...
|
||||
"第五组S21参数_acz_持续时间30ns_下降沿后10ns.fig",...
|
||||
"第五组S21参数_acz_持续时间50ns_下降沿后10ns.fig";
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
|
||||
"第一组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
|
||||
"第一组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
|
||||
"第一组S21参数_acz_持续时间50ns_下降沿后1us.fig";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
|
||||
"第二组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
|
||||
"第二组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
|
||||
"第二组S21参数_acz_持续时间50ns_下降沿后1us.fig";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
|
||||
"第三组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
|
||||
"第三组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
|
||||
"第三组S21参数_acz_持续时间50ns_下降沿后1us.fig";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
|
||||
"第四组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
|
||||
"第四组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
|
||||
"第四组S21参数_acz_持续时间50ns_下降沿后1us.fig";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_下降沿后1us",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_下降沿后1us",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_下降沿后1us",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间1000ns_下降沿后1us",...
|
||||
"第五组S21参数_flattop_上升沿100ns_持续时间10000ns_下降沿后1us",...
|
||||
"第五组S21参数_acz_持续时间30ns_下降沿后1us.fig",...
|
||||
"第五组S21参数_acz_持续时间50ns_下降沿后1us.fig";
|
||||
];
|
||||
|
||||
Delay_mode = mode(Delay,'all');
|
||||
fileID = fopen('20241223_output.txt', 'w');
|
||||
if fileID == -1
|
||||
disp('文件打开失败');
|
||||
else
|
||||
|
||||
end
|
||||
|
||||
for j = 1:route_num
|
||||
for i = 1:env_num
|
||||
start_time(i) = abs(Delay_mode)/(TargetFrequency/1e9)*1e-9;%由于相位修正后会有偏移的点数，所以需要考虑上这个偏移的时间，采样率为3GHz，3个点对应1ns
|
||||
edge_Align(i) = FallingEdge(i) + start_time(i);
|
||||
tmp(i) = edge_Align(i) + 10e-9;
|
||||
a{i} = [start_time(i)-5e-9 tmp(i)];%[1/fs_H 50e-9];[50e-9 1.5e-6],[500e-9+10e-9 tmp-20e-9]
|
||||
b{i} = [tmp(i) 20e-6];
|
||||
fig1 = figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
|
||||
diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',a{i},Amp,edge_Align(i),fileID);
|
||||
title(name(i,1),Interpreter="none");
|
||||
savefig(name(j,i));
|
||||
fig2 = figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]);
|
||||
diff_plot_py(TargetFrequency,HardwareMeanIntpDataAlign{j,i}', DownsamplingBy12GDataAlign{j,i}(1:floor(TargetFrequency*20e-6)),'HardwareRevised','ScriptRevised',b{i},Amp,edge_Align(i),fileID);
|
||||
title(name(i,2),Interpreter="none");
|
||||
savefig(name(j+5,i));
|
||||
end
|
||||
end
|
||||
fclose(fileID);
|
||||
%% 可视化S21参数
|
||||
t = 0:1/(1e2):10000;
|
||||
|
||||
for i = 1:1:length(amp_routing)
|
||||
S21_time(:,i) = amp_routing(i)*exp(time_routing(i)*t);
|
||||
end
|
||||
|
||||
figure
|
||||
plot(t*1e-9,real(sum(S21_time,2)));
|
||||
grid on
|
||||
title("s(t)");
|
||||
% savefig("S21参数");
|
||||
|
||||
% signalAnalyzer(real(sum(S21_time,2)),'SampleRate',1e11);%时间是1ns，还得加上采样率
|
||||
|
||||
% rmpath(genpath('D:\Work\EnvData'));
|
||||
% rmpath(genpath('D:\Work\EnvData\data-v2'));
|
||||
% rmpath(genpath('D:\Work\TailCorr_20241008_NoGit'));
|
||||
%% 图像可视化
|
||||
cd("D:\Work\TailCorr\仿真结果\20241101_125M八倍内插至1G_第1组S21参数")
|
||||
for i = 1:8
|
||||
close all
|
||||
open(name(i,1));
|
||||
open(name(i,2));
|
||||
pause()
|
||||
end
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
clc;clear;close all
|
||||
% hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','D:\SoftWare\Xilinx\Vivado\2019.2\bin\vivado.bat');
|
||||
|
||||
fs_L = 0.75e9; %硬件频率
|
||||
fs_H = 12e9; %以高频近似理想信号
|
||||
TargetFrequency = 3e9;
|
||||
simulink_time = 20e-6; %1.5*16e-6;1.5e-3
|
||||
intp_mode = 3; %0不内插，1内插2倍，2内插4倍,3内插8倍
|
||||
route_num = 1; %线路个数
|
||||
env_num = 1; %包络个数
|
||||
alpha_wideth=32; %滤波器系数定点化
|
||||
beta_width=32;
|
||||
G = 1;
|
||||
dac_mode_sel = 0; %选择DAC模式，0出八路，1邻近插值，2邻近插值
|
||||
|
||||
z_dsp1 = z_dsp(fs_L,fs_H,TargetFrequency,G,simulink_time,intp_mode,dac_mode_sel);
|
||||
z_dsp1.filename = 'output.txt';
|
||||
z_dsp1.rpt_num = 1;
|
||||
if(z_dsp1.rpt_num > 1)
|
||||
z_dsp1.name = [
|
||||
"第一组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第一组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第一组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第一组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第二组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第二组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第二组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第二组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第三组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第三组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第三组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第三组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第四组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第四组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第四组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第四组S21参数_acz_持续时间50ns_重复100次";
|
||||
"第五组S21参数_flattop_上升沿2ns_持续时间30ns_重复100次",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间30ns_重复100次",...
|
||||
"第五组S21参数_flattop_上升沿4ns_持续时间50ns_重复100次",...
|
||||
"第五组S21参数_acz_持续时间30ns_重复100次",...
|
||||
"第五组S21参数_acz_持续时间50ns_重复100次";
|
||||
];
|
||||
z_dsp1.FallingEdge = [30e-9 30e-9 50e-9 30e-9 50e-9];
|
||||
z_dsp1.itv_time = 30e-9;
|
||||
end
|
||||
z_dsp1.env(); %产生理想z信号
|
||||
z_dsp1.route(); %配置线路参数
|
||||
% z_dsp1.route_num = 1;
|
||||
% z_dsp1.env_num = 1;
|
||||
z_dsp1.py_cal(); %12G采样率，基于python脚本计算校正后的波形
|
||||
z_dsp1.FIL(); %调用FIL模块计算校正后的波形
|
||||
z_dsp1.DataShow("save"); %计算结束后展示波形，有save时保存图片
|
||||
%%
|
||||
z_dsp1.FigDisplay(); %图片播放
|
||||
%%
|
||||
z_dsp1.RouteShow("save"); %可视化线路参数
|
||||
%%
|
||||
z_dsp1.ErrAny("save") %对关心的指标进行可视化处理
|
||||
%%
|
||||
close all
|
||||
z_dsp1.pause_time = 0.3;
|
||||
z_dsp1.LoadFigAndDisplay()
|
||||
19
sim/Makefile
19
sim/Makefile
|
|
@ -1,19 +0,0 @@
|
|||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
|
||||
SIMV = ./simv -l sim.log
|
||||
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -f files.f -top TB -nologo &
|
||||
file:
|
||||
find ../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
ifdef seed
|
||||
vcs_run_opts += +ntb_random_seed=${seed}
|
||||
else
|
||||
vcs_run_opts += +ntb_random_seed_automatic
|
||||
endif
|
||||
|
||||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
|
||||
file:
|
||||
find ../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
../../rtl/z_dsp/mult_C.v
|
||||
../../rtl/z_dsp/FixRound.v
|
||||
../../rtl/z_dsp/TailCorr_top.v
|
||||
../../rtl/z_dsp/IIR_top.v
|
||||
../../rtl/z_dsp/diff_p.v
|
||||
../../rtl/z_dsp/s2p_2.v
|
||||
../../rtl/z_dsp/IIR_Filter_p8.v
|
||||
../../rtl/model/DW02_mult.v
|
||||
|
||||
tb_TailCorr_en.v
|
||||
|
||||
|
|
@ -0,0 +1,601 @@
|
|||
module TB();
|
||||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : tb_TailCorr_en.v
|
||||
// Department : HFNL
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 2025-03-03 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
reg [1 :0] source_mode;
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
$fsdbDumpMDA();
|
||||
// $srandom(417492050);
|
||||
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
|
||||
end
|
||||
|
||||
|
||||
reg rstn;
|
||||
reg [31:0] a_re0;
|
||||
reg [31:0] a_im0;
|
||||
reg [31:0] ab_re0;
|
||||
reg [31:0] ab_im0;
|
||||
reg [31:0] abb_re0;
|
||||
reg [31:0] abb_im0;
|
||||
reg [31:0] ab_pow3_re0;
|
||||
reg [31:0] ab_pow3_im0;
|
||||
reg [31:0] ab_pow4_re0;
|
||||
reg [31:0] ab_pow4_im0;
|
||||
reg [31:0] ab_pow5_re0;
|
||||
reg [31:0] ab_pow5_im0;
|
||||
reg [31:0] ab_pow6_re0;
|
||||
reg [31:0] ab_pow6_im0;
|
||||
reg [31:0] ab_pow7_re0;
|
||||
reg [31:0] ab_pow7_im0;
|
||||
reg [31:0] b_pow8_re0;
|
||||
reg [31:0] b_pow8_im0;
|
||||
reg [31:0] a_re1;
|
||||
reg [31:0] a_im1;
|
||||
reg [31:0] ab_re1;
|
||||
reg [31:0] ab_im1;
|
||||
reg [31:0] abb_re1;
|
||||
reg [31:0] abb_im1;
|
||||
reg [31:0] ab_pow3_re1;
|
||||
reg [31:0] ab_pow3_im1;
|
||||
reg [31:0] ab_pow4_re1;
|
||||
reg [31:0] ab_pow4_im1;
|
||||
reg [31:0] ab_pow5_re1;
|
||||
reg [31:0] ab_pow5_im1;
|
||||
reg [31:0] ab_pow6_re1;
|
||||
reg [31:0] ab_pow6_im1;
|
||||
reg [31:0] ab_pow7_re1;
|
||||
reg [31:0] ab_pow7_im1;
|
||||
reg [31:0] b_pow8_re1;
|
||||
reg [31:0] b_pow8_im1;
|
||||
reg [31:0] a_re2;
|
||||
reg [31:0] a_im2;
|
||||
reg [31:0] ab_re2;
|
||||
reg [31:0] ab_im2;
|
||||
reg [31:0] abb_re2;
|
||||
reg [31:0] abb_im2;
|
||||
reg [31:0] ab_pow3_re2;
|
||||
reg [31:0] ab_pow3_im2;
|
||||
reg [31:0] ab_pow4_re2;
|
||||
reg [31:0] ab_pow4_im2;
|
||||
reg [31:0] ab_pow5_re2;
|
||||
reg [31:0] ab_pow5_im2;
|
||||
reg [31:0] ab_pow6_re2;
|
||||
reg [31:0] ab_pow6_im2;
|
||||
reg [31:0] ab_pow7_re2;
|
||||
reg [31:0] ab_pow7_im2;
|
||||
reg [31:0] b_pow8_re2;
|
||||
reg [31:0] b_pow8_im2;
|
||||
reg [31:0] a_re3;
|
||||
reg [31:0] a_im3;
|
||||
reg [31:0] ab_re3;
|
||||
reg [31:0] ab_im3;
|
||||
reg [31:0] abb_re3;
|
||||
reg [31:0] abb_im3;
|
||||
reg [31:0] ab_pow3_re3;
|
||||
reg [31:0] ab_pow3_im3;
|
||||
reg [31:0] ab_pow4_re3;
|
||||
reg [31:0] ab_pow4_im3;
|
||||
reg [31:0] ab_pow5_re3;
|
||||
reg [31:0] ab_pow5_im3;
|
||||
reg [31:0] ab_pow6_re3;
|
||||
reg [31:0] ab_pow6_im3;
|
||||
reg [31:0] ab_pow7_re3;
|
||||
reg [31:0] ab_pow7_im3;
|
||||
reg [31:0] b_pow8_re3;
|
||||
reg [31:0] b_pow8_im3;
|
||||
reg [31:0] a_re4;
|
||||
reg [31:0] a_im4;
|
||||
reg [31:0] ab_re4;
|
||||
reg [31:0] ab_im4;
|
||||
reg [31:0] abb_re4;
|
||||
reg [31:0] abb_im4;
|
||||
reg [31:0] ab_pow3_re4;
|
||||
reg [31:0] ab_pow3_im4;
|
||||
reg [31:0] ab_pow4_re4;
|
||||
reg [31:0] ab_pow4_im4;
|
||||
reg [31:0] ab_pow5_re4;
|
||||
reg [31:0] ab_pow5_im4;
|
||||
reg [31:0] ab_pow6_re4;
|
||||
reg [31:0] ab_pow6_im4;
|
||||
reg [31:0] ab_pow7_re4;
|
||||
reg [31:0] ab_pow7_im4;
|
||||
reg [31:0] b_pow8_re4;
|
||||
reg [31:0] b_pow8_im4;
|
||||
reg [31:0] a_re5;
|
||||
reg [31:0] a_im5;
|
||||
reg [31:0] ab_re5;
|
||||
reg [31:0] ab_im5;
|
||||
reg [31:0] abb_re5;
|
||||
reg [31:0] abb_im5;
|
||||
reg [31:0] ab_pow3_re5;
|
||||
reg [31:0] ab_pow3_im5;
|
||||
reg [31:0] ab_pow4_re5;
|
||||
reg [31:0] ab_pow4_im5;
|
||||
reg [31:0] ab_pow5_re5;
|
||||
reg [31:0] ab_pow5_im5;
|
||||
reg [31:0] ab_pow6_re5;
|
||||
reg [31:0] ab_pow6_im5;
|
||||
reg [31:0] ab_pow7_re5;
|
||||
reg [31:0] ab_pow7_im5;
|
||||
reg [31:0] b_pow8_re5;
|
||||
reg [31:0] b_pow8_im5;
|
||||
|
||||
|
||||
|
||||
reg [15:0] din_rect;
|
||||
|
||||
|
||||
reg clk;
|
||||
|
||||
initial
|
||||
begin
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
|
||||
a_re0 = 32'd55007237;
|
||||
a_re1 = 32'd32690030;
|
||||
a_re2 = 32'd429516;
|
||||
a_re3 = 32'd0;
|
||||
a_re4 = 32'd0;
|
||||
a_re5 = 32'd0;
|
||||
a_im0 = 32'd0;
|
||||
a_im1 = 32'd0;
|
||||
a_im2 = 32'd0;
|
||||
a_im3 = 32'd0;
|
||||
a_im4 = 32'd0;
|
||||
a_im5 = 32'd0;
|
||||
ab_re0 = 32'd54894517;
|
||||
ab_re1 = 32'd32664510;
|
||||
ab_re2 = 32'd429381 ;
|
||||
ab_re3 = 32'd0;
|
||||
ab_re4 = 32'd0;
|
||||
ab_re5 = 32'd0;
|
||||
ab_im0 = 32'd0;
|
||||
ab_im1 = 32'd0;
|
||||
ab_im2 = 32'd0;
|
||||
ab_im3 = 32'd0;
|
||||
ab_im4 = 32'd0;
|
||||
ab_im5 = 32'd0;
|
||||
abb_re0 = 32'd54782028;
|
||||
abb_re1 = 32'd32639011;
|
||||
abb_re2 = 32'd429247 ;
|
||||
abb_re3 = 32'd0;
|
||||
abb_re4 = 32'd0;
|
||||
abb_re5 = 32'd0;
|
||||
abb_im0 = 32'd0;
|
||||
abb_im1 = 32'd0;
|
||||
abb_im2 = 32'd0;
|
||||
abb_im3 = 32'd0;
|
||||
abb_im4 = 32'd0;
|
||||
abb_im5 = 32'd0;
|
||||
ab_pow3_re0 = 32'd54669770;
|
||||
ab_pow3_re1 = 32'd32613532;
|
||||
ab_pow3_re2 = 32'd429113 ;
|
||||
ab_pow3_re3 = 32'd0;
|
||||
ab_pow3_re4 = 32'd0;
|
||||
ab_pow3_re5 = 32'd0;
|
||||
ab_pow3_im0 = 32'd0;
|
||||
ab_pow3_im1 = 32'd0;
|
||||
ab_pow3_im2 = 32'd0;
|
||||
ab_pow3_im3 = 32'd0;
|
||||
ab_pow3_im4 = 32'd0;
|
||||
ab_pow3_im5 = 32'd0;
|
||||
ab_pow4_re0 = 32'd54557742;
|
||||
ab_pow4_re1 = 32'd32588072;
|
||||
ab_pow4_re2 = 32'd428979 ;
|
||||
ab_pow4_re3 = 32'd0;
|
||||
ab_pow4_re4 = 32'd0;
|
||||
ab_pow4_re5 = 32'd0;
|
||||
ab_pow4_im0 = 32'd0;
|
||||
ab_pow4_im1 = 32'd0;
|
||||
ab_pow4_im2 = 32'd0;
|
||||
ab_pow4_im3 = 32'd0;
|
||||
ab_pow4_im4 = 32'd0;
|
||||
ab_pow4_im5 = 32'd0;
|
||||
ab_pow5_re0 = 32'd54445943;
|
||||
ab_pow5_re1 = 32'd32562633;
|
||||
ab_pow5_re2 = 32'd428845 ;
|
||||
ab_pow5_re3 = 32'd0;
|
||||
ab_pow5_re4 = 32'd0;
|
||||
ab_pow5_re5 = 32'd0;
|
||||
ab_pow5_im0 = 32'd0;
|
||||
ab_pow5_im1 = 32'd0;
|
||||
ab_pow5_im2 = 32'd0;
|
||||
ab_pow5_im3 = 32'd0;
|
||||
ab_pow5_im4 = 32'd0;
|
||||
ab_pow5_im5 = 32'd0;
|
||||
ab_pow6_re0 = 32'd54334374;
|
||||
ab_pow6_re1 = 32'd32537213;
|
||||
ab_pow6_re2 = 32'd428711 ;
|
||||
ab_pow6_re3 = 32'd0;
|
||||
ab_pow6_re4 = 32'd0;
|
||||
ab_pow6_re5 = 32'd0;
|
||||
ab_pow6_im0 = 32'd0;
|
||||
ab_pow6_im1 = 32'd0;
|
||||
ab_pow6_im2 = 32'd0;
|
||||
ab_pow6_im3 = 32'd0;
|
||||
ab_pow6_im4 = 32'd0;
|
||||
ab_pow6_im5 = 32'd0;
|
||||
ab_pow7_re0 = 32'd54223033;
|
||||
ab_pow7_re1 = 32'd32511813;
|
||||
ab_pow7_re2 = 32'd428577 ;
|
||||
ab_pow7_re3 = 32'd0;
|
||||
ab_pow7_re4 = 32'd0;
|
||||
ab_pow7_re5 = 32'd0;
|
||||
ab_pow7_im0 = 32'd0;
|
||||
ab_pow7_im1 = 32'd0;
|
||||
ab_pow7_im2 = 32'd0;
|
||||
ab_pow7_im3 = 32'd0;
|
||||
ab_pow7_im4 = 32'd0;
|
||||
ab_pow7_im5 = 32'd0;
|
||||
|
||||
b_pow8_re0 = 32'd2112530470;
|
||||
b_pow8_re1 = 32'd2134108939;
|
||||
b_pow8_re2 = 32'd2142120573;
|
||||
b_pow8_re3 = 32'd0;
|
||||
b_pow8_re4 = 32'd0;
|
||||
b_pow8_re5 = 32'd0;
|
||||
b_pow8_im0 = 32'd0;
|
||||
b_pow8_im1 = 32'd0;
|
||||
b_pow8_im2 = 32'd0;
|
||||
b_pow8_im3 = 32'd0;
|
||||
b_pow8_im4 = 32'd0;
|
||||
b_pow8_im5 = 32'd0;
|
||||
|
||||
din_rect = 16'd0;
|
||||
|
||||
#300;
|
||||
rstn = 1'b1;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
reg [21:0] cnt;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
wire vldi;
|
||||
assign vldi = cnt >= 100 && cnt <=10100;
|
||||
|
||||
reg vldi_r1;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
vldi_r1 <= 1'b0;
|
||||
else
|
||||
begin
|
||||
vldi_r1 <= vldi;
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
din_rect <= 22'd0;
|
||||
else if(vldi)
|
||||
begin
|
||||
din_rect <= 16'd30000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_rect <= 16'd0;
|
||||
end
|
||||
|
||||
reg signed [15:0] random_in [0:3];
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= 16'd0;
|
||||
end
|
||||
end
|
||||
else if (vldi) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= $urandom % 30000;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= 16'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
integer file[3:0];
|
||||
reg [15:0] data[3:0];
|
||||
integer status[3:0];
|
||||
reg [15:0] reg_array[3:0];
|
||||
|
||||
initial begin
|
||||
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
file[i] = $fopen(filenames[i], "r");
|
||||
if (file[i] == 0) begin
|
||||
$display("Failed to open file: %s", filenames[i]);
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [0:0] vldi_matlab [3:0];
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
reg_array[i] <= 16'd0;
|
||||
vldi_matlab[i] <= 16'd0;
|
||||
end
|
||||
end else begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
status[i] = $fscanf(file[i], "%d\n", data[i]);
|
||||
vldi_matlab[i] <= 16'd0;
|
||||
if (status[i] == 1 ) begin
|
||||
reg_array[i] <= data[i];
|
||||
vldi_matlab[i] <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
reg_array[i] <= 16'd0;
|
||||
vldi_matlab[i] <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
reg signed [15:0] iir_in[3:0];
|
||||
|
||||
always @(*)
|
||||
case(source_mode)
|
||||
2'b01 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = din_rect;
|
||||
end
|
||||
end
|
||||
2'b10 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = random_in[i];
|
||||
end
|
||||
end
|
||||
2'b11 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = reg_array[i];
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
assign intp_mode = 2'b10;
|
||||
|
||||
wire [1:0] dac_mode_sel;
|
||||
assign dac_mode_sel = 2'b00;
|
||||
|
||||
wire tc_bypass;
|
||||
wire vldo;
|
||||
|
||||
assign tc_bypass = 1'b0;
|
||||
|
||||
reg en;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
en <= 0;
|
||||
end
|
||||
else begin
|
||||
en <= ~en;
|
||||
end
|
||||
end
|
||||
wire signed [15:0] dout_p[7:0];
|
||||
|
||||
|
||||
TailCorr_top inst_TailCorr_top
|
||||
(
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
.rstn (rstn ),
|
||||
.vldi (vldi_matlab[0] ),
|
||||
// .dac_mode_sel (dac_mode_sel ),
|
||||
// .intp_mode (intp_mode ),
|
||||
.din0 (iir_in[0]),
|
||||
.din1 (iir_in[1]),
|
||||
.din2 (iir_in[2]),
|
||||
.din3 (iir_in[3]),
|
||||
.a_re0 (a_re0),
|
||||
.a_im0 (a_im0),
|
||||
.ab_re0 (ab_re0),
|
||||
.ab_im0 (ab_im0),
|
||||
.abb_re0 (abb_re0),
|
||||
.abb_im0 (abb_im0),
|
||||
.ab_pow3_re0 (ab_pow3_re0),
|
||||
.ab_pow3_im0 (ab_pow3_im0),
|
||||
.ab_pow4_re0 (ab_pow4_re0),
|
||||
.ab_pow4_im0 (ab_pow4_im0),
|
||||
.ab_pow5_re0 (ab_pow5_re0),
|
||||
.ab_pow5_im0 (ab_pow5_im0),
|
||||
.ab_pow6_re0 (ab_pow6_re0),
|
||||
.ab_pow6_im0 (ab_pow6_im0),
|
||||
.ab_pow7_re0 (ab_pow7_re0),
|
||||
.ab_pow7_im0 (ab_pow7_im0),
|
||||
.b_pow8_re0 (b_pow8_re0),
|
||||
.b_pow8_im0 (b_pow8_im0),
|
||||
.a_re1 (a_re1),
|
||||
.a_im1 (a_im1),
|
||||
.ab_re1 (ab_re1),
|
||||
.ab_im1 (ab_im1),
|
||||
.abb_re1 (abb_re1),
|
||||
.abb_im1 (abb_im1),
|
||||
.ab_pow3_re1 (ab_pow3_re1),
|
||||
.ab_pow3_im1 (ab_pow3_im1),
|
||||
.ab_pow4_re1 (ab_pow4_re1),
|
||||
.ab_pow4_im1 (ab_pow4_im1),
|
||||
.ab_pow5_re1 (ab_pow5_re1),
|
||||
.ab_pow5_im1 (ab_pow5_im1),
|
||||
.ab_pow6_re1 (ab_pow6_re1),
|
||||
.ab_pow6_im1 (ab_pow6_im1),
|
||||
.ab_pow7_re1 (ab_pow7_re1),
|
||||
.ab_pow7_im1 (ab_pow7_im1),
|
||||
.b_pow8_re1 (b_pow8_re1),
|
||||
.b_pow8_im1 (b_pow8_im1),
|
||||
.a_re2 (a_re2),
|
||||
.a_im2 (a_im2),
|
||||
.ab_re2 (ab_re2),
|
||||
.ab_im2 (ab_im2),
|
||||
.abb_re2 (abb_re2),
|
||||
.abb_im2 (abb_im2),
|
||||
.ab_pow3_re2 (ab_pow3_re2),
|
||||
.ab_pow3_im2 (ab_pow3_im2),
|
||||
.ab_pow4_re2 (ab_pow4_re2),
|
||||
.ab_pow4_im2 (ab_pow4_im2),
|
||||
.ab_pow5_re2 (ab_pow5_re2),
|
||||
.ab_pow5_im2 (ab_pow5_im2),
|
||||
.ab_pow6_re2 (ab_pow6_re2),
|
||||
.ab_pow6_im2 (ab_pow6_im2),
|
||||
.ab_pow7_re2 (ab_pow7_re2),
|
||||
.ab_pow7_im2 (ab_pow7_im2),
|
||||
.b_pow8_re2 (b_pow8_re2),
|
||||
.b_pow8_im2 (b_pow8_im2),
|
||||
.a_re3 (a_re3),
|
||||
.a_im3 (a_im3),
|
||||
.ab_re3 (ab_re3),
|
||||
.ab_im3 (ab_im3),
|
||||
.abb_re3 (abb_re3),
|
||||
.abb_im3 (abb_im3),
|
||||
.ab_pow3_re3 (ab_pow3_re3),
|
||||
.ab_pow3_im3 (ab_pow3_im3),
|
||||
.ab_pow4_re3 (ab_pow4_re3),
|
||||
.ab_pow4_im3 (ab_pow4_im3),
|
||||
.ab_pow5_re3 (ab_pow5_re3),
|
||||
.ab_pow5_im3 (ab_pow5_im3),
|
||||
.ab_pow6_re3 (ab_pow6_re3),
|
||||
.ab_pow6_im3 (ab_pow6_im3),
|
||||
.ab_pow7_re3 (ab_pow7_re3),
|
||||
.ab_pow7_im3 (ab_pow7_im3),
|
||||
.b_pow8_re3 (b_pow8_re3),
|
||||
.b_pow8_im3 (b_pow8_im3),
|
||||
.a_re4 (a_re4),
|
||||
.a_im4 (a_im4),
|
||||
.ab_re4 (ab_re4),
|
||||
.ab_im4 (ab_im4),
|
||||
.abb_re4 (abb_re4),
|
||||
.abb_im4 (abb_im4),
|
||||
.ab_pow3_re4 (ab_pow3_re4),
|
||||
.ab_pow3_im4 (ab_pow3_im4),
|
||||
.ab_pow4_re4 (ab_pow4_re4),
|
||||
.ab_pow4_im4 (ab_pow4_im4),
|
||||
.ab_pow5_re4 (ab_pow5_re4),
|
||||
.ab_pow5_im4 (ab_pow5_im4),
|
||||
.ab_pow6_re4 (ab_pow6_re4),
|
||||
.ab_pow6_im4 (ab_pow6_im4),
|
||||
.ab_pow7_re4 (ab_pow7_re4),
|
||||
.ab_pow7_im4 (ab_pow7_im4),
|
||||
.b_pow8_re4 (b_pow8_re4),
|
||||
.b_pow8_im4 (b_pow8_im4),
|
||||
.a_re5 (a_re5),
|
||||
.a_im5 (a_im5),
|
||||
.ab_re5 (ab_re5),
|
||||
.ab_im5 (ab_im5),
|
||||
.abb_re5 (abb_re5),
|
||||
.abb_im5 (abb_im5),
|
||||
.ab_pow3_re5 (ab_pow3_re5),
|
||||
.ab_pow3_im5 (ab_pow3_im5),
|
||||
.ab_pow4_re5 (ab_pow4_re5),
|
||||
.ab_pow4_im5 (ab_pow4_im5),
|
||||
.ab_pow5_re5 (ab_pow5_re5),
|
||||
.ab_pow5_im5 (ab_pow5_im5),
|
||||
.ab_pow6_re5 (ab_pow6_re5),
|
||||
.ab_pow6_im5 (ab_pow6_im5),
|
||||
.ab_pow7_re5 (ab_pow7_re5),
|
||||
.ab_pow7_im5 (ab_pow7_im5),
|
||||
.b_pow8_re5 (b_pow8_re5),
|
||||
.b_pow8_im5 (b_pow8_im5),
|
||||
.dout_p0 (dout_p[0] ),
|
||||
.dout_p1 (dout_p[1] ),
|
||||
.dout_p2 (dout_p[2] ),
|
||||
.dout_p3 (dout_p[3] ),
|
||||
.dout_p4 (dout_p[4] ),
|
||||
.dout_p5 (dout_p[5] ),
|
||||
.dout_p6 (dout_p[6] ),
|
||||
.dout_p7 (dout_p[7] ),
|
||||
|
||||
.vldo (vldo )
|
||||
|
||||
);
|
||||
|
||||
|
||||
integer signed In_fid[0:3];
|
||||
integer signed dout_fid[0:7];
|
||||
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
|
||||
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
In_fid[i] = $fopen(filenames_in[i]);
|
||||
end
|
||||
for (int i = 0; i < 8; i = i + 1) begin
|
||||
dout_fid[i] = $fopen(filenames_dout[i]);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cnt >= 90) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
|
||||
end
|
||||
// for (int i = 0; i < 8; i = i + 1) begin
|
||||
// $fclose(In_fid[i]);
|
||||
// end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (vldo && en) begin
|
||||
for (int i = 0; i < 8; i = i + 1) begin
|
||||
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
|
||||
end
|
||||
// for (int i = 0; i < 8; i = i + 1) begin
|
||||
// $fclose(dout_fid[i]);
|
||||
// end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
25
sim/files.f
25
sim/files.f
|
|
@ -1,25 +0,0 @@
|
|||
|
||||
../rtl/nco/coef_c.v
|
||||
../rtl/nco/pipe_acc_48bit.v
|
||||
../rtl/nco/pipe_add_48bit.v
|
||||
../rtl/nco/p_nco.v
|
||||
../rtl/nco/coef_s.v
|
||||
../rtl/nco/nco.v
|
||||
../rtl/nco/sin_op.v
|
||||
../rtl/nco/ph2amp.v
|
||||
../rtl/nco/cos_op.v
|
||||
|
||||
../rtl/z_dsp/diff.v
|
||||
../rtl/z_dsp_en_Test.v
|
||||
../rtl/z_dsp/TailCorr_top.v
|
||||
../rtl/z_dsp/z_dsp.v
|
||||
../rtl/z_dsp/MeanIntp_8.v
|
||||
../rtl/z_dsp/FixRound.v
|
||||
../rtl/z_dsp/DW_iir_dc_m.v
|
||||
|
||||
../rtl/model/DW02_mult.v
|
||||
../rtl/model/DW_iir_dc.v
|
||||
../tb/clk_gen.v
|
||||
../tb/DW_mult_pipe.v
|
||||
../tb/tb_z_dsp.v
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +fsdb+delta
|
||||
SIMV = ./simv -l sim.log +fsdb+delta
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
|
||||
file:
|
||||
find ../../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
../../rtl/z_dsp/s2p_2.v
|
||||
tb_s2p_2.v
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
|
||||
reg clk;
|
||||
reg rst_n;
|
||||
reg [15:0] din;
|
||||
reg enable;
|
||||
reg [21:0] cnt;
|
||||
wire [15:0] dout0;
|
||||
wire [15:0] dout1;
|
||||
|
||||
|
||||
s2p_2 uut (
|
||||
.clk (clk),
|
||||
.rst_n (rst_n),
|
||||
.din (din),
|
||||
.en (enable),
|
||||
.dout0 (dout0),
|
||||
.dout1 (dout1)
|
||||
);
|
||||
|
||||
reg[15:0] din_r1;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
din_r1 <= 0;
|
||||
end
|
||||
else begin
|
||||
din_r1 <= din;
|
||||
end
|
||||
end
|
||||
|
||||
wire signed [15:0] diff;
|
||||
assign diff = din - din_r1;
|
||||
|
||||
reg[15:0] dout1_r1;
|
||||
reg[15:0] dout1_r2;
|
||||
always @(posedge clk or negedge rst_n)begin
|
||||
if(rst_n==1'b0)begin
|
||||
dout1_r1 <= 0;
|
||||
dout1_r2 <= 0;
|
||||
end
|
||||
else begin
|
||||
dout1_r1 <= dout1;
|
||||
dout1_r2 <= dout1_r1;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
wire signed [15:0] diff12;
|
||||
wire signed [15:0] diff23;
|
||||
assign diff12 = dout0 - dout1_r2;
|
||||
assign diff23 = dout1 - dout0;
|
||||
|
||||
initial begin
|
||||
rst_n = 0;
|
||||
enable = 0;
|
||||
clk = 1'b0;
|
||||
din = 16'h0000;
|
||||
|
||||
|
||||
#20;
|
||||
rst_n = 1;
|
||||
|
||||
|
||||
#10;
|
||||
|
||||
end
|
||||
|
||||
|
||||
always #5 clk = ~clk;
|
||||
|
||||
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (rst_n == 1'b0) begin
|
||||
cnt <= 22'd0;
|
||||
end else begin
|
||||
cnt <= cnt + 22'd1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [15:0] enable_cnt;
|
||||
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (rst_n == 1'b0) begin
|
||||
enable <= 0;
|
||||
din <= 16'd0;
|
||||
enable_cnt <= 0;
|
||||
end else begin
|
||||
|
||||
if (cnt < 1000) begin
|
||||
if (enable_cnt == 0) begin
|
||||
if ($urandom % 2 == 0) begin
|
||||
enable <= 1;
|
||||
enable_cnt <= $urandom % 10 + 5;
|
||||
din <= $urandom;
|
||||
end else begin
|
||||
enable <= 0;
|
||||
din <= 16'd0;
|
||||
end
|
||||
end else begin
|
||||
|
||||
enable <= 1;
|
||||
enable_cnt <= enable_cnt - 1;
|
||||
din <= $urandom;
|
||||
end
|
||||
end else begin
|
||||
enable <= 0;
|
||||
din <= 16'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
initial begin
|
||||
wait(cnt[11] == 1);
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
ifdef seed
|
||||
vcs_run_opts += +ntb_random_seed=${seed}
|
||||
else
|
||||
vcs_run_opts += +ntb_random_seed_automatic
|
||||
endif
|
||||
|
||||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
|
||||
file:
|
||||
find ../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
../../rtl/z_dsp/CoefGen.v
|
||||
../../rtl/z_dsp/FixRound.v
|
||||
../../rtl/z_dsp/mult_C.v
|
||||
../../rtl/model/DW02_mult.v
|
||||
tb_CoefGen.v
|
||||
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
|
||||
`timescale 1 ns/1 ns
|
||||
|
||||
module TB();
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
$fsdbDumpMDA();
|
||||
end
|
||||
|
||||
|
||||
|
||||
reg clk ;
|
||||
reg en;
|
||||
reg [5:0] vldi;
|
||||
reg rst_n;
|
||||
|
||||
|
||||
reg signed [31:0] a_re [5:0];
|
||||
reg signed [31:0] a_im [5:0];
|
||||
reg signed [31:0] b_re [5:0];
|
||||
reg signed [31:0] b_im [5:0];
|
||||
|
||||
|
||||
wire signed [31:0] ao_re [5:0];
|
||||
wire signed [31:0] ao_im [5:0];
|
||||
wire signed [31:0] ab_re [5:0];
|
||||
wire signed [31:0] ab_im [5:0];
|
||||
wire signed [31:0] abb_re [5:0];
|
||||
wire signed [31:0] abb_im [5:0];
|
||||
wire signed [31:0] ab_pow3_re [5:0];
|
||||
wire signed [31:0] ab_pow3_im [5:0];
|
||||
wire signed [31:0] ab_pow4_re [5:0];
|
||||
wire signed [31:0] ab_pow4_im [5:0];
|
||||
wire signed [31:0] ab_pow5_re [5:0];
|
||||
wire signed [31:0] ab_pow5_im [5:0];
|
||||
wire signed [31:0] ab_pow6_re [5:0];
|
||||
wire signed [31:0] ab_pow6_im [5:0];
|
||||
wire signed [31:0] ab_pow7_re [5:0];
|
||||
wire signed [31:0] ab_pow7_im [5:0];
|
||||
wire signed [31:0] b_pow8_re [5:0];
|
||||
wire signed [31:0] b_pow8_im [5:0];
|
||||
|
||||
|
||||
parameter CYCLE = 20;
|
||||
|
||||
|
||||
parameter RST_TIME = 3 ;
|
||||
|
||||
|
||||
CoefGen uut(
|
||||
.clk (clk ),
|
||||
.rstn (rst_n ),
|
||||
.vldi (vldi ),
|
||||
.a_re (a_re ),
|
||||
.a_im (a_im ),
|
||||
.b_re (b_re ),
|
||||
.b_im (b_im ),
|
||||
.ao_re (ao_re ),
|
||||
.ao_im (ao_im ),
|
||||
.ab_re (ab_re ),
|
||||
.ab_im (ab_im ),
|
||||
.abb_re (abb_re ),
|
||||
.abb_im (abb_im ),
|
||||
.ab_pow3_re (ab_pow3_re ),
|
||||
.ab_pow3_im (ab_pow3_im ),
|
||||
.ab_pow4_re (ab_pow4_re ),
|
||||
.ab_pow4_im (ab_pow4_im ),
|
||||
.ab_pow5_re (ab_pow5_re ),
|
||||
.ab_pow5_im (ab_pow5_im ),
|
||||
.ab_pow6_re (ab_pow6_re ),
|
||||
.ab_pow6_im (ab_pow6_im ),
|
||||
.ab_pow7_re (ab_pow7_re ),
|
||||
.ab_pow7_im (ab_pow7_im ),
|
||||
.b_pow8_re (b_pow8_re ),
|
||||
.b_pow8_im (b_pow8_im )
|
||||
);
|
||||
|
||||
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever
|
||||
#(CYCLE/2)
|
||||
clk=~clk;
|
||||
end
|
||||
reg [15:0] st1;
|
||||
reg [15:0] st2;
|
||||
reg [15:0] st3;
|
||||
reg [15:0] st4;
|
||||
|
||||
initial begin
|
||||
rst_n = 0;
|
||||
vldi <= 0;
|
||||
st1 = 100;
|
||||
st2 = 101;
|
||||
st3 = 110;
|
||||
st4 = 111;
|
||||
repeat(3) @(posedge clk);
|
||||
vldi[0] <= 1;
|
||||
rst_n = 1;
|
||||
a_re[0] <= 55007237;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 2143083068;
|
||||
b_im[0] <= 0;
|
||||
@(posedge clk);
|
||||
vldi[0] <= 0;
|
||||
a_re[0] <= 0;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 0;
|
||||
b_im[0] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi[1] <= 1;
|
||||
rst_n = 1;
|
||||
a_re[1] <= 32690030;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 2145807236;
|
||||
b_im[1] <= 0;
|
||||
@(posedge clk);
|
||||
vldi[1] <= 0;
|
||||
a_re[1] <= 0;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 0;
|
||||
b_im[1] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi[2] <= 1;
|
||||
rst_n = 1;
|
||||
a_re[2] <= 429516;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 2146812530;
|
||||
b_im[2] <= 0;
|
||||
@(posedge clk);
|
||||
vldi[2] <= 0;
|
||||
a_re[2] <= 0;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 0;
|
||||
b_im[2] <= 0;
|
||||
|
||||
end
|
||||
|
||||
|
||||
reg [21:0] cnt;
|
||||
always@(posedge clk or negedge rst_n)
|
||||
if(!rst_n) begin
|
||||
cnt <= 22'd0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 22'd1;
|
||||
end
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
ifdef seed
|
||||
vcs_run_opts += +ntb_random_seed=${seed}
|
||||
else
|
||||
vcs_run_opts += +ntb_random_seed_automatic
|
||||
endif
|
||||
|
||||
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log
|
||||
SIMV = ./simv $(vcs_run_opts) -l sim.log +fsdb+delta
|
||||
all:comp run
|
||||
|
||||
comp:
|
||||
${VCS} -f files.f
|
||||
|
||||
run:
|
||||
${SIMV}
|
||||
|
||||
dbg:
|
||||
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
|
||||
file:
|
||||
find ../ -name "*.*v" > files.f
|
||||
|
||||
clean:
|
||||
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
../../rtl/z_dsp/z_dsp.sv
|
||||
../../rtl/z_dsp/TailCorr_top.v
|
||||
../../rtl/z_dsp/IIR_top.v
|
||||
../../rtl/z_dsp/IIR_Filter_p8.v
|
||||
../../rtl/z_dsp/CoefGen.sv
|
||||
../../rtl/z_dsp/diff_p.v
|
||||
../../rtl/z_dsp/s2p_2.v
|
||||
../../rtl/z_dsp/FixRound.v
|
||||
../../rtl/z_dsp/mult_C.v
|
||||
../../rtl/z_dsp/mult_x.v
|
||||
../../rtl/z_dsp/syncer.v
|
||||
../../rtl/z_dsp/sirv_gnrl_dffs.v
|
||||
../../rtl/model/DW02_mult.v
|
||||
tb_z_dsp.v
|
||||
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
`timescale 1 ns/1 ns
|
||||
module TB();
|
||||
//+FHDR--------------------------------------------------------------------------------------------------------
|
||||
// Company:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// File Name : tb_TailCorr_en.v
|
||||
// Department : HFNL
|
||||
// Author : thfu
|
||||
// Author's Tel :
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Relese History
|
||||
// Version Date Author Description
|
||||
// 2025-03-03 thfu
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Keywords :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Parameter
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Purpose :
|
||||
//
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
//-----------------------------------------------------------------------------------------------------------------
|
||||
// Reuse Issues
|
||||
// Reset Strategy:
|
||||
// Clock Domains:
|
||||
// Critical Timing:
|
||||
// Asynchronous I/F:
|
||||
// Synthesizable (y/n):
|
||||
// Other:
|
||||
//-FHDR--------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
reg [1 :0] source_mode;
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
$fsdbDumpMDA();
|
||||
// $srandom(417492050);
|
||||
source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
|
||||
end
|
||||
|
||||
reg rstn;
|
||||
|
||||
reg [15:0] din_rect;
|
||||
reg [ 5:0] vldi_coef;
|
||||
reg vldi_data;
|
||||
|
||||
parameter CYCLE = 20;
|
||||
|
||||
reg clk;
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever
|
||||
#(CYCLE/2)
|
||||
clk=~clk;
|
||||
end
|
||||
|
||||
|
||||
reg signed [31:0] a_re [5:0];
|
||||
reg signed [31:0] a_im [5:0];
|
||||
reg signed [31:0] b_re [5:0];
|
||||
reg signed [31:0] b_im [5:0];
|
||||
|
||||
initial begin
|
||||
rstn = 0;
|
||||
vldi_data <= 0;
|
||||
vldi_coef <= 0;
|
||||
din_rect = 16'd0;
|
||||
repeat(3) @(posedge clk);
|
||||
vldi_coef[0] <= 1;
|
||||
rstn = 1;
|
||||
a_re[0] <= 55007237;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 2143083068;
|
||||
b_im[0] <= 0;
|
||||
@(posedge clk);
|
||||
vldi_coef[0] <= 0;
|
||||
a_re[0] <= 0;
|
||||
a_im[0] <= 0;
|
||||
b_re[0] <= 0;
|
||||
b_im[0] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi_coef[1] <= 1;
|
||||
rstn = 1;
|
||||
a_re[1] <= 32690030;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 2145807236;
|
||||
b_im[1] <= 0;
|
||||
@(posedge clk);
|
||||
vldi_coef[1] <= 0;
|
||||
a_re[1] <= 0;
|
||||
a_im[1] <= 0;
|
||||
b_re[1] <= 0;
|
||||
b_im[1] <= 0;
|
||||
repeat(8) @(posedge clk);
|
||||
vldi_coef[2] <= 1;
|
||||
rstn = 1;
|
||||
a_re[2] <= 429516;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 2146812530;
|
||||
b_im[2] <= 0;
|
||||
@(posedge clk);
|
||||
vldi_coef[2] <= 0;
|
||||
a_re[2] <= 0;
|
||||
a_im[2] <= 0;
|
||||
b_re[2] <= 0;
|
||||
b_im[2] <= 0;
|
||||
repeat(108) @(posedge clk);
|
||||
vldi_data <= 1;
|
||||
// repeat(10000) @(posedge clk);
|
||||
// vldi_data <= 0;
|
||||
|
||||
end
|
||||
|
||||
reg [21:0] cnt;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
reg vldi_data_r1;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
vldi_data_r1 <= 1'b0;
|
||||
else
|
||||
begin
|
||||
vldi_data_r1 <= vldi_data;
|
||||
end
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
din_rect <= 22'd0;
|
||||
else if(vldi_data)
|
||||
begin
|
||||
din_rect <= 16'd30000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_rect <= 16'd0;
|
||||
end
|
||||
|
||||
reg signed [15:0] random_in [0:3];
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= 16'd0;
|
||||
end
|
||||
end
|
||||
else if (vldi_data) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= $urandom % 30000;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
random_in[i] <= 16'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
integer file[3:0];
|
||||
reg [15:0] data[3:0];
|
||||
integer status[3:0];
|
||||
reg [15:0] reg_array[3:0];
|
||||
|
||||
initial begin
|
||||
string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
file[i] = $fopen(filenames[i], "r");
|
||||
if (file[i] == 0) begin
|
||||
$display("Failed to open file: %s", filenames[i]);
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
reg_array[i] <= 16'd0;
|
||||
end
|
||||
end else if(vldi_data) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
status[i] = $fscanf(file[i], "%d\n", data[i]);
|
||||
if (status[i] == 1 ) begin
|
||||
reg_array[i] <= data[i];
|
||||
end
|
||||
else begin
|
||||
reg_array[i] <= 16'd0;
|
||||
vldi_data <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
reg signed [15:0] iir_in[3:0];
|
||||
|
||||
always @(*)
|
||||
case(source_mode)
|
||||
2'b01 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = din_rect;
|
||||
end
|
||||
end
|
||||
2'b10 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = random_in[i];
|
||||
end
|
||||
end
|
||||
2'b11 : begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
iir_in[i] = reg_array[i];
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
assign intp_mode = 2'b10;
|
||||
|
||||
wire [1:0] dac_mode_sel;
|
||||
assign dac_mode_sel = 2'b00;
|
||||
|
||||
wire tc_bypass;
|
||||
wire vldo;
|
||||
|
||||
assign tc_bypass = 1'b0;
|
||||
|
||||
reg en;
|
||||
always @(posedge clk or negedge rstn)begin
|
||||
if(rstn==1'b0)begin
|
||||
en <= 1;
|
||||
end
|
||||
else begin
|
||||
en <= ~en;
|
||||
end
|
||||
end
|
||||
wire signed [15:0] dout_p[7:0];
|
||||
|
||||
z_dsp inst_z_dsp(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
// .tc_bypass (tc_bypass ),
|
||||
.vldi_coef (vldi_coef ),
|
||||
.vldi_data (vldi_data_r1 ),
|
||||
// .intp_mode (intp_mode ),
|
||||
// .dac_mode_sel (dac_mode_sel ),
|
||||
.din0 (iir_in[0] ),
|
||||
.din1 (iir_in[1] ),
|
||||
.din2 (iir_in[2] ),
|
||||
.din3 (iir_in[3] ),
|
||||
.a0_re (a_re[0] ),
|
||||
.a0_im (a_im[0] ),
|
||||
.b0_re (b_re[0] ),
|
||||
.b0_im (b_im[0] ),
|
||||
.a1_re (a_re[1] ),
|
||||
.a1_im (a_im[1] ),
|
||||
.b1_re (b_re[1] ),
|
||||
.b1_im (b_im[1] ),
|
||||
.a2_re (a_re[2] ),
|
||||
.a2_im (a_im[2] ),
|
||||
.b2_re (b_re[2] ),
|
||||
.b2_im (b_im[2] ),
|
||||
.a3_re (a_re[3] ),
|
||||
.a3_im (a_im[3] ),
|
||||
.b3_re (b_re[3] ),
|
||||
.b3_im (b_im[3] ),
|
||||
.a4_re (a_re[4] ),
|
||||
.a4_im (a_im[4] ),
|
||||
.b4_re (b_re[4] ),
|
||||
.b4_im (b_im[4] ),
|
||||
.a5_re (a_re[5] ),
|
||||
.a5_im (a_im[5] ),
|
||||
.b5_re (b_re[5] ),
|
||||
.b5_im (b_im[5] ),
|
||||
.dout0 (dout_p[0] ),
|
||||
.dout1 (dout_p[1] ),
|
||||
.dout2 (dout_p[2] ),
|
||||
.dout3 (dout_p[3] ),
|
||||
.vldo ( vldo )
|
||||
);
|
||||
|
||||
|
||||
integer signed In_fid[0:3];
|
||||
integer signed dout_fid[0:7];
|
||||
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
|
||||
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
In_fid[i] = $fopen(filenames_in[i]);
|
||||
end
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
dout_fid[i] = $fopen(filenames_dout[i]);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (vldi_data_r1) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (vldo) begin
|
||||
for (int i = 0; i < 4; i = i + 1) begin
|
||||
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,357 +0,0 @@
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This confidential and proprietary software may be used only
|
||||
// as authorized by a licensing agreement from Synopsys Inc.
|
||||
// In the event of publication, the following notice is applicable:
|
||||
//
|
||||
// (C) COPYRIGHT 2002 - 2018 SYNOPSYS INC.
|
||||
// ALL RIGHTS RESERVED
|
||||
//
|
||||
// The entire notice above must be reproduced on all authorized
|
||||
// copies.
|
||||
//
|
||||
// AUTHOR: Rajeev Huralikoppi Feb 15, 2002
|
||||
//
|
||||
// VERSION: Verilog Simulation Architecture
|
||||
//
|
||||
// DesignWare_version: 4e25d03d
|
||||
// DesignWare_release: O-2018.06-DWBB_201806.3
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//-----------------------------------------------------------------------------
|
||||
// ABSTRACT: An n stage pipelined multipler simulation model
|
||||
//
|
||||
// Parameters Valid Values Description
|
||||
// ========== ========= ===========
|
||||
// a_width >= 1 default: none
|
||||
// Word length of a
|
||||
//
|
||||
// b_width >= 1 default: none
|
||||
// Word length of b
|
||||
//
|
||||
// num_stages >= 2 default: 2
|
||||
// Number of pipelined stages
|
||||
//
|
||||
// stall_mode 0 or 1 default: 1
|
||||
// Stall mode
|
||||
// 0 => non-stallable
|
||||
// 1 => stallable
|
||||
//
|
||||
// rst_mode 0 to 2 default: 1
|
||||
// Reset mode
|
||||
// 0 => no reset
|
||||
// 1 => asynchronous reset
|
||||
// 2 => synchronous reset
|
||||
//
|
||||
// op_iso_mode 0 to 4 default: 0
|
||||
// Type of operand isolation
|
||||
// If 'stall_mode' is '0', this parameter is ignored and no isolation is applied
|
||||
// 0 => Follow intent defined by Power Compiler user setting
|
||||
// 1 => no operand isolation
|
||||
// 2 => 'and' gate operand isolaton
|
||||
// 3 => 'or' gate operand isolation
|
||||
// 4 => preferred isolation style: 'and'
|
||||
//
|
||||
//
|
||||
// Input Ports Size Description
|
||||
// =========== ==== ============
|
||||
// clk 1 Clock
|
||||
// rst_n 1 Reset, active low
|
||||
// en 1 Register enable, active high
|
||||
// tc 1 2's complement control
|
||||
// a a_width Multiplier
|
||||
// b b_width Multiplicand
|
||||
//
|
||||
// product a_width+b_width Product (a*b)
|
||||
//
|
||||
// MODIFIED:
|
||||
// RJK 05/14/15 Updated model to work with less propagated 'X's
|
||||
// so as to be more friendly with VCS-NLP
|
||||
//
|
||||
// RJK 05/28/13 Updated documentation in comments to properly
|
||||
// describe the "en" input (STAR 9000627580)
|
||||
//
|
||||
// DLL 02/01/08 Enhanced abstract and added "op_iso_mode" parameter
|
||||
// and related code.
|
||||
//
|
||||
// DLL 11/14/05 Changed legality checking of 'num_stages'
|
||||
// parameter along with its abstract "Valid Values"
|
||||
//
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
module DW_mult_pipe (clk,rst_n,en,tc,a,b,product);
|
||||
|
||||
parameter integer a_width = 2;
|
||||
parameter integer b_width = 2;
|
||||
parameter integer num_stages = 2;
|
||||
parameter integer stall_mode = 1;
|
||||
parameter integer rst_mode = 1;
|
||||
parameter integer op_iso_mode = 0;
|
||||
|
||||
|
||||
input clk;
|
||||
input rst_n;
|
||||
input [a_width-1 : 0] a;
|
||||
input [b_width-1 : 0] b;
|
||||
input tc;
|
||||
input en;
|
||||
|
||||
output [a_width+b_width-1: 0] product;
|
||||
|
||||
reg [a_width-1 : 0] a_reg [0 : num_stages-2];
|
||||
reg [b_width-1 : 0] b_reg [0 : num_stages-2];
|
||||
reg tc_reg [0 : num_stages-2];
|
||||
|
||||
// synopsys translate_off
|
||||
//---------------------------------------------------------------------------
|
||||
// Behavioral model
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
generate
|
||||
if (rst_mode == 0) begin : GEN_RSM_EQ_0
|
||||
|
||||
if (stall_mode == 0) begin : GEN_RM0_SM0
|
||||
always @(posedge clk) begin: rm0_sm0_pipe_reg_PROC
|
||||
integer i;
|
||||
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= a;
|
||||
b_reg[0] <= b;
|
||||
tc_reg[0] <= tc;
|
||||
end else begin
|
||||
a_reg[i] <= a_reg[i-1];
|
||||
b_reg[i] <= b_reg[i-1];
|
||||
tc_reg[i] <= tc_reg[i-1];
|
||||
end
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end // block: rm0_pipe_reg_PROC
|
||||
end else begin : GEN_RM0_SM1
|
||||
always @(posedge clk) begin: rm0_sm1_pipe_reg_PROC
|
||||
integer i;
|
||||
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
|
||||
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
|
||||
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
|
||||
end else begin
|
||||
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
|
||||
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
|
||||
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end else if (rst_mode == 1) begin : GEN_RM_EQ_1
|
||||
|
||||
if (stall_mode == 0) begin : GEN_RM1_SM0
|
||||
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
|
||||
integer i;
|
||||
|
||||
if (rst_n == 1'b0) begin
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'b0}};
|
||||
b_reg[i] <= {b_width{1'b0}};
|
||||
tc_reg[i] <= 1'b0;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else if (rst_n == 1'b1) begin
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= a;
|
||||
b_reg[0] <= b;
|
||||
tc_reg[0] <= tc;
|
||||
end else begin
|
||||
a_reg[i] <= a_reg[i-1];
|
||||
b_reg[i] <= b_reg[i-1];
|
||||
tc_reg[i] <= tc_reg[i-1];
|
||||
end
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else begin // rst_n not 1'b0 and not 1'b1
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'bx}};
|
||||
b_reg[i] <= {b_width{1'bx}};
|
||||
tc_reg[i] <= 1'bx;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end
|
||||
end // block: rm1_pipe_reg_PROC
|
||||
end else begin : GEN_RM1_SM1
|
||||
always @(posedge clk or negedge rst_n) begin: rm1_pipe_reg_PROC
|
||||
integer i;
|
||||
|
||||
if (rst_n == 1'b0) begin
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'b0}};
|
||||
b_reg[i] <= {b_width{1'b0}};
|
||||
tc_reg[i] <= 1'b0;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else if (rst_n == 1'b1) begin
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
|
||||
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
|
||||
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
|
||||
end else begin
|
||||
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
|
||||
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
|
||||
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
|
||||
end
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else begin // rst_n not 1'b0 and not 1'b1
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'bx}};
|
||||
b_reg[i] <= {b_width{1'bx}};
|
||||
tc_reg[i] <= 1'bx;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end
|
||||
end // block: rm1_pipe_reg_PROC
|
||||
end
|
||||
|
||||
end else begin : GEN_RM_GT_1
|
||||
|
||||
if (stall_mode == 0) begin : GEN_RM2_SM0
|
||||
always @(posedge clk) begin: rm2_pipe_reg_PROC
|
||||
integer i;
|
||||
|
||||
if (rst_n == 1'b0) begin
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'b0}};
|
||||
b_reg[i] <= {b_width{1'b0}};
|
||||
tc_reg[i] <= 1'b0;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else if (rst_n == 1'b1) begin
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= a;
|
||||
b_reg[0] <= b;
|
||||
tc_reg[0] <= tc;
|
||||
end else begin
|
||||
a_reg[i] <= a_reg[i-1];
|
||||
b_reg[i] <= b_reg[i-1];
|
||||
tc_reg[i] <= tc_reg[i-1];
|
||||
end
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else begin // rst_n not 1'b0 and not 1'b1
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'bx}};
|
||||
b_reg[i] <= {b_width{1'bx}};
|
||||
tc_reg[i] <= 1'bx;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end
|
||||
end // block: rm2_pipe_reg_PROC
|
||||
end else begin : GEN_RM2_SM1
|
||||
always @(posedge clk) begin: rm2_pipe_reg_PROC
|
||||
integer i;
|
||||
|
||||
if (rst_n == 1'b0) begin
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'b0}};
|
||||
b_reg[i] <= {b_width{1'b0}};
|
||||
tc_reg[i] <= 1'b0;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else if (rst_n == 1'b1) begin
|
||||
for(i= 0; i < num_stages-1; i=i+1) begin
|
||||
if (i == 0) begin
|
||||
a_reg[0] <= (en == 1'b0)? a_reg[0] : ((en == 1'b1)? a : {a_width{1'bx}});
|
||||
b_reg[0] <= (en == 1'b0)? b_reg[0] : ((en == 1'b1)? b : {b_width{1'bx}});
|
||||
tc_reg[0] <= (en == 1'b0)? tc_reg[0]: ((en == 1'b1)? tc: 1'bx);
|
||||
end else begin
|
||||
a_reg[i] <= (en == 1'b0)? a_reg[i] : ((en == 1'b1)? a_reg[i-1] : {a_width{1'bx}});
|
||||
b_reg[i] <= (en == 1'b0)? b_reg[i] : ((en == 1'b1)? b_reg[i-1] : {b_width{1'bx}});
|
||||
tc_reg[i] <= (en == 1'b0)? tc_reg[i]: ((en == 1'b1)? tc_reg[i-1]: 1'bx);
|
||||
end
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end else begin // rst_n not 1'b0 and not 1'b1
|
||||
for (i= 0; i < num_stages-1; i=i+1) begin
|
||||
a_reg[i] <= {a_width{1'bx}};
|
||||
b_reg[i] <= {b_width{1'bx}};
|
||||
tc_reg[i] <= 1'bx;
|
||||
end // for (i= 0; i < num_stages-1; i++)
|
||||
end
|
||||
end // block: rm2_pipe_reg_PROC
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
DW02_mult #(a_width, b_width)
|
||||
U1 (.A(a_reg[num_stages-2]),
|
||||
.B(b_reg[num_stages-2]),
|
||||
.TC(tc_reg[num_stages-2]),
|
||||
.PRODUCT(product));
|
||||
//---------------------------------------------------------------------------
|
||||
// Parameter legality check and initializations
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
initial begin : parameter_check
|
||||
integer param_err_flg;
|
||||
|
||||
param_err_flg = 0;
|
||||
|
||||
|
||||
if (a_width < 1) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter a_width (lower bound: 1)",
|
||||
a_width );
|
||||
end
|
||||
|
||||
if (b_width < 1) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter b_width (lower bound: 1)",
|
||||
b_width );
|
||||
end
|
||||
|
||||
if (num_stages < 2) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter num_stages (lower bound: 2)",
|
||||
num_stages );
|
||||
end
|
||||
|
||||
if ( (stall_mode < 0) || (stall_mode > 1) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter stall_mode (legal range: 0 to 1)",
|
||||
stall_mode );
|
||||
end
|
||||
|
||||
if ( (rst_mode < 0) || (rst_mode > 2) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter rst_mode (legal range: 0 to 2)",
|
||||
rst_mode );
|
||||
end
|
||||
|
||||
if ( (op_iso_mode < 0) || (op_iso_mode > 4) ) begin
|
||||
param_err_flg = 1;
|
||||
$display(
|
||||
"ERROR: %m :\n Invalid value (%d) for parameter op_iso_mode (legal range: 0 to 4)",
|
||||
op_iso_mode );
|
||||
end
|
||||
|
||||
if ( param_err_flg == 1) begin
|
||||
$display(
|
||||
"%m :\n Simulation aborted due to invalid parameter value(s)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
end // parameter_check
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Report unknown clock inputs
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
always @ (clk) begin : clk_monitor
|
||||
if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
|
||||
$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
|
||||
$time, clk );
|
||||
end // clk_monitor
|
||||
|
||||
// synopsys translate_on
|
||||
endmodule //
|
||||
141
tb/clk_gen.v
141
tb/clk_gen.v
|
|
@ -1,141 +0,0 @@
|
|||
module clk_gen(
|
||||
input rstn,
|
||||
input clk,
|
||||
output clk_div16_0,
|
||||
output clk_div16_1,
|
||||
output clk_div16_2,
|
||||
output clk_div16_3,
|
||||
output clk_div16_4,
|
||||
output clk_div16_5,
|
||||
output clk_div16_6,
|
||||
output clk_div16_7,
|
||||
output clk_div16_8,
|
||||
output clk_div16_9,
|
||||
output clk_div16_a,
|
||||
output clk_div16_b,
|
||||
output clk_div16_c,
|
||||
output clk_div16_d,
|
||||
output clk_div16_e,
|
||||
output clk_div16_f,
|
||||
|
||||
output clk_h,
|
||||
output clk_l
|
||||
);
|
||||
|
||||
reg [3:0] cnt_ini;
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt_ini <= 4'd0;
|
||||
else if(cnt_ini <= 4'd7)
|
||||
cnt_ini <= cnt_ini + 4'd1;
|
||||
else
|
||||
cnt_ini <= cnt_ini;
|
||||
wire div_en;
|
||||
assign div_en = (cnt_ini ==4'd8)? 1'b1:1'b0;
|
||||
|
||||
reg [3:0] cnt_0;
|
||||
reg [3:0] cnt_1;
|
||||
reg [3:0] cnt_2;
|
||||
reg [3:0] cnt_3;
|
||||
reg [3:0] cnt_4;
|
||||
reg [3:0] cnt_5;
|
||||
reg [3:0] cnt_6;
|
||||
reg [3:0] cnt_7;
|
||||
reg [3:0] cnt_8;
|
||||
reg [3:0] cnt_9;
|
||||
reg [3:0] cnt_a;
|
||||
reg [3:0] cnt_b;
|
||||
reg [3:0] cnt_c;
|
||||
reg [3:0] cnt_d;
|
||||
reg [3:0] cnt_e;
|
||||
reg [3:0] cnt_f;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn) begin
|
||||
cnt_0 <= 4'h0;
|
||||
cnt_1 <= 4'h1;
|
||||
cnt_2 <= 4'h2;
|
||||
cnt_3 <= 4'h3;
|
||||
cnt_4 <= 4'h4;
|
||||
cnt_5 <= 4'h5;
|
||||
cnt_6 <= 4'h6;
|
||||
cnt_7 <= 4'h7;
|
||||
cnt_8 <= 4'h8;
|
||||
cnt_9 <= 4'h9;
|
||||
cnt_a <= 4'ha;
|
||||
cnt_b <= 4'hb;
|
||||
cnt_c <= 4'hc;
|
||||
cnt_d <= 4'hd;
|
||||
cnt_e <= 4'he;
|
||||
cnt_f <= 4'hf;
|
||||
end
|
||||
else if(div_en) begin
|
||||
cnt_0 <= cnt_0 + 4'd1;
|
||||
cnt_1 <= cnt_1 + 4'd1;
|
||||
cnt_2 <= cnt_2 + 4'd1;
|
||||
cnt_3 <= cnt_3 + 4'd1;
|
||||
cnt_4 <= cnt_4 + 4'd1;
|
||||
cnt_5 <= cnt_5 + 4'd1;
|
||||
cnt_6 <= cnt_6 + 4'd1;
|
||||
cnt_7 <= cnt_7 + 4'd1;
|
||||
cnt_8 <= cnt_8 + 4'd1;
|
||||
cnt_9 <= cnt_9 + 4'd1;
|
||||
cnt_a <= cnt_a + 4'd1;
|
||||
cnt_b <= cnt_b + 4'd1;
|
||||
cnt_c <= cnt_c + 4'd1;
|
||||
cnt_d <= cnt_d + 4'd1;
|
||||
cnt_e <= cnt_e + 4'd1;
|
||||
cnt_f <= cnt_f + 4'd1;
|
||||
end
|
||||
else begin
|
||||
cnt_0 <= cnt_0;
|
||||
cnt_1 <= cnt_1;
|
||||
cnt_2 <= cnt_2;
|
||||
cnt_3 <= cnt_3;
|
||||
cnt_4 <= cnt_4;
|
||||
cnt_5 <= cnt_5;
|
||||
cnt_6 <= cnt_6;
|
||||
cnt_7 <= cnt_7;
|
||||
cnt_8 <= cnt_8;
|
||||
cnt_9 <= cnt_9;
|
||||
cnt_a <= cnt_a;
|
||||
cnt_b <= cnt_b;
|
||||
cnt_c <= cnt_c;
|
||||
cnt_d <= cnt_d;
|
||||
cnt_e <= cnt_e;
|
||||
cnt_f <= cnt_f;
|
||||
|
||||
end
|
||||
|
||||
assign clk_div16_0 = cnt_0[3];
|
||||
assign clk_div16_1 = cnt_1[3];
|
||||
assign clk_div16_2 = cnt_2[3];
|
||||
assign clk_div16_3 = cnt_3[3];
|
||||
assign clk_div16_4 = cnt_4[3];
|
||||
assign clk_div16_5 = cnt_5[3];
|
||||
assign clk_div16_6 = cnt_6[3];
|
||||
assign clk_div16_7 = cnt_7[3];
|
||||
assign clk_div16_8 = cnt_8[3];
|
||||
assign clk_div16_9 = cnt_9[3];
|
||||
assign clk_div16_a = cnt_a[3];
|
||||
assign clk_div16_b = cnt_b[3];
|
||||
assign clk_div16_c = cnt_c[3];
|
||||
assign clk_div16_d = cnt_d[3];
|
||||
assign clk_div16_e = cnt_e[3];
|
||||
assign clk_div16_f = cnt_f[3];
|
||||
|
||||
|
||||
reg [3:0] cnt_div16;
|
||||
always@(posedge clk_div16_0 or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt_div16 <= 4'd0;
|
||||
else if(div_en)
|
||||
cnt_div16 <= cnt_div16 + 4'd1;
|
||||
else
|
||||
cnt_div16 <= cnt_div16;
|
||||
|
||||
|
||||
assign clk_h = clk_div16_0;
|
||||
assign clk_l = cnt_div16[0];
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,168 +0,0 @@
|
|||
module TB();
|
||||
|
||||
parameter data_in_width = 16;
|
||||
parameter max_coef_width = 32;
|
||||
parameter frac_data_out_width = 20;//X for in,5
|
||||
parameter frac_coef_width = 31;//division
|
||||
parameter feedback_width = 36;
|
||||
parameter data_out_width = 36;
|
||||
parameter saturation_mode = 0;
|
||||
parameter out_reg = 1;
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg [15:0] din_im;
|
||||
|
||||
reg [36:0] a;
|
||||
reg [36:0] b;
|
||||
reg [20:0] c;
|
||||
reg [20:0] d;
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
reg [21:0] cnt;
|
||||
reg [15:0] din_imp;
|
||||
reg [15:0] din_rect;
|
||||
reg [15:0] din_cos;
|
||||
reg [15:0] diff_in;
|
||||
reg en;
|
||||
|
||||
wire [1 :0] source_mode;
|
||||
wire [15 :0] iir_in;
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
wire [35:0] dout_p0;
|
||||
|
||||
initial
|
||||
begin
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
|
||||
din_im = 16'd0;
|
||||
|
||||
a = 37'd1757225200;
|
||||
b = 37'd0;
|
||||
c = -21'd1042856;
|
||||
d = 21'd0;
|
||||
|
||||
fcw = 48'h0840_0000_0000;
|
||||
|
||||
din_imp = 16'd0;
|
||||
din_rect = 16'd0;
|
||||
din_cos = 16'd0;
|
||||
|
||||
#3600;
|
||||
en = 1'b1;
|
||||
#3800;
|
||||
rstn = 1'b1;
|
||||
din_imp = 16'd32767;
|
||||
din_rect = 8'd1;
|
||||
#400;
|
||||
din_imp = 16'd0;
|
||||
#12000;
|
||||
din_rect = 16'd0;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_cos <= 16'd0;
|
||||
diff_in <= 16'd0;
|
||||
end
|
||||
else
|
||||
din_cos <= cos;
|
||||
|
||||
assign source_mode = 2'b00;
|
||||
|
||||
always @(*)
|
||||
|
||||
case(source_mode)
|
||||
2'b00 : diff_in = din_imp;
|
||||
2'b01 : diff_in = din_rect;
|
||||
2'b10 : diff_in = din_cos;
|
||||
endcase
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
DW_iir_dc
|
||||
#(
|
||||
.data_in_width (data_in_width ),
|
||||
.data_out_width (data_out_width ),
|
||||
.frac_data_out_width (frac_data_out_width),
|
||||
.feedback_width (feedback_width ),
|
||||
.max_coef_width (max_coef_width ),
|
||||
.frac_coef_width (frac_coef_width ),
|
||||
.saturation_mode (saturation_mode ),
|
||||
.out_reg (out_reg )
|
||||
)
|
||||
inst_iir_0
|
||||
(
|
||||
.clk (clk ),
|
||||
.rst_n (rstn ),
|
||||
.init_n (rstn ),
|
||||
.enable (en ),
|
||||
.A1_coef (32'd2143083069 ),//Den
|
||||
.A2_coef ('h0 ),
|
||||
.B0_coef (32'd55007236 ),//Num
|
||||
.B1_coef ('h0 ),
|
||||
.B2_coef ('h0 ),
|
||||
.data_in (diff_in ),
|
||||
.data_out (dout_p0 ),
|
||||
.saturation ( )
|
||||
);
|
||||
|
||||
|
||||
integer signed In_fid;
|
||||
integer signed Out_fid;
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
In_fid = $fopen("./in");
|
||||
Out_fid = $fopen("./out");
|
||||
end
|
||||
|
||||
always@(posedge clk)
|
||||
|
||||
$fwrite(In_fid,"%d\n",{{~{diff_in[15]}},diff_in[14:0]});
|
||||
|
||||
always@(posedge clk)
|
||||
|
||||
$fwrite(Out_fid,"%d\n",{{~{dout_p0[35]}},dout_p0[34:0]});
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
61
tb/tb_diff.v
61
tb/tb_diff.v
|
|
@ -1,61 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg [15:0] din_in;
|
||||
reg [21:0] cnt;
|
||||
|
||||
|
||||
initial begin
|
||||
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
din_in = 1'b0;
|
||||
|
||||
#3400;
|
||||
rstn = 1'b1;
|
||||
din_in = 1'b1;
|
||||
|
||||
#6400;
|
||||
rstn = 1'b1;
|
||||
din_in = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
|
||||
initial begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
|
||||
diff inst_diff
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.din (din_in ),
|
||||
.dout (dout_p0 )
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
154
tb/tb_iir.v
154
tb/tb_iir.v
|
|
@ -1,154 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg [15:0] din_im;
|
||||
|
||||
reg [36:0] a;
|
||||
reg [36:0] b;
|
||||
reg [20:0] c;
|
||||
reg [20:0] d;
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
reg [21:0] cnt;
|
||||
reg [15:0] din_imp;
|
||||
reg [15:0] din_rect;
|
||||
reg [15:0] din_cos;
|
||||
reg [15:0] diff_in;
|
||||
reg en;
|
||||
|
||||
wire [1 :0] source_mode;
|
||||
wire [15 :0] iir_in;
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
wire [15:0] dout_p0;
|
||||
|
||||
initial
|
||||
begin
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
|
||||
din_im = 16'd0;
|
||||
|
||||
a = 37'd1757225200;
|
||||
b = 37'd0;
|
||||
c = -21'd1042856;
|
||||
d = 21'd0;
|
||||
|
||||
fcw = 48'h0840_0000_0000;
|
||||
|
||||
din_imp = 16'd0;
|
||||
din_rect = 16'd0;
|
||||
din_cos = 16'd0;
|
||||
|
||||
#3600;
|
||||
en = 1'b1;
|
||||
#3800;
|
||||
rstn = 1'b1;
|
||||
din_imp = 16'd32767;
|
||||
din_rect = 16'd30000;
|
||||
#400;
|
||||
din_imp = 16'd0;
|
||||
#12000;
|
||||
din_rect = 16'd0;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_cos <= 16'd0;
|
||||
diff_in <= 16'd0;
|
||||
end
|
||||
else
|
||||
din_cos <= cos;
|
||||
|
||||
assign source_mode = 2'b01;
|
||||
|
||||
always @(*)
|
||||
|
||||
case(source_mode)
|
||||
2'b00 : diff_in = din_imp;
|
||||
2'b01 : diff_in = din_rect;
|
||||
2'b10 : diff_in = din_cos;
|
||||
endcase
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
diff inst_diff
|
||||
(
|
||||
.clk (clk ),
|
||||
.en (en ),
|
||||
.rstn (rstn ),
|
||||
.din (diff_in ),
|
||||
.dout (iir_in )
|
||||
);
|
||||
|
||||
IIR_Filter inst1_IIR_Filter
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a_re (a ),
|
||||
.a_im (b ),
|
||||
.b_re (c ),
|
||||
.b_im (d ),
|
||||
.dout (dout_p0 )
|
||||
);
|
||||
|
||||
integer signed In_fid;
|
||||
integer signed Out_fid;
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
In_fid = $fopen("./in");
|
||||
Out_fid = $fopen("./out");
|
||||
end
|
||||
|
||||
always@(posedge clk)
|
||||
|
||||
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
|
||||
|
||||
always@(posedge clk)
|
||||
|
||||
$fwrite(Out_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg en;
|
||||
reg [15:0] din_in;
|
||||
reg [21:0] cnt;
|
||||
|
||||
|
||||
initial begin
|
||||
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
din_in = 1'b0;
|
||||
en = 1'b0;
|
||||
#300;
|
||||
rstn = 1'b1;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
|
||||
always@(posedge clk or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
|
||||
initial begin
|
||||
wait(cnt[17]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
always@(posedge clk or negedge rstn)
|
||||
begin
|
||||
if(cnt >= 2047 )
|
||||
begin
|
||||
en <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
initial begin
|
||||
fcw = 48'h0840_0000_0000;
|
||||
end
|
||||
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] dout_p0;
|
||||
wire [15:0] dout_p1;
|
||||
|
||||
MeanIntp2 inst_MeanIntp2
|
||||
(
|
||||
.clk (clk ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din (cos & {16{en}} ),
|
||||
.dout_m (dout_p0 ),
|
||||
.dout_o (dout_p1 )
|
||||
);
|
||||
|
||||
reg [15:0] cs_wave;
|
||||
|
||||
always@(posedge clk) cs_wave = dout_p1;
|
||||
always@(negedge clk) cs_wave = dout_p0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
142
tb/tb_mean4.v
142
tb/tb_mean4.v
|
|
@ -1,142 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg en;
|
||||
reg [21:0] cnt;
|
||||
|
||||
|
||||
initial begin
|
||||
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
en = 1'b0;
|
||||
#300;
|
||||
rstn = 1'b1;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
wire clk_div16_0;
|
||||
wire clk_div16_1;
|
||||
wire clk_div16_2;
|
||||
wire clk_div16_3;
|
||||
wire clk_div16_4;
|
||||
wire clk_div16_5;
|
||||
wire clk_div16_6;
|
||||
wire clk_div16_7;
|
||||
wire clk_div16_8;
|
||||
wire clk_div16_9;
|
||||
wire clk_div16_a;
|
||||
wire clk_div16_b;
|
||||
wire clk_div16_c;
|
||||
wire clk_div16_d;
|
||||
wire clk_div16_e;
|
||||
wire clk_div16_f;
|
||||
|
||||
|
||||
clk_gen inst_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.clk_div16_0 (clk_div16_0 ),
|
||||
.clk_div16_1 (clk_div16_1 ),
|
||||
.clk_div16_2 (clk_div16_2 ),
|
||||
.clk_div16_3 (clk_div16_3 ),
|
||||
.clk_div16_4 (clk_div16_4 ),
|
||||
.clk_div16_5 (clk_div16_5 ),
|
||||
.clk_div16_6 (clk_div16_6 ),
|
||||
.clk_div16_7 (clk_div16_7 ),
|
||||
.clk_div16_8 (clk_div16_8 ),
|
||||
.clk_div16_9 (clk_div16_9 ),
|
||||
.clk_div16_a (clk_div16_a ),
|
||||
.clk_div16_b (clk_div16_b ),
|
||||
.clk_div16_c (clk_div16_c ),
|
||||
.clk_div16_d (clk_div16_d ),
|
||||
.clk_div16_e (clk_div16_e ),
|
||||
.clk_div16_f (clk_div16_f ),
|
||||
.clk_h (clk_h ),
|
||||
.clk_l (clk_l )
|
||||
);
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
|
||||
initial begin
|
||||
wait(cnt[17]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
begin
|
||||
if(cnt >= 2047 )
|
||||
begin
|
||||
en <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
initial begin
|
||||
fcw = 48'h0840_0000_0000;
|
||||
end
|
||||
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk_div16_f ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] dout_p0;
|
||||
wire [15:0] dout_p1;
|
||||
wire [15:0] dout_p2;
|
||||
wire [15:0] dout_p3;
|
||||
|
||||
MeanIntp4 inst_MeanIntp4
|
||||
(
|
||||
.clk (clk_div16_f ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.din (cos & {16{en}} ),
|
||||
.dout4_0 (dout_p0 ),
|
||||
.dout4_1 (dout_p1 ),
|
||||
.dout4_2 (dout_p2 ),
|
||||
.dout4_3 (dout_p3 )
|
||||
);
|
||||
|
||||
reg [15:0] cs_wave;
|
||||
|
||||
always@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
always@(posedge clk_div16_a) cs_wave = dout_p1;
|
||||
always@(posedge clk_div16_6) cs_wave = dout_p2;
|
||||
always@(posedge clk_div16_2) cs_wave = dout_p3;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,164 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg en;
|
||||
reg [21:0] cnt;
|
||||
|
||||
|
||||
initial begin
|
||||
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
en = 1'b0;
|
||||
#300;
|
||||
rstn = 1'b1;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
wire clk_div16_0;
|
||||
wire clk_div16_1;
|
||||
wire clk_div16_2;
|
||||
wire clk_div16_3;
|
||||
wire clk_div16_4;
|
||||
wire clk_div16_5;
|
||||
wire clk_div16_6;
|
||||
wire clk_div16_7;
|
||||
wire clk_div16_8;
|
||||
wire clk_div16_9;
|
||||
wire clk_div16_a;
|
||||
wire clk_div16_b;
|
||||
wire clk_div16_c;
|
||||
wire clk_div16_d;
|
||||
wire clk_div16_e;
|
||||
wire clk_div16_f;
|
||||
|
||||
|
||||
clk_gen inst_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.clk_div16_0 (clk_div16_0 ),
|
||||
.clk_div16_1 (clk_div16_1 ),
|
||||
.clk_div16_2 (clk_div16_2 ),
|
||||
.clk_div16_3 (clk_div16_3 ),
|
||||
.clk_div16_4 (clk_div16_4 ),
|
||||
.clk_div16_5 (clk_div16_5 ),
|
||||
.clk_div16_6 (clk_div16_6 ),
|
||||
.clk_div16_7 (clk_div16_7 ),
|
||||
.clk_div16_8 (clk_div16_8 ),
|
||||
.clk_div16_9 (clk_div16_9 ),
|
||||
.clk_div16_a (clk_div16_a ),
|
||||
.clk_div16_b (clk_div16_b ),
|
||||
.clk_div16_c (clk_div16_c ),
|
||||
.clk_div16_d (clk_div16_d ),
|
||||
.clk_div16_e (clk_div16_e ),
|
||||
.clk_div16_f (clk_div16_f ),
|
||||
.clk_h (clk_h ),
|
||||
.clk_l (clk_l )
|
||||
);
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
|
||||
initial begin
|
||||
wait(cnt[17]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
begin
|
||||
if(cnt >= 2047 )
|
||||
begin
|
||||
en <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
initial begin
|
||||
fcw = 48'h0840_0000_0000;
|
||||
end
|
||||
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk_div16_f ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] dout_p0;
|
||||
wire [15:0] dout_p1;
|
||||
wire [15:0] dout_p2;
|
||||
wire [15:0] dout_p3;
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
|
||||
assign intp_mode = 2'b10;
|
||||
|
||||
MeanIntp4_top inst_MeanIntp4
|
||||
(
|
||||
.clk (clk_div16_f ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din (cos & {16{en}} ),
|
||||
.dout_0 (dout_p0 ),
|
||||
.dout_1 (dout_p1 ),
|
||||
.dout_2 (dout_p2 ),
|
||||
.dout_3 (dout_p3 )
|
||||
);
|
||||
|
||||
reg [15:0] cs_wave;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave = dout_p3;
|
||||
end
|
||||
endcase
|
||||
join
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
reg clk;
|
||||
reg rstn;
|
||||
reg en;
|
||||
reg [21:0] cnt;
|
||||
|
||||
|
||||
initial begin
|
||||
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
en = 1'b0;
|
||||
#300;
|
||||
rstn = 1'b1;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
|
||||
wire clk_div16_0;
|
||||
wire clk_div16_1;
|
||||
wire clk_div16_2;
|
||||
wire clk_div16_3;
|
||||
wire clk_div16_4;
|
||||
wire clk_div16_5;
|
||||
wire clk_div16_6;
|
||||
wire clk_div16_7;
|
||||
wire clk_div16_8;
|
||||
wire clk_div16_9;
|
||||
wire clk_div16_a;
|
||||
wire clk_div16_b;
|
||||
wire clk_div16_c;
|
||||
wire clk_div16_d;
|
||||
wire clk_div16_e;
|
||||
wire clk_div16_f;
|
||||
|
||||
|
||||
clk_gen inst_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.clk_div16_0 (clk_div16_0 ),
|
||||
.clk_div16_1 (clk_div16_1 ),
|
||||
.clk_div16_2 (clk_div16_2 ),
|
||||
.clk_div16_3 (clk_div16_3 ),
|
||||
.clk_div16_4 (clk_div16_4 ),
|
||||
.clk_div16_5 (clk_div16_5 ),
|
||||
.clk_div16_6 (clk_div16_6 ),
|
||||
.clk_div16_7 (clk_div16_7 ),
|
||||
.clk_div16_8 (clk_div16_8 ),
|
||||
.clk_div16_9 (clk_div16_9 ),
|
||||
.clk_div16_a (clk_div16_a ),
|
||||
.clk_div16_b (clk_div16_b ),
|
||||
.clk_div16_c (clk_div16_c ),
|
||||
.clk_div16_d (clk_div16_d ),
|
||||
.clk_div16_e (clk_div16_e ),
|
||||
.clk_div16_f (clk_div16_f ),
|
||||
.clk_h (clk_h ),
|
||||
.clk_l (clk_l )
|
||||
);
|
||||
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
|
||||
initial begin
|
||||
wait(cnt[17]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
always@(posedge clk_div16_f or negedge rstn)
|
||||
begin
|
||||
if(cnt >= 2047 )
|
||||
begin
|
||||
en <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
initial begin
|
||||
fcw = 48'h0840_0000_0000;
|
||||
end
|
||||
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk_div16_f ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] dout_p0;
|
||||
wire [15:0] dout_p1;
|
||||
wire [15:0] dout_p2;
|
||||
wire [15:0] dout_p3;
|
||||
wire [15:0] dout_p4;
|
||||
wire [15:0] dout_p5;
|
||||
wire [15:0] dout_p6;
|
||||
wire [15:0] dout_p7;
|
||||
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
assign intp_mode = 2'b11;
|
||||
|
||||
MeanIntp_8 inst_MeanIntp8
|
||||
(
|
||||
.clk (clk_div16_f ),
|
||||
.rstn (rstn ),
|
||||
.en (en ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din (cos & {16{en}} ),
|
||||
.dout_0 (dout_p0 ),
|
||||
.dout_1 (dout_p1 ),
|
||||
.dout_2 (dout_p2 ),
|
||||
.dout_3 (dout_p3 ),
|
||||
.dout_4 (dout_p4 ),
|
||||
.dout_5 (dout_p5 ),
|
||||
.dout_6 (dout_p6 ),
|
||||
.dout_7 (dout_p7 )
|
||||
|
||||
);
|
||||
integer signed In_fid;
|
||||
integer X8_fid;
|
||||
|
||||
initial begin
|
||||
#0
|
||||
|
||||
In_fid = $fopen("./in_intp8.dat");
|
||||
X8_fid = $fopen("./out_intp8.dat");
|
||||
|
||||
end
|
||||
|
||||
always@(posedge clk_div16_f)
|
||||
if(cnt >= 90)
|
||||
$fwrite(In_fid,"%d\n",{{{~cos[15]}},cos[14:0]});
|
||||
|
||||
reg [15:0] cs_wave;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
// begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_c) cs_wave = dout_p1;
|
||||
@(posedge clk_div16_a) cs_wave = dout_p2;
|
||||
@(posedge clk_div16_8) cs_wave = dout_p3;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p4;
|
||||
@(posedge clk_div16_4) cs_wave = dout_p5;
|
||||
@(posedge clk_div16_2) cs_wave = dout_p6;
|
||||
@(posedge clk_div16_0) cs_wave = dout_p7;
|
||||
|
||||
// end
|
||||
join
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
|
||||
@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p0[15]}},dout_p0[14:0]});
|
||||
@(posedge clk_div16_c)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p1[15]}},dout_p1[14:0]});
|
||||
@(posedge clk_div16_a)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p2[15]}},dout_p2[14:0]});
|
||||
@(posedge clk_div16_8)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p3[15]}},dout_p3[14:0]});
|
||||
@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p4[15]}},dout_p4[14:0]});
|
||||
@(posedge clk_div16_4)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p5[15]}},dout_p5[14:0]});
|
||||
@(posedge clk_div16_2)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p6[15]}},dout_p6[14:0]});
|
||||
@(posedge clk_div16_0)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",{{{~dout_p7[15]}},dout_p7[14:0]});
|
||||
join
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
759
tb/tb_z_dsp.v
759
tb/tb_z_dsp.v
|
|
@ -1,759 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
|
||||
reg rstn;
|
||||
reg [15:0] din_im;
|
||||
|
||||
reg [31:0] a0_re;
|
||||
reg [31:0] a0_im;
|
||||
reg [31:0] b0_re;
|
||||
reg [31:0] b0_im;
|
||||
reg [31:0] a1_re;
|
||||
reg [31:0] a1_im;
|
||||
reg [31:0] b1_re;
|
||||
reg [31:0] b1_im;
|
||||
reg [31:0] a2_re;
|
||||
reg [31:0] a2_im;
|
||||
reg [31:0] b2_re;
|
||||
reg [31:0] b2_im;
|
||||
reg [31:0] a3_re;
|
||||
reg [31:0] a3_im;
|
||||
reg [31:0] b3_re;
|
||||
reg [31:0] b3_im;
|
||||
reg [31:0] a4_re;
|
||||
reg [31:0] a4_im;
|
||||
reg [31:0] b4_re;
|
||||
reg [31:0] b4_im;
|
||||
reg [31:0] a5_re;
|
||||
reg [31:0] a5_im;
|
||||
reg [31:0] b5_re;
|
||||
reg [31:0] b5_im;
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
reg [21:0] cnt;
|
||||
reg [15:0] din_imp;
|
||||
reg [15:0] din_rect;
|
||||
reg [15:0] din_cos;
|
||||
reg [15:0] iir_in;
|
||||
|
||||
wire [1 :0] source_mode;
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
|
||||
reg en;
|
||||
|
||||
reg clk;
|
||||
reg clk_div2;
|
||||
reg clk_div4;
|
||||
|
||||
initial
|
||||
begin
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
clk_div2 = 1'b0;
|
||||
clk_div4 = 1'b0;
|
||||
en = 1'b0;
|
||||
|
||||
din_im = 16'd0;
|
||||
|
||||
a0_re = 32'd55007237;
|
||||
a0_im = 32'd0;
|
||||
b0_re = 32'd2143083068;
|
||||
b0_im = 32'd0;
|
||||
a1_re = 32'd32690030;
|
||||
a1_im = 32'd0;
|
||||
b1_re = 32'd2145807236;
|
||||
b1_im = 32'd0;
|
||||
a2_re = 32'd429516;
|
||||
a2_im = 32'd0;
|
||||
b2_re = 32'd2146812530;
|
||||
b2_im = 32'd0;
|
||||
a3_re = 32'd0;
|
||||
a3_im = 32'd0;
|
||||
b3_re = 32'd0;
|
||||
b3_im = 32'd0;
|
||||
a4_re = 32'd0;
|
||||
a4_im = 32'd0;
|
||||
b4_re = 32'd0;
|
||||
b4_im = 32'd0;
|
||||
a5_re = 32'd0;
|
||||
a5_im = 32'd0;
|
||||
b5_re = -32'd0;
|
||||
b5_im = 32'd0;
|
||||
|
||||
fcw = 48'h0840_0000_0000;
|
||||
|
||||
din_imp = 16'd0;
|
||||
din_rect = 16'd0;
|
||||
din_cos = 16'd0;
|
||||
|
||||
#300;
|
||||
rstn = 1'b1;
|
||||
#16600300;
|
||||
// din_imp = 16'd30000;
|
||||
// din_rect = 16'd30000;
|
||||
// en = 1'b1;
|
||||
#6400;
|
||||
// din_imp = 16'd0;
|
||||
#64000;
|
||||
// din_rect = 16'd0;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
always #400 clk_div2 = ~clk_div2;
|
||||
always #800 clk_div4 = ~clk_div4;
|
||||
|
||||
wire clk_div16_0;
|
||||
wire clk_div16_1;
|
||||
wire clk_div16_2;
|
||||
wire clk_div16_3;
|
||||
wire clk_div16_4;
|
||||
wire clk_div16_5;
|
||||
wire clk_div16_6;
|
||||
wire clk_div16_7;
|
||||
wire clk_div16_8;
|
||||
wire clk_div16_9;
|
||||
wire clk_div16_a;
|
||||
wire clk_div16_b;
|
||||
wire clk_div16_c;
|
||||
wire clk_div16_d;
|
||||
wire clk_div16_e;
|
||||
wire clk_div16_f;
|
||||
wire clk_l;
|
||||
wire clk_h;
|
||||
|
||||
clk_gen inst_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.clk_div16_0 (clk_div16_0 ),
|
||||
.clk_div16_1 (clk_div16_1 ),
|
||||
.clk_div16_2 (clk_div16_2 ),
|
||||
.clk_div16_3 (clk_div16_3 ),
|
||||
.clk_div16_4 (clk_div16_4 ),
|
||||
.clk_div16_5 (clk_div16_5 ),
|
||||
.clk_div16_6 (clk_div16_6 ),
|
||||
.clk_div16_7 (clk_div16_7 ),
|
||||
.clk_div16_8 (clk_div16_8 ),
|
||||
.clk_div16_9 (clk_div16_9 ),
|
||||
.clk_div16_a (clk_div16_a ),
|
||||
.clk_div16_b (clk_div16_b ),
|
||||
.clk_div16_c (clk_div16_c ),
|
||||
.clk_div16_d (clk_div16_d ),
|
||||
.clk_div16_e (clk_div16_e ),
|
||||
.clk_div16_f (clk_div16_f ),
|
||||
.clk_h (clk_h ),
|
||||
.clk_l (clk_l )
|
||||
);
|
||||
|
||||
wire clk_div32_0;
|
||||
wire clk_div32_1;
|
||||
wire clk_div32_2;
|
||||
wire clk_div32_3;
|
||||
wire clk_div32_4;
|
||||
wire clk_div32_5;
|
||||
wire clk_div32_6;
|
||||
wire clk_div32_7;
|
||||
wire clk_div32_8;
|
||||
wire clk_div32_9;
|
||||
wire clk_div32_a;
|
||||
wire clk_div32_b;
|
||||
wire clk_div32_c;
|
||||
wire clk_div32_d;
|
||||
wire clk_div32_e;
|
||||
wire clk_div32_f;
|
||||
wire clk_l1;
|
||||
wire clk_h1;
|
||||
|
||||
clk_gen inst1_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk_div2 ),
|
||||
.clk_div16_0 (clk_div32_0 ),
|
||||
.clk_div16_1 (clk_div32_1 ),
|
||||
.clk_div16_2 (clk_div32_2 ),
|
||||
.clk_div16_3 (clk_div32_3 ),
|
||||
.clk_div16_4 (clk_div32_4 ),
|
||||
.clk_div16_5 (clk_div32_5 ),
|
||||
.clk_div16_6 (clk_div32_6 ),
|
||||
.clk_div16_7 (clk_div32_7 ),
|
||||
.clk_div16_8 (clk_div32_8 ),
|
||||
.clk_div16_9 (clk_div32_9 ),
|
||||
.clk_div16_a (clk_div32_a ),
|
||||
.clk_div16_b (clk_div32_b ),
|
||||
.clk_div16_c (clk_div32_c ),
|
||||
.clk_div16_d (clk_div32_d ),
|
||||
.clk_div16_e (clk_div32_e ),
|
||||
.clk_div16_f (clk_div32_f ),
|
||||
.clk_h (clk_h1 ),
|
||||
.clk_l (clk_l1 )
|
||||
);
|
||||
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_imp <= 22'd0;
|
||||
else if(cnt == 100)
|
||||
begin
|
||||
din_imp <= 16'd32767;
|
||||
//en <= 1'b1;
|
||||
end
|
||||
else
|
||||
din_imp <= 'h0;
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_rect <= 22'd0;
|
||||
else if(cnt >= 100 && cnt <=10100)
|
||||
begin
|
||||
din_rect <= 16'd30000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_rect <= 16'd0;
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
en <= 22'd0;
|
||||
else if(cnt >= 90 )
|
||||
begin
|
||||
en <= 1'b1;
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_cos <= 16'd0;
|
||||
iir_in <= 16'd0;
|
||||
end
|
||||
else
|
||||
din_cos <= {cos[15],cos[15:1]};
|
||||
|
||||
assign source_mode = 2'b01;
|
||||
|
||||
always @(*)
|
||||
|
||||
case(source_mode)
|
||||
2'b00 : iir_in = din_imp;
|
||||
2'b01 : iir_in = din_rect;
|
||||
2'b10 : iir_in = din_cos;
|
||||
endcase
|
||||
|
||||
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
assign intp_mode = 2'b11;
|
||||
|
||||
wire [1:0] dac_mode_sel;
|
||||
assign dac_mode_sel = 2'b00;
|
||||
|
||||
wire tc_bypass;
|
||||
assign tc_bypass = 1'b0;
|
||||
/*
|
||||
wire [15:0] dout_clkl_p0;
|
||||
wire [15:0] dout_clkl_p1;
|
||||
wire [15:0] dout_clkl_p2;
|
||||
wire [15:0] dout_clkl_p3;
|
||||
wire [15:0] dout_clkl_p4;
|
||||
wire [15:0] dout_clkl_p5;
|
||||
wire [15:0] dout_clkl_p6;
|
||||
wire [15:0] dout_clkl_p7;
|
||||
|
||||
z_dsp inst_Z_dsp
|
||||
(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.vldi (iir_in[14] ),
|
||||
.en (en ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout_clkl_p0 ),
|
||||
.dout1 (dout_clkl_p1 ),
|
||||
.dout2 (dout_clkl_p2 ),
|
||||
.dout3 (dout_clkl_p3 ),
|
||||
.vldo ( ),
|
||||
.saturation_0 ( ),
|
||||
.saturation_1 ( ),
|
||||
.saturation_2 ( ),
|
||||
.saturation_3 ( ),
|
||||
.saturation_4 ( ),
|
||||
.saturation_5 ( )
|
||||
|
||||
);
|
||||
*/
|
||||
wire [15:0] dout_p0;
|
||||
wire [15:0] dout_p1;
|
||||
wire [15:0] dout_p2;
|
||||
wire [15:0] dout_p3;
|
||||
|
||||
z_dsp_en_Test inst_z_dsp_en_Test
|
||||
(
|
||||
.clk (clk_h ),
|
||||
.rstn (rstn ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.vldi (iir_in[14] ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout_p0 ),
|
||||
.dout1 (dout_p1 ),
|
||||
.dout2 (dout_p2 ),
|
||||
.dout3 (dout_p3 ),
|
||||
.vldo ( ),
|
||||
.saturation_0 ( ),
|
||||
.saturation_1 ( ),
|
||||
.saturation_2 ( ),
|
||||
.saturation_3 ( ),
|
||||
.saturation_4 ( ),
|
||||
.saturation_5 ( )
|
||||
);
|
||||
|
||||
/*
|
||||
reg [15:0] dout_p0_r1 = 0;
|
||||
reg [15:0] dout_p1_r1 = 0;
|
||||
reg [15:0] dout_p2_r1 = 0;
|
||||
reg [15:0] dout_p3_r1 = 0;
|
||||
reg [15:0] dout_p4_r1 = 0;
|
||||
reg [15:0] dout_p5_r1 = 0;
|
||||
reg [15:0] dout_p6_r1 = 0;
|
||||
reg [15:0] dout_p7_r1 = 0;
|
||||
|
||||
reg [15:0] dout_p0_r2 = 0;
|
||||
reg [15:0] dout_p1_r2 = 0;
|
||||
reg [15:0] dout_p2_r2 = 0;
|
||||
reg [15:0] dout_p3_r2 = 0;
|
||||
reg [15:0] dout_p4_r2 = 0;
|
||||
reg [15:0] dout_p5_r2 = 0;
|
||||
reg [15:0] dout_p6_r2 = 0;
|
||||
reg [15:0] dout_p7_r2 = 0;
|
||||
|
||||
reg [15:0] dout_p0_r3 = 0;
|
||||
reg [15:0] dout_p1_r3 = 0;
|
||||
reg [15:0] dout_p2_r3 = 0;
|
||||
reg [15:0] dout_p3_r3 = 0;
|
||||
reg [15:0] dout_p4_r3 = 0;
|
||||
reg [15:0] dout_p5_r3 = 0;
|
||||
reg [15:0] dout_p6_r3 = 0;
|
||||
reg [15:0] dout_p7_r3 = 0;
|
||||
|
||||
reg [15:0] dout_p0_r4 = 0;
|
||||
reg [15:0] dout_p1_r4 = 0;
|
||||
reg [15:0] dout_p2_r4 = 0;
|
||||
reg [15:0] dout_p3_r4 = 0;
|
||||
reg [15:0] dout_p4_r4 = 0;
|
||||
reg [15:0] dout_p5_r4 = 0;
|
||||
reg [15:0] dout_p6_r4 = 0;
|
||||
reg [15:0] dout_p7_r4 = 0;
|
||||
|
||||
reg [15:0] dout_p0_r5 = 0;
|
||||
reg [15:0] dout_p1_r5 = 0;
|
||||
reg [15:0] dout_p2_r5 = 0;
|
||||
reg [15:0] dout_p3_r5 = 0;
|
||||
reg [15:0] dout_p4_r5 = 0;
|
||||
reg [15:0] dout_p5_r5 = 0;
|
||||
reg [15:0] dout_p6_r5 = 0;
|
||||
reg [15:0] dout_p7_r5 = 0;
|
||||
|
||||
|
||||
always @(posedge clk_h or negedge rstn ) begin
|
||||
if(!rstn) begin
|
||||
dout_p0_r1 <= 0;
|
||||
dout_p1_r1 <= 0;
|
||||
dout_p2_r1 <= 0;
|
||||
dout_p3_r1 <= 0;
|
||||
dout_p4_r1 <= 0;
|
||||
dout_p5_r1 <= 0;
|
||||
dout_p6_r1 <= 0;
|
||||
dout_p7_r1 <= 0;
|
||||
dout_p0_r2 <= 0;
|
||||
dout_p1_r2 <= 0;
|
||||
dout_p2_r2 <= 0;
|
||||
dout_p3_r2 <= 0;
|
||||
dout_p4_r2 <= 0;
|
||||
dout_p5_r2 <= 0;
|
||||
dout_p6_r2 <= 0;
|
||||
dout_p7_r2 <= 0;
|
||||
dout_p0_r3 <= 0;
|
||||
dout_p1_r3 <= 0;
|
||||
dout_p2_r3 <= 0;
|
||||
dout_p3_r3 <= 0;
|
||||
dout_p4_r3 <= 0;
|
||||
dout_p5_r3 <= 0;
|
||||
dout_p6_r3 <= 0;
|
||||
dout_p7_r3 <= 0;
|
||||
end
|
||||
else begin
|
||||
dout_p0_r1 <= dout_p0;
|
||||
dout_p1_r1 <= dout_p1;
|
||||
dout_p2_r1 <= dout_p2;
|
||||
dout_p3_r1 <= dout_p3;
|
||||
dout_p4_r1 <= dout_p4;
|
||||
dout_p5_r1 <= dout_p5;
|
||||
dout_p6_r1 <= dout_p6;
|
||||
dout_p7_r1 <= dout_p7;
|
||||
|
||||
dout_p0_r2 <= dout_p0_r1;
|
||||
dout_p1_r2 <= dout_p1_r1;
|
||||
dout_p2_r2 <= dout_p2_r1;
|
||||
dout_p3_r2 <= dout_p3_r1;
|
||||
dout_p4_r2 <= dout_p4_r1;
|
||||
dout_p5_r2 <= dout_p5_r1;
|
||||
dout_p6_r2 <= dout_p6_r1;
|
||||
dout_p7_r2 <= dout_p7_r1;
|
||||
|
||||
dout_p0_r3 <= dout_p0_r2;
|
||||
dout_p1_r3 <= dout_p1_r2;
|
||||
dout_p2_r3 <= dout_p2_r2;
|
||||
dout_p3_r3 <= dout_p3_r2;
|
||||
dout_p4_r3 <= dout_p4_r2;
|
||||
dout_p5_r3 <= dout_p5_r2;
|
||||
dout_p6_r3 <= dout_p6_r2;
|
||||
dout_p7_r3 <= dout_p7_r2;
|
||||
|
||||
dout_p0_r4 <= dout_p0_r3;
|
||||
dout_p1_r4 <= dout_p1_r3;
|
||||
dout_p2_r4 <= dout_p2_r3;
|
||||
dout_p3_r4 <= dout_p3_r3;
|
||||
dout_p4_r4 <= dout_p4_r3;
|
||||
dout_p5_r4 <= dout_p5_r3;
|
||||
dout_p6_r4 <= dout_p6_r3;
|
||||
dout_p7_r4 <= dout_p7_r3;
|
||||
|
||||
dout_p0_r5 <= dout_p0_r4;
|
||||
dout_p1_r5 <= dout_p1_r4;
|
||||
dout_p2_r5 <= dout_p2_r4;
|
||||
dout_p3_r5 <= dout_p3_r4;
|
||||
dout_p4_r5 <= dout_p4_r4;
|
||||
dout_p5_r5 <= dout_p5_r4;
|
||||
dout_p6_r5 <= dout_p6_r4;
|
||||
dout_p7_r5 <= dout_p7_r4;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] cs_wave = 0;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave = dout_p3;
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
|
||||
@(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
|
||||
@(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
|
||||
@(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
|
||||
@(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
|
||||
@(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
|
||||
@(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
|
||||
@(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
reg [15:0] cs_wave1 = 0;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave1 = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave1 = dout_p3;
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
|
||||
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
|
||||
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
|
||||
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
|
||||
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
|
||||
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
|
||||
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
|
||||
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
wire [15:0] diff;
|
||||
assign diff = cs_wave1 - cs_wave;
|
||||
*/
|
||||
integer signed In_fid;
|
||||
integer signed diff_fid;
|
||||
integer signed OrgOut_fid;
|
||||
integer signed dout0_fid;
|
||||
integer signed dout1_fid;
|
||||
integer signed dout2_fid;
|
||||
integer signed dout3_fid;
|
||||
integer X1_fid;
|
||||
integer X2_fid;
|
||||
integer X4_fid;
|
||||
integer X8_fid;
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
In_fid = $fopen("./in.dat");
|
||||
diff_fid = $fopen("./diff_in.dat");
|
||||
OrgOut_fid = $fopen("./OrgOut.dat");
|
||||
dout0_fid = $fopen("./dout0.dat");
|
||||
dout1_fid = $fopen("./dout1.dat");
|
||||
dout2_fid = $fopen("./dout2.dat");
|
||||
dout3_fid = $fopen("./dout3.dat");
|
||||
case (intp_mode)
|
||||
2'b00 : X1_fid = $fopen("./X1_data.dat");
|
||||
2'b01 : X2_fid = $fopen("./X2_data.dat");
|
||||
2'b10 : X4_fid = $fopen("./X4_data.dat");
|
||||
2'b11 : X8_fid = $fopen("./X8_data.dat");
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk_l)
|
||||
if(cnt >= 90)
|
||||
begin
|
||||
$fwrite(In_fid,"%d\n", $signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.din_r1));
|
||||
$fwrite(diff_fid,"%d\n", $signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.IIRin_re));
|
||||
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst_z_dsp_en_Test.inst_z_dsp.inst_TailCorr_top.dout));
|
||||
end
|
||||
|
||||
always@(posedge clk_h)
|
||||
if(cnt >= 90)
|
||||
begin
|
||||
$fwrite(dout0_fid,"%d\n",$signed(dout_p0));
|
||||
$fwrite(dout1_fid,"%d\n",$signed(dout_p1));
|
||||
$fwrite(dout2_fid,"%d\n",$signed(dout_p2));
|
||||
$fwrite(dout3_fid,"%d\n",$signed(dout_p3));
|
||||
end
|
||||
/*
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
|
||||
@(posedge clk_div16_a)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
|
||||
@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
|
||||
@(posedge clk_div16_2)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_f)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout0));
|
||||
@(posedge clk_div32_d)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout1));
|
||||
@(posedge clk_div32_b)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout2));
|
||||
@(posedge clk_div32_9)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout3));
|
||||
@(posedge clk_div32_7)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout4));
|
||||
@(posedge clk_div32_5)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout5));
|
||||
@(posedge clk_div32_3)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout6));
|
||||
@(posedge clk_div32_1)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X8_fid,"%d\n",$signed(dout7));
|
||||
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
*/
|
||||
/*
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
|
||||
always@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
|
||||
always@(posedge clk_div16_a)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
|
||||
always@(posedge clk_div16_6)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
|
||||
always@(posedge clk_div16_2)
|
||||
if(cnt >= 90)
|
||||
)
|
||||
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1)
|
||||
$fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
|
||||
always@(posedge clk_div16_e)
|
||||
if(cnt >= 90)
|
||||
$fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1 $fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
|
||||
*/
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,593 +0,0 @@
|
|||
module TB();
|
||||
|
||||
initial
|
||||
begin
|
||||
$fsdbDumpfile("TB.fsdb");
|
||||
$fsdbDumpvars(0, TB);
|
||||
end
|
||||
|
||||
|
||||
reg rstn;
|
||||
reg [15:0] din_im;
|
||||
|
||||
reg [31:0] a0_re;
|
||||
reg [31:0] a0_im;
|
||||
reg [31:0] b0_re;
|
||||
reg [31:0] b0_im;
|
||||
reg [31:0] a1_re;
|
||||
reg [31:0] a1_im;
|
||||
reg [31:0] b1_re;
|
||||
reg [31:0] b1_im;
|
||||
reg [31:0] a2_re;
|
||||
reg [31:0] a2_im;
|
||||
reg [31:0] b2_re;
|
||||
reg [31:0] b2_im;
|
||||
reg [31:0] a3_re;
|
||||
reg [31:0] a3_im;
|
||||
reg [31:0] b3_re;
|
||||
reg [31:0] b3_im;
|
||||
reg [31:0] a4_re;
|
||||
reg [31:0] a4_im;
|
||||
reg [31:0] b4_re;
|
||||
reg [31:0] b4_im;
|
||||
reg [31:0] a5_re;
|
||||
reg [31:0] a5_im;
|
||||
reg [31:0] b5_re;
|
||||
reg [31:0] b5_im;
|
||||
|
||||
reg [47:0] fcw;
|
||||
|
||||
reg [21:0] cnt;
|
||||
reg [15:0] din_imp;
|
||||
reg [15:0] din_rect;
|
||||
reg [15:0] din_cos;
|
||||
reg [15:0] iir_in;
|
||||
|
||||
wire [1 :0] source_mode;
|
||||
wire [15:0] cos;
|
||||
wire [15:0] sin;
|
||||
wire [15:0] dout_p0;
|
||||
|
||||
reg en;
|
||||
|
||||
reg clk;
|
||||
reg clk_div2;
|
||||
reg clk_div4;
|
||||
|
||||
//a_fix is 55007237
|
||||
//a_fix is 32690030
|
||||
//a_fix is 429516
|
||||
//a_fix is 0
|
||||
//b_fix is 2143083068
|
||||
//b_fix is 2145807236
|
||||
//b_fix is 2146812530
|
||||
//b_fix is 2147483648
|
||||
|
||||
initial
|
||||
begin
|
||||
#0;
|
||||
rstn = 1'b0;
|
||||
clk = 1'b0;
|
||||
clk_div2 = 1'b0;
|
||||
clk_div4 = 1'b0;
|
||||
en = 1'b0;
|
||||
|
||||
din_im = 16'd0;
|
||||
|
||||
a0_re = 32'd55007237 ;
|
||||
a1_re = 32'd32690030 ;
|
||||
a2_re = 32'd429516;
|
||||
a3_re = 32'd0;
|
||||
a4_re = 32'd0;
|
||||
a5_re = 32'd0;
|
||||
|
||||
a0_im = 32'd0;
|
||||
a1_im = 32'd0;
|
||||
a2_im = 32'd0;
|
||||
a3_im = 32'd0;
|
||||
a4_im = 32'd0;
|
||||
a5_im = 32'd0;
|
||||
|
||||
b0_re = -32'd2143083068;
|
||||
b1_re = -32'd2145807236;
|
||||
b2_re = -32'd2146812530;
|
||||
b3_re = -32'd0;
|
||||
b4_re = -32'd0;
|
||||
b5_re = -32'd0;
|
||||
|
||||
b0_im = 32'd0;
|
||||
b1_im = 32'd0;
|
||||
b2_im = 32'd0;
|
||||
b3_im = 32'd0;
|
||||
b4_im = 32'd0;
|
||||
b5_im = 32'd0;
|
||||
|
||||
fcw = 48'h0840_0000_0000;
|
||||
|
||||
din_imp = 16'd0;
|
||||
din_rect = 16'd0;
|
||||
din_cos = 16'd0;
|
||||
|
||||
#300;
|
||||
rstn = 1'b1;
|
||||
#16600300;
|
||||
// din_imp = 16'd30000;
|
||||
// din_rect = 16'd30000;
|
||||
// en = 1'b1;
|
||||
#6400;
|
||||
// din_imp = 16'd0;
|
||||
#64000;
|
||||
// din_rect = 16'd0;
|
||||
|
||||
end
|
||||
|
||||
always #200 clk = ~clk;
|
||||
always #400 clk_div2 = ~clk_div2;
|
||||
always #800 clk_div4 = ~clk_div4;
|
||||
|
||||
wire clk_div16_0;
|
||||
wire clk_div16_1;
|
||||
wire clk_div16_2;
|
||||
wire clk_div16_3;
|
||||
wire clk_div16_4;
|
||||
wire clk_div16_5;
|
||||
wire clk_div16_6;
|
||||
wire clk_div16_7;
|
||||
wire clk_div16_8;
|
||||
wire clk_div16_9;
|
||||
wire clk_div16_a;
|
||||
wire clk_div16_b;
|
||||
wire clk_div16_c;
|
||||
wire clk_div16_d;
|
||||
wire clk_div16_e;
|
||||
wire clk_div16_f;
|
||||
wire clk_l;
|
||||
wire clk_h;
|
||||
|
||||
clk_gen inst_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk ),
|
||||
.clk_div16_0 (clk_div16_0 ),
|
||||
.clk_div16_1 (clk_div16_1 ),
|
||||
.clk_div16_2 (clk_div16_2 ),
|
||||
.clk_div16_3 (clk_div16_3 ),
|
||||
.clk_div16_4 (clk_div16_4 ),
|
||||
.clk_div16_5 (clk_div16_5 ),
|
||||
.clk_div16_6 (clk_div16_6 ),
|
||||
.clk_div16_7 (clk_div16_7 ),
|
||||
.clk_div16_8 (clk_div16_8 ),
|
||||
.clk_div16_9 (clk_div16_9 ),
|
||||
.clk_div16_a (clk_div16_a ),
|
||||
.clk_div16_b (clk_div16_b ),
|
||||
.clk_div16_c (clk_div16_c ),
|
||||
.clk_div16_d (clk_div16_d ),
|
||||
.clk_div16_e (clk_div16_e ),
|
||||
.clk_div16_f (clk_div16_f ),
|
||||
.clk_h (clk_h ),
|
||||
.clk_l (clk_l )
|
||||
);
|
||||
|
||||
wire clk_div32_0;
|
||||
wire clk_div32_1;
|
||||
wire clk_div32_2;
|
||||
wire clk_div32_3;
|
||||
wire clk_div32_4;
|
||||
wire clk_div32_5;
|
||||
wire clk_div32_6;
|
||||
wire clk_div32_7;
|
||||
wire clk_div32_8;
|
||||
wire clk_div32_9;
|
||||
wire clk_div32_a;
|
||||
wire clk_div32_b;
|
||||
wire clk_div32_c;
|
||||
wire clk_div32_d;
|
||||
wire clk_div32_e;
|
||||
wire clk_div32_f;
|
||||
wire clk_l1;
|
||||
wire clk_h1;
|
||||
|
||||
clk_gen inst1_clk_gen(
|
||||
.rstn (rstn ),
|
||||
.clk (clk_div2 ),
|
||||
.clk_div16_0 (clk_div32_0 ),
|
||||
.clk_div16_1 (clk_div32_1 ),
|
||||
.clk_div16_2 (clk_div32_2 ),
|
||||
.clk_div16_3 (clk_div32_3 ),
|
||||
.clk_div16_4 (clk_div32_4 ),
|
||||
.clk_div16_5 (clk_div32_5 ),
|
||||
.clk_div16_6 (clk_div32_6 ),
|
||||
.clk_div16_7 (clk_div32_7 ),
|
||||
.clk_div16_8 (clk_div32_8 ),
|
||||
.clk_div16_9 (clk_div32_9 ),
|
||||
.clk_div16_a (clk_div32_a ),
|
||||
.clk_div16_b (clk_div32_b ),
|
||||
.clk_div16_c (clk_div32_c ),
|
||||
.clk_div16_d (clk_div32_d ),
|
||||
.clk_div16_e (clk_div32_e ),
|
||||
.clk_div16_f (clk_div32_f ),
|
||||
.clk_h (clk_h1 ),
|
||||
.clk_l (clk_l1 )
|
||||
);
|
||||
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
cnt <= 22'd0;
|
||||
else
|
||||
cnt <= cnt + 22'd1;
|
||||
|
||||
initial
|
||||
begin
|
||||
wait(cnt[16]==1'b1)
|
||||
$finish(0);
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_imp <= 22'd0;
|
||||
else if(cnt == 100)
|
||||
begin
|
||||
din_imp <= 16'd32767;
|
||||
//en <= 1'b1;
|
||||
end
|
||||
else
|
||||
din_imp <= 'h0;
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
din_rect <= 22'd0;
|
||||
else if(cnt >= 100 && cnt <=10100)
|
||||
begin
|
||||
din_rect <= 16'd30000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
din_rect <= 16'd0;
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
en <= 22'd0;
|
||||
else if(cnt >= 90 )
|
||||
begin
|
||||
en <= 1'b1;
|
||||
end
|
||||
|
||||
always@(posedge clk_l or negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
din_cos <= 16'd0;
|
||||
iir_in <= 16'd0;
|
||||
end
|
||||
else
|
||||
din_cos <= {cos[15],cos[15:1]};
|
||||
|
||||
assign source_mode = 2'b01;
|
||||
|
||||
always @(*)
|
||||
|
||||
case(source_mode)
|
||||
2'b00 : iir_in = din_imp;
|
||||
2'b01 : iir_in = din_rect;
|
||||
2'b10 : iir_in = din_cos;
|
||||
endcase
|
||||
|
||||
|
||||
|
||||
|
||||
NCO inst_nco_0(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.phase_manual_clr (1'b0 ),
|
||||
.phase_auto_clr (1'b0 ),
|
||||
.fcw (fcw ),
|
||||
.pha (16'd0 ),
|
||||
.cos (cos ),
|
||||
.sin (sin )
|
||||
);
|
||||
|
||||
|
||||
wire [15:0] dout_p0;
|
||||
wire [15:0] dout_p1;
|
||||
wire [15:0] dout_p2;
|
||||
wire [15:0] dout_p3;
|
||||
wire [15:0] dout_p4;
|
||||
wire [15:0] dout_p5;
|
||||
wire [15:0] dout_p6;
|
||||
wire [15:0] dout_p7;
|
||||
|
||||
wire [1:0] intp_mode;
|
||||
assign intp_mode = 2'b11;
|
||||
|
||||
wire [1:0] dac_mode_sel;
|
||||
assign dac_mode_sel = 2'b00;
|
||||
|
||||
wire tc_bypass;
|
||||
assign tc_bypass = 1'b0;
|
||||
|
||||
z_dsp_en_Test inst_Z_dsp_en_Test
|
||||
(
|
||||
.clk (clk_h ),
|
||||
.rstn (rstn ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout_p0 ),
|
||||
.dout1 (dout_p1 ),
|
||||
.dout2 (dout_p2 ),
|
||||
.dout3 (dout_p3 ),
|
||||
.dout4 (dout_p4 ),
|
||||
.dout5 (dout_p5 ),
|
||||
.dout6 (dout_p6 ),
|
||||
.dout7 (dout_p7 ),
|
||||
.vldo (vldo ),
|
||||
.saturation_0 ( ),
|
||||
.saturation_1 ( ),
|
||||
.saturation_2 ( ),
|
||||
.saturation_3 ( ),
|
||||
.saturation_4 ( ),
|
||||
.saturation_5 ( )
|
||||
|
||||
|
||||
);
|
||||
|
||||
wire [15:0] dout_clkl_p0;
|
||||
wire [15:0] dout_clkl_p1;
|
||||
wire [15:0] dout_clkl_p2;
|
||||
wire [15:0] dout_clkl_p3;
|
||||
wire [15:0] dout_clkl_p4;
|
||||
wire [15:0] dout_clkl_p5;
|
||||
wire [15:0] dout_clkl_p6;
|
||||
wire [15:0] dout_clkl_p7;
|
||||
|
||||
|
||||
z_dsp_en_Test inst_z_dsp_en_Test
|
||||
(
|
||||
.clk (clk_l ),
|
||||
.rstn (rstn ),
|
||||
.tc_bypass (tc_bypass ),
|
||||
.dac_mode_sel (dac_mode_sel ),
|
||||
.intp_mode (intp_mode ),
|
||||
.din_re (iir_in ),
|
||||
.din_im (din_im ),
|
||||
.a0_re (a0_re ),
|
||||
.a0_im (a0_im ),
|
||||
.b0_re (b0_re ),
|
||||
.b0_im (b0_im ),
|
||||
.a1_re (a1_re ),
|
||||
.a1_im (a1_im ),
|
||||
.b1_re (b1_re ),
|
||||
.b1_im (b1_im ),
|
||||
.a2_re (a2_re ),
|
||||
.a2_im (a2_im ),
|
||||
.b2_re (b2_re ),
|
||||
.b2_im (b2_im ),
|
||||
.a3_re (a3_re ),
|
||||
.a3_im (a3_im ),
|
||||
.b3_re (b3_re ),
|
||||
.b3_im (b3_im ),
|
||||
.a4_re (a4_re ),
|
||||
.a4_im (a4_im ),
|
||||
.b4_re (b4_re ),
|
||||
.b4_im (b4_im ),
|
||||
.a5_re (a5_re ),
|
||||
.a5_im (a5_im ),
|
||||
.b5_re (b5_re ),
|
||||
.b5_im (b5_im ),
|
||||
.dout0 (dout_clkl_p0 ),
|
||||
.dout1 (dout_clkl_p1 ),
|
||||
.dout2 (dout_clkl_p2 ),
|
||||
.dout3 (dout_clkl_p3 ),
|
||||
.dout4 (dout_clkl_p4 ),
|
||||
.dout5 (dout_clkl_p5 ),
|
||||
.dout6 (dout_clkl_p6 ),
|
||||
.dout7 (dout_clkl_p7 )
|
||||
|
||||
);
|
||||
|
||||
reg [15:0] dout_p0_r1 = 0;
|
||||
reg [15:0] dout_p1_r1 = 0;
|
||||
reg [15:0] dout_p2_r1 = 0;
|
||||
reg [15:0] dout_p3_r1 = 0;
|
||||
reg [15:0] dout_p4_r1 = 0;
|
||||
reg [15:0] dout_p5_r1 = 0;
|
||||
reg [15:0] dout_p6_r1 = 0;
|
||||
reg [15:0] dout_p7_r1 = 0;
|
||||
reg [15:0] dout_p0_r2 = 0;
|
||||
reg [15:0] dout_p1_r2 = 0;
|
||||
reg [15:0] dout_p2_r2 = 0;
|
||||
reg [15:0] dout_p3_r2 = 0;
|
||||
reg [15:0] dout_p4_r2 = 0;
|
||||
reg [15:0] dout_p5_r2 = 0;
|
||||
reg [15:0] dout_p6_r2 = 0;
|
||||
reg [15:0] dout_p7_r2 = 0;
|
||||
reg [15:0] dout_p0_r3 = 0;
|
||||
reg [15:0] dout_p1_r3 = 0;
|
||||
reg [15:0] dout_p2_r3 = 0;
|
||||
reg [15:0] dout_p3_r3 = 0;
|
||||
reg [15:0] dout_p4_r3 = 0;
|
||||
reg [15:0] dout_p5_r3 = 0;
|
||||
reg [15:0] dout_p6_r3 = 0;
|
||||
reg [15:0] dout_p7_r3 = 0;
|
||||
|
||||
|
||||
always @(posedge clk_h or negedge rstn ) begin
|
||||
if(!rstn) begin
|
||||
dout_p0_r1 <= 0;
|
||||
dout_p1_r1 <= 0;
|
||||
dout_p2_r1 <= 0;
|
||||
dout_p3_r1 <= 0;
|
||||
dout_p4_r1 <= 0;
|
||||
dout_p5_r1 <= 0;
|
||||
dout_p6_r1 <= 0;
|
||||
dout_p7_r1 <= 0;
|
||||
dout_p0_r2 <= 0;
|
||||
dout_p1_r2 <= 0;
|
||||
dout_p2_r2 <= 0;
|
||||
dout_p3_r2 <= 0;
|
||||
dout_p4_r2 <= 0;
|
||||
dout_p5_r2 <= 0;
|
||||
dout_p6_r2 <= 0;
|
||||
dout_p7_r2 <= 0;
|
||||
dout_p0_r3 <= 0;
|
||||
dout_p1_r3 <= 0;
|
||||
dout_p2_r3 <= 0;
|
||||
dout_p3_r3 <= 0;
|
||||
dout_p4_r3 <= 0;
|
||||
dout_p5_r3 <= 0;
|
||||
dout_p6_r3 <= 0;
|
||||
dout_p7_r3 <= 0;
|
||||
end
|
||||
else begin
|
||||
dout_p0_r1 <= dout_p0;
|
||||
dout_p1_r1 <= dout_p1;
|
||||
dout_p2_r1 <= dout_p2;
|
||||
dout_p3_r1 <= dout_p3;
|
||||
dout_p4_r1 <= dout_p4;
|
||||
dout_p5_r1 <= dout_p5;
|
||||
dout_p6_r1 <= dout_p6;
|
||||
dout_p7_r1 <= dout_p7;
|
||||
dout_p0_r2 <= dout_p0_r1;
|
||||
dout_p1_r2 <= dout_p1_r1;
|
||||
dout_p2_r2 <= dout_p2_r1;
|
||||
dout_p3_r2 <= dout_p3_r1;
|
||||
dout_p4_r2 <= dout_p4_r1;
|
||||
dout_p5_r2 <= dout_p5_r1;
|
||||
dout_p6_r2 <= dout_p6_r1;
|
||||
dout_p7_r2 <= dout_p7_r1;
|
||||
dout_p0_r3 <= dout_p0_r2;
|
||||
dout_p1_r3 <= dout_p1_r2;
|
||||
dout_p2_r3 <= dout_p2_r2;
|
||||
dout_p3_r3 <= dout_p3_r2;
|
||||
dout_p4_r3 <= dout_p4_r2;
|
||||
dout_p5_r3 <= dout_p5_r2;
|
||||
dout_p6_r3 <= dout_p6_r2;
|
||||
dout_p7_r3 <= dout_p7_r2;
|
||||
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] cs_wave = 0;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave = dout_p3;
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_7) cs_wave = dout_p0_r3;//f
|
||||
@(posedge clk_div32_5) cs_wave = dout_p1_r3;//d
|
||||
@(posedge clk_div32_3) cs_wave = dout_p2_r3;//b
|
||||
@(posedge clk_div32_1) cs_wave = dout_p3_r3;//9
|
||||
@(posedge clk_div32_f) cs_wave = dout_p4_r3;//7
|
||||
@(posedge clk_div32_d) cs_wave = dout_p5_r3;//5
|
||||
@(posedge clk_div32_b) cs_wave = dout_p6_r3;//3
|
||||
@(posedge clk_div32_9) cs_wave = dout_p7_r3;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
reg [15:0] cs_wave1 = 0;
|
||||
|
||||
always@(*)
|
||||
fork
|
||||
case (intp_mode)
|
||||
2'b00 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
end
|
||||
2'b01 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p1;
|
||||
end
|
||||
2'b10 :
|
||||
begin
|
||||
@(posedge clk_div16_e) cs_wave1 = dout_p0;
|
||||
@(posedge clk_div16_a) cs_wave1 = dout_p1;
|
||||
@(posedge clk_div16_6) cs_wave1 = dout_p2;
|
||||
@(posedge clk_div16_2) cs_wave1 = dout_p3;
|
||||
end
|
||||
2'b11 :
|
||||
begin
|
||||
@(posedge clk_div32_7) cs_wave1 = dout_clkl_p0;//f
|
||||
@(posedge clk_div32_5) cs_wave1 = dout_clkl_p1;//d
|
||||
@(posedge clk_div32_3) cs_wave1 = dout_clkl_p2;//b
|
||||
@(posedge clk_div32_1) cs_wave1 = dout_clkl_p3;//9
|
||||
@(posedge clk_div32_f) cs_wave1 = dout_clkl_p4;//7
|
||||
@(posedge clk_div32_d) cs_wave1 = dout_clkl_p5;//5
|
||||
@(posedge clk_div32_b) cs_wave1 = dout_clkl_p6;//3
|
||||
@(posedge clk_div32_9) cs_wave1 = dout_clkl_p7;//1
|
||||
end
|
||||
|
||||
endcase
|
||||
join
|
||||
|
||||
|
||||
wire [15:0] diff;
|
||||
assign diff = cs_wave1 - cs_wave;
|
||||
integer signed In_fid;
|
||||
integer signed OrgOut_fid;
|
||||
|
||||
initial begin
|
||||
#0;
|
||||
In_fid = $fopen("./in.dat") ;
|
||||
OrgOut_fid = $fopen("./OrgOut.dat");
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk_div32_f)
|
||||
if(cnt >= 90) begin
|
||||
$fwrite(In_fid, "%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.din_re));
|
||||
$fwrite(OrgOut_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.dout ));
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue