diff --git a/sim/Makefile b/sim/Makefile
new file mode 100644
index 0000000..371a70e
--- /dev/null
+++ b/sim/Makefile
@@ -0,0 +1,19 @@
+VCS  = vcs -full64  -sverilog +lint=TFIPC-L +v2k -debug_access+all  -q -timescale=1ns/1ps +nospecify  -l compile.log
+
+SIMV = ./simv -l sim.log
+
+all:comp run
+
+comp:
+	${VCS} -f files.f
+
+run:
+	${SIMV}
+
+dbg:
+	verdi -f files.f -top TB -nologo &
+file: 
+	find ../ -name "*.*v" > files.f
+
+clean:
+	rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~
diff --git a/sim/files.f b/sim/files.f
new file mode 100644
index 0000000..418ad70
--- /dev/null
+++ b/sim/files.f
@@ -0,0 +1,22 @@
+../rtl/Tail/diff.v
+../rtl/Tail/DW02_mult.v
+../rtl/Tail/IIR_Filter.v
+../rtl/Tail/lsdacif.v
+../rtl/Tail/MeanIntp_8.v
+../rtl/Tail/mult_C.v
+../rtl/Tail/TailCorr_top.v
+//../rtl/Tail/z_dsp.v
+../rtl/Tail/sirv_gnrl_dffs.v
+../rtl/Tail/sirv_gnrl_xchecker.v
+../rtl/nco/coef_s.v
+../rtl/nco/nco.v
+../rtl/nco/coef_c.v
+../rtl/nco/ph2amp.v
+../rtl/nco/sin_op.v
+../rtl/nco/p_nco.v
+../rtl/nco/pipe_add_48bit.v
+../rtl/nco/cos_op.v
+../rtl/nco/pipe_acc_48bit.v
+../rtl/nco/DW_mult_pipe.v
+../tb/tb_mean8_top.v
+../tb/clk_gen.v