diff --git a/rtl/IIR_Filter.v b/rtl/IIR_Filter.v
index 5c316c9..43c2451 100644
--- a/rtl/IIR_Filter.v
+++ b/rtl/IIR_Filter.v
@@ -31,75 +31,81 @@
 //  Synthesizable (y/n): 
 //  Other:
 //-FHDR--------------------------------------------------------------------------------------------------------
+
+parameter  data_in_width       = 16; 
+parameter  coef_width          = 32; 
+parameter  frac_data_out_width = 20;//X for in,5
+parameter  frac_coef_width     = 31;//division
+parameter  feedback_width      = 36; 
+parameter  data_out_width      = 36;  
+parameter  saturation_mode     =  0;
+parameter  out_reg             =  1;
+
 module  IIR_Filter (
-                         rstn,
-                         en,
-                         clk,
-                         din_re,
-                         din_im,
-                         a_re,
-                         a_im,
-                         b_re,
-                         b_im,
-                         dout
+ input	 rstn
+,input	 clk
+,input	 en
+,input   signed	[data_in_width-1:0]   din_re
+,input   signed	[data_in_width-1:0]   din_im
+,input   signed	[coef_width-1   :0]   a_re
+,input   signed	[coef_width-1   :0]   a_im
+,input   signed	[coef_width-1   :0]   b_re
+,input   signed	[coef_width-1   :0]   b_im
+
+,output  signed	[data_in_width-1:0]   dout
                    );
 
-input	                 rstn;
-input	                 clk;
-input	                 en;
-input   signed	[15:0]   din_re;
-input   signed	[15:0]   din_im;
-input   signed	[36:0]   a_re;
-input   signed	[36:0]   a_im;
-input   signed	[20:0]   b_re;
-input   signed	[20:0]   b_im;
 
-output  signed	[15:0]   dout;
-
-wire	signed	[31:0] 	 x1_re;
-wire	signed	[31:0]	 x1_im;
-wire	signed	[31:0] 	 x2_re;
-wire	signed	[31:0]	 x2_im;
-wire	signed	[31:0] 	 v_re;
-wire	signed	[31:0]	 v_im;
-reg 	signed	[31:0]	 v1_re;
-reg 	signed	[31:0]	 v1_im;
-
-wire    signed	[31:0]	 y_re;
-wire    signed	[31:0]	 y_im;
-wire    signed	[31:0]	 y1_re;
-wire    signed	[31:0]	 y1_im;
-wire    signed	[31:0]	 y2_re;
-wire    signed	[31:0]	 y2_im;
-
-reg 	signed	[15:0]   dout_re;
-
-mult_C	#(16,16,37,37)	inst_c1         (
+wire	signed	[data_in_width+frac_data_out_width:0] 	 x1_re;
+wire	signed	[data_in_width+frac_data_out_width:0]	 x1_im;
+mult_C
+#(
+ .A_width(data_in_width) 
+,.B_width(data_in_width) 
+,.C_width(coef_width+frac_data_out_width) 
+,.D_width(coef_width+frac_data_out_width) 
+,.frac_coef_width(frac_coef_width) 
+)
+inst_c1         (
                                             .clk	(clk    	),
                                             .rstn	(rstn   	),
                                             .en		(en     	),
                                             .a		(din_re		),
                                             .b		(din_im		),
-                                            .c		(a_re		),
-                                            .d		(a_im		),
-                                            .Re		(x1_re   	),
+                                            .c		({a_re,{frac_data_out_width{1'b0}}}),
+                                            .d		({a_im,{frac_data_out_width{1'b0}}}),
+                                            .Re		(x1_re   	),//a*x(n)
                                             .Im		(x1_im   	)
-				);
-
-mult_C	#(32,32,21,21)	inst_c2         (
+	        );
+wire	signed	[data_in_width+frac_data_out_width+1:0]  x2_re;
+wire	signed	[data_in_width+frac_data_out_width+1:0]	 x2_im;
+mult_C	
+#(
+ .A_width(data_in_width+frac_data_out_width+1) 
+,.B_width(data_in_width+frac_data_out_width+1) 
+,.C_width(coef_width) 
+,.D_width(coef_width) 
+,.frac_coef_width(frac_coef_width) 
+)
+inst_c2         (
                                             .clk	(clk    	),
                                             .rstn	(rstn   	),
                                             .en		(en     	),
-                                            .a		(x1_re		),
+                                            .a		(x1_re		),//a*x(n)
                                             .b		(x1_im		),
                                             .c		(b_re	  	),
                                             .d		(b_im	  	),
-                                            .Re		(x2_re     	),
+                                            .Re		(x2_re     	),//a*b*x(n-1)
                                             .Im		(x2_im     	)
-				);
+		);
+wire	signed	[data_in_width+frac_data_out_width+1:0]  v_re;
+wire	signed	[data_in_width+frac_data_out_width+1:0]	 v_im;
 
-assign	v_re       =   x1_re - x2_re;
-assign	v_im       =   x1_im - x2_im;
+assign	v_re       =   x1_re + x2_re;
+assign	v_im       =   x1_im + x2_im;
+
+reg	signed	[data_in_width+frac_data_out_width+1:0]  v1_re;
+reg	signed	[data_in_width+frac_data_out_width+1:0]	 v1_im;
 
 always @(posedge clk or negedge rstn) 
   	if (!rstn)
@@ -118,19 +124,44 @@ always @(posedge clk or negedge rstn)
                 v1_im    <=    v1_im;
 		  end
 
-mult_C	#(32,32,21,21)	inst_c3         (
+wire    signed	[data_in_width+frac_data_out_width+1:0]	 y_re;
+wire    signed	[data_in_width+frac_data_out_width+1:0]	 y_im;
+wire    signed	[data_in_width+frac_data_out_width+1:0]	 y1_re;
+wire    signed	[data_in_width+frac_data_out_width+1:0]	 y1_im;
+wire    signed	[data_in_width+frac_data_out_width+1:0]	 y2_re;
+wire    signed	[data_in_width+frac_data_out_width+1:0]	 y2_im;
+
+reg 	signed	[data_in_width-1:0]   dout_re;
+
+mult_C
+#(
+ .A_width(data_in_width+frac_data_out_width+2) 
+,.B_width(data_in_width+frac_data_out_width+2) 
+,.C_width(coef_width) 
+,.D_width(coef_width) 
+,.frac_coef_width(frac_coef_width) 
+)
+inst_c3         (
                                             .clk	(clk    	),
                                             .rstn	(rstn   	),
                                             .en		(en     	),
-                                            .a		(y_re		),
+                                            .a		(y_re		),//y(n)=a*x(n)+a*b*x(n-1)+b^2*y(n-2)
                                             .b		(y_im		),
                                             .c		(b_re	  	),
                                             .d		(b_im	  	),
-                                            .Re		(y1_re     	),
+                                            .Re		(y1_re     	),//b*y(n-1)
                                             .Im		(y1_im     	)
-				);
+		);
 
-mult_C	#(32,32,21,21)	inst_c4         (
+mult_C	
+#(
+ .A_width(data_in_width+frac_data_out_width+2) 
+,.B_width(data_in_width+frac_data_out_width+2) 
+,.C_width(coef_width) 
+,.D_width(coef_width) 
+,.frac_coef_width(frac_coef_width) 
+)
+inst_c4         (
                                             .clk	(clk    	),
                                             .rstn	(rstn   	),
                                             .en		(en     	),
@@ -138,13 +169,34 @@ mult_C	#(32,32,21,21)	inst_c4         (
                                             .b		(y1_im		),
                                             .c		(b_re	  	),
                                             .d		(b_im	  	),
-                                            .Re		(y2_re     	),
+                                            .Re		(y2_re     	),//b^2*y(n-2)
                                             .Im		(y2_im     	)
-				);
+		);
 
 assign	y_re       =   v1_re + y2_re;
 assign	y_im       =   v1_im + y2_im;
 
+reg signed	[data_in_width+frac_data_out_width+2:0] dout_round;
+
+always@(posedge clk or negedge rstn)
+	if(!rstn)
+		begin
+		dout_round <= 'h0;
+		end
+	else  if(en)  begin
+		if(y_re[data_in_width+frac_data_out_width+1] == 1'b0)
+			begin
+				dout_round <= y_re + {{1'b1},{(frac_data_out_width-1){1'b0}}};
+			end
+		else if (y_re[data_in_width+frac_data_out_width+1] == 1'b1)
+			begin	
+				dout_round <= y_re + {{1'b1},{(frac_data_out_width-1){1'b0}}} - 1'b1;
+			end
+	end
+	else  begin
+		dout_round <=  dout_round;
+	end
+
 always @(posedge clk or negedge rstn) 
   	if (!rstn)
 		 begin
@@ -152,7 +204,7 @@ always @(posedge clk or negedge rstn)
 		 end 
 	 else if(en)
 		 begin
-		    dout_re  <= y_re[31:16];
+		    dout_re  <= dout_round[data_in_width+frac_data_out_width+2:frac_data_out_width];
 		  end
 	 else
 		 begin
diff --git a/rtl/TailCorr_top.v b/rtl/TailCorr_top.v
index 40d6f7a..8eb0d46 100644
--- a/rtl/TailCorr_top.v
+++ b/rtl/TailCorr_top.v
@@ -71,32 +71,32 @@ input rstn;
 input clk;
 input  en;
 input  tc_bypass;
-input  signed [15:0] din_re;
-input  signed [15:0] din_im;
-input  signed [36:0] a0_re;
-input  signed [36:0] a0_im;
-input  signed [20:0] b0_re;
-input  signed [20:0] b0_im;
-input  signed [36:0] a1_re;
-input  signed [36:0] a1_im;
-input  signed [20:0] b1_re;
-input  signed [20:0] b1_im;
-input  signed [36:0] a2_re;
-input  signed [36:0] a2_im;
-input  signed [20:0] b2_re;
-input  signed [20:0] b2_im;
-input  signed [36:0] a3_re;
-input  signed [36:0] a3_im;
-input  signed [20:0] b3_re;
-input  signed [20:0] b3_im;
-input  signed [36:0] a4_re;
-input  signed [36:0] a4_im;
-input  signed [20:0] b4_re;
-input  signed [20:0] b4_im;
-input  signed [36:0] a5_re;
-input  signed [36:0] a5_im;
-input  signed [20:0] b5_re;
-input  signed [20:0] b5_im;
+input  signed [31:0] din_re;
+input  signed [31:0] din_im;
+input  signed [31:0] a0_re;
+input  signed [31:0] a0_im;
+input  signed [31:0] b0_re;
+input  signed [31:0] b0_im;
+input  signed [31:0] a1_re;
+input  signed [31:0] a1_im;
+input  signed [31:0] b1_re;
+input  signed [31:0] b1_im;
+input  signed [31:0] a2_re;
+input  signed [31:0] a2_im;
+input  signed [31:0] b2_re;
+input  signed [31:0] b2_im;
+input  signed [31:0] a3_re;
+input  signed [31:0] a3_im;
+input  signed [31:0] b3_re;
+input  signed [31:0] b3_im;
+input  signed [31:0] a4_re;
+input  signed [31:0] a4_im;
+input  signed [31:0] b4_re;
+input  signed [31:0] b4_im;
+input  signed [31:0] a5_re;
+input  signed [31:0] a5_im;
+input  signed [31:0] b5_re;
+input  signed [31:0] b5_im;
 
 output signed [15:0] dout;
 
@@ -116,6 +116,8 @@ reg signed [15:0] din_r1;
 reg signed [15:0] din_r2;
 reg signed [15:0] din_r3;
 reg signed [15:0] din_r4;
+reg signed [15:0] din_r5;
+
 reg signed [15:0] dout_r;
 
 diff	inst_diffRe
@@ -223,6 +225,7 @@ always @(posedge clk or negedge rstn)
 		    din_r2  <= 'h0;
 		    din_r3  <= 'h0;
 		    din_r4  <= 'h0;
+		    din_r5  <= 'h0;
 		 end 
 	 else if(en)
 		 begin
@@ -231,6 +234,7 @@ always @(posedge clk or negedge rstn)
 		    din_r2  <= din_r1;
 		    din_r3  <= din_r2;
 		    din_r4  <= din_r3;
+		    din_r5  <= din_r4;
 		  end
 	 else
 		 begin
@@ -239,9 +243,10 @@ always @(posedge clk or negedge rstn)
 		    din_r2  <= din_r2;
 		    din_r3  <= din_r3;
 		    din_r4  <= din_r4;
+		    din_r5  <= din_r5;
 		  end
 
-assign		Ysum =       dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r4;
+assign		Ysum =       dout_0 + dout_1 + dout_2 + dout_3 + dout_4 + dout_5 + din_r5;
 
 always@(posedge clk or negedge rstn) 
   if (!rstn)begin
diff --git a/rtl/mult_C.v b/rtl/mult_C.v
index 2fa2ab1..8bbefb5 100644
--- a/rtl/mult_C.v
+++ b/rtl/mult_C.v
@@ -43,10 +43,11 @@ module mult_C(
 			Im
 );
 
-parameter	integer A_width = 8;
-parameter	integer B_width = 8;
-parameter	integer C_width = 8;
-parameter	integer D_width = 8;
+parameter    integer    A_width = 8;
+parameter    integer    B_width = 8;
+parameter    integer    C_width = 8;
+parameter    integer    D_width = 8;
+parameter    integer    frac_coef_width = 31;//division
 
 input                                       rstn;
 input                                       clk;
@@ -56,8 +57,8 @@ input       signed  [B_width-1:0]           b;
 input       signed  [C_width-1:0]           c;
 input       signed  [D_width-1:0]           d;
 
-output      signed  [A_width+C_width-22:0]  Re;
-output      signed  [A_width+D_width-22:0]  Im;
+output      signed  [A_width+C_width-frac_coef_width-1:0]  Re;
+output      signed  [A_width+D_width-frac_coef_width-1:0]  Im;
 
 wire	    signed	[A_width+C_width-1:0]	ac;
 wire	    signed	[B_width+D_width-1:0]	bd;
@@ -107,7 +108,7 @@ always@(posedge clk or negedge rstn)
 				Im_tmp	<=	Im_tmp;
 			 end 
 
-assign	Re = Re_tmp[A_width+D_width-1:20];
-assign	Im = Im_tmp[A_width+D_width-1:20];
+assign	Re = Re_tmp[A_width+D_width-1:frac_coef_width];
+assign	Im = Im_tmp[A_width+D_width-1:frac_coef_width];
 
 endmodule
diff --git a/rtl/z_dsp.v b/rtl/z_dsp.v
index 5fb2b28..28d79f1 100644
--- a/rtl/z_dsp.v
+++ b/rtl/z_dsp.v
@@ -85,30 +85,30 @@ input  [1:0]	intp_mode;
 input  [1:0]	dac_mode_sel;
 input  signed [15:0] din_re;
 input  signed [15:0] din_im;
-input  signed [36:0] a0_re;
-input  signed [36:0] a0_im;
-input  signed [20:0] b0_re;
-input  signed [20:0] b0_im;
-input  signed [36:0] a1_re;
-input  signed [36:0] a1_im;
-input  signed [20:0] b1_re;
-input  signed [20:0] b1_im;
-input  signed [36:0] a2_re;
-input  signed [36:0] a2_im;
-input  signed [20:0] b2_re;
-input  signed [20:0] b2_im;
-input  signed [36:0] a3_re;
-input  signed [36:0] a3_im;
-input  signed [20:0] b3_re;
-input  signed [20:0] b3_im;
-input  signed [36:0] a4_re;
-input  signed [36:0] a4_im;
-input  signed [20:0] b4_re;
-input  signed [20:0] b4_im;
-input  signed [36:0] a5_re;
-input  signed [36:0] a5_im;
-input  signed [20:0] b5_re;
-input  signed [20:0] b5_im;
+input  signed [31:0] a0_re;
+input  signed [31:0] a0_im;
+input  signed [31:0] b0_re;
+input  signed [31:0] b0_im;
+input  signed [31:0] a1_re;
+input  signed [31:0] a1_im;
+input  signed [31:0] b1_re;
+input  signed [31:0] b1_im;
+input  signed [31:0] a2_re;
+input  signed [31:0] a2_im;
+input  signed [31:0] b2_re;
+input  signed [31:0] b2_im;
+input  signed [31:0] a3_re;
+input  signed [31:0] a3_im;
+input  signed [31:0] b3_re;
+input  signed [31:0] b3_im;
+input  signed [31:0] a4_re;
+input  signed [31:0] a4_im;
+input  signed [31:0] b4_re;
+input  signed [31:0] b4_im;
+input  signed [31:0] a5_re;
+input  signed [31:0] a5_im;
+input  signed [31:0] b5_re;
+input  signed [31:0] b5_im;
 
 output signed [15:0] dout0;
 output signed [15:0] dout1;
diff --git a/script_m/MeanIntp.m b/script_m/MeanIntp.m
deleted file mode 100755
index e14a871..0000000
--- a/script_m/MeanIntp.m
+++ /dev/null
@@ -1,6 +0,0 @@
-%%% so means original, s_mean means mean value
-function [s,s_mean] = MeanIntp(s,s_r1)
-
-    s_mean = (s+s_r1)/2;
-
-end
diff --git a/script_m/MyIIR.m b/script_m/MyIIR.m
deleted file mode 100755
index cc739bc..0000000
--- a/script_m/MyIIR.m
+++ /dev/null
@@ -1,35 +0,0 @@
-function out = MyIIR(a,b,x,YStartState,sel_double)
-
-len = length(x);
-
-switch sel_double 
-    case 0
-        x = int64(x);
-        a = int64(a);
-        b = int64(b);
-        y(1) = int64(YStartState);
-    case 1
-        x = double(x);
-        a = double(a);
-        b = double(b);
-        y(1) = double(YStartState);
-end
-
-switch sel_double 
-
-    case 0
-
-        for i = 1:len-1       
-            y_tmp(i+1) = a*x(i+1) - b*y(i)';
-            y(i+1) = bitsra(y_tmp(i+1),20) + bitget(y_tmp(i+1),64);       
-        end
-        out = bitsra(y,16);
-
-    case 1
-
-        for i = 1:len-1
-            y_tmp(i+1) = floor(a*x(i+1) - b*y(i)');
-            y(i+1) = floor(y_tmp(i+1)/2^20) + bitget(int64(y_tmp(i+1)),64);    
-        end
-        out = floor(y/2^16);
-end
diff --git a/script_m/MyIIR_test.m b/script_m/MyIIR_test.m
deleted file mode 100755
index 66b6dd5..0000000
--- a/script_m/MyIIR_test.m
+++ /dev/null
@@ -1,31 +0,0 @@
-clc;clear;close all
-
-%%%verification of single IIR Filter by comparing matlab and verilog
-cd('/data/work/thfu/TailCorr/script_m');
-
-a = 13740916;
-b = -1047703;
-y(1) = 0;
-
-sel_double = 0;
-
-switch sel_double
-    case 0
-        iir_in = int64(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
-        iir_out = int64(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
-    case 1
-        iir_in = double(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
-        iir_out = double(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
-end
-
-Script_out = MyIIR(a,b,iir_in,y(1),sel_double)';
-y_revised = iir_in + Script_out;
-tau = finddelay(y_revised,iir_out);
-
-Script_outPhi = cat(1,zeros(1,tau)',Script_out(1:end-tau,1));
-
-n = 1:length(iir_in);
-diff = iir_out(n)-Script_outPhi(n);
-
-diff_plot(iir_out, Script_outPhi)
-tau
diff --git a/script_m/PolyMean_Test.m b/script_m/PolyMean_Test.m
deleted file mode 100755
index d6c0c52..0000000
--- a/script_m/PolyMean_Test.m
+++ /dev/null
@@ -1,45 +0,0 @@
-%%%verification of polyphase structures using trig
-clc;clear all;close all
-
-fs = 1e8;
-t = (0:1:1e2)'/fs;
-% f = 20e6;
-% s = sin(2*pi*f*t);
-s = triang(1e2-1);
-s = [zeros(1,10) s' zeros(1,10)]';
-N = length(s);
-ts = (0:1:N-1)'/fs;
-%%%
-s_r1 = [0 s(1:end-1,1)']';
-[s2,s2_mean] = MeanIntp(s,s_r1);
-
-s_intp2 = zeros(2*N,1);
-s_intp2(1:2:2*N) = s2_mean;
-s_intp2(2:2:2*N) = s2;
-t_intp2 = (0:1:2*N-1)'/fs/2;
-%%%
-s2_r1 = [0 s2(1:end-1,1)']';
-
-[s4_4,s4_3] = MeanIntp(s2,s2_mean);
-[s4_2,s4_1] = MeanIntp(s2_mean,s2_r1);
-
-s_intp4 = zeros(4*N,1);
-s_intp4(1:4:4*N) = s4_1;
-s_intp4(2:4:4*N) = s4_2;
-s_intp4(3:4:4*N) = s4_3;
-s_intp4(4:4:4*N) = s4_4;
-
-t_intp4 = (0:1:4*N-1)'/fs/4;
-
-
-figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
-plot(ts,s,t_intp2,s_intp2)
-grid on
-% xlim([0.58 0.62]*1e-6)
-% 
-% 
-figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]);
-plot(t_intp4,s_intp4)
-grid on
-% xlim([0.58 0.62]*1e-6)
-
diff --git a/script_m/TailCorr.m b/script_m/TailCorr.m
deleted file mode 100755
index 8bec983..0000000
--- a/script_m/TailCorr.m
+++ /dev/null
@@ -1,27 +0,0 @@
-function out = TailCorr(alpha,beta,iir_in,YStartState,sel_double)
-
-len = length(iir_in);
-N = length(alpha);
-
-iir_inR1 = cat(1,0,iir_in(1:end-1,1));
-
-diff = iir_in - iir_inR1;
-
-Ystart = YStartState;
-
-for i = 1:1:N
-    y(1:len,i) = MyIIR(alpha(i),beta(i),diff,Ystart,sel_double);
-    y = floor(y);
-end
-
-switch sel_double 
-
-    case 0
-        y_sum = int64(sum(y,2));      
-
-    case 1
-        y_sum = double(sum(y,2));      
-
-end
-
-out = iir_in+y_sum;
diff --git a/script_m/TailCorr_8inpt_test.m b/script_m/TailCorr_8inpt_test.m
deleted file mode 100644
index dc24b6a..0000000
--- a/script_m/TailCorr_8inpt_test.m
+++ /dev/null
@@ -1,63 +0,0 @@
-%%%2024-10-15
-%%%verification 8 linear interpolation result by comparing matlab and verilog result
-clc;clear;close all
-
-cd('/data/work/thfu/TailCorr/script_m');
-
-sel_double = 0;
-
-switch sel_double
-
-    case 0
-        iir_in_verilog     = int64(importdata("/home/thfu/work/TailCorr/sim/in.dat") - 32768);
-%        iir_out_x1 = int64(importdata("/home/thfu/work/TailCorr/sim/X1_data.dat") -32768);
-%        iir_out_x2 = int64(importdata("/home/thfu/work/TailCorr/sim/X2_data.dat") -32768);
-%        iir_out_x4 = int64(importdata("/home/thfu/work/TailCorr/sim/X4_data.dat") -32768);
-        iir_out_verilog_x8 = int64(importdata("/home/thfu/work/TailCorr/sim/X8_data.dat") -32768);
-        
-    case 1
-        iir_in     = double(importdata("/home/thfu/work/TailCorr/sim/in") + 0);
-        iir_out_x1 = double(importdata("/home/thfu/work/TailCorr/sim/X1_data.dat") - 32768);
-        iir_out_x2 = double(importdata("/home/thfu/work/TailCorr/sim/X2_data.dat") - 32768);
-        iir_out_x4 = double(importdata("/home/thfu/work/TailCorr/sim/X4_data.dat") - 32768);
-        iir_out_x8 = double(importdata("/home/thfu/work/TailCorr/sim/X8_data.dat") - 32768);
-        
-end
-% iir_out_x1 = [iir_out_x1' zeros(1,2)]';
-% iir_out_x2 = [iir_out_x2' zeros(1,3)]';
-% iir_out_x4 = [iir_out_x4' zeros(1,6)]';
-
-alpha = [1757225200, 1045400392, 13740916];
-beta = -[1042856 1046395 1047703];
-
-
-Ystart = 0;
-
-y_revised_matlab = TailCorr(alpha,beta,iir_in_verilog,Ystart,sel_double);
-
-N = length(y_revised_matlab);
-x1 = (1:1:N)';
-x8 = (1:1/8:N+1-1/8)';
-y_revised_intp8_matlab = int64(interp1(x1,double(y_revised_matlab),x8,'linear'));
-
-
-%%%
-%tau0 = finddelay(y_revised_matlab,iir_out_x1);
-%y_revisedPhi0 = cat(1,zeros(1,tau0)',y_revised_matlab(1:end-tau0,1));
-%figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]);
-%diff_plot(iir_out_x1, y_revisedPhi0,'verdi','matlab',[200 N]);
-%%%
-%tau2 = finddelay(s_intp2,iir_out_x2);
-%y_revisedPhi2 = cat(1,zeros(1,tau2)',s_intp2(1:end-tau2,1));
-%figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]);
-%diff_plot(iir_out_x2, y_revisedPhi2,'verdi','matlab',[0 4e4])
-%%%
-%tau4 = finddelay(s_intp4,iir_out_x4);
-%y_revisedPhi4 = cat(1,zeros(1,tau4)',s_intp4(1:end-tau4,1));
-%figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]);
-%diff_plot(iir_out_x4, y_revisedPhi4,'verdi','matlab',[0 8e4])
-%%%
-tau8 = finddelay(y_revised_intp8_matlab,iir_out_verilog_x8);
-y_revisedPhi8 = cat(1,zeros(1,tau8)',y_revised_intp8_matlab(1:end-tau8,1));
-figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
-diff_plot(iir_out_verilog_x8, y_revisedPhi8,'verdi','matlab',[400 800]);
diff --git a/script_m/TailCorr_Test.m b/script_m/TailCorr_Test.m
new file mode 100644
index 0000000..3fead06
--- /dev/null
+++ b/script_m/TailCorr_Test.m
@@ -0,0 +1,60 @@
+%in+iir_out with 8 intp
+clc;clear;close all
+
+in         = importdata("/home/thfu/work/TailCorr/sim/in.dat");       
+wave_verdi = importdata("/home/thfu/work/TailCorr/sim/OrgOut.dat");   
+
+dout0 = importdata("/home/thfu/work/TailCorr/sim/dout0.dat");  
+dout1 = importdata("/home/thfu/work/TailCorr/sim/dout1.dat");
+dout2 = importdata("/home/thfu/work/TailCorr/sim/dout2.dat");
+dout3 = importdata("/home/thfu/work/TailCorr/sim/dout3.dat");
+
+N = length(dout0);
+cs_wave = zeros(4*N,1);
+cs_wave(1:4:4*N) = dout0;
+cs_wave(2:4:4*N) = dout1;
+cs_wave(3:4:4*N) = dout2;
+cs_wave(4:4:4*N) = dout3;
+
+A   =  [0.025 0.015 0.0002 0];
+tau = -[1/250 1/650 1/1600 0];
+fs  = 2e9;
+
+coef_len = length(A);
+for i = 1:coef_len
+    b(i) = exp(1e9/fs/(1-A(i))*tau(i));
+    a(i) = A(i)/1/(1-A(i))*exp(1e9/fs/(1-A(i))/2*tau(i));  
+    h_ideal(:,i) = filter(a(i),[1 -b(i)],diff(in));
+end
+
+wave_float = in(2:end)+ sum(h_ideal,2);
+
+wave_float_len = length(wave_float);
+wave_float_8 = interp1(1:wave_float_len,wave_float,1:1/8:(wave_float_len+1-1/8),'linear')';
+
+[cs_wave_A,wave_float_8_A,Delay] = alignsignals(cs_wave,wave_float_8);
+N = min(length(wave_float_8_A),length(cs_wave_A));
+% figure()
+% diff_plot(wave_float_8_A(90:end), cs_wave_A(154:end),'float','verdi',[0 N]);
+%
+%Test of iir filter
+[wave_float_A,wave_verdi_A,Delay] = alignsignals(wave_float,wave_verdi);
+N = min(length(wave_float_A),length(wave_verdi_A));
+figure()
+diff_plot(wave_float_A, wave_verdi_A,'float','verdi',[0 N]);
+%%
+signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
+%%
+
+a_fix = round(a*2^31);
+b_fix = round(b*2^31);
+
+a_hex = dec2hex(a_fix,8);
+b_hex = dec2hex(b_fix,8);
+
+a_bin = dec2bin(a_fix,32);
+b_bin = dec2bin(b_fix,32);
+
+fprintf('a_fix is %d\n',a_fix);
+fprintf('b_fix is %d\n',b_fix);
+
diff --git a/script_m/TailCorr_test.m b/script_m/TailCorr_test.m
deleted file mode 100755
index c4f3247..0000000
--- a/script_m/TailCorr_test.m
+++ /dev/null
@@ -1,27 +0,0 @@
-clc;clear;close all
-
-cd('/data/work/thfu/TailCorr/script_m');
-
-sel_double = 1;
-
-switch sel_double
-    case 0
-        iir_in = int64(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
-        iir_out = int64(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
-    case 1
-        iir_in = double(importdata("/home/thfu/work/TailCorr/v02/sim/in") -32768);
-        iir_out = double(importdata("/home/thfu/work/TailCorr/v02/sim/out") -32768);
-end
-
-alpha = [1757225200, 1045400392, 13740916];
-beta = -[1042856 1046395 1047703];
-
-
-Ystart = 0;
-
-y_revised = TailCorr(alpha,beta,iir_in,Ystart,sel_double);
-
-tau = finddelay(y_revised,iir_out);
-y_revisedPhi = cat(1,zeros(1,tau)',y_revised(1:end-tau,1));
-
-diff_plot(iir_out, y_revisedPhi,'verdi','matlab',[0 1e4])
diff --git a/script_m/TailCorr_test_P.m b/script_m/TailCorr_test_P.m
deleted file mode 100755
index 8dbe9ef..0000000
--- a/script_m/TailCorr_test_P.m
+++ /dev/null
@@ -1,73 +0,0 @@
-%%%20241009,comparing matlab and verilog result
-clc;clear;close all
-
-cd('/data/work/thfu/TailCorr/script_m');
-
-sel_double = 1;
-
-switch sel_double
-
-    case 0
-        iir_in     = int64(importdata("/home/thfu/work/TailCorr/Test/sim/in") -32768);
-        iir_out_x1 = int64(importdata("/home/thfu/work/TailCorr/Test/sim/X1_data.dat") -32768);
-        iir_out_x2 = int64(importdata("/home/thfu/work/TailCorr/Test/sim/X2_data.dat") -32768);
-        iir_out_x4 = int64(importdata("/home/thfu/work/TailCorr/Test/sim/X4_data.dat") -32768);
-    case 1
-        iir_in     = double(importdata("/home/thfu/work/TailCorr/Test/sim/in") + 0);
-        iir_out_x1 = double(importdata("/home/thfu/work/TailCorr/Test/sim/X1_data.dat") - 32768);
-        iir_out_x2 = double(importdata("/home/thfu/work/TailCorr/Test/sim/X2_data.dat") - 32768);
-        iir_out_x4 = double(importdata("/home/thfu/work/TailCorr/Test/sim/X4_data.dat") - 32768);
-        
-end
-% iir_out_x1 = [iir_out_x1' zeros(1,2)]';
-% iir_out_x2 = [iir_out_x2' zeros(1,3)]';
-% iir_out_x4 = [iir_out_x4' zeros(1,6)]';
-
-alpha = [1757225200, 1045400392, 13740916];
-beta = -[1042856 1046395 1047703];
-
-
-Ystart = 0;
-
-y_revised = TailCorr(alpha,beta,iir_in,Ystart,sel_double);
-
-s = round(y_revised);
-N = length(s);
-
-s_r1 = [0 s(1:end-1,1)']';
-[s2,s2_mean] = MeanIntp(s,s_r1);
-s2 = floor(s2);
-s2_mean = floor(s2_mean);
-
-s2_r1 = [0 s2(1:end-1,1)']';
-[s4_4,s4_3] = MeanIntp(s2,s2_mean);
-[s4_2,s4_1] = MeanIntp(s2_mean,s2_r1);
-s4_1 = floor(s4_1);
-s4_2 = floor(s4_2);
-s4_3 = floor(s4_3);
-s4_4 = floor(s4_4);
-
-s_intp2 = zeros(2*N,1);
-s_intp2(1:2:2*N) = s2_mean;
-s_intp2(2:2:2*N) = s2;
-
-s_intp4 = zeros(4*N,1);
-s_intp4(1:4:4*N) = s4_1;
-s_intp4(2:4:4*N) = s4_2;
-s_intp4(3:4:4*N) = s4_3;
-s_intp4(4:4:4*N) = s4_4;
-%%%
-tau1 = finddelay(y_revised,iir_out_x1);
-y_revisedPhi1 = cat(1,zeros(1,tau1)',y_revised(1:end-tau1,1));
-figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
-diff_plot(iir_out_x1, y_revisedPhi1,'verdi','matlab',[0 2e4])
-
-tau2 = finddelay(s_intp2,iir_out_x2);
-y_revisedPhi2 = cat(1,zeros(1,tau2)',s_intp2(1:end-tau2,1));
-figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]);
-diff_plot(iir_out_x2, y_revisedPhi2,'verdi','matlab',[0 4e4])
-
-tau4 = finddelay(s_intp4,iir_out_x4);
-y_revisedPhi4 = cat(1,zeros(1,tau4)',s_intp4(1:end-tau4,1));
-figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]);
-diff_plot(iir_out_x4, y_revisedPhi4,'verdi','matlab',[0 8e4])
\ No newline at end of file
diff --git a/script_m/diff_plot.m b/script_m/diff_plot.m
index 19bf93a..8e1cdee 100755
--- a/script_m/diff_plot.m
+++ b/script_m/diff_plot.m
@@ -6,7 +6,8 @@ Script_out = Script_out(1:N);
 n = 0:1:N-1;
 diff = iir_out-Script_out;
 
-subplot(211)
+tiledlayout(2,1)
+ax1 = nexttile;
 plot(n,iir_out,n,Script_out)
 xlabel('n')
 legend(leg1,leg2)
@@ -14,15 +15,20 @@ xlim(a)
 title('time domain')
 grid on
 
-subplot(212)
+ax2 = nexttile;
 plot(n,diff)
 xlabel('n')
 title('diff')
 grid on
 hold on
 xlim(a)
+linkaxes([ax1,ax2],'x');
 
-[diff_max,R_mpos] = max(abs(diff));
-plot(n(R_mpos),diff(R_mpos),'r*')
-text(n(R_mpos), diff(R_mpos), ['(',num2str(n(R_mpos)),',',num2str(diff(R_mpos)),')'],'color','k');
-% max(abs(diff))
\ No newline at end of file
+[~,R_mpos_max] = max(diff);
+[~,R_mpos_min] = min(diff);
+
+plot(n(R_mpos_max),diff(R_mpos_max),'r*')
+plot(n(R_mpos_min),diff(R_mpos_min),'r*')
+
+text(n(R_mpos_max), diff(R_mpos_max), ['(',num2str(n(R_mpos_max)),',',num2str(diff(R_mpos_max)),')'],'color','k');
+text(n(R_mpos_min), diff(R_mpos_min), ['(',num2str(n(R_mpos_min)),',',num2str(diff(R_mpos_min)),')'],'color','k');
diff --git a/script_m/intp8_Test.m b/script_m/intp8_Test.m
deleted file mode 100755
index dfd425f..0000000
--- a/script_m/intp8_Test.m
+++ /dev/null
@@ -1,21 +0,0 @@
-%%%2024-10-17,verify 8 intp by comparing matlab and verilog
-clc;clear all;close all;
-
-in = importdata("/home/thfu/work/TailCorr/sim/in_intp8.dat");
-intp8_verilog = importdata("/home/thfu/work/TailCorr/sim/out_intp8.dat");
-
-N = length(in);
-time = 1:1:N;
-time8 = 1:1/8:N+1-1/8;
-intp8_matlab = floor(interp1(time,in,time8,'linear'))';
-
-%figure
-%plot(time,in);
-%hold on
-%plot(time8,intp8_verilog);
-%xlim([4500 5500])
-
-tau8 = finddelay(intp8_matlab(1.8e4:3e4),intp8_verilog(1.8e4:3e4));
-intp8_matlab_revised = cat(1,zeros(1,tau8)',intp8_matlab(1:end-tau8,1));
-figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]);
-diff_plot(intp8_verilog, intp8_matlab_revised,'verdi','matlab',[2e4 2.2e4]);
diff --git a/tb/tb_z_dsp_en_Test.v b/tb/tb_z_dsp_en_Test.v
index f2e7606..d73e905 100644
--- a/tb/tb_z_dsp_en_Test.v
+++ b/tb/tb_z_dsp_en_Test.v
@@ -54,6 +54,15 @@ reg             clk;
 reg             clk_div2;
 reg             clk_div4;
 
+//a_fix is 55007237
+//a_fix is 32690030
+//a_fix is 429516
+//a_fix is 0
+//b_fix is 2143083068
+//b_fix is 2145807236
+//b_fix is 2146812530
+//b_fix is 2147483648
+
 initial 
 begin
                 #0;
@@ -64,29 +73,33 @@ begin
                 en  =   1'b0; 
 
                 din_im  =        16'd0;
-                a0_re   =        32'd1757225200;
-                a0_im   =        32'd0;
-                b0_re   =       -32'd1042856;
-                b0_im   =        32'd0;
-                a1_re   =        32'd1045400392;
-                a1_im   =        32'd0;
-                b1_re   =       -32'd1046395;
-                b1_im   =        32'd0;
-                a2_re   =        32'd13740916;
-                a2_im   =        32'd0;
-                b2_re   =       -32'd1047703;
-                b2_im   =        32'd0;
+
+                a0_re   =        32'd55007237 ;
+                a1_re   =        32'd32690030 ;
+                a2_re   =        32'd429516;
                 a3_re   =        32'd0;
-                a3_im   =        32'd0;
-                b3_re   =       -32'd0;
-                b3_im   =        32'd0;
                 a4_re   =        32'd0;
-                a4_im   =        32'd0;
-                b4_re   =       -32'd0;
-                b4_im   =        32'd0;
                 a5_re   =        32'd0;
+
+                a0_im   =        32'd0;
+                a1_im   =        32'd0;
+                a2_im   =        32'd0;
+                a3_im   =        32'd0;
+                a4_im   =        32'd0;
                 a5_im   =        32'd0;
-                b5_re   =       -32'd0;
+
+                b0_re   =        32'd2143083068;
+                b1_re   =        32'd2145807236;
+                b2_re   =        32'd2146812530;
+                b3_re   =        32'd0;
+                b4_re   =        32'd0;
+                b5_re   =        32'd0;
+
+                b0_im   =        32'd0;
+                b1_im   =        32'd0;
+                b2_im   =        32'd0;
+                b3_im   =        32'd0;
+                b4_im   =        32'd0;
                 b5_im   =        32'd0;
 
                 fcw     =       48'h0840_0000_0000;
@@ -551,123 +564,22 @@ always@(*)
 wire     [15:0] diff;
 assign	diff = cs_wave1 - cs_wave;
 integer signed In_fid;
-integer X1_fid;
-integer X2_fid;
-integer X4_fid;
-integer X8_fid;
+integer signed OrgOut_fid;
 
 initial begin
-        #0;
-        In_fid  =       $fopen("./in.dat");
-        case (intp_mode)
-                2'b00 :         X1_fid  =       $fopen("./X1_data.dat");
-                2'b01 :         X2_fid  =       $fopen("./X2_data.dat");
-                2'b10 :         X4_fid  =       $fopen("./X4_data.dat");
-                2'b11 :         X8_fid  =       $fopen("./X8_data.dat");
-
-        endcase
+    #0;
+    In_fid      = $fopen("./in.dat")    ;
+    OrgOut_fid  = $fopen("./OrgOut.dat");
 end
 
 
-always@(posedge clk_div16_f)
-          if(cnt >= 90)
-                $fwrite(In_fid,"%d\n",{{{~iir_in[15]}},iir_in[14:0]});
+always@(posedge clk_div32_f)
+    if(cnt >= 90)  begin
+            $fwrite(In_fid,    "%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.din_re));
+            $fwrite(OrgOut_fid,"%d\n",$signed(TB.inst1_Z_dsp.inst_TailCorr_top.dout  ));
+        end
 
 
-always@(*)
-  fork
-        case (intp_mode)
-        2'b00 : 
-                begin
-                        @(posedge clk_div16_e)
-                          if(cnt >= 90)
-                                $fwrite(X1_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
-                end
-        2'b01 : 
-                begin
-                        @(posedge clk_div16_e)
-                          if(cnt >= 90)
-                                $fwrite(X2_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
-                        @(posedge clk_div16_6)
-                          if(cnt >= 90)
-                                $fwrite(X2_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
-                end
-        2'b10 : 
-                begin
-                        @(posedge clk_div16_e)
-                          if(cnt >= 90)
-                                $fwrite(X4_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
-                        @(posedge clk_div16_a)
-                          if(cnt >= 90)
-                                $fwrite(X4_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
-                        @(posedge clk_div16_6)
-                          if(cnt >= 90)
-                                $fwrite(X4_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
-                        @(posedge clk_div16_2)
-                          if(cnt >= 90)
-                                $fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
-                end
-        2'b11 : 
-                begin
-                        @(posedge clk_div32_f)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]});
-                        @(posedge clk_div32_d)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]});
-                        @(posedge clk_div32_b)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]});
-                        @(posedge clk_div32_9)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]});
-                        @(posedge clk_div32_7)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]});
-                        @(posedge clk_div32_5)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]});
-                        @(posedge clk_div32_3)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]});
-                        @(posedge clk_div32_1)
-                          if(cnt >= 90)
-                                $fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]});
-
-                end
-
-        endcase
-  join
-
-/*
-always@(posedge clk_div16_e)
-          if(cnt >= 90)
-              $fwrite(In_fid,"%d\n",{{~{iir_in[15]}},iir_in[14:0]});
-
-always@(posedge clk_div16_e)
-          if(cnt >= 90)
-              $fwrite(X1_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
-
-always@(posedge clk_div16_e)
-          if(cnt >= 90)
-              $fwrite(X2_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
-always@(posedge clk_div16_6)
-          if(cnt >= 90)
-              $fwrite(X2_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
-
-always@(posedge clk_div16_e)
-          if(cnt >= 90)
-              $fwrite(X4_fid,"%d\n",{{~{dout_p0[15]}},dout_p0[14:0]});
-always@(posedge clk_div16_a)
-          if(cnt >= 90)
-              $fwrite(X4_fid,"%d\n",{{~{dout_p1[15]}},dout_p1[14:0]});
-always@(posedge clk_div16_6)
-          if(cnt >= 90)
-              $fwrite(X4_fid,"%d\n",{{~{dout_p2[15]}},dout_p2[14:0]});
-always@(posedge clk_div16_2)
-          if(cnt >= 90)
-              $fwrite(X4_fid,"%d\n",{{~{dout_p3[15]}},dout_p3[14:0]});
-*/
 endmodule