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v04-z_dsp's netlist used to z_chip_top

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thfu 2024-11-23 21:58:54 +08:00
parent 5f68519f8d
commit cdfd6d716d
2 changed files with 89047 additions and 7 deletions
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89041
edfFile/z_dsp.edf Normal file
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13
rtl/z_dsp_wrapper.v → edfFile/z_dsp.v
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@ -1,3 +1,4 @@
//+FHDR-------------------------------------------------------------------------------------------------------- //+FHDR--------------------------------------------------------------------------------------------------------
// Company: // Company:
//----------------------------------------------------------------------------------------------------------------- //-----------------------------------------------------------------------------------------------------------------
@ -31,14 +32,16 @@
// Other: // Other:
//-FHDR-------------------------------------------------------------------------------------------------------- //-FHDR--------------------------------------------------------------------------------------------------------
module z_dsp_wrapper module z_dsp
( (
input clk, input clk,
input rstn, input rstn,
input en, //enable
input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode; input [1:0] dac_mode_sel, //2'b00:NRZ mode;2'b01:Double data mode;
//2'b10:Double Double data mode;2'b11:reserve; //2'b10:Double Double data mode;2'b11:reserve;
input tc_bypass, input tc_bypass,
input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve; input [1:0] intp_mode, //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
input vldi,
input signed [15:0] din_re, input signed [15:0] din_re,
input signed [15:0] din_im, input signed [15:0] din_im,
input signed [31:0] a0_re, //a0's real part input signed [31:0] a0_re, //a0's real part
@ -69,10 +72,6 @@ output signed [15:0] dout0,
output signed [15:0] dout1, output signed [15:0] dout1,
output signed [15:0] dout2, output signed [15:0] dout2,
output signed [15:0] dout3, output signed [15:0] dout3,
output signed [15:0] dout4,
output signed [15:0] dout5,
output signed [15:0] dout6,
output signed [15:0] dout7,
output vldo, output vldo,
output saturation_0, output saturation_0,
output saturation_1, output saturation_1,
@ -80,6 +79,6 @@ output saturation_2,
output saturation_3, output saturation_3,
output saturation_4, output saturation_4,
output saturation_5 output saturation_5
); );
endmodule endmodule