From c99d9baaeafbc81cfc87f910027cf0b7b2552524 Mon Sep 17 00:00:00 2001 From: thfu <2779155576@qq.com> Date: Thu, 17 Oct 2024 17:29:11 +0800 Subject: [PATCH] =?UTF-8?q?=E5=86=85=E6=8F=92=E6=A8=A1=E5=9D=97=E5=A2=9E?= =?UTF-8?q?=E5=8A=A0=E4=BA=86=E5=86=85=E6=8F=92=E5=80=8D=E6=95=B0=E9=80=89?= =?UTF-8?q?=E6=8B=A9=E6=A8=A1=E5=9D=97=EF=BC=9B=20DAC=E6=8E=A5=E5=8F=A3?= =?UTF-8?q?=E5=81=9A=E4=BA=86=E5=AF=B9=E5=BA=94=E7=9A=84=E4=BF=AE=E6=94=B9?= =?UTF-8?q?=EF=BC=9B=20=E5=A2=9E=E5=8A=A0=E4=BA=86matlab=E4=B8=AD=E7=9A=84?= =?UTF-8?q?=E5=85=AB=E5=80=8D=E5=86=85=E6=8F=92=E6=A8=A1=E5=9D=97=EF=BC=8C?= =?UTF-8?q?=E6=9D=A5=E9=AA=8C=E8=AF=81rtl=E4=BB=A3=E7=A0=81=E7=9A=84?= =?UTF-8?q?=E5=87=86=E7=A1=AE=E6=80=A7=EF=BC=9B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- rtl/MeanIntp_8.v | 92 ++++++++++-- rtl/lsdacif.v | 52 ++++++- rtl/nco/coef_c.v | 150 +++++++++++++++++++ rtl/nco/coef_s.v | 155 +++++++++++++++++++ rtl/nco/cos_op.v | 144 ++++++++++++++++++ rtl/nco/nco.v | 51 +++++++ rtl/nco/p_nco.v | 62 ++++++++ rtl/nco/ph2amp.v | 83 +++++++++++ rtl/nco/pipe_acc_48bit.v | 64 ++++++++ rtl/nco/pipe_add_48bit.v | 50 +++++++ rtl/nco/sin_op.v | 144 ++++++++++++++++++ rtl/z_dsp.v | 38 ++++- script_m/MyIIR_test.m | 1 + script_m/PolyMean_Test.m | 1 + script_m/TailCorr_8inpt_test.m | 63 ++++++++ script_m/TailCorr_test_P.m | 1 + script_m/intp8_Test.m | 21 +++ sim/files.f | 34 ++--- tb/tb_mean8_top.v | 265 +++++++++++++++++++-------------- tb/tb_top.v | 73 ++++++++- 20 files changed, 1390 insertions(+), 154 deletions(-) create mode 100755 rtl/nco/coef_c.v create mode 100755 rtl/nco/coef_s.v create mode 100755 rtl/nco/cos_op.v create mode 100755 rtl/nco/nco.v create mode 100755 rtl/nco/p_nco.v create mode 100755 rtl/nco/ph2amp.v create mode 100755 rtl/nco/pipe_acc_48bit.v create mode 100755 rtl/nco/pipe_add_48bit.v create mode 100755 rtl/nco/sin_op.v create mode 100644 script_m/TailCorr_8inpt_test.m create mode 100755 script_m/intp8_Test.m diff --git a/rtl/MeanIntp_8.v b/rtl/MeanIntp_8.v index ba66b88..50912c8 100644 --- a/rtl/MeanIntp_8.v +++ b/rtl/MeanIntp_8.v @@ -34,6 +34,7 @@ module MeanIntp_8( clk, rstn, en, + intp_mode, din, //input dout_0,//output dout_1, @@ -48,9 +49,10 @@ module MeanIntp_8( input rstn; input clk; -input en; - +input en; +input [1:0] intp_mode; input signed [15:0] din; + output signed [15:0] dout_0; output signed [15:0] dout_1; output signed [15:0] dout_2; @@ -132,13 +134,83 @@ always@(posedge clk or negedge rstn) dout_r7 <= dout_r7; end -assign dout_0 = dout_r0[15:0]; -assign dout_1 = dout_r1[15:0]; -assign dout_2 = dout_r2[15:0]; -assign dout_3 = dout_r3[15:0]; -assign dout_4 = dout_r4[15:0]; -assign dout_5 = dout_r5[15:0]; -assign dout_6 = dout_r6[15:0]; -assign dout_7 = dout_r7[15:0]; +reg signed [15:0] mux_p_0; +reg signed [15:0] mux_p_1; +reg signed [15:0] mux_p_2; +reg signed [15:0] mux_p_3; +reg signed [15:0] mux_p_4; +reg signed [15:0] mux_p_5; +reg signed [15:0] mux_p_6; +reg signed [15:0] mux_p_7; + +always@(posedge clk) begin + case(intp_mode) + 2'b00: + begin + mux_p_0 <= dout_r0; + mux_p_1 <= 16'h0; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + mux_p_4 <= 16'h0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + end + 2'b01: + begin + mux_p_0 <= dout_r0; + mux_p_1 <= dout_r4; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + mux_p_4 <= 16'h0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + end + 2'b10: + begin + mux_p_0 <= dout_r0; + mux_p_1 <= dout_r2; + mux_p_2 <= dout_r4; + mux_p_3 <= dout_r6; + mux_p_4 <= 16'h0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + end + 2'b11: + begin + mux_p_0 <= dout_r0; + mux_p_1 <= dout_r1; + mux_p_2 <= dout_r2; + mux_p_3 <= dout_r3; + mux_p_4 <= dout_r4; + mux_p_5 <= dout_r5; + mux_p_6 <= dout_r6; + mux_p_7 <= dout_r7; + end + default: + begin + mux_p_0 <= 16'h0; + mux_p_1 <= 16'h0; + mux_p_2 <= 16'h0; + mux_p_3 <= 16'h0; + mux_p_4 <= 16'h0; + mux_p_5 <= 16'h0; + mux_p_6 <= 16'h0; + mux_p_7 <= 16'h0; + end + + endcase +end + +assign dout_0 = mux_p_0[15:0]; +assign dout_1 = mux_p_1[15:0]; +assign dout_2 = mux_p_2[15:0]; +assign dout_3 = mux_p_3[15:0]; +assign dout_4 = mux_p_4[15:0]; +assign dout_5 = mux_p_5[15:0]; +assign dout_6 = mux_p_6[15:0]; +assign dout_7 = mux_p_7[15:0]; endmodule diff --git a/rtl/lsdacif.v b/rtl/lsdacif.v index 330793b..d1dac1c 100644 --- a/rtl/lsdacif.v +++ b/rtl/lsdacif.v @@ -8,7 +8,8 @@ //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description -// 0.1 2024-05-11 thfu +// 0.2 2024-10-09 thfu modify port from 4 to 8 to fit +// 8 interpolation //----------------------------------------------------------------------------------------------------------------- // Keywords : // @@ -43,11 +44,21 @@ module lsdacif ( ,input [15:0] din1 ,input [15:0] din2 ,input [15:0] din3 + ,input [15:0] din4 + ,input [15:0] din5 + ,input [15:0] din6 + ,input [15:0] din7 + //data output ,output [15:0] dout0 ,output [15:0] dout1 ,output [15:0] dout2 ,output [15:0] dout3 + ,output [15:0] dout4 + ,output [15:0] dout5 + ,output [15:0] dout6 + ,output [15:0] dout7 + ); //////////////////////////////////////////////////// @@ -57,6 +68,10 @@ reg [15:0] dout0_r ; reg [15:0] dout1_r ; reg [15:0] dout2_r ; reg [15:0] dout3_r ; +reg [15:0] dout4_r ; +reg [15:0] dout5_r ; +reg [15:0] dout6_r ; +reg [15:0] dout7_r ; //////////////////////////////////////////////////// // intp mode select @@ -100,6 +115,11 @@ always @(posedge clk or negedge rstn) begin dout1_r <= 16'h0; dout2_r <= 16'h0; dout3_r <= 16'h0; + dout4_r <= 16'h0; + dout5_r <= 16'h0; + dout6_r <= 16'h0; + dout7_r <= 16'h0; + end else begin case(dac_mode_sel) @@ -107,25 +127,45 @@ always @(posedge clk or negedge rstn) begin dout0_r <= {~din0[15],din0[14:0]}; dout1_r <= {~din1[15],din1[14:0]}; dout2_r <= {~din2[15],din2[14:0]}; - dout3_r <= {~din3[15],din3[14:0]}; + dout3_r <= {~din3[15],din3[14:0]}; + dout4_r <= {~din4[15],din4[14:0]}; + dout5_r <= {~din5[15],din5[14:0]}; + dout6_r <= {~din6[15],din6[14:0]}; + dout7_r <= {~din7[15],din7[14:0]}; + end 2'b01 : begin dout0_r <= {~din0[15],din0[14:0]}; dout1_r <= {~din0[15],din0[14:0]}; dout2_r <= {~din1[15],din1[14:0]}; - dout3_r <= {~din1[15],din1[14:0]}; + dout3_r <= {~din1[15],din1[14:0]}; + dout4_r <= {~din2[15],din2[14:0]}; + dout5_r <= {~din2[15],din2[14:0]}; + dout6_r <= {~din3[15],din3[14:0]}; + dout7_r <= {~din3[15],din3[14:0]}; + end 2'b10 : begin dout0_r <= {~din0[15],din0[14:0]}; dout1_r <= {~din0[15],din0[14:0]}; dout2_r <= {~din0[15],din0[14:0]}; dout3_r <= {~din0[15],din0[14:0]}; + dout4_r <= {~din1[15],din1[14:0]}; + dout5_r <= {~din1[15],din1[14:0]}; + dout6_r <= {~din1[15],din1[14:0]}; + dout7_r <= {~din1[15],din1[14:0]}; + end default : begin dout0_r <= {~din0[15],din0[14:0]}; dout1_r <= {~din1[15],din1[14:0]}; dout2_r <= {~din2[15],din2[14:0]}; - dout3_r <= {~din3[15],din3[14:0]}; + dout3_r <= {~din3[15],din3[14:0]}; + dout4_r <= {~din4[15],din4[14:0]}; + dout5_r <= {~din5[15],din5[14:0]}; + dout6_r <= {~din6[15],din6[14:0]}; + dout7_r <= {~din7[15],din7[14:0]}; + end endcase end @@ -135,5 +175,9 @@ assign dout0 = dout0_r ; assign dout1 = dout1_r ; assign dout2 = dout2_r ; assign dout3 = dout3_r ; +assign dout4 = dout4_r ; +assign dout5 = dout5_r ; +assign dout6 = dout6_r ; +assign dout7 = dout7_r ; endmodule diff --git a/rtl/nco/coef_c.v b/rtl/nco/coef_c.v new file mode 100755 index 0000000..8563555 --- /dev/null +++ b/rtl/nco/coef_c.v @@ -0,0 +1,150 @@ +module COEF_C( + index , + C0_C , + C1_C , + C2_C + ); +input [4:0] index; + +output [17:0] C0_C; +output [11:0] C1_C; +output [5:0] C2_C; + +reg [17:0] C0_C; +reg [11:0] C1_C; +reg [5:0] C2_C; + + + +//------------------------ +//----C0_C OK +always@(*) +begin + + case(index) + 5'd 0 : C0_C =18'h3ffff; + 5'd 1 : C0_C =18'h3ffb1; + 5'd 2 : C0_C =18'h3fec4; + 5'd 3 : C0_C =18'h3fd3a; + 5'd 4 : C0_C =18'h3fb12; + 5'd 5 : C0_C =18'h3f84d; + 5'd 6 : C0_C =18'h3f4eb; + 5'd 7 : C0_C =18'h3f0ed; + 5'd 8 : C0_C =18'h3ec53; + 5'd 9 : C0_C =18'h3e71e; + 5'd10 : C0_C =18'h3e150; + 5'd11 : C0_C =18'h3dae8; + 5'd12 : C0_C =18'h3d3e8; + 5'd13 : C0_C =18'h3cc51; + 5'd14 : C0_C =18'h3c424; + 5'd15 : C0_C =18'h3bb62; + 5'd16 : C0_C =18'h3b20d; + 5'd17 : C0_C =18'h3a827; + 5'd18 : C0_C =18'h39daf; + 5'd19 : C0_C =18'h392a9; + 5'd20 : C0_C =18'h38716; + 5'd21 : C0_C =18'h37af8; + 5'd22 : C0_C =18'h36e50; + 5'd23 : C0_C =18'h36121; + 5'd24 : C0_C =18'h3536d; + 5'd25 : C0_C =18'h34535; + 5'd26 : C0_C =18'h3367c; + 5'd27 : C0_C =18'h32744; + 5'd28 : C0_C =18'h31790; + 5'd29 : C0_C =18'h30762; + 5'd30 : C0_C =18'h2f6bc; + 5'd31 : C0_C =18'h2e5a1; + // default : C0_C = C0_C; + endcase + +end + +//------------------------ +//----C1_C OK +always@(*) +begin + + case(index) + 5'd 0 : C1_C =12'd 0; + 5'd 1 : C1_C =12'd 79; + 5'd 2 : C1_C =12'd 158; + 5'd 3 : C1_C =12'd 237; + 5'd 4 : C1_C =12'd 315; + 5'd 5 : C1_C =12'd 394; + 5'd 6 : C1_C =12'd 472; + 5'd 7 : C1_C =12'd 550; + 5'd 8 : C1_C =12'd 628; + 5'd 9 : C1_C =12'd 705; + 5'd10 : C1_C =12'd 782; + 5'd11 : C1_C =12'd 858; + 5'd12 : C1_C =12'd 934; + 5'd13 : C1_C =12'd1009; + 5'd14 : C1_C =12'd1084; + 5'd15 : C1_C =12'd1158; + 5'd16 : C1_C =12'd1231; + 5'd17 : C1_C =12'd1304; + 5'd18 : C1_C =12'd1376; + 5'd19 : C1_C =12'd1446; + 5'd20 : C1_C =12'd1517; + 5'd21 : C1_C =12'd1586; + 5'd22 : C1_C =12'd1654; + 5'd23 : C1_C =12'd1721; + 5'd24 : C1_C =12'd1787; + 5'd25 : C1_C =12'd1852; + 5'd26 : C1_C =12'd1916; + 5'd27 : C1_C =12'd1979; + 5'd28 : C1_C =12'd2041; + 5'd29 : C1_C =12'd2101; + 5'd30 : C1_C =12'd2161; + 5'd31 : C1_C =12'd2218; + // default : C1_C = C1_C; + endcase + +end +//------------------------ +//----C2_C +always@(*) +begin + + + case(index) + 5'd 0 : C2_C =6'd39; + 5'd 1 : C2_C =6'd39; + 5'd 2 : C2_C =6'd39; + 5'd 3 : C2_C =6'd39; + 5'd 4 : C2_C =6'd39; + 5'd 5 : C2_C =6'd39; + 5'd 6 : C2_C =6'd39; + 5'd 7 : C2_C =6'd39; + 5'd 8 : C2_C =6'd39; + 5'd 9 : C2_C =6'd38; + 5'd10 : C2_C =6'd38; + 5'd11 : C2_C =6'd38; + 5'd12 : C2_C =6'd38; + 5'd13 : C2_C =6'd37; + 5'd14 : C2_C =6'd37; + 5'd15 : C2_C =6'd37; + 5'd16 : C2_C =6'd36; + 5'd17 : C2_C =6'd36; + 5'd18 : C2_C =6'd35; + 5'd19 : C2_C =6'd35; + 5'd20 : C2_C =6'd35; + 5'd21 : C2_C =6'd34; + 5'd22 : C2_C =6'd34; + 5'd23 : C2_C =6'd33; + 5'd24 : C2_C =6'd33; + 5'd25 : C2_C =6'd32; + 5'd26 : C2_C =6'd31; + 5'd27 : C2_C =6'd31; + 5'd28 : C2_C =6'd30; + 5'd29 : C2_C =6'd30; + 5'd30 : C2_C =6'd29; + 5'd31 : C2_C =6'd28; + // default : C2_C = C2_C; + endcase + + +end +endmodule + + diff --git a/rtl/nco/coef_s.v b/rtl/nco/coef_s.v new file mode 100755 index 0000000..4fcbba5 --- /dev/null +++ b/rtl/nco/coef_s.v @@ -0,0 +1,155 @@ +module COEF_S( + + index , + C0_S , + C1_S , + C2_S + + ); + +input [4:0] index; + +output [17:0] C0_S; +output [11:0] C1_S; +output [4:0] C2_S; + + +reg [17:0] C0_S; +reg [11:0] C1_S; +reg [4:0] C2_S; + +//------------------------ +//----C0_S +always@(*) +begin + + case(index) + 5'd 0 : C0_S =18'd 0; + 5'd 1 : C0_S =18'd 6433; + 5'd 2 : C0_S =18'd 12863; + 5'd 3 : C0_S =18'd 19284; + 5'd 4 : C0_S =18'd 25695; + 5'd 5 : C0_S =18'd 32089; + 5'd 6 : C0_S =18'd 38464; + 5'd 7 : C0_S =18'd 44817; + 5'd 8 : C0_S =18'd 51142; + 5'd 9 : C0_S =18'd 57436; + 5'd10 : C0_S =18'd 63696; + 5'd11 : C0_S =18'd 69917; + 5'd12 : C0_S =18'd 76096; + 5'd13 : C0_S =18'd 82230; + 5'd14 : C0_S =18'd 88314; + 5'd15 : C0_S =18'd 94344; + 5'd16 : C0_S =18'd100318; + 5'd17 : C0_S =18'd106232; + 5'd18 : C0_S =18'd112081; + 5'd19 : C0_S =18'd117863; + 5'd20 : C0_S =18'd123574; + 5'd21 : C0_S =18'd129210; + 5'd22 : C0_S =18'd134769; + 5'd23 : C0_S =18'd140246; + 5'd24 : C0_S =18'd145639; + 5'd25 : C0_S =18'd150945; + 5'd26 : C0_S =18'd156159; + 5'd27 : C0_S =18'd161279; + 5'd28 : C0_S =18'd166302; + 5'd29 : C0_S =18'd171225; + 5'd30 : C0_S =18'd176045; + 5'd31 : C0_S =18'd180759; + // default : C0_S = C0_S; + endcase + +end + +//------------------------ + + +//------------------------ +//----C1_S OK +always@(*) +begin + + case(index) + 5'd 0 : C1_S =12'd3217; + 5'd 1 : C1_S =12'd3216; + 5'd 2 : C1_S =12'd3213; + 5'd 3 : C1_S =12'd3208; + 5'd 4 : C1_S =12'd3202; + 5'd 5 : C1_S =12'd3193; + 5'd 6 : C1_S =12'd3182; + 5'd 7 : C1_S =12'd3170; + 5'd 8 : C1_S =12'd3155; + 5'd 9 : C1_S =12'd3139; + 5'd10 : C1_S =12'd3121; + 5'd11 : C1_S =12'd3101; + 5'd12 : C1_S =12'd3079; + 5'd13 : C1_S =12'd3055; + 5'd14 : C1_S =12'd3029; + 5'd15 : C1_S =12'd3002; + 5'd16 : C1_S =12'd2972; + 5'd17 : C1_S =12'd2941; + 5'd18 : C1_S =12'd2908; + 5'd19 : C1_S =12'd2874; + 5'd20 : C1_S =12'd2837; + 5'd21 : C1_S =12'd2799; + 5'd22 : C1_S =12'd2759; + 5'd23 : C1_S =12'd2718; + 5'd24 : C1_S =12'd2675; + 5'd25 : C1_S =12'd2630; + 5'd26 : C1_S =12'd2584; + 5'd27 : C1_S =12'd2536; + 5'd28 : C1_S =12'd2487; + 5'd29 : C1_S =12'd2436; + 5'd30 : C1_S =12'd2384; + 5'd31 : C1_S =12'd2330; + // default : C1_S = C1_S; + endcase + +end + +//------------------------ +//----C2_S +always@(*) +begin + + case(index) + 5'd 0 : C2_S =5'd 0; + 5'd 1 : C2_S =5'd 1; + 5'd 2 : C2_S =5'd 2; + 5'd 3 : C2_S =5'd 3; + 5'd 4 : C2_S =5'd 4; + 5'd 5 : C2_S =5'd 5; + 5'd 6 : C2_S =5'd 6; + 5'd 7 : C2_S =5'd 7; + 5'd 8 : C2_S =5'd 8; + 5'd 9 : C2_S =5'd 9; + 5'd10 : C2_S =5'd10; + 5'd11 : C2_S =5'd11; + 5'd12 : C2_S =5'd12; + 5'd13 : C2_S =5'd13; + 5'd14 : C2_S =5'd14; + 5'd15 : C2_S =5'd15; + 5'd16 : C2_S =5'd16; + 5'd17 : C2_S =5'd16; + 5'd18 : C2_S =5'd17; + 5'd19 : C2_S =5'd18; + 5'd20 : C2_S =5'd19; + 5'd21 : C2_S =5'd20; + 5'd22 : C2_S =5'd21; + 5'd23 : C2_S =5'd22; + 5'd24 : C2_S =5'd22; + 5'd25 : C2_S =5'd23; + 5'd26 : C2_S =5'd24; + 5'd27 : C2_S =5'd25; + 5'd28 : C2_S =5'd25; + 5'd29 : C2_S =5'd26; + 5'd30 : C2_S =5'd27; + 5'd31 : C2_S =5'd28; + // default : C2_S = C2_S; + endcase + +end + +endmodule + + diff --git a/rtl/nco/cos_op.v b/rtl/nco/cos_op.v new file mode 100755 index 0000000..25ded3c --- /dev/null +++ b/rtl/nco/cos_op.v @@ -0,0 +1,144 @@ +module COS_OP( + clk , + rstn , + pha_map , + pha_indx_msb , + cos_op_o + ); + +input clk; +input rstn; +input [18:0] pha_map; +output [2:0] pha_indx_msb; +output [14:0] cos_op_o; + +wire [2:0] pha_indx_msb_w; +assign pha_indx_msb_w=pha_map[18:16]; + +wire [15:0] pha_indx_lsb; +assign pha_indx_lsb=pha_map[15:0]; +wire [15:0] pha_op; +assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb; + +wire [4:0] indx; +assign indx=pha_op[15:11]; +wire [10:0] x_w; +assign x_w=pha_op[10:0]; +wire [17:0] c0; +wire [11:0] c1; +wire [5:0] c2; + + +COEF_C coef_c_inst1( + .index(indx) , + .C0_C(c0) , + .C1_C(c1) , + .C2_C(c2) + ); + +reg[17:0] c0_r1; +reg[17:0] c0_r2; +reg[17:0] c0_r3; +reg[17:0] c0_r4; +reg[17:0] c0_r5; +reg[17:0] c0_r6; +always@(posedge clk) + begin + c0_r1<=c0; + c0_r2<=c0_r1; + c0_r3<=c0_r2; + c0_r4<=c0_r3; + c0_r5<=c0_r4; + c0_r6<=c0_r5; + end +reg [11:0] c1_r1; +reg [11:0] c1_r2; +reg [11:0] c1_r3; +always@(posedge clk) + begin + c1_r1<=c1; + c1_r2<=c1_r1; + c1_r3<=c1_r2; + end +reg [5:0] c2_r1; +always@(posedge clk) + c2_r1<=c2; +reg[10:0] x_r1; +reg[10:0] x_r2; +reg[10:0] x_r3; +reg[10:0] x_r4; +always@(posedge clk) + begin + x_r1<=x_w; + x_r2<=x_r1; + x_r3<=x_r2; + x_r4<=x_r3; + end + +wire [16:0] c2x; + +DW_mult_pipe #(11,6,2,0,1) inst_mult_0( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r1 ), + .b (c2_r1 ), + .tc (1'b0 ), + .product (c2x ) + ); + +wire [5:0] c2x_w; +assign c2x_w=c2x[10]?(c2x[16:11]+6'd1):c2x[16:11]; + +reg [11:0] c2xc1; +always@(posedge clk) + c2xc1<=c1_r2+c2x_w; +wire [22:0] c2xc1x; +DW_mult_pipe #(11,12,3,0,1) inst_mult_1( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r3 ), + .b (c2xc1 ), + .tc (1'b0 ), + .product (c2xc1x ) + ); + + +wire [12:0] c2xc1x_w; +assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10]; +reg [12:0] c2xc1x_r; +always@(posedge clk) + c2xc1x_r<=c2xc1x_w; +wire [17:0] c2xc1xc0; +assign c2xc1xc0 =c0_r6-c2xc1x_r; + +wire[15:0] c2xc1xc0_w1; +assign c2xc1xc0_w1=c2xc1xc0[2]?({1'b0,c2xc1xc0[17:3]}+15'd1):{1'b0,c2xc1xc0[17:3]}; + +wire[14:0] c2xc1xc0_w; +assign c2xc1xc0_w=(c2xc1xc0_w1>=15'd32767)?15'd32767:c2xc1xc0_w1[14:0]; +reg [14:0] c2xc1xc0_r; +always@(posedge clk) + c2xc1xc0_r<=c2xc1xc0_w; +assign cos_op_o=c2xc1xc0_r; +reg[2:0] pha_indx_msb_r1; +reg[2:0] pha_indx_msb_r2; +reg[2:0] pha_indx_msb_r3; +reg[2:0] pha_indx_msb_r4; +reg[2:0] pha_indx_msb_r5; +reg[2:0] pha_indx_msb_r6; +reg[2:0] pha_indx_msb_r7; +always@(posedge clk) + begin + pha_indx_msb_r1<=pha_indx_msb_w; + pha_indx_msb_r2<=pha_indx_msb_r1; + pha_indx_msb_r3<=pha_indx_msb_r2; + pha_indx_msb_r4<=pha_indx_msb_r3; + pha_indx_msb_r5<=pha_indx_msb_r4; + pha_indx_msb_r6<=pha_indx_msb_r5; + pha_indx_msb_r7<=pha_indx_msb_r6; + end + +assign pha_indx_msb=pha_indx_msb_r7; +endmodule diff --git a/rtl/nco/nco.v b/rtl/nco/nco.v new file mode 100755 index 0000000..4c12483 --- /dev/null +++ b/rtl/nco/nco.v @@ -0,0 +1,51 @@ +module NCO( + clk, + rstn, + phase_manual_clr, + phase_auto_clr, + fcw, + pha, + + cos, + + sin + ); + +input clk; +input rstn; +input phase_manual_clr; +input phase_auto_clr; +input [47:0] fcw; +input [15:0] pha; + +output [15:0] cos; +output [15:0] sin; + + +wire clr_acc; +wire clr_fix; +assign clr_acc = phase_auto_clr | phase_manual_clr; +assign clr_fix = phase_manual_clr; + +wire [15:0] s1_i_o; +wire [15:0] s2_i_o; +wire [15:0] s3_i_o; + +P_NCO inst_p_nco( + .clk (clk ), + .rstn (rstn ), + .clr (clr_fix ), + .clr_acc (clr_acc ), + .pha (pha ), + .s1 (s1_i_o ), + .s2 (s2_i_o ), + .s3 (s3_i_o ), + .s1_o (s1_i_o ), + .s2_o (s2_i_o ), + .s3_o (s3_i_o ), + .fcw (fcw ), + .cos (cos ), + .sin (sin ) + + ); +endmodule diff --git a/rtl/nco/p_nco.v b/rtl/nco/p_nco.v new file mode 100755 index 0000000..8c1e221 --- /dev/null +++ b/rtl/nco/p_nco.v @@ -0,0 +1,62 @@ +module P_NCO( + clk, + rstn, + clr, + clr_acc, + pha, + + s1, + s2, + s3, + + s1_o, + s2_o, + s3_o, + + fcw, + + cos, + sin + ); + +input clk; +input rstn; +input clr; +input clr_acc; +input [15:0] pha; + +input [15:0] s1; +input [15:0] s2; +input [15:0] s3; + +output [15:0] s1_o; +output [15:0] s2_o; +output [15:0] s3_o; + +output [15:0] cos; +output [15:0] sin; + + +input [47:0] fcw; + + +reg [15:0] pha_r; +always@(posedge clk or negedge rstn) + if(!rstn) + pha_r <= 16'd0; + else + pha_r <= pha; + +wire [18:0] pha0; + +PIPE3_ACC_48BIT inst_pipe(.clk(clk),.rstn(rstn),.in(fcw),.clr(clr_acc),.ptw(pha),.s_o_1(s1_o),.s_o_2(s2_o),.s_o_3(s3_o),.s_i_1(s1),.s_i_2(s2),.s_i_3(s3),.out(pha0)); + +PH2AMP inst_ph2amp_0( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha0) , + .sin_o(sin) , + .cos_o(cos) + ); + +endmodule diff --git a/rtl/nco/ph2amp.v b/rtl/nco/ph2amp.v new file mode 100755 index 0000000..ef26d32 --- /dev/null +++ b/rtl/nco/ph2amp.v @@ -0,0 +1,83 @@ +module PH2AMP( + clk , + rstn , + pha_map , + sin_o , + cos_o + ); +input clk; +input rstn; +input [18:0] pha_map; + +output [15:0] sin_o; +output [15:0] cos_o; + +//wire [2:0] pha_indx_msb_s; +wire [14:0] sin_w; +SIN_OP inst_sin_op( + .clk(clk), + .rstn(rstn), + .pha_map(pha_map), + // .pha_indx_msb(pha_indx_msb_s), + .sin_op_o(sin_w) + ); +wire [2:0] pha_indx_msb_c; +wire [14:0] cos_w; +COS_OP inst_cos_op( + .clk(clk) , + .rstn(rstn) , + .pha_map(pha_map) , + .pha_indx_msb(pha_indx_msb_c), + .cos_op_o(cos_w) + ); +wire[15:0] cos_w_1; +wire[15:0] sin_w_1; +wire[15:0] cos_w_0; +wire[15:0] sin_w_0;//0:-,1:+ + +assign cos_w_1={1'b0,cos_w}; +assign sin_w_1={1'b0,sin_w}; +assign cos_w_0=(cos_w_1==16'd0)?16'd0:~cos_w_1+16'd1; +assign sin_w_0=(sin_w_1==16'd0)?16'd0:~sin_w_1+16'd1; + +reg[15:0] cos_tmp; +reg[15:0] sin_tmp; +always@(posedge clk) + case(pha_indx_msb_c)//synopsys parallel_case + 3'b000:begin + cos_tmp<=cos_w_1; + sin_tmp<=sin_w_1; + end + 3'b001:begin + cos_tmp<=sin_w_1; + sin_tmp<=cos_w_1; + end + 3'b010:begin + cos_tmp<=sin_w_0; + sin_tmp<=cos_w_1; + end + 3'b011:begin + cos_tmp<=cos_w_0; + sin_tmp<=sin_w_1; + end + 3'b100:begin + cos_tmp<=cos_w_0; + sin_tmp<=sin_w_0; + end + 3'b101:begin + cos_tmp<=sin_w_0; + sin_tmp<=cos_w_0; + end + 3'b110:begin + cos_tmp<=sin_w_1; + sin_tmp<=cos_w_0; + end + 3'b111:begin + cos_tmp<=cos_w_1; + sin_tmp<=sin_w_0; + end + endcase + +assign sin_o=sin_tmp; +assign cos_o=cos_tmp; +endmodule diff --git a/rtl/nco/pipe_acc_48bit.v b/rtl/nco/pipe_acc_48bit.v new file mode 100755 index 0000000..05ca377 --- /dev/null +++ b/rtl/nco/pipe_acc_48bit.v @@ -0,0 +1,64 @@ + + +module PIPE3_ACC_48BIT( + clk, + rstn, + in, + clr, + ptw, + s_i_1, + s_i_2, + s_i_3, + s_o_1, + s_o_2, + s_o_3, + out +); + +//--- + + input clk; + input rstn; + input [47:0] in; + input clr; + input [15:0] ptw; + + input [15:0] s_i_1; + input [15:0] s_i_2; + input [15:0] s_i_3; + + output [15:0] s_o_1; + output [15:0] s_o_2; + output [15:0] s_o_3; + output [18:0] out; + +//---------------------------------------------------------------------------------------------------- + + reg [47:0] acc; + always@(posedge clk or negedge rstn) + if(!rstn) + acc<=48'h0; + else if(clr) + acc<=48'h0; + else + acc<={s_i_1,s_i_2,s_i_3}+in; + + +//---------------------------------------------------------------------------------------------------- + wire [15:0] s1; + wire [15:0] s2; + wire [15:0] s3; + + assign s_o_1 = acc[47:32]; + assign s_o_2 = acc[31:16]; + assign s_o_3 = acc[15:0]; + + wire[18:0] pha_w; + assign pha_w=acc[47:29]; + reg[18:0] pha_r; + always@(posedge clk) + pha_r<=pha_w+{ptw,3'b0}; + + assign out=pha_r; +//END +endmodule diff --git a/rtl/nco/pipe_add_48bit.v b/rtl/nco/pipe_add_48bit.v new file mode 100755 index 0000000..aeb5aa0 --- /dev/null +++ b/rtl/nco/pipe_add_48bit.v @@ -0,0 +1,50 @@ + + +module PIPE3_ADD_48BIT( + clk, + rstn, + in, + clr, + ptw, + s1, + s2, + s3, + out +); + +//--- + + input clk; + input rstn; + input [47:0] in; + input clr; + input [15:0] ptw; + + input [15:0] s1; + input [15:0] s2; + input [15:0] s3; + output [18:0] out; + + +//---------------------------------------------------------------------------------------------------- + + reg [47:0] acc; + always@(posedge clk or negedge rstn) + if(!rstn) + acc<=48'h0; + else if(clr) + acc<=48'h0; + else + acc<={s1,s2,s3}+in; +//--- + +wire[18:0] pha_w; +assign pha_w=acc[47:29]; +reg[18:0] pha_r; +always@(posedge clk) + pha_r<=pha_w+{ptw,3'b0}; + + + assign out=pha_r; +//END +endmodule diff --git a/rtl/nco/sin_op.v b/rtl/nco/sin_op.v new file mode 100755 index 0000000..de9b6c4 --- /dev/null +++ b/rtl/nco/sin_op.v @@ -0,0 +1,144 @@ +module SIN_OP( + clk, + rstn, + pha_map, + // pha_indx_msb, + sin_op_o + ); + +input clk; +input rstn; +input[18:0] pha_map; +//output [2:0] pha_indx_msb; +output [14:0] sin_op_o; + +wire [2:0] pha_indx_msb_w; +assign pha_indx_msb_w=pha_map[18:16]; + +wire [15:0] pha_indx_lsb; +assign pha_indx_lsb=pha_map[15:0]; +wire [15:0] pha_op; +assign pha_op=pha_indx_msb_w[0]?(~pha_indx_lsb):pha_indx_lsb; + +wire [4:0] indx; +assign indx=pha_op[15:11]; +wire [10:0] x_w; +assign x_w=pha_op[10:0]; +wire [17:0] c0; +wire [11:0] c1; +wire [4:0] c2; + +COEF_S coef_s_inst1( + .index(indx) , + .C0_S(c0) , + .C1_S(c1) , + .C2_S(c2) + ); + +reg[17:0] c0_r1; +reg[17:0] c0_r2; +reg[17:0] c0_r3; +reg[17:0] c0_r4; +reg[17:0] c0_r5; +reg[17:0] c0_r6; +always@(posedge clk) + begin + c0_r1<=c0; + c0_r2<=c0_r1; + c0_r3<=c0_r2; + c0_r4<=c0_r3; + c0_r5<=c0_r4; + c0_r6<=c0_r5; + end +reg [11:0] c1_r1; +reg [11:0] c1_r2; +reg [11:0] c1_r3; +always@(posedge clk) + begin + c1_r1<=c1; + c1_r2<=c1_r1; + c1_r3<=c1_r2; + end +reg [4:0] c2_r1; +always@(posedge clk) + c2_r1<=c2; +reg[10:0] x_r1; +reg[10:0] x_r2; +reg[10:0] x_r3; +reg[10:0] x_r4; +always@(posedge clk) + begin + x_r1<=x_w; + x_r2<=x_r1; + x_r3<=x_r2; + x_r4<=x_r3; + end + +wire [15:0] c2x; + +DW_mult_pipe #(11,5,2,0,1) inst_mult_0( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r1 ), + .b (c2_r1 ), + .tc (1'b0 ), + .product (c2x ) + ); + + +wire [4:0] c2x_w; +assign c2x_w=c2x[10]?(c2x[15:11]+5'd1):c2x[15:11]; +reg [11:0] c2xc1; +always@(posedge clk) + c2xc1<=c1_r2-c2x_w; + +wire [22:0] c2xc1x; + +DW_mult_pipe #(11,12,3,0,1) inst_mult_1( + .clk (clk ), + .rst_n (rstn ), + .en (1'b1 ), + .a (x_r3 ), + .b (c2xc1 ), + .tc (1'b0 ), + .product (c2xc1x ) + ); + +wire [12:0] c2xc1x_w; +assign c2xc1x_w=c2xc1x[9]?(c2xc1x[22:10]+13'd1):c2xc1x[22:10]; +reg [12:0] c2xc1x_r; +always@(posedge clk) + c2xc1x_r<=c2xc1x_w; +wire[17:0] c2xc1xc0; +assign c2xc1xc0=c0_r6+c2xc1x_r; +wire [14:0] c2xc1xc0_w; +assign c2xc1xc0_w=c2xc1xc0[2]?(c2xc1xc0[17:3]+13'd1):c2xc1xc0[17:3]; +reg [14:0] c2xc1xc0_r; +always@(posedge clk) + c2xc1xc0_r<=c2xc1xc0_w; + +assign sin_op_o=c2xc1xc0_r; +/* +reg[2:0] pha_indx_msb_r1; +reg[2:0] pha_indx_msb_r2; +reg[2:0] pha_indx_msb_r3; +reg[2:0] pha_indx_msb_r4; +reg[2:0] pha_indx_msb_r5; +reg[2:0] pha_indx_msb_r6; +reg[2:0] pha_indx_msb_r7; +always@(posedge clk) + begin + pha_indx_msb_r1<=pha_indx_msb_w; + pha_indx_msb_r2<=pha_indx_msb_r1; + pha_indx_msb_r3<=pha_indx_msb_r2; + pha_indx_msb_r4<=pha_indx_msb_r3; + pha_indx_msb_r5<=pha_indx_msb_r4; + pha_indx_msb_r6<=pha_indx_msb_r5; + pha_indx_msb_r7<=pha_indx_msb_r6; + end + +end +assign pha_indx_msb=pha_indx_msb_r7; +*/ +endmodule diff --git a/rtl/z_dsp.v b/rtl/z_dsp.v index 9c020ae..7afa898 100644 --- a/rtl/z_dsp.v +++ b/rtl/z_dsp.v @@ -8,7 +8,7 @@ //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description -// 0.1 2024-05-15 thfu +// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation //----------------------------------------------------------------------------------------------------------------- // Keywords : // @@ -69,7 +69,11 @@ module z_dsp dout0, dout1, dout2, - dout3 + dout3, + dout4, + dout5, + dout6, + dout7 ); input rstn; @@ -109,6 +113,11 @@ output signed [15:0] dout0; output signed [15:0] dout1; output signed [15:0] dout2; output signed [15:0] dout3; +output signed [15:0] dout4; +output signed [15:0] dout5; +output signed [15:0] dout6; +output signed [15:0] dout7; + wire signed [15:0] IIR_out; @@ -151,8 +160,13 @@ wire signed [15:0] dout_0; wire signed [15:0] dout_1; wire signed [15:0] dout_2; wire signed [15:0] dout_3; +wire signed [15:0] dout_4; +wire signed [15:0] dout_5; +wire signed [15:0] dout_6; +wire signed [15:0] dout_7; -MeanIntp4_top inst_MeanIntp4 + +MeanIntp_8 inst_MeanIntp_8 ( .clk (clk ), .rstn (rstn ), @@ -162,7 +176,12 @@ MeanIntp4_top inst_MeanIntp4 .dout_0 (dout_0 ), .dout_1 (dout_1 ), .dout_2 (dout_2 ), - .dout_3 (dout_3 ) + .dout_3 (dout_3 ), + .dout_4 (dout_4 ), + .dout_5 (dout_5 ), + .dout_6 (dout_6 ), + .dout_7 (dout_7 ) + ); lsdacif inst_lsdacif @@ -175,10 +194,19 @@ lsdacif inst_lsdacif .din1 (dout_1 ), .din2 (dout_2 ), .din3 (dout_3 ), + .din4 (dout_4 ), + .din5 (dout_5 ), + .din6 (dout_6 ), + .din7 (dout_7 ), .dout0 (dout0 ), .dout1 (dout1 ), .dout2 (dout2 ), - .dout3 (dout3 ) + .dout3 (dout3 ), + .dout4 (dout4 ), + .dout5 (dout5 ), + .dout6 (dout6 ), + .dout7 (dout7 ) + ); endmodule diff --git a/script_m/MyIIR_test.m b/script_m/MyIIR_test.m index 739e03a..66b6dd5 100755 --- a/script_m/MyIIR_test.m +++ b/script_m/MyIIR_test.m @@ -1,5 +1,6 @@ clc;clear;close all +%%%verification of single IIR Filter by comparing matlab and verilog cd('/data/work/thfu/TailCorr/script_m'); a = 13740916; diff --git a/script_m/PolyMean_Test.m b/script_m/PolyMean_Test.m index e60c531..d6c0c52 100755 --- a/script_m/PolyMean_Test.m +++ b/script_m/PolyMean_Test.m @@ -1,3 +1,4 @@ +%%%verification of polyphase structures using trig clc;clear all;close all fs = 1e8; diff --git a/script_m/TailCorr_8inpt_test.m b/script_m/TailCorr_8inpt_test.m new file mode 100644 index 0000000..dc24b6a --- /dev/null +++ b/script_m/TailCorr_8inpt_test.m @@ -0,0 +1,63 @@ +%%%2024-10-15 +%%%verification 8 linear interpolation result by comparing matlab and verilog result +clc;clear;close all + +cd('/data/work/thfu/TailCorr/script_m'); + +sel_double = 0; + +switch sel_double + + case 0 + iir_in_verilog = int64(importdata("/home/thfu/work/TailCorr/sim/in.dat") - 32768); +% iir_out_x1 = int64(importdata("/home/thfu/work/TailCorr/sim/X1_data.dat") -32768); +% iir_out_x2 = int64(importdata("/home/thfu/work/TailCorr/sim/X2_data.dat") -32768); +% iir_out_x4 = int64(importdata("/home/thfu/work/TailCorr/sim/X4_data.dat") -32768); + iir_out_verilog_x8 = int64(importdata("/home/thfu/work/TailCorr/sim/X8_data.dat") -32768); + + case 1 + iir_in = double(importdata("/home/thfu/work/TailCorr/sim/in") + 0); + iir_out_x1 = double(importdata("/home/thfu/work/TailCorr/sim/X1_data.dat") - 32768); + iir_out_x2 = double(importdata("/home/thfu/work/TailCorr/sim/X2_data.dat") - 32768); + iir_out_x4 = double(importdata("/home/thfu/work/TailCorr/sim/X4_data.dat") - 32768); + iir_out_x8 = double(importdata("/home/thfu/work/TailCorr/sim/X8_data.dat") - 32768); + +end +% iir_out_x1 = [iir_out_x1' zeros(1,2)]'; +% iir_out_x2 = [iir_out_x2' zeros(1,3)]'; +% iir_out_x4 = [iir_out_x4' zeros(1,6)]'; + +alpha = [1757225200, 1045400392, 13740916]; +beta = -[1042856 1046395 1047703]; + + +Ystart = 0; + +y_revised_matlab = TailCorr(alpha,beta,iir_in_verilog,Ystart,sel_double); + +N = length(y_revised_matlab); +x1 = (1:1:N)'; +x8 = (1:1/8:N+1-1/8)'; +y_revised_intp8_matlab = int64(interp1(x1,double(y_revised_matlab),x8,'linear')); + + +%%% +%tau0 = finddelay(y_revised_matlab,iir_out_x1); +%y_revisedPhi0 = cat(1,zeros(1,tau0)',y_revised_matlab(1:end-tau0,1)); +%figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]); +%diff_plot(iir_out_x1, y_revisedPhi0,'verdi','matlab',[200 N]); +%%% +%tau2 = finddelay(s_intp2,iir_out_x2); +%y_revisedPhi2 = cat(1,zeros(1,tau2)',s_intp2(1:end-tau2,1)); +%figure('Units','normalized','Position',[0.500390625,0.517361111111111,0.49921875,0.422916666666667]); +%diff_plot(iir_out_x2, y_revisedPhi2,'verdi','matlab',[0 4e4]) +%%% +%tau4 = finddelay(s_intp4,iir_out_x4); +%y_revisedPhi4 = cat(1,zeros(1,tau4)',s_intp4(1:end-tau4,1)); +%figure('Units','normalized','Position',[0.000390625,0.034027777777778,0.49921875,0.422916666666667]); +%diff_plot(iir_out_x4, y_revisedPhi4,'verdi','matlab',[0 8e4]) +%%% +tau8 = finddelay(y_revised_intp8_matlab,iir_out_verilog_x8); +y_revisedPhi8 = cat(1,zeros(1,tau8)',y_revised_intp8_matlab(1:end-tau8,1)); +figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]); +diff_plot(iir_out_verilog_x8, y_revisedPhi8,'verdi','matlab',[400 800]); diff --git a/script_m/TailCorr_test_P.m b/script_m/TailCorr_test_P.m index 40fad92..8dbe9ef 100755 --- a/script_m/TailCorr_test_P.m +++ b/script_m/TailCorr_test_P.m @@ -1,3 +1,4 @@ +%%%20241009,comparing matlab and verilog result clc;clear;close all cd('/data/work/thfu/TailCorr/script_m'); diff --git a/script_m/intp8_Test.m b/script_m/intp8_Test.m new file mode 100755 index 0000000..dfd425f --- /dev/null +++ b/script_m/intp8_Test.m @@ -0,0 +1,21 @@ +%%%2024-10-17,verify 8 intp by comparing matlab and verilog +clc;clear all;close all; + +in = importdata("/home/thfu/work/TailCorr/sim/in_intp8.dat"); +intp8_verilog = importdata("/home/thfu/work/TailCorr/sim/out_intp8.dat"); + +N = length(in); +time = 1:1:N; +time8 = 1:1/8:N+1-1/8; +intp8_matlab = floor(interp1(time,in,time8,'linear'))'; + +%figure +%plot(time,in); +%hold on +%plot(time8,intp8_verilog); +%xlim([4500 5500]) + +tau8 = finddelay(intp8_matlab(1.8e4:3e4),intp8_verilog(1.8e4:3e4)); +intp8_matlab_revised = cat(1,zeros(1,tau8)',intp8_matlab(1:end-tau8,1)); +figure('Units','normalized','Position',[0.000390625,0.517361111111111,0.49921875,0.422916666666667]); +diff_plot(intp8_verilog, intp8_matlab_revised,'verdi','matlab',[2e4 2.2e4]); diff --git a/sim/files.f b/sim/files.f index 418ad70..a8bf052 100644 --- a/sim/files.f +++ b/sim/files.f @@ -1,22 +1,22 @@ -../rtl/Tail/diff.v -../rtl/Tail/DW02_mult.v -../rtl/Tail/IIR_Filter.v -../rtl/Tail/lsdacif.v -../rtl/Tail/MeanIntp_8.v -../rtl/Tail/mult_C.v -../rtl/Tail/TailCorr_top.v -//../rtl/Tail/z_dsp.v -../rtl/Tail/sirv_gnrl_dffs.v -../rtl/Tail/sirv_gnrl_xchecker.v +../rtl/diff.v +../rtl/DW_mult_pipe.v +../rtl/mult_C.v +//../rtl/z_data_mux.v +../rtl/nco/coef_c.v +../rtl/nco/pipe_acc_48bit.v +../rtl/nco/pipe_add_48bit.v +../rtl/nco/p_nco.v ../rtl/nco/coef_s.v ../rtl/nco/nco.v -../rtl/nco/coef_c.v -../rtl/nco/ph2amp.v ../rtl/nco/sin_op.v -../rtl/nco/p_nco.v -../rtl/nco/pipe_add_48bit.v +../rtl/nco/ph2amp.v ../rtl/nco/cos_op.v -../rtl/nco/pipe_acc_48bit.v -../rtl/nco/DW_mult_pipe.v -../tb/tb_mean8_top.v +../rtl/lsdacif.v +../rtl/TailCorr_top.v +../rtl/z_dsp.v +../rtl/MeanIntp_8.v +../rtl/DW02_mult.v +../rtl/IIR_Filter.v ../tb/clk_gen.v +../tb/tb_top.v + diff --git a/tb/tb_mean8_top.v b/tb/tb_mean8_top.v index d329eca..0b2356f 100644 --- a/tb/tb_mean8_top.v +++ b/tb/tb_mean8_top.v @@ -6,159 +6,204 @@ begin $fsdbDumpvars(0, TB); end -reg clk; -reg rstn; -reg en; -reg [21:0] cnt; +reg clk; +reg rstn; +reg en; +reg [21:0] cnt; -initial begin +initial begin - #0; - rstn = 1'b0; - clk = 1'b0; - en = 1'b0; - #300; - rstn = 1'b1; + #0; + rstn = 1'b0; + clk = 1'b0; + en = 1'b0; + #300; + rstn = 1'b1; end always #200 clk = ~clk; -wire clk_div16_0; -wire clk_div16_1; -wire clk_div16_2; -wire clk_div16_3; -wire clk_div16_4; -wire clk_div16_5; -wire clk_div16_6; -wire clk_div16_7; -wire clk_div16_8; -wire clk_div16_9; -wire clk_div16_a; -wire clk_div16_b; -wire clk_div16_c; -wire clk_div16_d; -wire clk_div16_e; -wire clk_div16_f; +wire clk_div16_0; +wire clk_div16_1; +wire clk_div16_2; +wire clk_div16_3; +wire clk_div16_4; +wire clk_div16_5; +wire clk_div16_6; +wire clk_div16_7; +wire clk_div16_8; +wire clk_div16_9; +wire clk_div16_a; +wire clk_div16_b; +wire clk_div16_c; +wire clk_div16_d; +wire clk_div16_e; +wire clk_div16_f; clk_gen inst_clk_gen( - .rstn (rstn ), - .clk (clk ), - .clk_div16_0 (clk_div16_0 ), - .clk_div16_1 (clk_div16_1 ), - .clk_div16_2 (clk_div16_2 ), - .clk_div16_3 (clk_div16_3 ), - .clk_div16_4 (clk_div16_4 ), - .clk_div16_5 (clk_div16_5 ), - .clk_div16_6 (clk_div16_6 ), - .clk_div16_7 (clk_div16_7 ), - .clk_div16_8 (clk_div16_8 ), - .clk_div16_9 (clk_div16_9 ), - .clk_div16_a (clk_div16_a ), - .clk_div16_b (clk_div16_b ), - .clk_div16_c (clk_div16_c ), - .clk_div16_d (clk_div16_d ), - .clk_div16_e (clk_div16_e ), - .clk_div16_f (clk_div16_f ), + .rstn (rstn ), + .clk (clk ), + .clk_div16_0 (clk_div16_0 ), + .clk_div16_1 (clk_div16_1 ), + .clk_div16_2 (clk_div16_2 ), + .clk_div16_3 (clk_div16_3 ), + .clk_div16_4 (clk_div16_4 ), + .clk_div16_5 (clk_div16_5 ), + .clk_div16_6 (clk_div16_6 ), + .clk_div16_7 (clk_div16_7 ), + .clk_div16_8 (clk_div16_8 ), + .clk_div16_9 (clk_div16_9 ), + .clk_div16_a (clk_div16_a ), + .clk_div16_b (clk_div16_b ), + .clk_div16_c (clk_div16_c ), + .clk_div16_d (clk_div16_d ), + .clk_div16_e (clk_div16_e ), + .clk_div16_f (clk_div16_f ), .clk_h (clk_h ), .clk_l (clk_l ) - ); + ); always@(posedge clk_div16_f or negedge rstn) - if(!rstn) - cnt <= 22'd0; - else - cnt <= cnt + 22'd1; + if(!rstn) + cnt <= 22'd0; + else + cnt <= cnt + 22'd1; -initial begin - wait(cnt[17]==1'b1) - $finish(0); +initial begin + wait(cnt[17]==1'b1) + $finish(0); end always@(posedge clk_div16_f or negedge rstn) begin - if(cnt >= 2047 ) - begin - en <= 1'b1; - end - else - begin - en <= 1'b0; - end + if(cnt >= 2047 ) + begin + en <= 1'b1; + end + else + begin + en <= 1'b0; + end end -reg [47:0] fcw; +reg [47:0] fcw; -initial begin - fcw = 48'h0840_0000_0000; +initial begin + fcw = 48'h0840_0000_0000; end wire [15:0] cos; wire [15:0] sin; -NCO inst_nco_0( - .clk (clk_div16_f ), - .rstn (rstn ), - .phase_manual_clr (1'b0 ), - .phase_auto_clr (1'b0 ), - .fcw (fcw ), - .pha (16'd0 ), - .cos (cos ), - .sin (sin ) - ); +NCO inst_nco_0( + .clk (clk_div16_f ), + .rstn (rstn ), + .phase_manual_clr (1'b0 ), + .phase_auto_clr (1'b0 ), + .fcw (fcw ), + .pha (16'd0 ), + .cos (cos ), + .sin (sin ) + ); -wire [15:0] dout_p0; -wire [15:0] dout_p1; -wire [15:0] dout_p2; -wire [15:0] dout_p3; -wire [15:0] dout_p4; -wire [15:0] dout_p5; -wire [15:0] dout_p6; -wire [15:0] dout_p7; +wire [15:0] dout_p0; +wire [15:0] dout_p1; +wire [15:0] dout_p2; +wire [15:0] dout_p3; +wire [15:0] dout_p4; +wire [15:0] dout_p5; +wire [15:0] dout_p6; +wire [15:0] dout_p7; -assign intp_mode = 2'b10; +wire [1:0] intp_mode; +assign intp_mode = 2'b11; -MeanIntp_8 inst_MeanIntp8 - ( - .clk (clk_div16_f ), - .rstn (rstn ), - .en (en ), - .din (cos & {16{en}} ), - .dout_0 (dout_p0 ), - .dout_1 (dout_p1 ), - .dout_2 (dout_p2 ), - .dout_3 (dout_p3 ), - .dout_4 (dout_p4 ), - .dout_5 (dout_p5 ), - .dout_6 (dout_p6 ), - .dout_7 (dout_p7 ) +MeanIntp_8 inst_MeanIntp8 + ( + .clk (clk_div16_f ), + .rstn (rstn ), + .en (en ), + .intp_mode (intp_mode ), + .din (cos & {16{en}} ), + .dout_0 (dout_p0 ), + .dout_1 (dout_p1 ), + .dout_2 (dout_p2 ), + .dout_3 (dout_p3 ), + .dout_4 (dout_p4 ), + .dout_5 (dout_p5 ), + .dout_6 (dout_p6 ), + .dout_7 (dout_p7 ) ); +integer signed In_fid; +integer X8_fid; -reg [15:0] cs_wave; +initial begin + #0 + + In_fid = $fopen("./in_intp8.dat"); + X8_fid = $fopen("./out_intp8.dat"); + +end + +always@(posedge clk_div16_f) + if(cnt >= 90) + $fwrite(In_fid,"%d\n",{{{~cos[15]}},cos[14:0]}); + +reg [15:0] cs_wave; always@(*) fork -// begin - @(posedge clk_div16_e) cs_wave = dout_p0; - @(posedge clk_div16_c) cs_wave = dout_p1; - @(posedge clk_div16_a) cs_wave = dout_p2; - @(posedge clk_div16_8) cs_wave = dout_p3; - @(posedge clk_div16_6) cs_wave = dout_p4; - @(posedge clk_div16_4) cs_wave = dout_p5; - @(posedge clk_div16_2) cs_wave = dout_p6; - @(posedge clk_div16_0) cs_wave = dout_p7; +// begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_c) cs_wave = dout_p1; + @(posedge clk_div16_a) cs_wave = dout_p2; + @(posedge clk_div16_8) cs_wave = dout_p3; + @(posedge clk_div16_6) cs_wave = dout_p4; + @(posedge clk_div16_4) cs_wave = dout_p5; + @(posedge clk_div16_2) cs_wave = dout_p6; + @(posedge clk_div16_0) cs_wave = dout_p7; // end join -endmodule - - +always@(*) + fork + + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p0[15]}},dout_p0[14:0]}); + @(posedge clk_div16_c) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p1[15]}},dout_p1[14:0]}); + @(posedge clk_div16_a) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p2[15]}},dout_p2[14:0]}); + @(posedge clk_div16_8) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p3[15]}},dout_p3[14:0]}); + @(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p4[15]}},dout_p4[14:0]}); + @(posedge clk_div16_4) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p5[15]}},dout_p5[14:0]}); + @(posedge clk_div16_2) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p6[15]}},dout_p6[14:0]}); + @(posedge clk_div16_0) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{~dout_p7[15]}},dout_p7[14:0]}); + join + +endmodule + + diff --git a/tb/tb_top.v b/tb/tb_top.v index fc51c3c..26b7c17 100644 --- a/tb/tb_top.v +++ b/tb/tb_top.v @@ -184,7 +184,7 @@ always@(posedge clk_div16_f or negedge rstn) always@(posedge clk_div16_f or negedge rstn) if(!rstn) en <= 22'd0; - else if(cnt >= 100 ) + else if(cnt >= 90 ) begin en <= 1'b1; end @@ -196,9 +196,9 @@ always@(posedge clk_div16_f or negedge rstn) iir_in <= 16'd0; end else - din_cos <= cos; + din_cos <= {cos[15],cos[15:1]}; -assign source_mode = 2'b01; +assign source_mode = 2'b10; always @(*) @@ -227,18 +227,26 @@ wire [15:0] dout_p0; wire [15:0] dout_p1; wire [15:0] dout_p2; wire [15:0] dout_p3; +wire [15:0] dout_p4; +wire [15:0] dout_p5; +wire [15:0] dout_p6; +wire [15:0] dout_p7; wire [1:0] intp_mode; -assign intp_mode = 2'b10; +assign intp_mode = 2'b11; wire [1:0] dac_mode_sel; assign dac_mode_sel = 2'b00; +wire tc_bypass; +assign tc_bypass = 1'b0; + z_dsp inst_Z_dsp ( - .clk (clk_div16_f ), + .clk (clk_div16_f ), .rstn (rstn ), .en (en ), + .tc_bypass (tc_bypass ), .dac_mode_sel (dac_mode_sel ), .intp_mode (intp_mode ), .din_re (iir_in ), @@ -270,7 +278,12 @@ z_dsp inst_Z_dsp .dout0 (dout_p0 ), .dout1 (dout_p1 ), .dout2 (dout_p2 ), - .dout3 (dout_p3 ) + .dout3 (dout_p3 ), + .dout4 (dout_p4 ), + .dout5 (dout_p5 ), + .dout6 (dout_p6 ), + .dout7 (dout_p7 ) + ); @@ -295,6 +308,18 @@ always@(*) @(posedge clk_div16_6) cs_wave = dout_p2; @(posedge clk_div16_2) cs_wave = dout_p3; end + 2'b11 : + begin + @(posedge clk_div16_e) cs_wave = dout_p0; + @(posedge clk_div16_c) cs_wave = dout_p1; + @(posedge clk_div16_a) cs_wave = dout_p2; + @(posedge clk_div16_8) cs_wave = dout_p3; + @(posedge clk_div16_6) cs_wave = dout_p4; + @(posedge clk_div16_4) cs_wave = dout_p5; + @(posedge clk_div16_2) cs_wave = dout_p6; + @(posedge clk_div16_0) cs_wave = dout_p7; + end + endcase join @@ -302,21 +327,24 @@ integer signed In_fid; integer X1_fid; integer X2_fid; integer X4_fid; +integer X8_fid; initial begin #0; - In_fid = $fopen("./in"); + In_fid = $fopen("./in.dat"); case (intp_mode) 2'b00 : X1_fid = $fopen("./X1_data.dat"); 2'b01 : X2_fid = $fopen("./X2_data.dat"); 2'b10 : X4_fid = $fopen("./X4_data.dat"); + 2'b11 : X8_fid = $fopen("./X8_data.dat"); + endcase end always@(posedge clk_div16_f) if(cnt >= 90) - $fwrite(In_fid,"%d\n",{{{iir_in[15]}},iir_in[14:0]}); + $fwrite(In_fid,"%d\n",{{{~iir_in[15]}},iir_in[14:0]}); always@(*) @@ -352,6 +380,35 @@ always@(*) if(cnt >= 90) $fwrite(X4_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]}); end + 2'b11 : + begin + @(posedge clk_div16_e) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p0[15]}},dout_p0[14:0]}); + @(posedge clk_div16_c) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p1[15]}},dout_p1[14:0]}); + @(posedge clk_div16_a) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p2[15]}},dout_p2[14:0]}); + @(posedge clk_div16_8) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p3[15]}},dout_p3[14:0]}); + @(posedge clk_div16_6) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p4[15]}},dout_p4[14:0]}); + @(posedge clk_div16_4) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p5[15]}},dout_p5[14:0]}); + @(posedge clk_div16_2) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p6[15]}},dout_p6[14:0]}); + @(posedge clk_div16_0) + if(cnt >= 90) + $fwrite(X8_fid,"%d\n",{{{dout_p7[15]}},dout_p7[14:0]}); + + end + endcase join