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复数乘法器资源优化 

乘法器开销由4个优化至3个
This commit is contained in:
futh0403 2025-05-26 18:19:26 +08:00
parent c2e7492c21
commit bcd12f7063
1 changed files with 12 additions and 43 deletions
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53
rtl/z_dsp/mult_C.v
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@ -1,36 +1,3 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : mult_C.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.1 2024-05-28 thfu
//2024-05-28 10:22:18
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C #( module mult_C #(
parameter integer A_width = 8 parameter integer A_width = 8
,parameter integer B_width = 8 ,parameter integer B_width = 8
@ -72,6 +39,13 @@ wire signed [A_width+D_width :0] Im_tmp;
wire signed [o_width-1 :0] Re_trunc; wire signed [o_width-1 :0] Re_trunc;
wire signed [o_width-1 :0] Im_trunc; wire signed [o_width-1 :0] Im_trunc;
wire signed [A_width:0] sum_ab;
wire signed [C_width:0] sum_cd;
wire signed [A_width+C_width+1:0] product_of_sums;
assign sum_ab = a + b;
assign sum_cd = c + d;
DW02_mult #(A_width,C_width) inst_c1( .A (a ), DW02_mult #(A_width,C_width) inst_c1( .A (a ),
.B (c ), .B (c ),
@ -85,19 +59,14 @@ DW02_mult #(B_width,D_width) inst_c2( .A (b
.PRODUCT (bd ) .PRODUCT (bd )
); );
DW02_mult #(A_width,D_width) inst_c3( .A (a ), DW02_mult #(A_width+1,D_width+1) inst_c3( .A (sum_ab ),
.B (d ), .B (sum_cd ),
.TC (1'b1 ), .TC (1'b1 ),
.PRODUCT (ad ) .PRODUCT (product_of_sums)
);
DW02_mult #(B_width,C_width) inst_c4( .A (b ),
.B (c ),
.TC (1'b1 ),
.PRODUCT (bc )
); );
assign Re_tmp = ac - bd; assign Re_tmp = ac - bd;
assign Im_tmp = ad + bc; assign Im_tmp = product_of_sums - ac - bd;
trunc #( trunc #(
.diw (A_width+C_width+1 ) .diw (A_width+C_width+1 )