diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v
index d386159..41a130f 100644
--- a/rtl/z_dsp/mult_C.v
+++ b/rtl/z_dsp/mult_C.v
@@ -1,36 +1,3 @@
-//+FHDR--------------------------------------------------------------------------------------------------------
-//  Company: 
-//-----------------------------------------------------------------------------------------------------------------
-//  File Name             :    mult_C.v
-//  Department            :    
-//  Author                :    thfu
-//  Author's Tel          :     
-//-----------------------------------------------------------------------------------------------------------------
-//  Relese History
-//  Version     Date            Author          Description
-//  0.1         2024-05-28      thfu
-//2024-05-28 10:22:18 
-//-----------------------------------------------------------------------------------------------------------------
-//  Keywords            :       
-//
-//-----------------------------------------------------------------------------------------------------------------
-//  Parameter
-//
-//-----------------------------------------------------------------------------------------------------------------
-//  Purpose                 :
-//                      
-//-----------------------------------------------------------------------------------------------------------------
-//  Target Device:        
-//  Tool versions:        
-//-----------------------------------------------------------------------------------------------------------------
-//  Reuse Issues
-//  Reset Strategy: 
-//  Clock Domains: 
-//  Critical Timing:
-//  Asynchronous I/F:
-//  Synthesizable (y/n): 
-//  Other:
-//-FHDR--------------------------------------------------------------------------------------------------------
 module mult_C #(
  parameter    integer    A_width = 8
 ,parameter    integer    B_width = 8
@@ -72,6 +39,13 @@ wire        signed  [A_width+D_width  :0]       Im_tmp;
 wire        signed  [o_width-1        :0]       Re_trunc;
 wire        signed  [o_width-1        :0]       Im_trunc;
 
+wire        signed  [A_width:0]       sum_ab;   
+wire        signed  [C_width:0]       sum_cd;   
+wire        signed  [A_width+C_width+1:0]       product_of_sums;
+
+assign sum_ab = a + b;
+assign sum_cd = c + d;
+
 
 DW02_mult       #(A_width,C_width) inst_c1(     .A              (a              ),
                                                 .B              (c              ),
@@ -85,19 +59,14 @@ DW02_mult       #(B_width,D_width) inst_c2(     .A              (b
                                                 .PRODUCT        (bd             )
                                 );
 
-DW02_mult       #(A_width,D_width) inst_c3(     .A              (a              ),
-                                                .B              (d              ),
+DW02_mult       #(A_width+1,D_width+1) inst_c3( .A              (sum_ab         ),
+                                                .B              (sum_cd         ),
                                                 .TC             (1'b1           ),
-                                                .PRODUCT        (ad             )
-                                );
-DW02_mult       #(B_width,C_width) inst_c4(     .A              (b              ),
-                                                .B              (c              ),
-                                                .TC             (1'b1           ),
-                                                .PRODUCT        (bc             )
+                                                .PRODUCT        (product_of_sums)
                                 );
 
 assign    Re_tmp  =  ac - bd;
-assign    Im_tmp  =  ad + bc;
+assign    Im_tmp  =  product_of_sums - ac - bd;
 
 trunc #(
          .diw   (A_width+C_width+1              )
@@ -114,4 +83,4 @@ trunc #(
 assign  Re = Re_trunc;
 assign  Im = Im_trunc;
 
-endmodule
+endmodule
\ No newline at end of file