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八路并行的IIR滤波器； 

未来需要在片上实时生成系数；
需要提高代码可读性
This commit is contained in:
thfu 2025-03-03 18:10:00 +08:00 committed by futh0403
parent 59eb3f1d1c
commit ba57872c55
10 changed files with 1808 additions and 675 deletions
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216
rtl/z_dsp/IIR_Filter_p2.v
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@ -1,216 +0,0 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p2 #(
parameter data_in_width = 16
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1:0] din
,input signed [data_in_width-1:0] din_r1
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] bb_re
,input signed [coef_width-1 :0] bb_im
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width+frac_data_out_width:0] x1_re;
wire signed [data_in_width+frac_data_out_width:0] x1_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din ),//x(n)
.b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x(n-1)
.Im (x1_im )
);
wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (din_r1 ),//x(n-1)
.b (16'd0 ),
.c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*x(n-2)
.Im (x2_im )
);
wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im;
assign v_re = x1_re + x2_re;//a*x(n-1)+a*b*x(n-2)
assign v_im = x1_im + x2_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re;//a*x(n-2)+a*b*x(n-3)
reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im;
reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
reg signed [data_in_width+frac_data_out_width+3:0] y2_re;
reg signed [data_in_width+frac_data_out_width+3:0] y2_im;
reg signed [data_in_width-1:0] dout_re;
mult_C
#(
.A_width(data_in_width+frac_data_out_width+2)
,.B_width(data_in_width+frac_data_out_width+2)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),//y(n-2)=a*x(n-2)+a*b*x(n-3)+b^2*y(n-4)
.b (y_im ),
.c (bb_re ),
.d (bb_im ),
.Re (y1_re ),//b*y(n-3)
.Im (y1_im )
);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
y2_re <= 'h0;
y2_im <= 'h0;
end
else if(en)
begin
y2_re <= y1_re;
y2_im <= y1_im;
end
else
begin
y2_re <= y2_re;
y2_im <= y2_im;
end
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule

345
rtl/z_dsp/IIR_Filter_p8.v Normal file
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : IIR_Filter.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.4 2024-05-28 thfu
//2024-05-28 10:22:49
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_Filter_p8 #(
parameter data_in_width = 16
,parameter coef_width = 32
,parameter frac_data_out_width = 20//X for in,5
,parameter frac_coef_width = 31//division
)
(
input rstn
,input clk
,input en
,input signed [data_in_width-1:0] dinp0
,input signed [data_in_width-1:0] dinp1
,input signed [data_in_width-1:0] dinp2
,input signed [data_in_width-1:0] dinp3
,input signed [data_in_width-1:0] dinp4
,input signed [data_in_width-1:0] dinp5
,input signed [data_in_width-1:0] dinp6
,input signed [data_in_width-1:0] dinp7
,input signed [coef_width-1 :0] a_re
,input signed [coef_width-1 :0] a_im
,input signed [coef_width-1 :0] ab_re
,input signed [coef_width-1 :0] ab_im
,input signed [coef_width-1 :0] abb_re
,input signed [coef_width-1 :0] abb_im
,input signed [coef_width-1 :0] ab_pow3_re
,input signed [coef_width-1 :0] ab_pow3_im
,input signed [coef_width-1 :0] ab_pow4_re
,input signed [coef_width-1 :0] ab_pow4_im
,input signed [coef_width-1 :0] ab_pow5_re
,input signed [coef_width-1 :0] ab_pow5_im
,input signed [coef_width-1 :0] ab_pow6_re
,input signed [coef_width-1 :0] ab_pow6_im
,input signed [coef_width-1 :0] ab_pow7_re
,input signed [coef_width-1 :0] ab_pow7_im
,input signed [coef_width-1 :0] b_pow8_re
,input signed [coef_width-1 :0] b_pow8_im
,output signed [data_in_width-1:0] dout
);
wire signed [data_in_width+frac_data_out_width:0] x1_re;
wire signed [data_in_width+frac_data_out_width:0] x1_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp0 ),
.b (16'b0 ),
.c ({a_re,{frac_data_out_width{1'b0}}}),
.d ({a_im,{frac_data_out_width{1'b0}}}),
.Re (x1_re ),//a*x*dinp0
.Im (x1_im )
);
wire signed [data_in_width+frac_data_out_width:0] x2_re;
wire signed [data_in_width+frac_data_out_width:0] x2_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp1 ),
.b (16'd0 ),
.c ({ab_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_im,{frac_data_out_width{1'b0}}} ),
.Re (x2_re ),//a*b*dinp1
.Im (x2_im )
);
wire signed [data_in_width+frac_data_out_width:0] x3_re;
wire signed [data_in_width+frac_data_out_width:0] x3_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp2 ),
.b (16'd0 ),
.c ({abb_re,{frac_data_out_width{1'b0}}} ),
.d ({abb_im,{frac_data_out_width{1'b0}}} ),
.Re (x3_re ),//a*b*b*dinp2
.Im (x3_im )
);
wire signed [data_in_width+frac_data_out_width:0] x4_re;
wire signed [data_in_width+frac_data_out_width:0] x4_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp3 ),
.b (16'd0 ),
.c ({ab_pow3_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow3_im,{frac_data_out_width{1'b0}}} ),
.Re (x4_re ),//a*b^3*dinp3
.Im (x4_im )
);
wire signed [data_in_width+frac_data_out_width:0] x5_re;
wire signed [data_in_width+frac_data_out_width:0] x5_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp4 ),
.b (16'd0 ),
.c ({ab_pow4_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow4_im,{frac_data_out_width{1'b0}}} ),
.Re (x5_re ),//a*b^4*dinp4
.Im (x5_im )
);
wire signed [data_in_width+frac_data_out_width:0] x6_re;
wire signed [data_in_width+frac_data_out_width:0] x6_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp5 ),
.b (16'd0 ),
.c ({ab_pow5_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow5_im,{frac_data_out_width{1'b0}}} ),
.Re (x6_re ),//a*b^5*dinp5
.Im (x6_im )
);
wire signed [data_in_width+frac_data_out_width:0] x7_re;
wire signed [data_in_width+frac_data_out_width:0] x7_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp6 ),
.b (16'd0 ),
.c ({ab_pow6_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow6_im,{frac_data_out_width{1'b0}}} ),
.Re (x7_re ),//a*b^6*dinp6
.Im (x7_im )
);
wire signed [data_in_width+frac_data_out_width:0] x8_re;
wire signed [data_in_width+frac_data_out_width:0] x8_im;
mult_C
#(
.A_width(data_in_width)
,.B_width(data_in_width)
,.C_width(coef_width+frac_data_out_width)
,.D_width(coef_width+frac_data_out_width)
,.frac_coef_width(frac_coef_width)
)
inst_c8 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (dinp7 ),
.b (16'd0 ),
.c ({ab_pow7_re,{frac_data_out_width{1'b0}}} ),
.d ({ab_pow7_im,{frac_data_out_width{1'b0}}} ),
.Re (x8_re ),//a*b^7*dinp7
.Im (x8_im )
);
wire signed [data_in_width+frac_data_out_width+1:0] v_re;
wire signed [data_in_width+frac_data_out_width+1:0] v_im;
assign v_re = x1_re + x2_re + x3_re + x4_re + x5_re + x6_re + x7_re + x8_re;
assign v_im = x1_im + x2_im + x3_im + x4_im + x5_im + x6_im + x7_im + x8_im;
reg signed [data_in_width+frac_data_out_width+1:0] v1_re;
reg signed [data_in_width+frac_data_out_width+1:0] v1_im;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
v1_re <= 'h0;
v1_im <= 'h0;
end
else if(en)
begin
v1_re <= v_re;
v1_im <= v_im;
end
else
begin
v1_re <= v1_re;
v1_im <= v1_im;
end
wire signed [data_in_width+frac_data_out_width+1:0] y_re;
wire signed [data_in_width+frac_data_out_width+1:0] y_im;
reg signed [data_in_width+frac_data_out_width+2:0] y1_re;
reg signed [data_in_width+frac_data_out_width+2:0] y1_im;
reg signed [data_in_width-1:0] dout_re;
mult_C
#(
.A_width(data_in_width+frac_data_out_width+2)
,.B_width(data_in_width+frac_data_out_width+2)
,.C_width(coef_width)
,.D_width(coef_width)
,.frac_coef_width(frac_coef_width)
)
inst_c9 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.a (y_re ),
.b (y_im ),
.c (b_pow8_re ),
.d (b_pow8_im ),
.Re (y1_re ),//b^8*y(n-1)
.Im (y1_im )
);
assign y_re = v1_re + y1_re;
assign y_im = v1_im + y1_im;
wire signed [data_in_width+frac_data_out_width+1:0] dout_round;
FixRound #(data_in_width+frac_data_out_width+2,frac_data_out_width) u_round1 (clk, rstn, en, y_re, dout_round);
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_re <= 'h0;
end
else if(en)
begin
dout_re <= dout_round[frac_data_out_width+15:frac_data_out_width];
end
else
begin
dout_re <= dout_re;
end
reg signed [data_in_width-1:0] dout_clip;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
dout_clip <= 'h0;
end
else if(en)
begin
if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b01)
dout_clip <= 16'd32767;
else if(dout_round[frac_data_out_width+16:frac_data_out_width+15]==2'b10)
dout_clip <= -16'd32768;
else
dout_clip <= dout_re;
end
else
begin
dout_clip <= dout_clip;
end
assign dout = dout_clip;
endmodule

379
rtl/z_dsp/IIR_top.v Normal file
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//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module IIR_top
(
input rstn
,input clk
,input en
,input signed [15:0] IIRin_p0
,input signed [15:0] IIRin_p1
,input signed [15:0] IIRin_p2
,input signed [15:0] IIRin_p3
,input signed [15:0] IIRin_p4
,input signed [15:0] IIRin_p5
,input signed [15:0] IIRin_p6
,input signed [15:0] IIRin_p7
,input signed [31 :0] a_re
,input signed [31 :0] a_im
,input signed [31 :0] ab_re
,input signed [31 :0] ab_im
,input signed [31 :0] abb_re
,input signed [31 :0] abb_im
,input signed [31 :0] ab_pow3_re
,input signed [31 :0] ab_pow3_im
,input signed [31 :0] ab_pow4_re
,input signed [31 :0] ab_pow4_im
,input signed [31 :0] ab_pow5_re
,input signed [31 :0] ab_pow5_im
,input signed [31 :0] ab_pow6_re
,input signed [31 :0] ab_pow6_im
,input signed [31 :0] ab_pow7_re
,input signed [31 :0] ab_pow7_im
,input signed [31 :0] b_pow8_re
,input signed [31 :0] b_pow8_im
,output signed [15:0] IIRout_p0
,output signed [15:0] IIRout_p1
,output signed [15:0] IIRout_p2
,output signed [15:0] IIRout_p3
,output signed [15:0] IIRout_p4
,output signed [15:0] IIRout_p5
,output signed [15:0] IIRout_p6
,output signed [15:0] IIRout_p7
);
reg signed [15:0] IIRin_p0_r1;
reg signed [15:0] IIRin_p1_r1;
reg signed [15:0] IIRin_p2_r1;
reg signed [15:0] IIRin_p3_r1;
reg signed [15:0] IIRin_p4_r1;
reg signed [15:0] IIRin_p5_r1;
reg signed [15:0] IIRin_p6_r1;
reg signed [15:0] IIRin_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
IIRin_p0_r1 <= 'h0;
IIRin_p1_r1 <= 'h0;
IIRin_p2_r1 <= 'h0;
IIRin_p3_r1 <= 'h0;
IIRin_p4_r1 <= 'h0;
IIRin_p5_r1 <= 'h0;
IIRin_p6_r1 <= 'h0;
IIRin_p7_r1 <= 'h0;
end
else if(en)
begin
IIRin_p0_r1 <= IIRin_p0;
IIRin_p1_r1 <= IIRin_p1;
IIRin_p2_r1 <= IIRin_p2;
IIRin_p3_r1 <= IIRin_p3;
IIRin_p4_r1 <= IIRin_p4;
IIRin_p5_r1 <= IIRin_p5;
IIRin_p6_r1 <= IIRin_p6;
IIRin_p7_r1 <= IIRin_p7;
end
else
begin
IIRin_p0_r1 <= IIRin_p0_r1;
IIRin_p1_r1 <= IIRin_p1_r1;
IIRin_p2_r1 <= IIRin_p2_r1;
IIRin_p3_r1 <= IIRin_p3_r1;
IIRin_p4_r1 <= IIRin_p4_r1;
IIRin_p5_r1 <= IIRin_p5_r1;
IIRin_p6_r1 <= IIRin_p6_r1;
IIRin_p7_r1 <= IIRin_p7_r1;
end
IIR_Filter_p8 inst_iir_0_p0 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p0 ),
.dinp1 (IIRin_p7_r1 ),
.dinp2 (IIRin_p6_r1 ),
.dinp3 (IIRin_p5_r1 ),
.dinp4 (IIRin_p4_r1 ),
.dinp5 (IIRin_p3_r1 ),
.dinp6 (IIRin_p2_r1 ),
.dinp7 (IIRin_p1_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p0 )
);
IIR_Filter_p8 inst_iir_o_p1 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p1 ),
.dinp1 (IIRin_p0 ),
.dinp2 (IIRin_p7_r1 ),
.dinp3 (IIRin_p6_r1 ),
.dinp4 (IIRin_p5_r1 ),
.dinp5 (IIRin_p4_r1 ),
.dinp6 (IIRin_p3_r1 ),
.dinp7 (IIRin_p2_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p1 )
);
IIR_Filter_p8 inst_iir_0_p2 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p2 ),
.dinp1 (IIRin_p1 ),
.dinp2 (IIRin_p0 ),
.dinp3 (IIRin_p7_r1 ),
.dinp4 (IIRin_p6_r1 ),
.dinp5 (IIRin_p5_r1 ),
.dinp6 (IIRin_p4_r1 ),
.dinp7 (IIRin_p3_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p2 )
);
IIR_Filter_p8 inst_iir_0_p3 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p3 ),
.dinp1 (IIRin_p2 ),
.dinp2 (IIRin_p1 ),
.dinp3 (IIRin_p0 ),
.dinp4 (IIRin_p7_r1 ),
.dinp5 (IIRin_p6_r1 ),
.dinp6 (IIRin_p5_r1 ),
.dinp7 (IIRin_p4_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p3 )
);
IIR_Filter_p8 inst_iir_0_p4 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p4 ),
.dinp1 (IIRin_p3 ),
.dinp2 (IIRin_p2 ),
.dinp3 (IIRin_p1 ),
.dinp4 (IIRin_p0 ),
.dinp5 (IIRin_p7_r1 ),
.dinp6 (IIRin_p6_r1 ),
.dinp7 (IIRin_p5_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p4 )
);
IIR_Filter_p8 inst_iir_0_p5 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p5 ),
.dinp1 (IIRin_p4 ),
.dinp2 (IIRin_p3 ),
.dinp3 (IIRin_p2 ),
.dinp4 (IIRin_p1 ),
.dinp5 (IIRin_p0 ),
.dinp6 (IIRin_p7_r1 ),
.dinp7 (IIRin_p6_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p5 )
);
IIR_Filter_p8 inst_iir_0_p6 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p6 ),
.dinp1 (IIRin_p5 ),
.dinp2 (IIRin_p4 ),
.dinp3 (IIRin_p3 ),
.dinp4 (IIRin_p2 ),
.dinp5 (IIRin_p1 ),
.dinp6 (IIRin_p0 ),
.dinp7 (IIRin_p7_r1 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p6 )
);
IIR_Filter_p8 inst_iir_0_p7 (
.clk (clk ),
.rstn (rstn ),
.en (en ),
.dinp0 (IIRin_p7 ),
.dinp1 (IIRin_p6 ),
.dinp2 (IIRin_p5 ),
.dinp3 (IIRin_p4 ),
.dinp4 (IIRin_p3 ),
.dinp5 (IIRin_p2 ),
.dinp6 (IIRin_p1 ),
.dinp7 (IIRin_p0 ),
.a_re (a_re ),
.a_im (a_im ),
.ab_re (ab_re ),
.ab_im (ab_im ),
.abb_re (abb_re ),
.abb_im (abb_im ),
.ab_pow3_re (ab_pow3_re ),
.ab_pow3_im (ab_pow3_im ),
.ab_pow4_re (ab_pow4_re ),
.ab_pow4_im (ab_pow4_im ),
.ab_pow5_re (ab_pow5_re ),
.ab_pow5_im (ab_pow5_im ),
.ab_pow6_re (ab_pow6_re ),
.ab_pow6_im (ab_pow6_im ),
.ab_pow7_re (ab_pow7_re ),
.ab_pow7_im (ab_pow7_im ),
.b_pow8_re (b_pow8_re ),
.b_pow8_im (b_pow8_im ),
.dout (IIRout_p7 )
);
endmodule

1102
rtl/z_dsp/TailCorr_top.v
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File diff suppressed because it is too large Load Diff

236
rtl/z_dsp/diff_p.v Normal file
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@ -0,0 +1,236 @@
//+FHDR--------------------------------------------------------------------------------------------------------
// Company:
//-----------------------------------------------------------------------------------------------------------------
// File Name : TailCorr_top.v
// Department :
// Author : thfu
// Author's Tel :
//-----------------------------------------------------------------------------------------------------------------
// Relese History
// Version Date Author Description
// 0.3 2024-05-15 thfu
//-----------------------------------------------------------------------------------------------------------------
// Keywords :
//
//-----------------------------------------------------------------------------------------------------------------
// Parameter
//
//-----------------------------------------------------------------------------------------------------------------
// Purpose :
//
//-----------------------------------------------------------------------------------------------------------------
// Target Device:
// Tool versions:
//-----------------------------------------------------------------------------------------------------------------
// Reuse Issues
// Reset Strategy:
// Clock Domains:
// Critical Timing:
// Asynchronous I/F:
// Synthesizable (y/n):
// Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module diff_p
(
input rstn
,input clk
,input en
,input vldi
,input signed [15:0] din0
,input signed [15:0] din1
,input signed [15:0] din2
,input signed [15:0] din3
,output vldo
,output signed [15:0] dout_p0
,output signed [15:0] dout_p1
,output signed [15:0] dout_p2
,output signed [15:0] dout_p3
,output signed [15:0] dout_p4
,output signed [15:0] dout_p5
,output signed [15:0] dout_p6
,output signed [15:0] dout_p7
,output signed [15:0] diff_p0
,output signed [15:0] diff_p1
,output signed [15:0] diff_p2
,output signed [15:0] diff_p3
,output signed [15:0] diff_p4
,output signed [15:0] diff_p5
,output signed [15:0] diff_p6
,output signed [15:0] diff_p7
);
wire signed [15:0] din_p0_r0;
wire signed [15:0] din_p1_r0;
wire signed [15:0] din_p2_r0;
wire signed [15:0] din_p3_r0;
wire signed [15:0] din_p4_r0;
wire signed [15:0] din_p5_r0;
wire signed [15:0] din_p6_r0;
wire signed [15:0] din_p7_r0;
s2p_2 inst1_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din0),
.en (vldi),
.dout0 (din_p0_r0),
.dout1 (din_p4_r0)
,.vldo( vldo)
);
s2p_2 inst2_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din1),
.en (vldi),
.dout0 (din_p1_r0),
.dout1 (din_p5_r0)
,.vldo( )
);
s2p_2 inst3_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din2),
.en (vldi),
.dout0 (din_p2_r0),
.dout1 (din_p6_r0)
,.vldo( )
);
s2p_2 inst4_s2p_2 (
.clk (clk),
.rst_n (rstn),
.din (din3),
.en (vldi),
.dout0 (din_p3_r0),
.dout1 (din_p7_r0)
,.vldo( )
);
reg signed [15:0] din_p0_r1;
reg signed [15:0] din_p1_r1;
reg signed [15:0] din_p2_r1;
reg signed [15:0] din_p3_r1;
reg signed [15:0] din_p4_r1;
reg signed [15:0] din_p5_r1;
reg signed [15:0] din_p6_r1;
reg signed [15:0] din_p7_r1;
always @(posedge clk or negedge rstn)
if (!rstn)
begin
din_p0_r1 <= 'h0;
din_p1_r1 <= 'h0;
din_p2_r1 <= 'h0;
din_p3_r1 <= 'h0;
din_p4_r1 <= 'h0;
din_p5_r1 <= 'h0;
din_p6_r1 <= 'h0;
din_p7_r1 <= 'h0;
end
else if(en)
begin
din_p0_r1 <= din_p0_r0;
din_p1_r1 <= din_p1_r0;
din_p2_r1 <= din_p2_r0;
din_p3_r1 <= din_p3_r0;
din_p4_r1 <= din_p4_r0;
din_p5_r1 <= din_p5_r0;
din_p6_r1 <= din_p6_r0;
din_p7_r1 <= din_p7_r0;
end
else
begin
din_p0_r1 <= din_p0_r1;
din_p1_r1 <= din_p1_r1;
din_p2_r1 <= din_p2_r1;
din_p3_r1 <= din_p3_r1;
din_p4_r1 <= din_p4_r1;
din_p5_r1 <= din_p5_r1;
din_p6_r1 <= din_p6_r1;
din_p7_r1 <= din_p7_r1;
end
assign dout_p0 = din_p0_r1;
assign dout_p1 = din_p1_r1;
assign dout_p2 = din_p2_r1;
assign dout_p3 = din_p3_r1;
assign dout_p4 = din_p4_r1;
assign dout_p5 = din_p5_r1;
assign dout_p6 = din_p6_r1;
assign dout_p7 = din_p7_r1;
wire signed [15:0] diff_p0_r0;
wire signed [15:0] diff_p1_r0;
wire signed [15:0] diff_p2_r0;
wire signed [15:0] diff_p3_r0;
wire signed [15:0] diff_p4_r0;
wire signed [15:0] diff_p5_r0;
wire signed [15:0] diff_p6_r0;
wire signed [15:0] diff_p7_r0;
assign diff_p0_r0 = din_p0_r0 - din_p7_r1;
assign diff_p1_r0 = din_p1_r0 - din_p0_r0;
assign diff_p2_r0 = din_p2_r0 - din_p1_r0;
assign diff_p3_r0 = din_p3_r0 - din_p2_r0;
assign diff_p4_r0 = din_p4_r0 - din_p3_r0;
assign diff_p5_r0 = din_p5_r0 - din_p4_r0;
assign diff_p6_r0 = din_p6_r0 - din_p5_r0;
assign diff_p7_r0 = din_p7_r0 - din_p6_r0;
reg signed [15:0] diff_p0_r1;
reg signed [15:0] diff_p1_r1;
reg signed [15:0] diff_p2_r1;
reg signed [15:0] diff_p3_r1;
reg signed [15:0] diff_p4_r1;
reg signed [15:0] diff_p5_r1;
reg signed [15:0] diff_p6_r1;
reg signed [15:0] diff_p7_r1;
always @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
diff_p0_r1 <= 0;
diff_p1_r1 <= 0;
diff_p2_r1 <= 0;
diff_p3_r1 <= 0;
diff_p4_r1 <= 0;
diff_p5_r1 <= 0;
diff_p6_r1 <= 0;
diff_p7_r1 <= 0;
end
else if(en)begin
diff_p0_r1 <= diff_p0_r0;
diff_p1_r1 <= diff_p1_r0;
diff_p2_r1 <= diff_p2_r0;
diff_p3_r1 <= diff_p3_r0;
diff_p4_r1 <= diff_p4_r0;
diff_p5_r1 <= diff_p5_r0;
diff_p6_r1 <= diff_p6_r0;
diff_p7_r1 <= diff_p7_r0;
end
else begin
diff_p0_r1 <= diff_p0_r1;
diff_p1_r1 <= diff_p1_r1;
diff_p2_r1 <= diff_p2_r1;
diff_p3_r1 <= diff_p3_r1;
diff_p4_r1 <= diff_p4_r1;
diff_p5_r1 <= diff_p5_r1;
diff_p6_r1 <= diff_p6_r1;
diff_p7_r1 <= diff_p7_r1;
end
end
assign diff_p0 = diff_p0_r1;
assign diff_p1 = diff_p1_r1;
assign diff_p2 = diff_p2_r1;
assign diff_p3 = diff_p3_r1;
assign diff_p4 = diff_p4_r1;
assign diff_p5 = diff_p5_r1;
assign diff_p6 = diff_p6_r1;
assign diff_p7 = diff_p7_r1;
endmodule

71
script_m/TailCorr_Test_Verdi.m
View File

@ -1,21 +1,47 @@
%in+iir_out with 8 intp %in+iir_out with 8 intp
clc;clear;close all clc;clear;close all
% addpath("/data/work/thfu/TailCorr/script_m"); % addpath("/data/work/thfu/TailCorr/script_m");
in = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/in.dat"); data_source = 'matlab';
wave_verdi = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/OrgOut.dat"); file_path = "/home/thfu/work/TailCorr/sim/TailCorr_en/";
rng('shuffle');
dout0 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/doutp0.dat"); if strcmp(data_source, 'matlab')
dout1 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/doutp1.dat"); in = floor(cat(1,zeros(4,1),3000*randn(4*2500+4,1)));
% dout2 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/dout2.dat"); for i = 0:3
% dout3 = importdata("/home/thfu/work/TailCorr/sim/z_dsp_en/dout3.dat"); filename = strcat(file_path, "in", num2str(i), "_matlab.dat");
subset = in(i+1:4:end);
fileID = fopen(filename, 'w');
fprintf(fileID, '%d\n', subset);
fclose(fileID);
end
in = [in; zeros(6e4,1)];
system('make all');
elseif strcmp(data_source, 'verdi')
system('make all');
in = [];
for i = 0:3
filename = strcat(file_path, "in", num2str(i), ".dat");
in_data = importdata(filename);
if isempty(in)
N = length(in_data);
in = zeros(4*N, 1);
end
in(i+1:4:end) = in_data;
end
else
end
N = length(dout0);
cs_wave = zeros(2*N,1);
cs_wave(1:2:2*N) = dout0;
cs_wave(2:2:2*N) = dout1;
%cs_wave(3:4:4*N) = dout2;
%cs_wave(4:4:4*N) = dout3;
cs_wave = [];
for i = 0:7
filename = strcat(file_path, "dout", num2str(i), ".dat");
dout_data = importdata(filename);
if isempty(cs_wave)
N = length(dout_data);
cs_wave = zeros(8*N, 1);
end
cs_wave(i+1:8:end) = dout_data;
end
A = [0.025 0.015*1 0.0002*1 0]; A = [0.025 0.015*1 0.0002*1 0];
tau = -[1/250 1/650 1/1600 0]; tau = -[1/250 1/650 1/1600 0];
@ -27,7 +53,9 @@ for i = 1:coef_len
a(i) = A(i)/1/(1-A(i))*exp(1e9/fs/(1-A(i))/2*tau(i)); a(i) = A(i)/1/(1-A(i))*exp(1e9/fs/(1-A(i))/2*tau(i));
h_ideal(:,i) = filter(a(i),[1 -b(i)],diff(in)); h_ideal(:,i) = filter(a(i),[1 -b(i)],diff(in));
end end
len_in = length(in);
len_h_ideal = length(h_ideal);
in = [in; zeros(1, len_h_ideal - len_in + 1)'];
wave_float = in(2:end)+ sum(h_ideal,2); wave_float = in(2:end)+ sum(h_ideal,2);
wave_float_len = length(wave_float); wave_float_len = length(wave_float);
@ -50,7 +78,13 @@ signalAnalyzer(wave_float,wave_verdi,'SampleRate',1);
a_fix = round(a*2^31); a_fix = round(a*2^31);
ab_fix = round(a.*b*2^31); ab_fix = round(a.*b*2^31);
b2_fix = round(b.^2*2^31); ab2_fix = round(a.*b.^2*2^31);
ab3_fix = round(a.*b.^3*2^31);
ab4_fix = round(a.*b.^4*2^31);
ab5_fix = round(a.*b.^5*2^31);
ab6_fix = round(a.*b.^6*2^31);
ab7_fix = round(a.*b.^7*2^31);
b8_fix = round(b.^8*2^31);
a_hex = dec2hex(a_fix,8); a_hex = dec2hex(a_fix,8);
@ -58,6 +92,11 @@ a_bin = dec2bin(a_fix,32);
fprintf('a_fix is %d\n',a_fix); fprintf('a_fix is %d\n',a_fix);
fprintf('ab_fix is %d\n',ab_fix); fprintf('ab_fix is %d\n',ab_fix);
fprintf('b2_fix is %d\n',b2_fix); fprintf('ab2_fix is %d\n', ab2_fix);
fprintf('ab3_fix is %d\n', ab3_fix);
fprintf('ab4_fix is %d\n', ab4_fix);
fprintf('ab5_fix is %d\n', ab5_fix);
fprintf('ab6_fix is %d\n', ab6_fix);
fprintf('ab7_fix is %d\n', ab7_fix);
fprintf('b8_fix is %d\n',b8_fix);

2
sim/s2p_2/files.f
View File

@ -1,2 +1,2 @@
../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/s2p_2.v
../../tb/tb_s2p_2.v tb_s2p_2.v

46
tb/tb_s2p_2.v → sim/s2p_2/tb_s2p_2.v
View File

@ -9,7 +9,7 @@ begin
$fsdbDumpvars(0, TB); $fsdbDumpvars(0, TB);
end end
// 信号声明
reg clk; reg clk;
reg rst_n; reg rst_n;
reg [15:0] din; reg [15:0] din;
@ -18,7 +18,7 @@ end
wire [15:0] dout0; wire [15:0] dout0;
wire [15:0] dout1; wire [15:0] dout1;
// 实例化被测模块
s2p_2 uut ( s2p_2 uut (
.clk (clk), .clk (clk),
.rst_n (rst_n), .rst_n (rst_n),
@ -59,26 +59,26 @@ wire signed [15:0] diff12;
wire signed [15:0] diff23; wire signed [15:0] diff23;
assign diff12 = dout0 - dout1_r2; assign diff12 = dout0 - dout1_r2;
assign diff23 = dout1 - dout0; assign diff23 = dout1 - dout0;
// 复位和使能控制
initial begin initial begin
rst_n = 0; rst_n = 0;
enable = 0; enable = 0;
clk = 1'b0; clk = 1'b0;
din = 16'h0000; din = 16'h0000;
// 复位保持20 ns
#20; #20;
rst_n = 1; rst_n = 1;
// 等待复位释放后一个时钟周期
#10; #10;
end end
// 时钟生成
always #5 clk = ~clk; // 100MHz 时钟
// 计数器，控制生成数据的周期 always #5 clk = ~clk;
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin if (rst_n == 1'b0) begin
cnt <= 22'd0; cnt <= 22'd0;
@ -87,42 +87,42 @@ assign diff23 = dout1 - dout0;
end end
end end
// 随机生成使能信号和输入数据
reg [15:0] enable_cnt; reg [15:0] enable_cnt;
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin if (rst_n == 1'b0) begin
enable <= 0; enable <= 0;
din <= 16'd0; din <= 16'd0;
enable_cnt <= 0; // 新增计数器，用于控制 enable 的持续时间 enable_cnt <= 0;
end else begin end else begin
// 随机控制使能信号的持续时间
if (cnt < 1000) begin // 控制数据生成的时长，模拟随机数据 if (cnt < 1000) begin
if (enable_cnt == 0) begin if (enable_cnt == 0) begin
if ($urandom % 2 == 0) begin // 随机决定是否启动 enable if ($urandom % 2 == 0) begin
enable <= 1; enable <= 1;
enable_cnt <= $urandom % 10 + 5; // 随机决定使能信号持续时间，范围 5~14 个时钟周期 enable_cnt <= $urandom % 10 + 5;
din <= $urandom; // 随机生成 16 位数据 din <= $urandom;
end else begin end else begin
enable <= 0; enable <= 0;
din <= 16'd0; // 当不使能时，确保数据为 0 din <= 16'd0;
end end
end else begin end else begin
// 如果使能信号已启动，继续保持 enable 高电平，直到计数器到达 0
enable <= 1; enable <= 1;
enable_cnt <= enable_cnt - 1; // 每个时钟周期减少使能计数器 enable_cnt <= enable_cnt - 1;
din <= $urandom; // 随机生成数据 din <= $urandom;
end end
end else begin end else begin
enable <= 0; // 超过指定时长后关闭 enable enable <= 0;
din <= 16'd0; // 数据归零 din <= 16'd0;
end end
end end
end end
// 终止仿真，随机次数的触发条件
initial begin initial begin
wait(cnt[11] == 1); // 控制仿真进行一段时间后结束 wait(cnt[11] == 1);
$finish; $finish;
end end

17
sim/z_dsp_en/Makefile
View File

@ -1,17 +0,0 @@
VCS = vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps +nospecify -l compile.log +fsdb+delta
SIMV = ./simv -l sim.log +fsdb+delta
all:comp run
comp:
${VCS} -f files.f
run:
${SIMV}
dbg:
verdi -sv -f files.f -top TB -nologo -ssf TB.fsdb &
file:
find ../ -name "*.*v" > files.f
clean:
rm -rf DVE* simv* *log ucli.key verdiLog urgReport csrc novas.* *.fsdb *.dat *.daidir *.vdb *~ vfastLog

25
sim/z_dsp_en/files.f
View File

@ -1,25 +0,0 @@
../../rtl/z_dsp_en_Test.v
../../rtl/z_dsp/diff.v
../../rtl/z_dsp/mult_C.v
../../rtl/z_dsp/FixRound.v
../../rtl/z_dsp/TailCorr_top.v
../../rtl/z_dsp/z_dsp.v
../../rtl/z_dsp/MeanIntp_8.v
../../rtl/z_dsp/IIR_Filter_s.v
../../rtl/z_dsp/IIR_Filter_p2.v
../../rtl/model/DW_mult_pipe.v
../../rtl/model/DW02_mult.v
../../rtl/nco/coef_c.v
../../rtl/nco/pipe_acc_48bit.v
../../rtl/nco/pipe_add_48bit.v
../../rtl/nco/p_nco.v
../../rtl/nco/coef_s.v
../../rtl/nco/nco.v
../../rtl/nco/sin_op.v
../../rtl/nco/ph2amp.v
../../rtl/nco/cos_op.v
../../rtl/z_dsp/s2p_2.v
../../tb/clk_gen.v
../../tb/tb_z_dsp_en_Test.v