From b0e8eaf996987b85197ef18e427c5ef308511758 Mon Sep 17 00:00:00 2001 From: thfu <2779155576@qq.com> Date: Fri, 18 Apr 2025 15:16:50 +0800 Subject: [PATCH] =?UTF-8?q?16=E8=B7=AF=E8=B6=85=E5=89=8D=E8=AE=A1=E7=AE=97?= =?UTF-8?q?=E5=88=B01G?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.16路62.5M输入，1G 2.使用实数乘法器 3.四指数修正 --- rtl/z_dsp/CoefGen.sv | 675 +++++++++++++---- rtl/z_dsp/IIR_Filter_p1.v | 56 +- rtl/z_dsp/IIR_Filter_p16.v | 237 ++++++ rtl/z_dsp/IIR_Filter_p8.v | 143 ---- rtl/z_dsp/IIR_top.v | 476 ++++++++++-- rtl/z_dsp/TailCorr_top.v | 1235 ++++++++++++++++++++++---------- rtl/z_dsp/diff_p.v | 180 +++-- rtl/z_dsp/mult_C.v | 86 +++ rtl/z_dsp/mult_real.v | 39 - rtl/z_dsp/mult_x.v | 66 ++ rtl/z_dsp/rate_adapter.v | 57 -- rtl/z_dsp/s2p_2.v | 84 --- rtl/z_dsp/z_dsp.v | 624 +++++++++++----- script_m/TailCorr_Test_Verdi.m | 30 +- sim/z_dsp/files.f | 7 +- sim/z_dsp/tb_z_dsp.v | 241 ++++--- 16 files changed, 2891 insertions(+), 1345 deletions(-) create mode 100644 rtl/z_dsp/IIR_Filter_p16.v delete mode 100644 rtl/z_dsp/IIR_Filter_p8.v create mode 100644 rtl/z_dsp/mult_C.v delete mode 100644 rtl/z_dsp/mult_real.v create mode 100644 rtl/z_dsp/mult_x.v delete mode 100644 rtl/z_dsp/rate_adapter.v delete mode 100644 rtl/z_dsp/s2p_2.v diff --git a/rtl/z_dsp/CoefGen.sv b/rtl/z_dsp/CoefGen.sv index a31dcf4..1e2c5d9 100644 --- a/rtl/z_dsp/CoefGen.sv +++ b/rtl/z_dsp/CoefGen.sv @@ -7,19 +7,23 @@ module CoefGen #( ( input rstn ,input clk -,input [5:0] vldi -,input signed [31:0] a0_re -,input signed [31:0] b0_re -,input signed [31:0] a1_re -,input signed [31:0] b1_re -,input signed [31:0] a2_re -,input signed [31:0] b2_re -,input signed [31:0] a3_re -,input signed [31:0] b3_re -,input signed [31:0] a4_re -,input signed [31:0] b4_re -,input signed [31:0] a5_re -,input signed [31:0] b5_re +,input [3:0] vldi +,input signed [31:0] a0_re +,input signed [31:0] b0_re +,input signed [31:0] a1_re +,input signed [31:0] b1_re +,input signed [31:0] a2_re +,input signed [31:0] b2_re +,input signed [31:0] a3_re +,input signed [31:0] b3_re +,input signed [31:0] a0_im +,input signed [31:0] b0_im +,input signed [31:0] a1_im +,input signed [31:0] b1_im +,input signed [31:0] a2_im +,input signed [31:0] b2_im +,input signed [31:0] a3_im +,input signed [31:0] b3_im ,output reg signed [31:0] a_re0 ,output reg signed [31:0] b_re0 ,output reg signed [31:0] ab_re0 @@ -29,7 +33,15 @@ module CoefGen #( ,output reg signed [31:0] ab_pow5_re0 ,output reg signed [31:0] ab_pow6_re0 ,output reg signed [31:0] ab_pow7_re0 -,output reg signed [31:0] b_pow8_re0 +,output reg signed [31:0] ab_pow8_re0 +,output reg signed [31:0] ab_pow9_re0 +,output reg signed [31:0] ab_powa_re0 +,output reg signed [31:0] ab_powb_re0 +,output reg signed [31:0] ab_powc_re0 +,output reg signed [31:0] ab_powd_re0 +,output reg signed [31:0] ab_powe_re0 +,output reg signed [31:0] ab_powf_re0 +,output reg signed [31:0] b_pow16_re0 ,output reg signed [31:0] a_re1 ,output reg signed [31:0] b_re1 ,output reg signed [31:0] ab_re1 @@ -39,7 +51,15 @@ module CoefGen #( ,output reg signed [31:0] ab_pow5_re1 ,output reg signed [31:0] ab_pow6_re1 ,output reg signed [31:0] ab_pow7_re1 -,output reg signed [31:0] b_pow8_re1 +,output reg signed [31:0] ab_pow8_re1 +,output reg signed [31:0] ab_pow9_re1 +,output reg signed [31:0] ab_powa_re1 +,output reg signed [31:0] ab_powb_re1 +,output reg signed [31:0] ab_powc_re1 +,output reg signed [31:0] ab_powd_re1 +,output reg signed [31:0] ab_powe_re1 +,output reg signed [31:0] ab_powf_re1 +,output reg signed [31:0] b_pow16_re1 ,output reg signed [31:0] a_re2 ,output reg signed [31:0] b_re2 ,output reg signed [31:0] ab_re2 @@ -49,7 +69,15 @@ module CoefGen #( ,output reg signed [31:0] ab_pow5_re2 ,output reg signed [31:0] ab_pow6_re2 ,output reg signed [31:0] ab_pow7_re2 -,output reg signed [31:0] b_pow8_re2 +,output reg signed [31:0] ab_pow8_re2 +,output reg signed [31:0] ab_pow9_re2 +,output reg signed [31:0] ab_powa_re2 +,output reg signed [31:0] ab_powb_re2 +,output reg signed [31:0] ab_powc_re2 +,output reg signed [31:0] ab_powd_re2 +,output reg signed [31:0] ab_powe_re2 +,output reg signed [31:0] ab_powf_re2 +,output reg signed [31:0] b_pow16_re2 ,output reg signed [31:0] a_re3 ,output reg signed [31:0] b_re3 ,output reg signed [31:0] ab_re3 @@ -59,27 +87,88 @@ module CoefGen #( ,output reg signed [31:0] ab_pow5_re3 ,output reg signed [31:0] ab_pow6_re3 ,output reg signed [31:0] ab_pow7_re3 -,output reg signed [31:0] b_pow8_re3 -,output reg signed [31:0] a_re4 -,output reg signed [31:0] b_re4 -,output reg signed [31:0] ab_re4 -,output reg signed [31:0] abb_re4 -,output reg signed [31:0] ab_pow3_re4 -,output reg signed [31:0] ab_pow4_re4 -,output reg signed [31:0] ab_pow5_re4 -,output reg signed [31:0] ab_pow6_re4 -,output reg signed [31:0] ab_pow7_re4 -,output reg signed [31:0] b_pow8_re4 -,output reg signed [31:0] a_re5 -,output reg signed [31:0] b_re5 -,output reg signed [31:0] ab_re5 -,output reg signed [31:0] abb_re5 -,output reg signed [31:0] ab_pow3_re5 -,output reg signed [31:0] ab_pow4_re5 -,output reg signed [31:0] ab_pow5_re5 -,output reg signed [31:0] ab_pow6_re5 -,output reg signed [31:0] ab_pow7_re5 -,output reg signed [31:0] b_pow8_re5 +,output reg signed [31:0] ab_pow8_re3 +,output reg signed [31:0] ab_pow9_re3 +,output reg signed [31:0] ab_powa_re3 +,output reg signed [31:0] ab_powb_re3 +,output reg signed [31:0] ab_powc_re3 +,output reg signed [31:0] ab_powd_re3 +,output reg signed [31:0] ab_powe_re3 +,output reg signed [31:0] ab_powf_re3 +,output reg signed [31:0] b_pow16_re3 +,output reg signed [31:0] a_im0 +,output reg signed [31:0] b_im0 +,output reg signed [31:0] ab_im0 +,output reg signed [31:0] abb_im0 +,output reg signed [31:0] ab_pow3_im0 +,output reg signed [31:0] ab_pow4_im0 +,output reg signed [31:0] ab_pow5_im0 +,output reg signed [31:0] ab_pow6_im0 +,output reg signed [31:0] ab_pow7_im0 +,output reg signed [31:0] ab_pow8_im0 +,output reg signed [31:0] ab_pow9_im0 +,output reg signed [31:0] ab_powa_im0 +,output reg signed [31:0] ab_powb_im0 +,output reg signed [31:0] ab_powc_im0 +,output reg signed [31:0] ab_powd_im0 +,output reg signed [31:0] ab_powe_im0 +,output reg signed [31:0] ab_powf_im0 +,output reg signed [31:0] b_pow16_im0 +,output reg signed [31:0] a_im1 +,output reg signed [31:0] b_im1 +,output reg signed [31:0] ab_im1 +,output reg signed [31:0] abb_im1 +,output reg signed [31:0] ab_pow3_im1 +,output reg signed [31:0] ab_pow4_im1 +,output reg signed [31:0] ab_pow5_im1 +,output reg signed [31:0] ab_pow6_im1 +,output reg signed [31:0] ab_pow7_im1 +,output reg signed [31:0] ab_pow8_im1 +,output reg signed [31:0] ab_pow9_im1 +,output reg signed [31:0] ab_powa_im1 +,output reg signed [31:0] ab_powb_im1 +,output reg signed [31:0] ab_powc_im1 +,output reg signed [31:0] ab_powd_im1 +,output reg signed [31:0] ab_powe_im1 +,output reg signed [31:0] ab_powf_im1 +,output reg signed [31:0] b_pow16_im1 +,output reg signed [31:0] a_im2 +,output reg signed [31:0] b_im2 +,output reg signed [31:0] ab_im2 +,output reg signed [31:0] abb_im2 +,output reg signed [31:0] ab_pow3_im2 +,output reg signed [31:0] ab_pow4_im2 +,output reg signed [31:0] ab_pow5_im2 +,output reg signed [31:0] ab_pow6_im2 +,output reg signed [31:0] ab_pow7_im2 +,output reg signed [31:0] ab_pow8_im2 +,output reg signed [31:0] ab_pow9_im2 +,output reg signed [31:0] ab_powa_im2 +,output reg signed [31:0] ab_powb_im2 +,output reg signed [31:0] ab_powc_im2 +,output reg signed [31:0] ab_powd_im2 +,output reg signed [31:0] ab_powe_im2 +,output reg signed [31:0] ab_powf_im2 +,output reg signed [31:0] b_pow16_im2 +,output reg signed [31:0] a_im3 +,output reg signed [31:0] b_im3 +,output reg signed [31:0] ab_im3 +,output reg signed [31:0] abb_im3 +,output reg signed [31:0] ab_pow3_im3 +,output reg signed [31:0] ab_pow4_im3 +,output reg signed [31:0] ab_pow5_im3 +,output reg signed [31:0] ab_pow6_im3 +,output reg signed [31:0] ab_pow7_im3 +,output reg signed [31:0] ab_pow8_im3 +,output reg signed [31:0] ab_pow9_im3 +,output reg signed [31:0] ab_powa_im3 +,output reg signed [31:0] ab_powb_im3 +,output reg signed [31:0] ab_powc_im3 +,output reg signed [31:0] ab_powd_im3 +,output reg signed [31:0] ab_powe_im3 +,output reg signed [31:0] ab_powf_im3 +,output reg signed [31:0] b_pow16_im3 + ); @@ -89,6 +178,8 @@ sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn); reg signed [data_in_width-1:0] a_re_r1; reg signed [data_in_width-1:0] b_re_r1; +reg signed [data_in_width-1:0] a_im_r1; +reg signed [data_in_width-1:0] b_im_r1; always @(posedge clk or negedge rstn) begin if(rstn == 1'b0) begin @@ -99,27 +190,27 @@ always @(posedge clk or negedge rstn) begin case(1'b1) vldi[0]: begin a_re_r1 <= a0_re; - b_re_r1 <= b0_re; + b_re_r1 <= b0_re; + a_im_r1 <= a0_im; + b_im_r1 <= b0_im; end vldi[1]: begin a_re_r1 <= a1_re; b_re_r1 <= b1_re; + a_im_r1 <= a1_im; + b_im_r1 <= b1_im; end vldi[2]: begin a_re_r1 <= a2_re; b_re_r1 <= b2_re; + a_im_r1 <= a2_im; + b_im_r1 <= b2_im; end vldi[3]: begin a_re_r1 <= a3_re; b_re_r1 <= b3_re; - end - vldi[4]: begin - a_re_r1 <= a4_re; - b_re_r1 <= b4_re; - end - vldi[5]: begin - a_re_r1 <= a5_re; - b_re_r1 <= b5_re; + a_im_r1 <= a3_im; + b_im_r1 <= b3_im; end // default: begin // a_re_r1 <= a_re[0]; @@ -133,7 +224,7 @@ reg en; reg en_r1; sirv_gnrl_dffr #(1) dff_en_1(en, en_r1 ,clk,rstn); -reg [3:0] cnt0; +reg [4:0] cnt0; wire add_cnt0; wire end_cnt0; always @(posedge clk or negedge rstn)begin @@ -149,7 +240,7 @@ always @(posedge clk or negedge rstn)begin end assign add_cnt0 = en; -assign end_cnt0 = add_cnt0 && cnt0== 8-1; +assign end_cnt0 = add_cnt0 && cnt0== 16-1; wire en_l; wire en_h; @@ -170,57 +261,98 @@ assign en_l = end_cnt0; reg signed [data_in_width-1:0] bin_re; wire signed [data_in_width-1:0] bout_re; +reg signed [data_in_width-1:0] bin_im; +wire signed [data_in_width-1:0] bout_im; always @(*)begin if(en_r1) begin bin_re <= bout_re; + bin_im <= bout_im; end else begin bin_re <= 32'd2147483647; + bin_im <= 0; end end -mult_real +mult_C #( .A_width(data_in_width) +,.B_width(data_in_width) ,.C_width(coef_width) +,.D_width(coef_width) ,.o_width(data_in_width) ) inst_c1 ( .clk (clk ), .rstn (rstn ), .en (en ), - .din (bin_re ), - .coef (b_re_r1 ), - .dout (bout_re ) + .a (bin_re ), + .b (bin_im ), + .c (b_re_r1 ), + .d (b_im_r1 ), + .Re (bout_re ), + .Im (bout_im ) ); wire signed [data_in_width-1:0] abo_re; -mult_real +wire signed [data_in_width-1:0] abo_im; +mult_C #( .A_width(data_in_width) +,.B_width(data_in_width) ,.C_width(coef_width) +,.D_width(coef_width) ,.o_width(data_in_width) ) inst_c2 ( .clk (clk ), .rstn (rstn ), .en (en ), - .din (bin_re ), - .coef (a_re_r1 ), - .dout (abo_re ) + .a (bin_re ), + .b (bin_im ), + .c (a_re_r1 ), + .d (a_im_r1 ), + .Re (abo_re ), + .Im (abo_im ) ); -reg signed [coef_width-1 :0] ao_re_r1 ; -reg signed [coef_width-1 :0] ab_re_r1 ; -reg signed [coef_width-1 :0] abb_re_r1 ; -reg signed [coef_width-1 :0] ab_pow3_re_r1 ; -reg signed [coef_width-1 :0] ab_pow4_re_r1 ; -reg signed [coef_width-1 :0] ab_pow5_re_r1 ; -reg signed [coef_width-1 :0] ab_pow6_re_r1 ; -reg signed [coef_width-1 :0] ab_pow7_re_r1 ; -reg signed [coef_width-1 :0] bo_re_r1 ; -reg signed [coef_width-1 :0] b_pow8_re_r1 ; +reg signed [coef_width-1 :0] ao_re_r1 ; +reg signed [coef_width-1 :0] ab_re_r1 ; +reg signed [coef_width-1 :0] abb_re_r1 ; +reg signed [coef_width-1 :0] ab_pow3_re_r1; +reg signed [coef_width-1 :0] ab_pow4_re_r1; +reg signed [coef_width-1 :0] ab_pow5_re_r1; +reg signed [coef_width-1 :0] ab_pow6_re_r1; +reg signed [coef_width-1 :0] ab_pow7_re_r1; +reg signed [coef_width-1 :0] ab_pow8_re_r1; +reg signed [coef_width-1 :0] ab_pow9_re_r1; +reg signed [coef_width-1 :0] ab_powa_re_r1; +reg signed [coef_width-1 :0] ab_powb_re_r1; +reg signed [coef_width-1 :0] ab_powc_re_r1; +reg signed [coef_width-1 :0] ab_powd_re_r1; +reg signed [coef_width-1 :0] ab_powe_re_r1; +reg signed [coef_width-1 :0] ab_powf_re_r1; +reg signed [coef_width-1 :0] bo_re_r1 ; +reg signed [coef_width-1 :0] b_pow16_re_r1 ; +reg signed [coef_width-1 :0] ao_im_r1 ; +reg signed [coef_width-1 :0] ab_im_r1 ; +reg signed [coef_width-1 :0] abb_im_r1 ; +reg signed [coef_width-1 :0] ab_pow3_im_r1; +reg signed [coef_width-1 :0] ab_pow4_im_r1; +reg signed [coef_width-1 :0] ab_pow5_im_r1; +reg signed [coef_width-1 :0] ab_pow6_im_r1; +reg signed [coef_width-1 :0] ab_pow7_im_r1; +reg signed [coef_width-1 :0] ab_pow8_im_r1; +reg signed [coef_width-1 :0] ab_pow9_im_r1; +reg signed [coef_width-1 :0] ab_powa_im_r1; +reg signed [coef_width-1 :0] ab_powb_im_r1; +reg signed [coef_width-1 :0] ab_powc_im_r1; +reg signed [coef_width-1 :0] ab_powd_im_r1; +reg signed [coef_width-1 :0] ab_powe_im_r1; +reg signed [coef_width-1 :0] ab_powf_im_r1; +reg signed [coef_width-1 :0] bo_im_r1 ; +reg signed [coef_width-1 :0] b_pow16_im_r1 ; always @(posedge clk or negedge rstn)begin if(!rstn)begin @@ -232,60 +364,145 @@ always @(posedge clk or negedge rstn)begin ab_pow5_re_r1 <= 0; ab_pow6_re_r1 <= 0; ab_pow7_re_r1 <= 0; + ab_pow8_re_r1 <= 0; + ab_pow9_re_r1 <= 0; + ab_powa_re_r1 <= 0; + ab_powb_re_r1 <= 0; + ab_powc_re_r1 <= 0; + ab_powd_re_r1 <= 0; + ab_powe_re_r1 <= 0; + ab_powf_re_r1 <= 0; bo_re_r1 <= 0; - b_pow8_re_r1 <= 0; + b_pow16_re_r1 <= 0; + ao_im_r1 <= 0; + ab_im_r1 <= 0; + abb_im_r1 <= 0; + ab_pow3_im_r1 <= 0; + ab_pow4_im_r1 <= 0; + ab_pow5_im_r1 <= 0; + ab_pow6_im_r1 <= 0; + ab_pow7_im_r1 <= 0; + ab_pow8_im_r1 <= 0; + ab_pow9_im_r1 <= 0; + ab_powa_im_r1 <= 0; + ab_powb_im_r1 <= 0; + ab_powc_im_r1 <= 0; + ab_powd_im_r1 <= 0; + ab_powe_im_r1 <= 0; + ab_powf_im_r1 <= 0; + bo_im_r1 <= 0; + b_pow16_im_r1 <= 0; end else if(add_cnt0 && cnt0 == 1 && en_r1)begin ao_re_r1 <= abo_re; bo_re_r1 <= bin_re; + ao_im_r1 <= abo_im; + bo_im_r1 <= bin_im; end else if(add_cnt0 && cnt0 == 2 && en_r1)begin ab_re_r1 <= abo_re; + ab_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 3 && en_r1)begin abb_re_r1 <= abo_re; + abb_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 4 && en_r1)begin ab_pow3_re_r1 <= abo_re; + ab_pow3_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 5 && en_r1)begin ab_pow4_re_r1 <= abo_re; + ab_pow4_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 6 && en_r1)begin ab_pow5_re_r1 <= abo_re; + ab_pow5_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 7 && en_r1)begin ab_pow6_re_r1 <= abo_re; + ab_pow6_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 8 && en_r1)begin + ab_pow7_re_r1 <= abo_re; + ab_pow7_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 9 && en_r1)begin + ab_pow8_re_r1 <= abo_re; + ab_pow8_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 10 && en_r1)begin + ab_pow9_re_r1 <= abo_re; + ab_pow9_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 11 && en_r1)begin + ab_powa_re_r1 <= abo_re; + ab_powa_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 12 && en_r1)begin + ab_powb_re_r1 <= abo_re; + ab_powb_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 13 && en_r1)begin + ab_powc_re_r1 <= abo_re; + ab_powc_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 14 && en_r1)begin + ab_powd_re_r1 <= abo_re; + ab_powd_im_r1 <= abo_im; + end + else if(add_cnt0 && cnt0 == 15 && en_r1)begin + ab_powe_re_r1 <= abo_re; + ab_powe_im_r1 <= abo_im; end else if(cnt0 == 0 && en_r1)begin - ab_pow7_re_r1 <= abo_re; - b_pow8_re_r1 <= bin_re; + ab_powf_re_r1 <= abo_re; + b_pow16_re_r1 <= bin_re; + ab_powf_im_r1 <= abo_im; + b_pow16_im_r1 <= bin_im; end + // else begin // end end -reg [5:0] vldi_r1; -reg [5:0] vldi_r2; -reg [5:0] vldi_r3; -reg [5:0] vldi_r4; -reg [5:0] vldi_r5; -reg [5:0] vldi_r6; -reg [5:0] vldi_r7; -reg [5:0] vldi_r8; -reg [5:0] vldi_r9; -reg [5:0] vldi_r10; +reg [3:0] vldi_r1; +reg [3:0] vldi_r2; +reg [3:0] vldi_r3; +reg [3:0] vldi_r4; +reg [3:0] vldi_r5; +reg [3:0] vldi_r6; +reg [3:0] vldi_r7; +reg [3:0] vldi_r8; +reg [3:0] vldi_r9; +reg [3:0] vldi_r10; +reg [3:0] vldi_r11; +reg [3:0] vldi_r12; +reg [3:0] vldi_r13; +reg [3:0] vldi_r14; +reg [3:0] vldi_r15; +reg [3:0] vldi_r16; +reg [3:0] vldi_r17; +reg [3:0] vldi_r18; //syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10); -sirv_gnrl_dffr #(6) dff_vldi_1(vldi,vldi_r1,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn); -sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_1(vldi,vldi_r1,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_11(vldi_r10, vldi_r11,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_12(vldi_r11, vldi_r12,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_13(vldi_r12, vldi_r13,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_14(vldi_r13, vldi_r14,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_15(vldi_r14, vldi_r15,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_16(vldi_r15, vldi_r16,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_17(vldi_r16, vldi_r17,clk,rstn); +sirv_gnrl_dffr #(4) dff_vldi_18(vldi_r17, vldi_r18,clk,rstn); always @(posedge clk or negedge rstn) begin if(!rstn) begin a_re0 <= 0; @@ -297,7 +514,15 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re0 <= 0; ab_pow6_re0 <= 0; ab_pow7_re0 <= 0; - b_pow8_re0 <= 0; + ab_pow8_re0 <= 0; + ab_pow9_re0 <= 0; + ab_powa_re0 <= 0; + ab_powb_re0 <= 0; + ab_powc_re0 <= 0; + ab_powd_re0 <= 0; + ab_powe_re0 <= 0; + ab_powf_re0 <= 0; + b_pow16_re0 <= 0; a_re1 <= 0; b_re1 <= 0; ab_re1 <= 0; @@ -307,7 +532,15 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re1 <= 0; ab_pow6_re1 <= 0; ab_pow7_re1 <= 0; - b_pow8_re1 <= 0; + ab_pow8_re1 <= 0; + ab_pow9_re1 <= 0; + ab_powa_re1 <= 0; + ab_powb_re1 <= 0; + ab_powc_re1 <= 0; + ab_powd_re1 <= 0; + ab_powe_re1 <= 0; + ab_powf_re1 <= 0; + b_pow16_re1 <= 0; a_re2 <= 0; b_re2 <= 0; ab_re2 <= 0; @@ -317,7 +550,15 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re2 <= 0; ab_pow6_re2 <= 0; ab_pow7_re2 <= 0; - b_pow8_re2 <= 0; + ab_pow8_re2 <= 0; + ab_pow9_re2 <= 0; + ab_powa_re2 <= 0; + ab_powb_re2 <= 0; + ab_powc_re2 <= 0; + ab_powd_re2 <= 0; + ab_powe_re2 <= 0; + ab_powf_re2 <= 0; + b_pow16_re2 <= 0; a_re3 <= 0; b_re3 <= 0; ab_re3 <= 0; @@ -327,31 +568,91 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re3 <= 0; ab_pow6_re3 <= 0; ab_pow7_re3 <= 0; - b_pow8_re3 <= 0; - a_re4 <= 0; - b_re4 <= 0; - ab_re4 <= 0; - abb_re4 <= 0; - ab_pow3_re4 <= 0; - ab_pow4_re4 <= 0; - ab_pow5_re4 <= 0; - ab_pow6_re4 <= 0; - ab_pow7_re4 <= 0; - b_pow8_re4 <= 0; - a_re5 <= 0; - b_re5 <= 0; - ab_re5 <= 0; - abb_re5 <= 0; - ab_pow3_re5 <= 0; - ab_pow4_re5 <= 0; - ab_pow5_re5 <= 0; - ab_pow6_re5 <= 0; - ab_pow7_re5 <= 0; - b_pow8_re5 <= 0; - end - else if(|vldi_r10) begin + ab_pow8_re3 <= 0; + ab_pow9_re3 <= 0; + ab_powa_re3 <= 0; + ab_powb_re3 <= 0; + ab_powc_re3 <= 0; + ab_powd_re3 <= 0; + ab_powe_re3 <= 0; + ab_powf_re3 <= 0; + b_pow16_re3 <= 0; + a_im0 <= 0; + b_im0 <= 0; + ab_im0 <= 0; + abb_im0 <= 0; + ab_pow3_im0 <= 0; + ab_pow4_im0 <= 0; + ab_pow5_im0 <= 0; + ab_pow6_im0 <= 0; + ab_pow7_im0 <= 0; + ab_pow8_im0 <= 0; + ab_pow9_im0 <= 0; + ab_powa_im0 <= 0; + ab_powb_im0 <= 0; + ab_powc_im0 <= 0; + ab_powd_im0 <= 0; + ab_powe_im0 <= 0; + ab_powf_im0 <= 0; + b_pow16_im0 <= 0; + a_im1 <= 0; + b_im1 <= 0; + ab_im1 <= 0; + abb_im1 <= 0; + ab_pow3_im1 <= 0; + ab_pow4_im1 <= 0; + ab_pow5_im1 <= 0; + ab_pow6_im1 <= 0; + ab_pow7_im1 <= 0; + ab_pow8_im1 <= 0; + ab_pow9_im1 <= 0; + ab_powa_im1 <= 0; + ab_powb_im1 <= 0; + ab_powc_im1 <= 0; + ab_powd_im1 <= 0; + ab_powe_im1 <= 0; + ab_powf_im1 <= 0; + b_pow16_im1 <= 0; + a_im2 <= 0; + b_im2 <= 0; + ab_im2 <= 0; + abb_im2 <= 0; + ab_pow3_im2 <= 0; + ab_pow4_im2 <= 0; + ab_pow5_im2 <= 0; + ab_pow6_im2 <= 0; + ab_pow7_im2 <= 0; + ab_pow8_im2 <= 0; + ab_pow9_im2 <= 0; + ab_powa_im2 <= 0; + ab_powb_im2 <= 0; + ab_powc_im2 <= 0; + ab_powd_im2 <= 0; + ab_powe_im2 <= 0; + ab_powf_im2 <= 0; + b_pow16_im2 <= 0; + a_im3 <= 0; + b_im3 <= 0; + ab_im3 <= 0; + abb_im3 <= 0; + ab_pow3_im3 <= 0; + ab_pow4_im3 <= 0; + ab_pow5_im3 <= 0; + ab_pow6_im3 <= 0; + ab_pow7_im3 <= 0; + ab_pow8_im3 <= 0; + ab_pow9_im3 <= 0; + ab_powa_im3 <= 0; + ab_powb_im3 <= 0; + ab_powc_im3 <= 0; + ab_powd_im3 <= 0; + ab_powe_im3 <= 0; + ab_powf_im3 <= 0; + b_pow16_im3 <= 0; + end + else if(|vldi_r18) begin case(1'b1) - vldi_r10[0]: begin + vldi_r18[0]: begin a_re0 <= ao_re_r1 ; b_re0 <= bo_re_r1 ; ab_re0 <= ab_re_r1 ; @@ -361,9 +662,35 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re0 <= ab_pow5_re_r1; ab_pow6_re0 <= ab_pow6_re_r1; ab_pow7_re0 <= ab_pow7_re_r1; - b_pow8_re0 <= b_pow8_re_r1 ; + ab_pow8_re0 <= ab_pow8_re_r1; + ab_pow9_re0 <= ab_pow9_re_r1; + ab_powa_re0 <= ab_powa_re_r1; + ab_powb_re0 <= ab_powb_re_r1; + ab_powc_re0 <= ab_powc_re_r1; + ab_powd_re0 <= ab_powd_re_r1; + ab_powe_re0 <= ab_powe_re_r1; + ab_powf_re0 <= ab_powf_re_r1; + b_pow16_re0 <= b_pow16_re_r1; + a_im0 <= ao_im_r1 ; + b_im0 <= bo_im_r1 ; + ab_im0 <= ab_im_r1 ; + abb_im0 <= abb_im_r1 ; + ab_pow3_im0 <= ab_pow3_im_r1; + ab_pow4_im0 <= ab_pow4_im_r1; + ab_pow5_im0 <= ab_pow5_im_r1; + ab_pow6_im0 <= ab_pow6_im_r1; + ab_pow7_im0 <= ab_pow7_im_r1; + ab_pow8_im0 <= ab_pow8_im_r1; + ab_pow9_im0 <= ab_pow9_im_r1; + ab_powa_im0 <= ab_powa_im_r1; + ab_powb_im0 <= ab_powb_im_r1; + ab_powc_im0 <= ab_powc_im_r1; + ab_powd_im0 <= ab_powd_im_r1; + ab_powe_im0 <= ab_powe_im_r1; + ab_powf_im0 <= ab_powf_im_r1; + b_pow16_im0 <= b_pow16_im_r1; end - vldi_r10[1]: begin + vldi_r18[1]: begin a_re1 <= ao_re_r1 ; b_re1 <= bo_re_r1 ; ab_re1 <= ab_re_r1 ; @@ -373,9 +700,35 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re1 <= ab_pow5_re_r1; ab_pow6_re1 <= ab_pow6_re_r1; ab_pow7_re1 <= ab_pow7_re_r1; - b_pow8_re1 <= b_pow8_re_r1 ; + ab_pow8_re1 <= ab_pow8_re_r1; + ab_pow9_re1 <= ab_pow9_re_r1; + ab_powa_re1 <= ab_powa_re_r1; + ab_powb_re1 <= ab_powb_re_r1; + ab_powc_re1 <= ab_powc_re_r1; + ab_powd_re1 <= ab_powd_re_r1; + ab_powe_re1 <= ab_powe_re_r1; + ab_powf_re1 <= ab_powf_re_r1; + b_pow16_re1 <= b_pow16_re_r1; + a_im1 <= ao_im_r1 ; + b_im1 <= bo_im_r1 ; + ab_im1 <= ab_im_r1 ; + abb_im1 <= abb_im_r1 ; + ab_pow3_im1 <= ab_pow3_im_r1; + ab_pow4_im1 <= ab_pow4_im_r1; + ab_pow5_im1 <= ab_pow5_im_r1; + ab_pow6_im1 <= ab_pow6_im_r1; + ab_pow7_im1 <= ab_pow7_im_r1; + ab_pow8_im1 <= ab_pow8_im_r1; + ab_pow9_im1 <= ab_pow9_im_r1; + ab_powa_im1 <= ab_powa_im_r1; + ab_powb_im1 <= ab_powb_im_r1; + ab_powc_im1 <= ab_powc_im_r1; + ab_powd_im1 <= ab_powd_im_r1; + ab_powe_im1 <= ab_powe_im_r1; + ab_powf_im1 <= ab_powf_im_r1; + b_pow16_im1 <= b_pow16_im_r1; end - vldi_r10[2]: begin + vldi_r18[2]: begin a_re2 <= ao_re_r1 ; b_re2 <= bo_re_r1 ; ab_re2 <= ab_re_r1 ; @@ -385,9 +738,35 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re2 <= ab_pow5_re_r1; ab_pow6_re2 <= ab_pow6_re_r1; ab_pow7_re2 <= ab_pow7_re_r1; - b_pow8_re2 <= b_pow8_re_r1 ; + ab_pow8_re2 <= ab_pow8_re_r1; + ab_pow9_re2 <= ab_pow9_re_r1; + ab_powa_re2 <= ab_powa_re_r1; + ab_powb_re2 <= ab_powb_re_r1; + ab_powc_re2 <= ab_powc_re_r1; + ab_powd_re2 <= ab_powd_re_r1; + ab_powe_re2 <= ab_powe_re_r1; + ab_powf_re2 <= ab_powf_re_r1; + b_pow16_re2 <= b_pow16_re_r1; + a_im2 <= ao_im_r1 ; + b_im2 <= bo_im_r1 ; + ab_im2 <= ab_im_r1 ; + abb_im2 <= abb_im_r1 ; + ab_pow3_im2 <= ab_pow3_im_r1; + ab_pow4_im2 <= ab_pow4_im_r1; + ab_pow5_im2 <= ab_pow5_im_r1; + ab_pow6_im2 <= ab_pow6_im_r1; + ab_pow7_im2 <= ab_pow7_im_r1; + ab_pow8_im2 <= ab_pow8_im_r1; + ab_pow9_im2 <= ab_pow9_im_r1; + ab_powa_im2 <= ab_powa_im_r1; + ab_powb_im2 <= ab_powb_im_r1; + ab_powc_im2 <= ab_powc_im_r1; + ab_powd_im2 <= ab_powd_im_r1; + ab_powe_im2 <= ab_powe_im_r1; + ab_powf_im2 <= ab_powf_im_r1; + b_pow16_im2 <= b_pow16_im_r1; end - vldi_r10[3]: begin + vldi_r18[3]: begin a_re3 <= ao_re_r1 ; b_re3 <= bo_re_r1 ; ab_re3 <= ab_re_r1 ; @@ -397,31 +776,33 @@ always @(posedge clk or negedge rstn) begin ab_pow5_re3 <= ab_pow5_re_r1; ab_pow6_re3 <= ab_pow6_re_r1; ab_pow7_re3 <= ab_pow7_re_r1; - b_pow8_re3 <= b_pow8_re_r1 ; - end - vldi_r10[4]: begin - a_re4 <= ao_re_r1 ; - b_re4 <= bo_re_r1 ; - ab_re4 <= ab_re_r1 ; - abb_re4 <= abb_re_r1 ; - ab_pow3_re4 <= ab_pow3_re_r1; - ab_pow4_re4 <= ab_pow4_re_r1; - ab_pow5_re4 <= ab_pow5_re_r1; - ab_pow6_re4 <= ab_pow6_re_r1; - ab_pow7_re4 <= ab_pow7_re_r1; - b_pow8_re4 <= b_pow8_re_r1 ; - end - vldi_r10[5]: begin - a_re5 <= ao_re_r1 ; - b_re5 <= bo_re_r1 ; - ab_re5 <= ab_re_r1 ; - abb_re5 <= abb_re_r1 ; - ab_pow3_re5 <= ab_pow3_re_r1; - ab_pow4_re5 <= ab_pow4_re_r1; - ab_pow5_re5 <= ab_pow5_re_r1; - ab_pow6_re5 <= ab_pow6_re_r1; - ab_pow7_re5 <= ab_pow7_re_r1; - b_pow8_re5 <= b_pow8_re_r1 ; + ab_pow8_re3 <= ab_pow8_re_r1; + ab_pow9_re3 <= ab_pow9_re_r1; + ab_powa_re3 <= ab_powa_re_r1; + ab_powb_re3 <= ab_powb_re_r1; + ab_powc_re3 <= ab_powc_re_r1; + ab_powd_re3 <= ab_powd_re_r1; + ab_powe_re3 <= ab_powe_re_r1; + ab_powf_re3 <= ab_powf_re_r1; + b_pow16_re3 <= b_pow16_re_r1; + a_im3 <= ao_im_r1 ; + b_im3 <= bo_im_r1 ; + ab_im3 <= ab_im_r1 ; + abb_im3 <= abb_im_r1 ; + ab_pow3_im3 <= ab_pow3_im_r1; + ab_pow4_im3 <= ab_pow4_im_r1; + ab_pow5_im3 <= ab_pow5_im_r1; + ab_pow6_im3 <= ab_pow6_im_r1; + ab_pow7_im3 <= ab_pow7_im_r1; + ab_pow8_im3 <= ab_pow8_im_r1; + ab_pow9_im3 <= ab_pow9_im_r1; + ab_powa_im3 <= ab_powa_im_r1; + ab_powb_im3 <= ab_powb_im_r1; + ab_powc_im3 <= ab_powc_im_r1; + ab_powd_im3 <= ab_powd_im_r1; + ab_powe_im3 <= ab_powe_im_r1; + ab_powf_im3 <= ab_powf_im_r1; + b_pow16_im3 <= b_pow16_im_r1; end // default: begin // ao_re[0] <= 'h0; diff --git a/rtl/z_dsp/IIR_Filter_p1.v b/rtl/z_dsp/IIR_Filter_p1.v index 4ea12e2..33e9412 100644 --- a/rtl/z_dsp/IIR_Filter_p1.v +++ b/rtl/z_dsp/IIR_Filter_p1.v @@ -49,8 +49,12 @@ module IIR_Filter_p1 #( ,input signed [cascade_in_width-1:0] dout_r1_re // Re(y(t-1)) ,input signed [coef_width-1 :0] a_re ,input signed [coef_width-1 :0] b_re +,input signed [cascade_in_width-1:0] dout_r1_im // Re(y(t-1)) +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] b_im ,output signed [data_out_width-1:0] dout_re // Re(y(t-16)) +,output signed [data_out_width-1:0] dout_im // Re(y(t-16)) ); @@ -60,43 +64,58 @@ wire signed [temp_var_width-1 :0] y1_re; wire signed [temp_var_width :0] y_re; wire signed [data_out_width-1:0] y_re_trunc; +wire signed [temp_var_width-1 :0] x1_im; + +wire signed [temp_var_width-1 :0] y1_im; +wire signed [temp_var_width :0] y_im; + +wire signed [data_out_width-1:0] y_im_trunc; // x1 = a * din delay M = a*x(t-8) -mult_real + +mult_x #( .A_width (data_in_width ) - ,.C_width (a_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) ,.o_width (temp_var_width ) ) inst_c1 ( .clk (clk ), .rstn (rstn ), .en (en ), - .din (din_re ), - .coef (a_re[coef_width-1 : coef_width-a_width]), - .dout (x1_re ) + .a (din_re ), + .c (a_re ), + .d (a_im ), + .Re (x1_re ), + .Im (x1_im ) ); - // y1 = b * dout_r1 delay M = b*y(t-9) // y = y1+x1 = a*x(t-8)+b*y(t-9) = y(t-8) -mult_real + +mult_C #( - .A_width (cascade_in_width ) - ,.C_width (b_width ) - ,.o_width (temp_var_width ) + .A_width (cascade_in_width ) + ,.B_width (cascade_in_width ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (temp_var_width ) ) -inst_c2 ( +inst_c3 ( .clk (clk ), .rstn (rstn ), .en (en ), - .din (dout_r1_re ), - .coef (b_re[coef_width-1 : coef_width-b_width]), - .dout (y1_re ) + .a (dout_r1_re ), + .b (dout_r1_im ), + .c (b_re ), + .d (b_im ), + .Re (y1_re ), + .Im (y1_im ) ); - assign y_re = x1_re + y1_re; +assign y_im = x1_im + y1_im; // dout = round(y) delay M = round(y(t-16)) @@ -105,7 +124,12 @@ trunc #( ,.msb (temp_var_width-1 ) ,.lsb (temp_var_width-data_out_width ) ) round_u1 (clk, rstn, en, y_re, y_re_trunc); - +trunc #( + .diw (temp_var_width+1 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) +) round_u2 (clk, rstn, en, y_im, y_im_trunc); assign dout_re = y_re_trunc; +assign dout_im = y_im_trunc; endmodule diff --git a/rtl/z_dsp/IIR_Filter_p16.v b/rtl/z_dsp/IIR_Filter_p16.v new file mode 100644 index 0000000..150e75d --- /dev/null +++ b/rtl/z_dsp/IIR_Filter_p16.v @@ -0,0 +1,237 @@ +module IIR_Filter_p16 #( + parameter coef_width = 32 +,parameter b_pow16_width = 29 +,parameter ab_pow_width = 32 +,parameter data_in_width = 16 +,parameter data_out_width = 16 +,parameter temp_var_width = 29 +) +// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) +( + input rstn +,input clk +,input en +,input signed [data_in_width-1 :0] dinp0 //x(8n+16) +,input signed [data_in_width-1 :0] dinp1 //x(8n+15) +,input signed [data_in_width-1 :0] dinp2 //x(8n+14) +,input signed [data_in_width-1 :0] dinp3 //x(8n+13) +,input signed [data_in_width-1 :0] dinp4 //x(8n+12) +,input signed [data_in_width-1 :0] dinp5 //x(8n+11) +,input signed [data_in_width-1 :0] dinp6 //x(8n+10) +,input signed [data_in_width-1 :0] dinp7 //x(8n+9) +,input signed [data_in_width-1 :0] dinp8 +,input signed [data_in_width-1 :0] dinp9 +,input signed [data_in_width-1 :0] dinpa +,input signed [data_in_width-1 :0] dinpb +,input signed [data_in_width-1 :0] dinpc +,input signed [data_in_width-1 :0] dinpd +,input signed [data_in_width-1 :0] dinpe +,input signed [data_in_width-1 :0] dinpf + +,input signed [coef_width-1 :0] a_re +,input signed [coef_width-1 :0] ab_re +,input signed [coef_width-1 :0] abb_re +,input signed [coef_width-1 :0] ab_pow3_re +,input signed [coef_width-1 :0] ab_pow4_re +,input signed [coef_width-1 :0] ab_pow5_re +,input signed [coef_width-1 :0] ab_pow6_re +,input signed [coef_width-1 :0] ab_pow7_re +,input signed [coef_width-1 :0] ab_pow8_re +,input signed [coef_width-1 :0] ab_pow9_re +,input signed [coef_width-1 :0] ab_powa_re +,input signed [coef_width-1 :0] ab_powb_re +,input signed [coef_width-1 :0] ab_powc_re +,input signed [coef_width-1 :0] ab_powd_re +,input signed [coef_width-1 :0] ab_powe_re +,input signed [coef_width-1 :0] ab_powf_re +,input signed [coef_width-1 :0] b_pow16_re +,input signed [coef_width-1 :0] a_im +,input signed [coef_width-1 :0] ab_im +,input signed [coef_width-1 :0] abb_im +,input signed [coef_width-1 :0] ab_pow3_im +,input signed [coef_width-1 :0] ab_pow4_im +,input signed [coef_width-1 :0] ab_pow5_im +,input signed [coef_width-1 :0] ab_pow6_im +,input signed [coef_width-1 :0] ab_pow7_im +,input signed [coef_width-1 :0] ab_pow8_im +,input signed [coef_width-1 :0] ab_pow9_im +,input signed [coef_width-1 :0] ab_powa_im +,input signed [coef_width-1 :0] ab_powb_im +,input signed [coef_width-1 :0] ab_powc_im +,input signed [coef_width-1 :0] ab_powd_im +,input signed [coef_width-1 :0] ab_powe_im +,input signed [coef_width-1 :0] ab_powf_im +,input signed [coef_width-1 :0] b_pow16_im + +,output signed [data_out_width-1:0] dout_re // Re(y(8n-8)) +,output signed [data_out_width-1:0] dout_im // Re(y(8n-8)) +); + +wire signed [data_in_width-1 :0] dinp [15:0]; +assign dinp[15] = dinpf; +assign dinp[14] = dinpe; +assign dinp[13] = dinpd; +assign dinp[12] = dinpc; +assign dinp[11] = dinpb; +assign dinp[10] = dinpa; +assign dinp[9 ] = dinp9; +assign dinp[8 ] = dinp8; +assign dinp[7 ] = dinp7; +assign dinp[6 ] = dinp6; +assign dinp[5 ] = dinp5; +assign dinp[4 ] = dinp4; +assign dinp[3 ] = dinp3; +assign dinp[2 ] = dinp2; +assign dinp[1 ] = dinp1; +assign dinp[0 ] = dinp0; + +wire signed [ab_pow_width-1 :0] ab_pow_re [15:0]; +wire signed [ab_pow_width-1 :0] ab_pow_im [15:0]; +assign ab_pow_re[15] = ab_powf_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[14] = ab_powe_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[13] = ab_powd_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[12] = ab_powc_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[11] = ab_powb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[10] = ab_powa_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[9 ] = ab_pow9_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[8 ] = ab_pow8_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[7 ] = ab_pow7_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[6 ] = ab_pow6_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[5 ] = ab_pow5_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[4 ] = ab_pow4_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[3 ] = ab_pow3_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[2 ] = abb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[1 ] = ab_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_re[0 ] = a_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; +assign ab_pow_im[15] = ab_powf_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[14] = ab_powe_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[13] = ab_powd_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[12] = ab_powc_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[11] = ab_powb_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[10] = ab_powa_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[9 ] = ab_pow9_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[8 ] = ab_pow8_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[7 ] = ab_pow7_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[6 ] = ab_pow6_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[5 ] = ab_pow5_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[4 ] = ab_pow4_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[3 ] = ab_pow3_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[2 ] = abb_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[1 ] = ab_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; +assign ab_pow_im[0 ] = a_im[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_im[coef_width-ab_pow_width-1]; + + + +wire signed [temp_var_width-1 :0] x_re [0:15]; + +wire signed [temp_var_width+3 :0] v_re; +reg signed [temp_var_width+3 :0] v1_re; + +wire signed [temp_var_width+3 :0] y_re; +wire signed [temp_var_width+3 :0] y1_re; + +wire signed [data_out_width-1:0] y_re_trunc; +wire signed [temp_var_width-1 :0] x_im [0:15]; + +wire signed [temp_var_width+3 :0] v_im; +reg signed [temp_var_width+3 :0] v1_im; + +wire signed [temp_var_width+3 :0] y_im; +wire signed [temp_var_width+3 :0] y1_im; + +wire signed [data_out_width-1:0] y_im_trunc; + +// x[0] = (dinp0 * a_re) delay M = a*x(8n+8) +// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7) +// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6) +// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5) +// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4) +// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3) +// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2) +// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1) +genvar i; +generate + for (i = 0; i < 16; i = i + 1) begin: mult_c_inst + mult_x #( + .A_width (data_in_width ), + .C_width (coef_width ), + .D_width (coef_width ), + .o_width (temp_var_width ) + ) inst_c ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (dinp[i] ), + .c (ab_pow_re[i] ), + .d (ab_pow_im[i] ), + .Re (x_re[i] ), + .Im (x_im[i] ) + ); + end +endgenerate + + +// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} +assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7] + x_re[8] + x_re[9] + x_re[10] + x_re[11] + x_re[12] + x_re[13] + x_re[14] + x_re[15] ; +assign v_im = x_im[0] + x_im[1] +x_im[2] +x_im[3] +x_im[4] +x_im[5] +x_im[6] +x_im[7] + x_im[8] + x_im[9] + x_im[10] + x_im[11] + x_im[12] + x_im[13] + x_im[14] + x_im[15] ; + +always @(posedge clk or negedge rstn) + if (!rstn) + begin + v1_re <= 'h0; + v1_im <= 'h0; + end + else if(en) + begin + v1_re <= v_re; + v1_im <= v_im; + end + else + begin + v1_re <= v1_re; + v1_im <= v1_im; + end + + +// y1 = (b^8 * y) delay M = b^8*y(8n-8) +// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) +mult_C +#( + .A_width (temp_var_width+4 ) + ,.B_width (temp_var_width+4 ) + ,.C_width (coef_width ) + ,.D_width (coef_width ) + ,.o_width (temp_var_width+4 ) +) +inst_c17 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .a (y_re ), + .b (y_im ), + .c (b_pow16_re ), + .d (b_pow16_im ), + .Re (y1_re ), + .Im (y1_im ) +); +assign y_re = v1_re + y1_re; +assign y_im = v1_im + y1_im; + +// dout = round(y) delay M = round(y(8n-8)) +trunc #( + .diw (temp_var_width+4 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) +) round_u1 (clk, rstn, en, y_re, y_re_trunc); + +trunc #( + .diw (temp_var_width+4 ) + ,.msb (temp_var_width-1 ) + ,.lsb (temp_var_width-data_out_width ) +) round_u2 (clk, rstn, en, y_im, y_im_trunc); + +assign dout_re = y_re_trunc; +assign dout_im = y_im_trunc; + +endmodule + diff --git a/rtl/z_dsp/IIR_Filter_p8.v b/rtl/z_dsp/IIR_Filter_p8.v deleted file mode 100644 index b53de74..0000000 --- a/rtl/z_dsp/IIR_Filter_p8.v +++ /dev/null @@ -1,143 +0,0 @@ -module IIR_Filter_p8 #( - parameter coef_width = 32 -,parameter b_pow8_width = 29 -,parameter ab_pow_width = 32 -,parameter data_in_width = 16 -,parameter data_out_width = 16 -,parameter temp_var_width = 29 -) -// H(z) = a(1 + b*z^-1 + b^2*z^-2 + b^3*z^-3 + b^4*z^-4 + b^5*z^-5 + b^6*z^-6 + b^7*z^-7) / (1 - b^8*z^-8) -( - input rstn -,input clk -,input en -,input signed [data_in_width-1 :0] dinp0 //x(8n+16) -,input signed [data_in_width-1 :0] dinp1 //x(8n+15) -,input signed [data_in_width-1 :0] dinp2 //x(8n+14) -,input signed [data_in_width-1 :0] dinp3 //x(8n+13) -,input signed [data_in_width-1 :0] dinp4 //x(8n+12) -,input signed [data_in_width-1 :0] dinp5 //x(8n+11) -,input signed [data_in_width-1 :0] dinp6 //x(8n+10) -,input signed [data_in_width-1 :0] dinp7 //x(8n+9) - -,input signed [coef_width-1 :0] a_re -,input signed [coef_width-1 :0] ab_re -,input signed [coef_width-1 :0] abb_re -,input signed [coef_width-1 :0] ab_pow3_re -,input signed [coef_width-1 :0] ab_pow4_re -,input signed [coef_width-1 :0] ab_pow5_re -,input signed [coef_width-1 :0] ab_pow6_re -,input signed [coef_width-1 :0] ab_pow7_re - -,input signed [coef_width-1 :0] b_pow8_re -,output signed [data_out_width-1:0] dout_re // Re(y(8n-8)) -); - -wire signed [data_in_width-1 :0] dinp [7:0]; -assign dinp[7] = dinp7; -assign dinp[6] = dinp6; -assign dinp[5] = dinp5; -assign dinp[4] = dinp4; -assign dinp[3] = dinp3; -assign dinp[2] = dinp2; -assign dinp[1] = dinp1; -assign dinp[0] = dinp0; - -wire signed [ab_pow_width-1 :0] ab_pow_re [7:0]; -assign ab_pow_re[7] = ab_pow7_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; -assign ab_pow_re[6] = ab_pow6_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; -assign ab_pow_re[5] = ab_pow5_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; -assign ab_pow_re[4] = ab_pow4_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; -assign ab_pow_re[3] = ab_pow3_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; -assign ab_pow_re[2] = abb_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; -assign ab_pow_re[1] = ab_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; -assign ab_pow_re[0] = a_re[coef_width-1 : coef_width-ab_pow_width];//+ab_pow7_re[coef_width-ab_pow_width-1]; - - - -wire signed [temp_var_width-1 :0] x_re [0:7]; - -wire signed [temp_var_width+3 :0] v_re; -reg signed [temp_var_width+3 :0] v1_re; - -wire signed [temp_var_width+3 :0] y_re; -wire signed [temp_var_width+3 :0] y1_re; - -wire signed [data_out_width-1:0] y_re_trunc; - -// x[0] = (dinp0 * a_re) delay M = a*x(8n+8) -// x[1] = (dinp1 * ab_re) delay M = a*b*x(8n+7) -// x[2] = (dinp2 * abb_re) delay M = a*b^2*x(8n+6) -// x[3] = (dinp3 * ab_pow3_re) delay M = a*b^3*x(8n+5) -// x[4] = (dinp4 * ab_pow4_re) delay M = a*b^4*x(8n+4) -// x[5] = (dinp5 * ab_pow5_re) delay M = a*b^5*x(8n+3) -// x[6] = (dinp6 * ab_pow6_re) delay M = a*b^6*x(8n+2) -// x[7] = (dinp7 * ab_pow7_re) delay M = a*b^7*x(8n+1) -genvar i; -generate - for (i = 0; i < 8; i = i + 1) begin: mult_c_inst - mult_real #( - .A_width (data_in_width ), - .C_width (ab_pow_width ), - .o_width (temp_var_width ) - ) inst_c ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .din (dinp[i] ), - .coef (ab_pow_re[i]), - .dout (x_re[i] ) - ); - end -endgenerate - - -// v1 = sum_{i=0,1,...,7}{x[i]} delay M = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} -assign v_re = x_re[0] + x_re[1] +x_re[2] +x_re[3] +x_re[4] +x_re[5] +x_re[6] +x_re[7]; - -always @(posedge clk or negedge rstn) - if (!rstn) - begin - v1_re <= 'h0; - end - else if(en) - begin - v1_re <= v_re; - end - else - begin - v1_re <= v1_re; - end - - -// y1 = (b^8 * y) delay M = b^8*y(8n-8) -// y = v1 + y1 = sum_{i=0,1,...,7}{a*b^i*x(8n-i)} + b^8*y(8n-8) = y(8n) -mult_real -#( - .A_width (temp_var_width+4 ) - ,.C_width (b_pow8_width ) - ,.o_width (temp_var_width+4 ) -) -inst_c9 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .din (y_re ), - .coef (b_pow8_re[coef_width-1 : coef_width-b_pow8_width]),//+b_pow8_re[coef_width-b_pow8_width-1]), - .dout (y1_re ) -); - -assign y_re = v1_re + y1_re; - -// dout = round(y) delay M = round(y(8n-8)) -trunc #( - .diw (temp_var_width+4 ) - ,.msb (temp_var_width-1 ) - ,.lsb (temp_var_width-data_out_width ) -) round_u1 (clk, rstn, en, y_re, y_re_trunc); - - -assign dout_re = y_re_trunc; - -endmodule - diff --git a/rtl/z_dsp/IIR_top.v b/rtl/z_dsp/IIR_top.v index c394752..7ee20da 100644 --- a/rtl/z_dsp/IIR_top.v +++ b/rtl/z_dsp/IIR_top.v @@ -34,6 +34,38 @@ module IIR_top #( ,parameter b7_width = 22 ,parameter b7_i_width = 18 ,parameter b7_o_width = 18 +,parameter a8_width = 23 +,parameter b8_width = 23 +,parameter b8_i_width = 18 +,parameter b8_o_width = 18 +,parameter a9_width = 24 +,parameter b9_width = 24 +,parameter b9_i_width = 18 +,parameter b9_o_width = 18 +,parameter a10_width = 25 +,parameter b10_width = 25 +,parameter b10_i_width = 18 +,parameter b10_o_width = 18 +,parameter a11_width = 26 +,parameter b11_width = 26 +,parameter b11_i_width = 18 +,parameter b11_o_width = 18 +,parameter a12_width = 27 +,parameter b12_width = 27 +,parameter b12_i_width = 18 +,parameter b12_o_width = 18 +,parameter a13_width = 28 +,parameter b13_width = 28 +,parameter b13_i_width = 18 +,parameter b13_o_width = 18 +,parameter a14_width = 29 +,parameter b14_width = 29 +,parameter b14_i_width = 18 +,parameter b14_o_width = 18 +,parameter a15_width = 29 +,parameter b15_width = 29 +,parameter b15_i_width = 18 +,parameter b15_o_width = 18 ) ( input rstn @@ -47,6 +79,14 @@ module IIR_top #( ,input signed [15 :0] IIRin_p5 // x(8n+14) ,input signed [15 :0] IIRin_p6 // x(8n+15) ,input signed [15 :0] IIRin_p7 // x(8n+16) +,input signed [15 :0] IIRin_p8 // x(8n+9) +,input signed [15 :0] IIRin_p9 // x(8n+10) +,input signed [15 :0] IIRin_pa // x(8n+11) +,input signed [15 :0] IIRin_pb // x(8n+12) +,input signed [15 :0] IIRin_pc // x(8n+13) +,input signed [15 :0] IIRin_pd // x(8n+14) +,input signed [15 :0] IIRin_pe // x(8n+15) +,input signed [15 :0] IIRin_pf // x(8n+16) ,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) ,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) ,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) @@ -54,6 +94,14 @@ module IIR_top #( ,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) ,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) ,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) +,input signed [15 :0] IIRin_p7_r16 // x(8n+16) delay 16M -> x(8n-112) +,input signed [15 :0] IIRin_p8_r18 // x(8n+15) delay 18M -> x(8n-127) +,input signed [15 :0] IIRin_p9_r20 // x(8n+14) delay 20M -> x(8n-142) +,input signed [15 :0] IIRin_pa_r22 // x(8n+13) delay 22M -> x(8n-157) +,input signed [15 :0] IIRin_pb_r24 // x(8n+12) delay 24M -> x(8n-172) +,input signed [15 :0] IIRin_pc_r26 // x(8n+11) delay 26M -> x(8n-187) +,input signed [15 :0] IIRin_pd_r28 // x(8n+10) delay 28M -> x(8n-202) +,input signed [15 :0] IIRin_pe_r30 // x(8n+9) delay 30M -> x(8n-217) ,input signed [31 :0] a_re ,input signed [31 :0] b_re ,input signed [31 :0] ab_re @@ -63,7 +111,33 @@ module IIR_top #( ,input signed [31 :0] ab_pow5_re ,input signed [31 :0] ab_pow6_re ,input signed [31 :0] ab_pow7_re -,input signed [31 :0] b_pow8_re +,input signed [31 :0] ab_pow8_re +,input signed [31 :0] ab_pow9_re +,input signed [31 :0] ab_powa_re +,input signed [31 :0] ab_powb_re +,input signed [31 :0] ab_powc_re +,input signed [31 :0] ab_powd_re +,input signed [31 :0] ab_powe_re +,input signed [31 :0] ab_powf_re +,input signed [31 :0] b_pow16_re +,input signed [31 :0] a_im +,input signed [31 :0] b_im +,input signed [31 :0] ab_im +,input signed [31 :0] abb_im +,input signed [31 :0] ab_pow3_im +,input signed [31 :0] ab_pow4_im +,input signed [31 :0] ab_pow5_im +,input signed [31 :0] ab_pow6_im +,input signed [31 :0] ab_pow7_im +,input signed [31 :0] ab_pow8_im +,input signed [31 :0] ab_pow9_im +,input signed [31 :0] ab_powa_im +,input signed [31 :0] ab_powb_im +,input signed [31 :0] ab_powc_im +,input signed [31 :0] ab_powd_im +,input signed [31 :0] ab_powe_im +,input signed [31 :0] ab_powf_im +,input signed [31 :0] b_pow16_im ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) @@ -73,6 +147,14 @@ module IIR_top #( ,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) ,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) +,output signed [data_out_width-1 :0] IIRout_p8 // y(8n-128) +,output signed [data_out_width-1 :0] IIRout_p9 // y(8n-143) +,output signed [data_out_width-1 :0] IIRout_pa // y(8n-158) +,output signed [data_out_width-1 :0] IIRout_pb // y(8n-173) +,output signed [data_out_width-1 :0] IIRout_pc // y(8n-188) +,output signed [data_out_width-1 :0] IIRout_pd // y(8n-203) +,output signed [data_out_width-1 :0] IIRout_pe // y(8n-218) +,output signed [data_out_width-1 :0] IIRout_pf // y(8n-233) ); wire signed [b0_o_width- 1:0] IIRout_p0_re; @@ -83,39 +165,98 @@ wire signed [b4_o_width- 1:0] IIRout_p4_re; wire signed [b5_o_width- 1:0] IIRout_p5_re; wire signed [b6_o_width- 1:0] IIRout_p6_re; wire signed [b7_o_width- 1:0] IIRout_p7_re; +wire signed [b8_o_width- 1:0] IIRout_p8_re; +wire signed [b9_o_width- 1:0] IIRout_p9_re; +wire signed [b10_o_width- 1:0] IIRout_pa_re; +wire signed [b11_o_width- 1:0] IIRout_pb_re; +wire signed [b12_o_width- 1:0] IIRout_pc_re; +wire signed [b13_o_width- 1:0] IIRout_pd_re; +wire signed [b14_o_width- 1:0] IIRout_pe_re; +wire signed [b15_o_width- 1:0] IIRout_pf_re; +wire signed [b0_o_width- 1:0] IIRout_p0_im; +wire signed [b1_o_width- 1:0] IIRout_p1_im; +wire signed [b2_o_width- 1:0] IIRout_p2_im; +wire signed [b3_o_width- 1:0] IIRout_p3_im; +wire signed [b4_o_width- 1:0] IIRout_p4_im; +wire signed [b5_o_width- 1:0] IIRout_p5_im; +wire signed [b6_o_width- 1:0] IIRout_p6_im; +wire signed [b7_o_width- 1:0] IIRout_p7_im; +wire signed [b8_o_width- 1:0] IIRout_p8_im; +wire signed [b9_o_width- 1:0] IIRout_p9_im; +wire signed [b10_o_width- 1:0] IIRout_pa_im; +wire signed [b11_o_width- 1:0] IIRout_pb_im; +wire signed [b12_o_width- 1:0] IIRout_pc_im; +wire signed [b13_o_width- 1:0] IIRout_pd_im; +wire signed [b14_o_width- 1:0] IIRout_pe_im; +wire signed [b15_o_width- 1:0] IIRout_pf_im; - - -IIR_Filter_p8 #( - .coef_width (coef_width ), - .b_pow8_width (b0_width ), - .ab_pow_width (a0_width ), - .temp_var_width (b0_i_width ), - .data_out_width (b0_o_width ) -) inst_iir_p0 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .dinp0 (IIRin_p7 ), // x(8n+16) - .dinp1 (IIRin_p6 ), // x(8n+15) - .dinp2 (IIRin_p5 ), // x(8n+14) - .dinp3 (IIRin_p4 ), // x(8n+13) - .dinp4 (IIRin_p3 ), // x(8n+12) - .dinp5 (IIRin_p2 ), // x(8n+11) - .dinp6 (IIRin_p1 ), // x(8n+10) - .dinp7 (IIRin_p0 ), // x(8n+9) - .a_re (a_re ), - .ab_re (ab_re ), - .abb_re (abb_re ), - .ab_pow3_re (ab_pow3_re ), - .ab_pow4_re (ab_pow4_re ), - .ab_pow5_re (ab_pow5_re ), - .ab_pow6_re (ab_pow6_re ), - .ab_pow7_re (ab_pow7_re ), - .b_pow8_re (b_pow8_re ), - .dout_re (IIRout_p0_re ) // Re(y(8n-8)) +IIR_Filter_p16#( + .coef_width ( coef_width ), + .b_pow16_width ( b0_width ), + .ab_pow_width ( a0_width ), + .temp_var_width ( b0_i_width ), + .data_out_width ( b0_o_width ) +)inst_iir_p0( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .dinp0 ( IIRin_pf ), + .dinp1 ( IIRin_pe ), + .dinp2 ( IIRin_pd ), + .dinp3 ( IIRin_pc ), + .dinp4 ( IIRin_pb ), + .dinp5 ( IIRin_pa ), + .dinp6 ( IIRin_p9 ), + .dinp7 ( IIRin_p8 ), + .dinp8 ( IIRin_p7 ), + .dinp9 ( IIRin_p6 ), + .dinpa ( IIRin_p5 ), + .dinpb ( IIRin_p4 ), + .dinpc ( IIRin_p3 ), + .dinpd ( IIRin_p2 ), + .dinpe ( IIRin_p1 ), + .dinpf ( IIRin_p0 ), + .a_re ( a_re ), + .ab_re ( ab_re ), + .abb_re ( abb_re ), + .ab_pow3_re ( ab_pow3_re ), + .ab_pow4_re ( ab_pow4_re ), + .ab_pow5_re ( ab_pow5_re ), + .ab_pow6_re ( ab_pow6_re ), + .ab_pow7_re ( ab_pow7_re ), + .ab_pow8_re ( ab_pow8_re ), + .ab_pow9_re ( ab_pow9_re ), + .ab_powa_re ( ab_powa_re ), + .ab_powb_re ( ab_powb_re ), + .ab_powc_re ( ab_powc_re ), + .ab_powd_re ( ab_powd_re ), + .ab_powe_re ( ab_powe_re ), + .ab_powf_re ( ab_powf_re ), + .b_pow16_re ( b_pow16_re ), + .a_im ( a_im ), + .ab_im ( ab_im ), + .abb_im ( abb_im ), + .ab_pow3_im ( ab_pow3_im ), + .ab_pow4_im ( ab_pow4_im ), + .ab_pow5_im ( ab_pow5_im ), + .ab_pow6_im ( ab_pow6_im ), + .ab_pow7_im ( ab_pow7_im ), + .ab_pow8_im ( ab_pow8_im ), + .ab_pow9_im ( ab_pow9_im ), + .ab_powa_im ( ab_powa_im ), + .ab_powb_im ( ab_powb_im ), + .ab_powc_im ( ab_powc_im ), + .ab_powd_im ( ab_powd_im ), + .ab_powe_im ( ab_powe_im ), + .ab_powf_im ( ab_powf_im ), + .b_pow16_im ( b_pow16_im ), + .dout_re ( IIRout_p0_re ), + .dout_im ( IIRout_p0_im ) ); + + + IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a1_width ), @@ -124,13 +265,17 @@ IIR_Filter_p1 #( .data_out_width (b1_o_width ) ) inst_iir_p1( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p0_r2 ), // x(8n-7) .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) - .a_re (a_re ), - .b_re (b_re ), - .dout_re (IIRout_p1_re ) // Re(y(8n-23)) + .dout_r1_im (IIRout_p0_im ), // Re(y(8n-8)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p1_re ), // Re(y(8n-23)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p1_im ) // Re(y(8n-23)) ); IIR_Filter_p1 #( .coef_width (coef_width ), @@ -140,13 +285,17 @@ IIR_Filter_p1 #( .data_out_width (b2_o_width ) ) inst_iir_p2 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p1_r4 ), // x(8n-22) .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) - .a_re (a_re ), - .b_re (b_re ), - .dout_re (IIRout_p2_re ) // Re(y(8n-38)) + .dout_r1_im (IIRout_p1_im ), // Re(y(8n-23)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p2_re ), // Re(y(8n-38)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p2_im ) // Re(y(8n-38)) ); IIR_Filter_p1 #( .coef_width (coef_width ), @@ -156,13 +305,17 @@ IIR_Filter_p1 #( .data_out_width (b3_o_width ) ) inst_iir_p3 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p2_r6 ), // x(8n-37) .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) - .a_re (a_re ), - .b_re (b_re ), - .dout_re (IIRout_p3_re ) // Re(y(8n-53)) + .dout_r1_im (IIRout_p2_im ), // Re(y(8n-38)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p3_re ), // Re(y(8n-53)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p3_im ) // Re(y(8n-53)) ); IIR_Filter_p1 #( .coef_width (coef_width ), @@ -172,13 +325,17 @@ IIR_Filter_p1 #( .data_out_width (b4_o_width ) ) inst_iir_p4 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p3_r8 ), // x(8n-52) .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) - .a_re (a_re ), - .b_re (b_re ), - .dout_re (IIRout_p4_re ) // Re(y(8n-68)) + .dout_r1_im (IIRout_p3_im ), // Re(y(8n-53)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p4_re ), // Re(y(8n-68)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p4_im ) // Re(y(8n-68)) ); IIR_Filter_p1 #( .coef_width (coef_width ), @@ -188,13 +345,17 @@ IIR_Filter_p1 #( .data_out_width (b5_o_width ) ) inst_iir_p5 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p4_r10 ), // x(8n-67) .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) - .a_re (a_re ), - .b_re (b_re ), - .dout_re (IIRout_p5_re ) // Re(y(8n-83)) + .dout_r1_im (IIRout_p4_im ), // Re(y(8n-68)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p5_re ), // Re(y(8n-83)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p5_im ) // Re(y(8n-83)) ); IIR_Filter_p1 #( .coef_width (coef_width ), @@ -204,13 +365,17 @@ IIR_Filter_p1 #( .data_out_width (b6_o_width ) ) inst_iir_p6 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p5_r12 ), // x(8n-82) .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) - .a_re (a_re ), - .b_re (b_re ), - .dout_re (IIRout_p6_re ) // Re(y(8n-98)) + .dout_r1_im (IIRout_p5_im ), // Re(y(8n-83)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p6_re ), // Re(y(8n-98)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p6_im ) // Re(y(8n-98)) ); IIR_Filter_p1 #( .coef_width (coef_width ), @@ -220,14 +385,185 @@ IIR_Filter_p1 #( .data_out_width (b7_o_width ) ) inst_iir_p7 ( .clk (clk ), - .rstn (rstn ), - .en (en ), + .rstn (rstn ), + .en (en ), .din_re (IIRin_p6_r14 ), // x(8n-97) .dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) - .a_re (a_re ), - .b_re (b_re ), - .dout_re (IIRout_p7_re ) // Re(y(8n-113)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p7_re ), // Re(y(8n-113)) + .dout_r1_im (IIRout_p6_im ), // Re(y(8n-98)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p7_im ) // Re(y(8n-113)) ); +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a8_width ), + .b_width (b8_width ), + .cascade_in_width (b8_i_width ), + .data_out_width (b8_o_width ) +) inst_iir_p8 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p7_r16 ), // x(8n-112) + .dout_r1_re (IIRout_p7_re ), // Re(y(8n-113)) + .dout_r1_im (IIRout_p7_im ), // Re(y(8n-113)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p8_re ), // Re(y(8n-128)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p8_im ) // Re(y(8n-128)) +); + +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a9_width ), + .b_width (b9_width ), + .cascade_in_width (b9_i_width ), + .data_out_width (b9_o_width ) +) inst_iir_p9 ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p8_r18 ), // x(8n-127) + .dout_r1_re (IIRout_p8_re ), // Re(y(8n-128)) + .dout_r1_im (IIRout_p8_im ), // Re(y(8n-128)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_p9_re ), // Re(y(8n-143)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_p9_im ) // Re(y(8n-143)) +); + +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a10_width ), + .b_width (b10_width ), + .cascade_in_width (b10_i_width ), + .data_out_width (b10_o_width ) +) inst_iir_pa ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_p9_r20 ), // x(8n-142) + .dout_r1_re (IIRout_p9_re ), // Re(y(8n-143)) + .dout_r1_im (IIRout_p9_im ), // Re(y(8n-143)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_pa_re ), // Re(y(8n-158)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_pa_im ) // Re(y(8n-158)) +); + +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a11_width ), + .b_width (b11_width ), + .cascade_in_width (b11_i_width ), + .data_out_width (b11_o_width ) +) inst_iir_pb ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_pa_r22 ), // x(8n-157) + .dout_r1_re (IIRout_pa_re ), // Re(y(8n-158)) + .dout_r1_im (IIRout_pa_im ), // Re(y(8n-158)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_pb_re ), // Re(y(8n-173)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_pb_im ) // Re(y(8n-173)) +); + +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a12_width ), + .b_width (b12_width ), + .cascade_in_width (b12_i_width ), + .data_out_width (b12_o_width ) +) inst_iir_pc ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_pb_r24 ), // x(8n-172) + .dout_r1_re (IIRout_pb_re ), // Re(y(8n-173)) + .dout_r1_im (IIRout_pb_im ), // Re(y(8n-173)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_pc_re ), // Re(y(8n-188)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_pc_im ) // Re(y(8n-188)) +); + +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a13_width ), + .b_width (b13_width ), + .cascade_in_width (b13_i_width ), + .data_out_width (b13_o_width ) +) inst_iir_pd ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_pc_r26 ), // x(8n-187) + .dout_r1_re (IIRout_pc_re ), // Re(y(8n-188)) + .dout_r1_im (IIRout_pc_im ), // Re(y(8n-188)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_pd_re ), // Re(y(8n-203)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_pd_im ) // Re(y(8n-203)) +); + +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a14_width ), + .b_width (b14_width ), + .cascade_in_width (b14_i_width ), + .data_out_width (b14_o_width ) +) inst_iir_pe ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_pd_r28 ), // x(8n-202) + .dout_r1_re (IIRout_pd_re ), // Re(y(8n-203)) + .dout_r1_im (IIRout_pd_im ), // Re(y(8n-203)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_pe_re ), // Re(y(8n-218)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_pe_im ) // Re(y(8n-218)) +); + +IIR_Filter_p1 #( + .coef_width (coef_width ), + .a_width (a15_width ), + .b_width (b15_width ), + .cascade_in_width (b15_i_width ), + .data_out_width (b15_o_width ) +) inst_iir_pf ( + .clk (clk ), + .rstn (rstn ), + .en (en ), + .din_re (IIRin_pe_r30 ), // x(8n-217) + .dout_r1_re (IIRout_pe_re ), // Re(y(8n-218)) + .dout_r1_im (IIRout_pe_im ), // Re(y(8n-218)) + .a_re (a_re ), + .b_re (b_re ), + .dout_re (IIRout_pf_re ), // Re(y(8n-233)) + .a_im (a_im ), + .b_im (b_im ), + .dout_im (IIRout_pf_im ) // Re(y(8n-233)) +); assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8) @@ -238,6 +574,14 @@ assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83) assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98) assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113) +assign IIRout_p8 = IIRout_p8_re[b8_o_width-1 : b8_o_width-data_out_width]; // y(8n-128) +assign IIRout_p9 = IIRout_p9_re[b9_o_width-1 : b9_o_width-data_out_width]; // y(8n-143) +assign IIRout_pa = IIRout_pa_re[b10_o_width-1 : b10_o_width-data_out_width]; // y(8n-158) +assign IIRout_pb = IIRout_pb_re[b11_o_width-1 : b11_o_width-data_out_width]; // y(8n-173) +assign IIRout_pc = IIRout_pc_re[b12_o_width-1 : b12_o_width-data_out_width]; // y(8n-188) +assign IIRout_pd = IIRout_pd_re[b13_o_width-1 : b13_o_width-data_out_width]; // y(8n-203) +assign IIRout_pe = IIRout_pe_re[b14_o_width-1 : b14_o_width-data_out_width]; // y(8n-218) +assign IIRout_pf = IIRout_pf_re[b15_o_width-1 : b15_o_width-data_out_width]; // y(8n-233) endmodule diff --git a/rtl/z_dsp/TailCorr_top.v b/rtl/z_dsp/TailCorr_top.v index 587f46b..5aaff11 100644 --- a/rtl/z_dsp/TailCorr_top.v +++ b/rtl/z_dsp/TailCorr_top.v @@ -1,6 +1,6 @@ module TailCorr_top #( - parameter temp_var_width = 18 +parameter temp_var_width = 18 ) ( input rstn @@ -11,6 +11,19 @@ module TailCorr_top #( ,input signed [15:0] din1 ,input signed [15:0] din2 ,input signed [15:0] din3 +,input signed [15:0] din4 +,input signed [15:0] din5 +,input signed [15:0] din6 +,input signed [15:0] din7 +,input signed [15:0] din8 +,input signed [15:0] din9 +,input signed [15:0] dina +,input signed [15:0] dinb +,input signed [15:0] dinc +,input signed [15:0] dind +,input signed [15:0] dine +,input signed [15:0] dinf + ,input signed [31:0] a_re0 ,input signed [31:0] b_re0 ,input signed [31:0] ab_re0 @@ -20,7 +33,34 @@ module TailCorr_top #( ,input signed [31:0] ab_pow5_re0 ,input signed [31:0] ab_pow6_re0 ,input signed [31:0] ab_pow7_re0 -,input signed [31:0] b_pow8_re0 +,input signed [31:0] ab_pow8_re0 +,input signed [31:0] ab_pow9_re0 +,input signed [31:0] ab_powa_re0 +,input signed [31:0] ab_powb_re0 +,input signed [31:0] ab_powc_re0 +,input signed [31:0] ab_powd_re0 +,input signed [31:0] ab_powe_re0 +,input signed [31:0] ab_powf_re0 +,input signed [31:0] b_pow16_re0 +,input signed [31:0] a_im0 +,input signed [31:0] b_im0 +,input signed [31:0] ab_im0 +,input signed [31:0] abb_im0 +,input signed [31:0] ab_pow3_im0 +,input signed [31:0] ab_pow4_im0 +,input signed [31:0] ab_pow5_im0 +,input signed [31:0] ab_pow6_im0 +,input signed [31:0] ab_pow7_im0 +,input signed [31:0] ab_pow8_im0 +,input signed [31:0] ab_pow9_im0 +,input signed [31:0] ab_powa_im0 +,input signed [31:0] ab_powb_im0 +,input signed [31:0] ab_powc_im0 +,input signed [31:0] ab_powd_im0 +,input signed [31:0] ab_powe_im0 +,input signed [31:0] ab_powf_im0 +,input signed [31:0] b_pow16_im0 + ,input signed [31:0] a_re1 ,input signed [31:0] b_re1 ,input signed [31:0] ab_re1 @@ -30,7 +70,34 @@ module TailCorr_top #( ,input signed [31:0] ab_pow5_re1 ,input signed [31:0] ab_pow6_re1 ,input signed [31:0] ab_pow7_re1 -,input signed [31:0] b_pow8_re1 +,input signed [31:0] ab_pow8_re1 +,input signed [31:0] ab_pow9_re1 +,input signed [31:0] ab_powa_re1 +,input signed [31:0] ab_powb_re1 +,input signed [31:0] ab_powc_re1 +,input signed [31:0] ab_powd_re1 +,input signed [31:0] ab_powe_re1 +,input signed [31:0] ab_powf_re1 +,input signed [31:0] b_pow16_re1 +,input signed [31:0] a_im1 +,input signed [31:0] b_im1 +,input signed [31:0] ab_im1 +,input signed [31:0] abb_im1 +,input signed [31:0] ab_pow3_im1 +,input signed [31:0] ab_pow4_im1 +,input signed [31:0] ab_pow5_im1 +,input signed [31:0] ab_pow6_im1 +,input signed [31:0] ab_pow7_im1 +,input signed [31:0] ab_pow8_im1 +,input signed [31:0] ab_pow9_im1 +,input signed [31:0] ab_powa_im1 +,input signed [31:0] ab_powb_im1 +,input signed [31:0] ab_powc_im1 +,input signed [31:0] ab_powd_im1 +,input signed [31:0] ab_powe_im1 +,input signed [31:0] ab_powf_im1 +,input signed [31:0] b_pow16_im1 + ,input signed [31:0] a_re2 ,input signed [31:0] b_re2 ,input signed [31:0] ab_re2 @@ -40,7 +107,34 @@ module TailCorr_top #( ,input signed [31:0] ab_pow5_re2 ,input signed [31:0] ab_pow6_re2 ,input signed [31:0] ab_pow7_re2 -,input signed [31:0] b_pow8_re2 +,input signed [31:0] ab_pow8_re2 +,input signed [31:0] ab_pow9_re2 +,input signed [31:0] ab_powa_re2 +,input signed [31:0] ab_powb_re2 +,input signed [31:0] ab_powc_re2 +,input signed [31:0] ab_powd_re2 +,input signed [31:0] ab_powe_re2 +,input signed [31:0] ab_powf_re2 +,input signed [31:0] b_pow16_re2 +,input signed [31:0] a_im2 +,input signed [31:0] b_im2 +,input signed [31:0] ab_im2 +,input signed [31:0] abb_im2 +,input signed [31:0] ab_pow3_im2 +,input signed [31:0] ab_pow4_im2 +,input signed [31:0] ab_pow5_im2 +,input signed [31:0] ab_pow6_im2 +,input signed [31:0] ab_pow7_im2 +,input signed [31:0] ab_pow8_im2 +,input signed [31:0] ab_pow9_im2 +,input signed [31:0] ab_powa_im2 +,input signed [31:0] ab_powb_im2 +,input signed [31:0] ab_powc_im2 +,input signed [31:0] ab_powd_im2 +,input signed [31:0] ab_powe_im2 +,input signed [31:0] ab_powf_im2 +,input signed [31:0] b_pow16_im2 + ,input signed [31:0] a_re3 ,input signed [31:0] b_re3 ,input signed [31:0] ab_re3 @@ -50,37 +144,51 @@ module TailCorr_top #( ,input signed [31:0] ab_pow5_re3 ,input signed [31:0] ab_pow6_re3 ,input signed [31:0] ab_pow7_re3 -,input signed [31:0] b_pow8_re3 -,input signed [31:0] a_re4 -,input signed [31:0] b_re4 -,input signed [31:0] ab_re4 -,input signed [31:0] abb_re4 -,input signed [31:0] ab_pow3_re4 -,input signed [31:0] ab_pow4_re4 -,input signed [31:0] ab_pow5_re4 -,input signed [31:0] ab_pow6_re4 -,input signed [31:0] ab_pow7_re4 -,input signed [31:0] b_pow8_re4 -,input signed [31:0] a_re5 -,input signed [31:0] b_re5 -,input signed [31:0] ab_re5 -,input signed [31:0] abb_re5 -,input signed [31:0] ab_pow3_re5 -,input signed [31:0] ab_pow4_re5 -,input signed [31:0] ab_pow5_re5 -,input signed [31:0] ab_pow6_re5 -,input signed [31:0] ab_pow7_re5 -,input signed [31:0] b_pow8_re5 +,input signed [31:0] ab_pow8_re3 +,input signed [31:0] ab_pow9_re3 +,input signed [31:0] ab_powa_re3 +,input signed [31:0] ab_powb_re3 +,input signed [31:0] ab_powc_re3 +,input signed [31:0] ab_powd_re3 +,input signed [31:0] ab_powe_re3 +,input signed [31:0] ab_powf_re3 +,input signed [31:0] b_pow16_re3 +,input signed [31:0] a_im3 +,input signed [31:0] b_im3 +,input signed [31:0] ab_im3 +,input signed [31:0] abb_im3 +,input signed [31:0] ab_pow3_im3 +,input signed [31:0] ab_pow4_im3 +,input signed [31:0] ab_pow5_im3 +,input signed [31:0] ab_pow6_im3 +,input signed [31:0] ab_pow7_im3 +,input signed [31:0] ab_pow8_im3 +,input signed [31:0] ab_pow9_im3 +,input signed [31:0] ab_powa_im3 +,input signed [31:0] ab_powb_im3 +,input signed [31:0] ab_powc_im3 +,input signed [31:0] ab_powd_im3 +,input signed [31:0] ab_powe_im3 +,input signed [31:0] ab_powf_im3 +,input signed [31:0] b_pow16_im3 -,output signed [15:0] dout_p0 -,output signed [15:0] dout_p1 -,output signed [15:0] dout_p2 -,output signed [15:0] dout_p3 -,output signed [15:0] dout_p4 -,output signed [15:0] dout_p5 -,output signed [15:0] dout_p6 -,output signed [15:0] dout_p7 -,output vldo +,output signed [15:0] dout_p0 +,output signed [15:0] dout_p1 +,output signed [15:0] dout_p2 +,output signed [15:0] dout_p3 +,output signed [15:0] dout_p4 +,output signed [15:0] dout_p5 +,output signed [15:0] dout_p6 +,output signed [15:0] dout_p7 +,output signed [15:0] dout_p8 +,output signed [15:0] dout_p9 +,output signed [15:0] dout_pa +,output signed [15:0] dout_pb +,output signed [15:0] dout_pc +,output signed [15:0] dout_pd +,output signed [15:0] dout_pe +,output signed [15:0] dout_pf +,output vldo ); wire signed [15:0] din_p0; @@ -91,6 +199,14 @@ wire signed [15:0] din_p4; wire signed [15:0] din_p5; wire signed [15:0] din_p6; wire signed [15:0] din_p7; +wire signed [15:0] din_p8; +wire signed [15:0] din_p9; +wire signed [15:0] din_pa; +wire signed [15:0] din_pb; +wire signed [15:0] din_pc; +wire signed [15:0] din_pd; +wire signed [15:0] din_pe; +wire signed [15:0] din_pf; wire signed [15:0] IIRin_p0; // iirin_x(8n+9) wire signed [15:0] IIRin_p1; // iirin_x(8n+10) wire signed [15:0] IIRin_p2; // iirin_x(8n+11) @@ -99,14 +215,30 @@ wire signed [15:0] IIRin_p4; // iirin_x(8n+13) wire signed [15:0] IIRin_p5; // iirin_x(8n+14) wire signed [15:0] IIRin_p6; // iirin_x(8n+15) wire signed [15:0] IIRin_p7; // iirin_x(8n+16) -wire signed [temp_var_width-1:0] IIRout_p0 [5:0]; // iirout_y(8n-8) -wire signed [temp_var_width-1:0] IIRout_p1 [5:0]; // iirout_y(8n-23) -wire signed [temp_var_width-1:0] IIRout_p2 [5:0]; // iirout_y(8n-38) -wire signed [temp_var_width-1:0] IIRout_p3 [5:0]; // iirout_y(8n-53) -wire signed [temp_var_width-1:0] IIRout_p4 [5:0]; // iirout_y(8n-68) -wire signed [temp_var_width-1:0] IIRout_p5 [5:0]; // iirout_y(8n-83) -wire signed [temp_var_width-1:0] IIRout_p6 [5:0]; // iirout_y(8n-98) -wire signed [temp_var_width-1:0] IIRout_p7 [5:0]; // iirout_y(8n-113) +wire signed [15:0] IIRin_p8; // iirin_x(8n+16) +wire signed [15:0] IIRin_p9; // iirin_x(8n+16) +wire signed [15:0] IIRin_pa; // iirin_x(8n+16) +wire signed [15:0] IIRin_pb; // iirin_x(8n+16) +wire signed [15:0] IIRin_pc; // iirin_x(8n+16) +wire signed [15:0] IIRin_pd; // iirin_x(8n+16) +wire signed [15:0] IIRin_pe; // iirin_x(8n+16) +wire signed [15:0] IIRin_pf; // iirin_x(8n+16) +wire signed [temp_var_width-1:0] IIRout_p0 [3:0]; // iirout_y(8n-8) +wire signed [temp_var_width-1:0] IIRout_p1 [3:0]; // iirout_y(8n-23) +wire signed [temp_var_width-1:0] IIRout_p2 [3:0]; // iirout_y(8n-38) +wire signed [temp_var_width-1:0] IIRout_p3 [3:0]; // iirout_y(8n-53) +wire signed [temp_var_width-1:0] IIRout_p4 [3:0]; // iirout_y(8n-68) +wire signed [temp_var_width-1:0] IIRout_p5 [3:0]; // iirout_y(8n-83) +wire signed [temp_var_width-1:0] IIRout_p6 [3:0]; // iirout_y(8n-98) +wire signed [temp_var_width-1:0] IIRout_p7 [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_p8 [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_p9 [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_pa [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_pb [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_pc [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_pd [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_pe [3:0]; // iirout_y(8n-113) +wire signed [temp_var_width-1:0] IIRout_pf [3:0]; // iirout_y(8n-113) wire signed [temp_var_width+2:0] sum_IIRout_p0; wire signed [temp_var_width+2:0] sum_IIRout_p1; wire signed [temp_var_width+2:0] sum_IIRout_p2; @@ -115,14 +247,30 @@ wire signed [temp_var_width+2:0] sum_IIRout_p4; wire signed [temp_var_width+2:0] sum_IIRout_p5; wire signed [temp_var_width+2:0] sum_IIRout_p6; wire signed [temp_var_width+2:0] sum_IIRout_p7; -reg signed [15:0] din_p0_r [16:0]; -reg signed [15:0] din_p1_r [16:0]; -reg signed [15:0] din_p2_r [16:0]; -reg signed [15:0] din_p3_r [16:0]; -reg signed [15:0] din_p4_r [16:0]; -reg signed [15:0] din_p5_r [16:0]; -reg signed [15:0] din_p6_r [16:0]; -reg signed [15:0] din_p7_r [16:0]; +wire signed [temp_var_width+2:0] sum_IIRout_p8; +wire signed [temp_var_width+2:0] sum_IIRout_p9; +wire signed [temp_var_width+2:0] sum_IIRout_pa; +wire signed [temp_var_width+2:0] sum_IIRout_pb; +wire signed [temp_var_width+2:0] sum_IIRout_pc; +wire signed [temp_var_width+2:0] sum_IIRout_pd; +wire signed [temp_var_width+2:0] sum_IIRout_pe; +wire signed [temp_var_width+2:0] sum_IIRout_pf; +reg signed [15:0] din_p0_r [32:0]; +reg signed [15:0] din_p1_r [32:0]; +reg signed [15:0] din_p2_r [32:0]; +reg signed [15:0] din_p3_r [32:0]; +reg signed [15:0] din_p4_r [32:0]; +reg signed [15:0] din_p5_r [32:0]; +reg signed [15:0] din_p6_r [32:0]; +reg signed [15:0] din_p7_r [32:0]; +reg signed [15:0] din_p8_r [32:0]; +reg signed [15:0] din_p9_r [32:0]; +reg signed [15:0] din_pa_r [32:0]; +reg signed [15:0] din_pb_r [32:0]; +reg signed [15:0] din_pc_r [32:0]; +reg signed [15:0] din_pd_r [32:0]; +reg signed [15:0] din_pe_r [32:0]; +reg signed [15:0] din_pf_r [32:0]; reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7) reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22) reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37) @@ -130,13 +278,29 @@ reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53) reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67) reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82) reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97) -reg signed [temp_var_width+2:0] sum_IIRout_p0_r [12:0]; -reg signed [temp_var_width+2:0] sum_IIRout_p1_r [11:0]; -reg signed [temp_var_width+2:0] sum_IIRout_p2_r [9 :0]; -reg signed [temp_var_width+2:0] sum_IIRout_p3_r [7 :0]; -reg signed [temp_var_width+2:0] sum_IIRout_p4_r [5 :0]; -reg signed [temp_var_width+2:0] sum_IIRout_p5_r [3 :0]; -reg signed [temp_var_width+2:0] sum_IIRout_p6_r [1 :0]; +reg signed [15:0] IIRin_p7_r [15:0]; // iirin_x(8n-97) +reg signed [15:0] IIRin_p8_r [17:0]; // iirin_x(8n-97) +reg signed [15:0] IIRin_p9_r [19:0]; // iirin_x(8n-97) +reg signed [15:0] IIRin_pa_r [21:0]; // iirin_x(8n-97) +reg signed [15:0] IIRin_pb_r [23:0]; // iirin_x(8n-97) +reg signed [15:0] IIRin_pc_r [25:0]; // iirin_x(8n-97) +reg signed [15:0] IIRin_pd_r [27:0]; // iirin_x(8n-97) +reg signed [15:0] IIRin_pe_r [29:0]; // iirin_x(8n-97) +reg signed [temp_var_width+2:0] sum_IIRout_p0_r [28:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p1_r [27:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p2_r [25:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p3_r [23:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p4_r [21:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p5_r [19:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p6_r [17:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p7_r [15:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p8_r [13:0]; +reg signed [temp_var_width+2:0] sum_IIRout_p9_r [11:0]; +reg signed [temp_var_width+2:0] sum_IIRout_pa_r [ 9:0]; +reg signed [temp_var_width+2:0] sum_IIRout_pb_r [ 7:0]; +reg signed [temp_var_width+2:0] sum_IIRout_pc_r [ 5:0]; +reg signed [temp_var_width+2:0] sum_IIRout_pd_r [ 3:0]; +reg signed [temp_var_width+2:0] sum_IIRout_pe_r [ 1:0]; wire signed [temp_var_width+2:0] dout_p0_r0; wire signed [temp_var_width+2:0] dout_p1_r0; wire signed [temp_var_width+2:0] dout_p2_r0; @@ -145,34 +309,54 @@ wire signed [temp_var_width+2:0] dout_p4_r0; wire signed [temp_var_width+2:0] dout_p5_r0; wire signed [temp_var_width+2:0] dout_p6_r0; wire signed [temp_var_width+2:0] dout_p7_r0; +wire signed [temp_var_width+2:0] dout_p8_r0; +wire signed [temp_var_width+2:0] dout_p9_r0; +wire signed [temp_var_width+2:0] dout_pa_r0; +wire signed [temp_var_width+2:0] dout_pb_r0; +wire signed [temp_var_width+2:0] dout_pc_r0; +wire signed [temp_var_width+2:0] dout_pd_r0; +wire signed [temp_var_width+2:0] dout_pe_r0; +wire signed [temp_var_width+2:0] dout_pf_r0; wire vldo_diff; -diff_p inst_diff_p ( - .rstn (rstn), - .clk (clk ), - .en (en ), - .vldi (vldi), - .din0 (din0), - .din1 (din1), - .din2 (din2), - .din3 (din3), - .vldo (vldo_diff), - .dout_p0 (din_p0), - .dout_p1 (din_p1), - .dout_p2 (din_p2), - .dout_p3 (din_p3), - .dout_p4 (din_p4), - .dout_p5 (din_p5), - .dout_p6 (din_p6), - .dout_p7 (din_p7), - .diff_p0 (IIRin_p0), - .diff_p1 (IIRin_p1), - .diff_p2 (IIRin_p2), - .diff_p3 (IIRin_p3), - .diff_p4 (IIRin_p4), - .diff_p5 (IIRin_p5), - .diff_p6 (IIRin_p6), - .diff_p7 (IIRin_p7) +diff_p u_diff_p( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .vldi ( vldi ), + .din0 ( din0 ), + .din1 ( din1 ), + .din2 ( din2 ), + .din3 ( din3 ), + .din4 ( din4 ), + .din5 ( din5 ), + .din6 ( din6 ), + .din7 ( din7 ), + .din8 ( din8 ), + .din9 ( din9 ), + .dina ( dina ), + .dinb ( dinb ), + .dinc ( dinc ), + .dind ( dind ), + .dine ( dine ), + .dinf ( dinf ), + .vldo ( vldo_diff ), + .diff_p0 ( IIRin_p0 ), + .diff_p1 ( IIRin_p1 ), + .diff_p2 ( IIRin_p2 ), + .diff_p3 ( IIRin_p3 ), + .diff_p4 ( IIRin_p4 ), + .diff_p5 ( IIRin_p5 ), + .diff_p6 ( IIRin_p6 ), + .diff_p7 ( IIRin_p7 ), + .diff_p8 ( IIRin_p8 ), + .diff_p9 ( IIRin_p9 ), + .diff_pa ( IIRin_pa ), + .diff_pb ( IIRin_pb ), + .diff_pc ( IIRin_pc ), + .diff_pd ( IIRin_pd ), + .diff_pe ( IIRin_pe ), + .diff_pf ( IIRin_pf ) ); integer i; @@ -187,18 +371,34 @@ always @(posedge clk or negedge rstn) begin din_p5_r[i] <= 'h0; din_p6_r[i] <= 'h0; din_p7_r[i] <= 'h0; + din_p8_r[i] <= 'h0; + din_p9_r[i] <= 'h0; + din_pa_r[i] <= 'h0; + din_pb_r[i] <= 'h0; + din_pc_r[i] <= 'h0; + din_pd_r[i] <= 'h0; + din_pe_r[i] <= 'h0; + din_pf_r[i] <= 'h0; end end else if (en) begin - din_p0_r[0] <= din_p0; - din_p1_r[0] <= din_p1; - din_p2_r[0] <= din_p2; - din_p3_r[0] <= din_p3; - din_p4_r[0] <= din_p4; - din_p5_r[0] <= din_p5; - din_p6_r[0] <= din_p6; - din_p7_r[0] <= din_p7; - for (i = 0; i < 16; i = i + 1) begin + din_p0_r[0] <= din0; + din_p1_r[0] <= din1; + din_p2_r[0] <= din2; + din_p3_r[0] <= din3; + din_p4_r[0] <= din4; + din_p5_r[0] <= din5; + din_p6_r[0] <= din6; + din_p7_r[0] <= din7; + din_p8_r[0] <= din8; + din_p9_r[0] <= din9; + din_pa_r[0] <= dina; + din_pb_r[0] <= dinb; + din_pc_r[0] <= dinc; + din_pd_r[0] <= dind; + din_pe_r[0] <= dine; + din_pf_r[0] <= dinf; + for (i = 0; i < 32; i = i + 1) begin din_p0_r[i+1] <= din_p0_r[i]; din_p1_r[i+1] <= din_p1_r[i]; din_p2_r[i+1] <= din_p2_r[i]; @@ -207,6 +407,14 @@ always @(posedge clk or negedge rstn) begin din_p5_r[i+1] <= din_p5_r[i]; din_p6_r[i+1] <= din_p6_r[i]; din_p7_r[i+1] <= din_p7_r[i]; + din_p8_r[i+1] <= din_p8_r[i]; + din_p9_r[i+1] <= din_p9_r[i]; + din_pa_r[i+1] <= din_pa_r[i]; + din_pb_r[i+1] <= din_pb_r[i]; + din_pc_r[i+1] <= din_pc_r[i]; + din_pd_r[i+1] <= din_pd_r[i]; + din_pe_r[i+1] <= din_pe_r[i]; + din_pf_r[i+1] <= din_pf_r[i]; end end end @@ -349,8 +557,33 @@ always @(posedge clk or negedge rstn) begin for (i = 0; i <14; i = i + 1) begin IIRin_p6_r[i] <= 'h0; end + for (i = 0; i < 16; i = i + 1) begin + IIRin_p7_r[i] <= 'h0; + end + for (i = 0; i < 18; i = i + 1) begin + IIRin_p8_r[i] <= 'h0; + end + for (i = 0; i < 20; i = i + 1) begin + IIRin_p9_r[i] <= 'h0; + end + for (i = 0; i < 22; i = i + 1) begin + IIRin_pa_r[i] <= 'h0; + end + for (i = 0; i < 24; i = i + 1) begin + IIRin_pb_r[i] <= 'h0; + end + for (i = 0; i < 26; i = i + 1) begin + IIRin_pc_r[i] <= 'h0; + end + for (i = 0; i < 28; i = i + 1) begin + IIRin_pd_r[i] <= 'h0; + end + for (i = 0; i < 30; i = i + 1) begin + IIRin_pe_r[i] <= 'h0; + end end else if (en) begin + IIRin_p0_r[0] <= IIRin_p0; IIRin_p1_r[0] <= IIRin_p1; IIRin_p2_r[0] <= IIRin_p2; @@ -358,6 +591,15 @@ always @(posedge clk or negedge rstn) begin IIRin_p4_r[0] <= IIRin_p4; IIRin_p5_r[0] <= IIRin_p5; IIRin_p6_r[0] <= IIRin_p6; + IIRin_p7_r[0] <= IIRin_p7; + IIRin_p8_r[0] <= IIRin_p8; + IIRin_p9_r[0] <= IIRin_p9; + IIRin_pa_r[0] <= IIRin_pa; + IIRin_pb_r[0] <= IIRin_pb; + IIRin_pc_r[0] <= IIRin_pc; + IIRin_pd_r[0] <= IIRin_pd; + IIRin_pe_r[0] <= IIRin_pe; + for (i = 0; i < 1; i = i + 1) begin IIRin_p0_r[i+1] <= IIRin_p0_r[i]; end @@ -379,268 +621,413 @@ always @(posedge clk or negedge rstn) begin for (i = 0; i <13; i = i + 1) begin IIRin_p6_r[i+1] <= IIRin_p6_r[i]; end + for (i = 0; i < 15; i = i + 1) begin + IIRin_p7_r[i+1] <= IIRin_p7_r[i]; + end + for (i = 0; i < 17; i = i + 1) begin + IIRin_p8_r[i+1] <= IIRin_p8_r[i]; + end + for (i = 0; i < 19; i = i + 1) begin + IIRin_p9_r[i+1] <= IIRin_p9_r[i]; + end + for (i = 0; i < 21; i = i + 1) begin + IIRin_pa_r[i+1] <= IIRin_pa_r[i]; + end + for (i = 0; i < 23; i = i + 1) begin + IIRin_pb_r[i+1] <= IIRin_pb_r[i]; + end + for (i = 0; i < 25; i = i + 1) begin + IIRin_pc_r[i+1] <= IIRin_pc_r[i]; + end + for (i = 0; i < 27; i = i + 1) begin + IIRin_pd_r[i+1] <= IIRin_pd_r[i]; + end + for (i = 0; i < 29; i = i + 1) begin + IIRin_pe_r[i+1] <= IIRin_pe_r[i]; + end end end +IIR_top#( + .data_out_width ( temp_var_width ) +)u_IIR_top_0( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .IIRin_p0 ( IIRin_p0 ), + .IIRin_p1 ( IIRin_p1 ), + .IIRin_p2 ( IIRin_p2 ), + .IIRin_p3 ( IIRin_p3 ), + .IIRin_p4 ( IIRin_p4 ), + .IIRin_p5 ( IIRin_p5 ), + .IIRin_p6 ( IIRin_p6 ), + .IIRin_p7 ( IIRin_p7 ), + .IIRin_p8 ( IIRin_p8 ), + .IIRin_p9 ( IIRin_p9 ), + .IIRin_pa ( IIRin_pa ), + .IIRin_pb ( IIRin_pb ), + .IIRin_pc ( IIRin_pc ), + .IIRin_pd ( IIRin_pd ), + .IIRin_pe ( IIRin_pe ), + .IIRin_pf ( IIRin_pf ), + .IIRin_p0_r2 ( IIRin_p0_r[1] ), + .IIRin_p1_r4 ( IIRin_p1_r[3] ), + .IIRin_p2_r6 ( IIRin_p2_r[5] ), + .IIRin_p3_r8 ( IIRin_p3_r[7] ), + .IIRin_p4_r10 ( IIRin_p4_r[9] ), + .IIRin_p5_r12 ( IIRin_p5_r[11] ), + .IIRin_p6_r14 ( IIRin_p6_r[13] ), + .IIRin_p7_r16 ( IIRin_p7_r[15] ), + .IIRin_p8_r18 ( IIRin_p8_r[17] ), + .IIRin_p9_r20 ( IIRin_p9_r[19] ), + .IIRin_pa_r22 ( IIRin_pa_r[21] ), + .IIRin_pb_r24 ( IIRin_pb_r[23] ), + .IIRin_pc_r26 ( IIRin_pc_r[25] ), + .IIRin_pd_r28 ( IIRin_pd_r[27] ), + .IIRin_pe_r30 ( IIRin_pe_r[29] ), + .a_re ( a_re0 ), + .b_re ( b_re0 ), + .ab_re ( ab_re0 ), + .abb_re ( abb_re0 ), + .ab_pow3_re ( ab_pow3_re0 ), + .ab_pow4_re ( ab_pow4_re0 ), + .ab_pow5_re ( ab_pow5_re0 ), + .ab_pow6_re ( ab_pow6_re0 ), + .ab_pow7_re ( ab_pow7_re0 ), + .ab_pow8_re ( ab_pow8_re0 ), + .ab_pow9_re ( ab_pow9_re0 ), + .ab_powa_re ( ab_powa_re0 ), + .ab_powb_re ( ab_powb_re0 ), + .ab_powc_re ( ab_powc_re0 ), + .ab_powd_re ( ab_powd_re0 ), + .ab_powe_re ( ab_powe_re0 ), + .ab_powf_re ( ab_powf_re0 ), + .b_pow16_re ( b_pow16_re0 ), + .a_im ( a_im0 ), + .b_im ( b_im0 ), + .ab_im ( ab_im0 ), + .abb_im ( abb_im0 ), + .ab_pow3_im ( ab_pow3_im0 ), + .ab_pow4_im ( ab_pow4_im0 ), + .ab_pow5_im ( ab_pow5_im0 ), + .ab_pow6_im ( ab_pow6_im0 ), + .ab_pow7_im ( ab_pow7_im0 ), + .ab_pow8_im ( ab_pow8_im0 ), + .ab_pow9_im ( ab_pow9_im0 ), + .ab_powa_im ( ab_powa_im0 ), + .ab_powb_im ( ab_powb_im0 ), + .ab_powc_im ( ab_powc_im0 ), + .ab_powd_im ( ab_powd_im0 ), + .ab_powe_im ( ab_powe_im0 ), + .ab_powf_im ( ab_powf_im0 ), + .b_pow16_im ( b_pow16_im0 ), + .IIRout_p0 ( IIRout_p0[0] ), + .IIRout_p1 ( IIRout_p1[0] ), + .IIRout_p2 ( IIRout_p2[0] ), + .IIRout_p3 ( IIRout_p3[0] ), + .IIRout_p4 ( IIRout_p4[0] ), + .IIRout_p5 ( IIRout_p5[0] ), + .IIRout_p6 ( IIRout_p6[0] ), + .IIRout_p7 ( IIRout_p7[0] ), + .IIRout_p8 ( IIRout_p8[0] ), + .IIRout_p9 ( IIRout_p9[0] ), + .IIRout_pa ( IIRout_pa[0] ), + .IIRout_pb ( IIRout_pb[0] ), + .IIRout_pc ( IIRout_pc[0] ), + .IIRout_pd ( IIRout_pd[0] ), + .IIRout_pe ( IIRout_pe[0] ), + .IIRout_pf ( IIRout_pf[0] ) +); +IIR_top#( + .data_out_width ( temp_var_width ) +) u_IIR_top_1 ( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .IIRin_p0 ( IIRin_p0 ), + .IIRin_p1 ( IIRin_p1 ), + .IIRin_p2 ( IIRin_p2 ), + .IIRin_p3 ( IIRin_p3 ), + .IIRin_p4 ( IIRin_p4 ), + .IIRin_p5 ( IIRin_p5 ), + .IIRin_p6 ( IIRin_p6 ), + .IIRin_p7 ( IIRin_p7 ), + .IIRin_p8 ( IIRin_p8 ), + .IIRin_p9 ( IIRin_p9 ), + .IIRin_pa ( IIRin_pa ), + .IIRin_pb ( IIRin_pb ), + .IIRin_pc ( IIRin_pc ), + .IIRin_pd ( IIRin_pd ), + .IIRin_pe ( IIRin_pe ), + .IIRin_pf ( IIRin_pf ), + .IIRin_p0_r2 ( IIRin_p0_r[1] ), + .IIRin_p1_r4 ( IIRin_p1_r[3] ), + .IIRin_p2_r6 ( IIRin_p2_r[5] ), + .IIRin_p3_r8 ( IIRin_p3_r[7] ), + .IIRin_p4_r10 ( IIRin_p4_r[9] ), + .IIRin_p5_r12 ( IIRin_p5_r[11] ), + .IIRin_p6_r14 ( IIRin_p6_r[13] ), + .IIRin_p7_r16 ( IIRin_p7_r[15] ), + .IIRin_p8_r18 ( IIRin_p8_r[17] ), + .IIRin_p9_r20 ( IIRin_p9_r[19] ), + .IIRin_pa_r22 ( IIRin_pa_r[21] ), + .IIRin_pb_r24 ( IIRin_pb_r[23] ), + .IIRin_pc_r26 ( IIRin_pc_r[25] ), + .IIRin_pd_r28 ( IIRin_pd_r[27] ), + .IIRin_pe_r30 ( IIRin_pe_r[29] ), + .a_re ( a_re1 ), + .b_re ( b_re1 ), + .ab_re ( ab_re1 ), + .abb_re ( abb_re1 ), + .ab_pow3_re ( ab_pow3_re1 ), + .ab_pow4_re ( ab_pow4_re1 ), + .ab_pow5_re ( ab_pow5_re1 ), + .ab_pow6_re ( ab_pow6_re1 ), + .ab_pow7_re ( ab_pow7_re1 ), + .ab_pow8_re ( ab_pow8_re1 ), + .ab_pow9_re ( ab_pow9_re1 ), + .ab_powa_re ( ab_powa_re1 ), + .ab_powb_re ( ab_powb_re1 ), + .ab_powc_re ( ab_powc_re1 ), + .ab_powd_re ( ab_powd_re1 ), + .ab_powe_re ( ab_powe_re1 ), + .ab_powf_re ( ab_powf_re1 ), + .b_pow16_re ( b_pow16_re1 ), + .a_im ( a_im1 ), + .b_im ( b_im1 ), + .ab_im ( ab_im1 ), + .abb_im ( abb_im1 ), + .ab_pow3_im ( ab_pow3_im1 ), + .ab_pow4_im ( ab_pow4_im1 ), + .ab_pow5_im ( ab_pow5_im1 ), + .ab_pow6_im ( ab_pow6_im1 ), + .ab_pow7_im ( ab_pow7_im1 ), + .ab_pow8_im ( ab_pow8_im1 ), + .ab_pow9_im ( ab_pow9_im1 ), + .ab_powa_im ( ab_powa_im1 ), + .ab_powb_im ( ab_powb_im1 ), + .ab_powc_im ( ab_powc_im1 ), + .ab_powd_im ( ab_powd_im1 ), + .ab_powe_im ( ab_powe_im1 ), + .ab_powf_im ( ab_powf_im1 ), + .b_pow16_im ( b_pow16_im1 ), + .IIRout_p0 ( IIRout_p0[1] ), + .IIRout_p1 ( IIRout_p1[1] ), + .IIRout_p2 ( IIRout_p2[1] ), + .IIRout_p3 ( IIRout_p3[1] ), + .IIRout_p4 ( IIRout_p4[1] ), + .IIRout_p5 ( IIRout_p5[1] ), + .IIRout_p6 ( IIRout_p6[1] ), + .IIRout_p7 ( IIRout_p7[1] ), + .IIRout_p8 ( IIRout_p8[1] ), + .IIRout_p9 ( IIRout_p9[1] ), + .IIRout_pa ( IIRout_pa[1] ), + .IIRout_pb ( IIRout_pb[1] ), + .IIRout_pc ( IIRout_pc[1] ), + .IIRout_pd ( IIRout_pd[1] ), + .IIRout_pe ( IIRout_pe[1] ), + .IIRout_pf ( IIRout_pf[1] ) +); +IIR_top#( + .data_out_width ( temp_var_width ) +) u_IIR_top_2 ( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .IIRin_p0 ( IIRin_p0 ), + .IIRin_p1 ( IIRin_p1 ), + .IIRin_p2 ( IIRin_p2 ), + .IIRin_p3 ( IIRin_p3 ), + .IIRin_p4 ( IIRin_p4 ), + .IIRin_p5 ( IIRin_p5 ), + .IIRin_p6 ( IIRin_p6 ), + .IIRin_p7 ( IIRin_p7 ), + .IIRin_p8 ( IIRin_p8 ), + .IIRin_p9 ( IIRin_p9 ), + .IIRin_pa ( IIRin_pa ), + .IIRin_pb ( IIRin_pb ), + .IIRin_pc ( IIRin_pc ), + .IIRin_pd ( IIRin_pd ), + .IIRin_pe ( IIRin_pe ), + .IIRin_pf ( IIRin_pf ), + .IIRin_p0_r2 ( IIRin_p0_r[1] ), + .IIRin_p1_r4 ( IIRin_p1_r[3] ), + .IIRin_p2_r6 ( IIRin_p2_r[5] ), + .IIRin_p3_r8 ( IIRin_p3_r[7] ), + .IIRin_p4_r10 ( IIRin_p4_r[9] ), + .IIRin_p5_r12 ( IIRin_p5_r[11] ), + .IIRin_p6_r14 ( IIRin_p6_r[13] ), + .IIRin_p7_r16 ( IIRin_p7_r[15] ), + .IIRin_p8_r18 ( IIRin_p8_r[17] ), + .IIRin_p9_r20 ( IIRin_p9_r[19] ), + .IIRin_pa_r22 ( IIRin_pa_r[21] ), + .IIRin_pb_r24 ( IIRin_pb_r[23] ), + .IIRin_pc_r26 ( IIRin_pc_r[25] ), + .IIRin_pd_r28 ( IIRin_pd_r[27] ), + .IIRin_pe_r30 ( IIRin_pe_r[29] ), + .a_re ( a_re2 ), + .b_re ( b_re2 ), + .ab_re ( ab_re2 ), + .abb_re ( abb_re2 ), + .ab_pow3_re ( ab_pow3_re2 ), + .ab_pow4_re ( ab_pow4_re2 ), + .ab_pow5_re ( ab_pow5_re2 ), + .ab_pow6_re ( ab_pow6_re2 ), + .ab_pow7_re ( ab_pow7_re2 ), + .ab_pow8_re ( ab_pow8_re2 ), + .ab_pow9_re ( ab_pow9_re2 ), + .ab_powa_re ( ab_powa_re2 ), + .ab_powb_re ( ab_powb_re2 ), + .ab_powc_re ( ab_powc_re2 ), + .ab_powd_re ( ab_powd_re2 ), + .ab_powe_re ( ab_powe_re2 ), + .ab_powf_re ( ab_powf_re2 ), + .b_pow16_re ( b_pow16_re2 ), + .a_im ( a_im2 ), + .b_im ( b_im2 ), + .ab_im ( ab_im2 ), + .abb_im ( abb_im2 ), + .ab_pow3_im ( ab_pow3_im2 ), + .ab_pow4_im ( ab_pow4_im2 ), + .ab_pow5_im ( ab_pow5_im2 ), + .ab_pow6_im ( ab_pow6_im2 ), + .ab_pow7_im ( ab_pow7_im2 ), + .ab_pow8_im ( ab_pow8_im2 ), + .ab_pow9_im ( ab_pow9_im2 ), + .ab_powa_im ( ab_powa_im2 ), + .ab_powb_im ( ab_powb_im2 ), + .ab_powc_im ( ab_powc_im2 ), + .ab_powd_im ( ab_powd_im2 ), + .ab_powe_im ( ab_powe_im2 ), + .ab_powf_im ( ab_powf_im2 ), + .b_pow16_im ( b_pow16_im2 ), + .IIRout_p0 ( IIRout_p0[2] ), + .IIRout_p1 ( IIRout_p1[2] ), + .IIRout_p2 ( IIRout_p2[2] ), + .IIRout_p3 ( IIRout_p3[2] ), + .IIRout_p4 ( IIRout_p4[2] ), + .IIRout_p5 ( IIRout_p5[2] ), + .IIRout_p6 ( IIRout_p6[2] ), + .IIRout_p7 ( IIRout_p7[2] ), + .IIRout_p8 ( IIRout_p8[2] ), + .IIRout_p9 ( IIRout_p9[2] ), + .IIRout_pa ( IIRout_pa[2] ), + .IIRout_pb ( IIRout_pb[2] ), + .IIRout_pc ( IIRout_pc[2] ), + .IIRout_pd ( IIRout_pd[2] ), + .IIRout_pe ( IIRout_pe[2] ), + .IIRout_pf ( IIRout_pf[2] ) +); +IIR_top#( + .data_out_width ( temp_var_width ) +) u_IIR_top_3 ( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .IIRin_p0 ( IIRin_p0 ), + .IIRin_p1 ( IIRin_p1 ), + .IIRin_p2 ( IIRin_p2 ), + .IIRin_p3 ( IIRin_p3 ), + .IIRin_p4 ( IIRin_p4 ), + .IIRin_p5 ( IIRin_p5 ), + .IIRin_p6 ( IIRin_p6 ), + .IIRin_p7 ( IIRin_p7 ), + .IIRin_p8 ( IIRin_p8 ), + .IIRin_p9 ( IIRin_p9 ), + .IIRin_pa ( IIRin_pa ), + .IIRin_pb ( IIRin_pb ), + .IIRin_pc ( IIRin_pc ), + .IIRin_pd ( IIRin_pd ), + .IIRin_pe ( IIRin_pe ), + .IIRin_pf ( IIRin_pf ), + .IIRin_p0_r2 ( IIRin_p0_r[1] ), + .IIRin_p1_r4 ( IIRin_p1_r[3] ), + .IIRin_p2_r6 ( IIRin_p2_r[5] ), + .IIRin_p3_r8 ( IIRin_p3_r[7] ), + .IIRin_p4_r10 ( IIRin_p4_r[9] ), + .IIRin_p5_r12 ( IIRin_p5_r[11] ), + .IIRin_p6_r14 ( IIRin_p6_r[13] ), + .IIRin_p7_r16 ( IIRin_p7_r[15] ), + .IIRin_p8_r18 ( IIRin_p8_r[17] ), + .IIRin_p9_r20 ( IIRin_p9_r[19] ), + .IIRin_pa_r22 ( IIRin_pa_r[21] ), + .IIRin_pb_r24 ( IIRin_pb_r[23] ), + .IIRin_pc_r26 ( IIRin_pc_r[25] ), + .IIRin_pd_r28 ( IIRin_pd_r[27] ), + .IIRin_pe_r30 ( IIRin_pe_r[29] ), + .a_re ( a_re3 ), + .b_re ( b_re3 ), + .ab_re ( ab_re3 ), + .abb_re ( abb_re3 ), + .ab_pow3_re ( ab_pow3_re3 ), + .ab_pow4_re ( ab_pow4_re3 ), + .ab_pow5_re ( ab_pow5_re3 ), + .ab_pow6_re ( ab_pow6_re3 ), + .ab_pow7_re ( ab_pow7_re3 ), + .ab_pow8_re ( ab_pow8_re3 ), + .ab_pow9_re ( ab_pow9_re3 ), + .ab_powa_re ( ab_powa_re3 ), + .ab_powb_re ( ab_powb_re3 ), + .ab_powc_re ( ab_powc_re3 ), + .ab_powd_re ( ab_powd_re3 ), + .ab_powe_re ( ab_powe_re3 ), + .ab_powf_re ( ab_powf_re3 ), + .b_pow16_re ( b_pow16_re3 ), + .a_im ( a_im3 ), + .b_im ( b_im3 ), + .ab_im ( ab_im3 ), + .abb_im ( abb_im3 ), + .ab_pow3_im ( ab_pow3_im3 ), + .ab_pow4_im ( ab_pow4_im3 ), + .ab_pow5_im ( ab_pow5_im3 ), + .ab_pow6_im ( ab_pow6_im3 ), + .ab_pow7_im ( ab_pow7_im3 ), + .ab_pow8_im ( ab_pow8_im3 ), + .ab_pow9_im ( ab_pow9_im3 ), + .ab_powa_im ( ab_powa_im3 ), + .ab_powb_im ( ab_powb_im3 ), + .ab_powc_im ( ab_powc_im3 ), + .ab_powd_im ( ab_powd_im3 ), + .ab_powe_im ( ab_powe_im3 ), + .ab_powf_im ( ab_powf_im3 ), + .b_pow16_im ( b_pow16_im3 ), + .IIRout_p0 ( IIRout_p0[3] ), + .IIRout_p1 ( IIRout_p1[3] ), + .IIRout_p2 ( IIRout_p2[3] ), + .IIRout_p3 ( IIRout_p3[3] ), + .IIRout_p4 ( IIRout_p4[3] ), + .IIRout_p5 ( IIRout_p5[3] ), + .IIRout_p6 ( IIRout_p6[3] ), + .IIRout_p7 ( IIRout_p7[3] ), + .IIRout_p8 ( IIRout_p8[3] ), + .IIRout_p9 ( IIRout_p9[3] ), + .IIRout_pa ( IIRout_pa[3] ), + .IIRout_pb ( IIRout_pb[3] ), + .IIRout_pc ( IIRout_pc[3] ), + .IIRout_pd ( IIRout_pd[3] ), + .IIRout_pe ( IIRout_pe[3] ), + .IIRout_pf ( IIRout_pf[3] ) +); -IIR_top #( - .data_out_width (temp_var_width ) -) inst_iir_top_0 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1] ), - .IIRin_p1_r4 (IIRin_p1_r[3] ), - .IIRin_p2_r6 (IIRin_p2_r[5] ), - .IIRin_p3_r8 (IIRin_p3_r[7] ), - .IIRin_p4_r10 (IIRin_p4_r[9] ), - .IIRin_p5_r12 (IIRin_p5_r[11] ), - .IIRin_p6_r14 (IIRin_p6_r[13] ), - .a_re (a_re0 ), - .b_re (b_re0 ), - .ab_re (ab_re0 ), - .abb_re (abb_re0 ), - .ab_pow3_re (ab_pow3_re0 ), - .ab_pow4_re (ab_pow4_re0 ), - .ab_pow5_re (ab_pow5_re0 ), - .ab_pow6_re (ab_pow6_re0 ), - .ab_pow7_re (ab_pow7_re0 ), - .b_pow8_re (b_pow8_re0 ), - .IIRout_p0 (IIRout_p0[0] ), - .IIRout_p1 (IIRout_p1[0] ), - .IIRout_p2 (IIRout_p2[0] ), - .IIRout_p3 (IIRout_p3[0] ), - .IIRout_p4 (IIRout_p4[0] ), - .IIRout_p5 (IIRout_p5[0] ), - .IIRout_p6 (IIRout_p6[0] ), - .IIRout_p7 (IIRout_p7[0] ) - ); - -IIR_top #( - .data_out_width (temp_var_width ) -) inst_iir_top_1 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1] ), - .IIRin_p1_r4 (IIRin_p1_r[3] ), - .IIRin_p2_r6 (IIRin_p2_r[5] ), - .IIRin_p3_r8 (IIRin_p3_r[7] ), - .IIRin_p4_r10 (IIRin_p4_r[9] ), - .IIRin_p5_r12 (IIRin_p5_r[11] ), - .IIRin_p6_r14 (IIRin_p6_r[13] ), - .a_re (a_re1 ), - .b_re (b_re1 ), - .ab_re (ab_re1 ), - .abb_re (abb_re1 ), - .ab_pow3_re (ab_pow3_re1 ), - .ab_pow4_re (ab_pow4_re1 ), - .ab_pow5_re (ab_pow5_re1 ), - .ab_pow6_re (ab_pow6_re1 ), - .ab_pow7_re (ab_pow7_re1 ), - .b_pow8_re (b_pow8_re1 ), - .IIRout_p0 (IIRout_p0[1] ), - .IIRout_p1 (IIRout_p1[1] ), - .IIRout_p2 (IIRout_p2[1] ), - .IIRout_p3 (IIRout_p3[1] ), - .IIRout_p4 (IIRout_p4[1] ), - .IIRout_p5 (IIRout_p5[1] ), - .IIRout_p6 (IIRout_p6[1] ), - .IIRout_p7 (IIRout_p7[1] ) - ); - -IIR_top #( - .data_out_width (temp_var_width ) -) inst_iir_top_2 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1] ), - .IIRin_p1_r4 (IIRin_p1_r[3] ), - .IIRin_p2_r6 (IIRin_p2_r[5] ), - .IIRin_p3_r8 (IIRin_p3_r[7] ), - .IIRin_p4_r10 (IIRin_p4_r[9] ), - .IIRin_p5_r12 (IIRin_p5_r[11] ), - .IIRin_p6_r14 (IIRin_p6_r[13] ), - .a_re (a_re2 ), - .b_re (b_re2 ), - .ab_re (ab_re2 ), - .abb_re (abb_re2 ), - .ab_pow3_re (ab_pow3_re2 ), - .ab_pow4_re (ab_pow4_re2 ), - .ab_pow5_re (ab_pow5_re2 ), - .ab_pow6_re (ab_pow6_re2 ), - .ab_pow7_re (ab_pow7_re2 ), - .b_pow8_re (b_pow8_re2 ), - .IIRout_p0 (IIRout_p0[2] ), - .IIRout_p1 (IIRout_p1[2] ), - .IIRout_p2 (IIRout_p2[2] ), - .IIRout_p3 (IIRout_p3[2] ), - .IIRout_p4 (IIRout_p4[2] ), - .IIRout_p5 (IIRout_p5[2] ), - .IIRout_p6 (IIRout_p6[2] ), - .IIRout_p7 (IIRout_p7[2] ) - ); - -IIR_top #( - .data_out_width (temp_var_width ) -) inst_iir_top_3 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1] ), - .IIRin_p1_r4 (IIRin_p1_r[3] ), - .IIRin_p2_r6 (IIRin_p2_r[5] ), - .IIRin_p3_r8 (IIRin_p3_r[7] ), - .IIRin_p4_r10 (IIRin_p4_r[9] ), - .IIRin_p5_r12 (IIRin_p5_r[11] ), - .IIRin_p6_r14 (IIRin_p6_r[13] ), - .a_re (a_re3 ), - .b_re (b_re3 ), - .ab_re (ab_re3 ), - .abb_re (abb_re3 ), - .ab_pow3_re (ab_pow3_re3 ), - .ab_pow4_re (ab_pow4_re3 ), - .ab_pow5_re (ab_pow5_re3 ), - .ab_pow6_re (ab_pow6_re3 ), - .ab_pow7_re (ab_pow7_re3 ), - .b_pow8_re (b_pow8_re3 ), - .IIRout_p0 (IIRout_p0[3] ), - .IIRout_p1 (IIRout_p1[3] ), - .IIRout_p2 (IIRout_p2[3] ), - .IIRout_p3 (IIRout_p3[3] ), - .IIRout_p4 (IIRout_p4[3] ), - .IIRout_p5 (IIRout_p5[3] ), - .IIRout_p6 (IIRout_p6[3] ), - .IIRout_p7 (IIRout_p7[3] ) - ); - -IIR_top #( - .data_out_width (temp_var_width ) -) inst_iir_top_4 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1] ), - .IIRin_p1_r4 (IIRin_p1_r[3] ), - .IIRin_p2_r6 (IIRin_p2_r[5] ), - .IIRin_p3_r8 (IIRin_p3_r[7] ), - .IIRin_p4_r10 (IIRin_p4_r[9] ), - .IIRin_p5_r12 (IIRin_p5_r[11] ), - .IIRin_p6_r14 (IIRin_p6_r[13] ), - .a_re (a_re4 ), - .b_re (b_re4 ), - .ab_re (ab_re4 ), - .abb_re (abb_re4 ), - .ab_pow3_re (ab_pow3_re4 ), - .ab_pow4_re (ab_pow4_re4 ), - .ab_pow5_re (ab_pow5_re4 ), - .ab_pow6_re (ab_pow6_re4 ), - .ab_pow7_re (ab_pow7_re4 ), - .b_pow8_re (b_pow8_re4 ), - .IIRout_p0 (IIRout_p0[4] ), - .IIRout_p1 (IIRout_p1[4] ), - .IIRout_p2 (IIRout_p2[4] ), - .IIRout_p3 (IIRout_p3[4] ), - .IIRout_p4 (IIRout_p4[4] ), - .IIRout_p5 (IIRout_p5[4] ), - .IIRout_p6 (IIRout_p6[4] ), - .IIRout_p7 (IIRout_p7[4] ) - ); - -IIR_top #( - .data_out_width (temp_var_width ) -) inst_iir_top_5 ( - .clk (clk ), - .rstn (rstn ), - .en (en ), - .IIRin_p0 (IIRin_p0 ), - .IIRin_p1 (IIRin_p1 ), - .IIRin_p2 (IIRin_p2 ), - .IIRin_p3 (IIRin_p3 ), - .IIRin_p4 (IIRin_p4 ), - .IIRin_p5 (IIRin_p5 ), - .IIRin_p6 (IIRin_p6 ), - .IIRin_p7 (IIRin_p7 ), - .IIRin_p0_r2 (IIRin_p0_r[1] ), - .IIRin_p1_r4 (IIRin_p1_r[3] ), - .IIRin_p2_r6 (IIRin_p2_r[5] ), - .IIRin_p3_r8 (IIRin_p3_r[7] ), - .IIRin_p4_r10 (IIRin_p4_r[9] ), - .IIRin_p5_r12 (IIRin_p5_r[11] ), - .IIRin_p6_r14 (IIRin_p6_r[13] ), - .a_re (a_re5 ), - .b_re (b_re5 ), - .ab_re (ab_re5 ), - .abb_re (abb_re5 ), - .ab_pow3_re (ab_pow3_re5 ), - .ab_pow4_re (ab_pow4_re5 ), - .ab_pow5_re (ab_pow5_re5 ), - .ab_pow6_re (ab_pow6_re5 ), - .ab_pow7_re (ab_pow7_re5 ), - .b_pow8_re (b_pow8_re5 ), - .IIRout_p0 (IIRout_p0[5] ), - .IIRout_p1 (IIRout_p1[5] ), - .IIRout_p2 (IIRout_p2[5] ), - .IIRout_p3 (IIRout_p3[5] ), - .IIRout_p4 (IIRout_p4[5] ), - .IIRout_p5 (IIRout_p5[5] ), - .IIRout_p6 (IIRout_p6[5] ), - .IIRout_p7 (IIRout_p7[5] ) - ); - -assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] +IIRout_p0[2] +IIRout_p0[3] +IIRout_p0[4] +IIRout_p0[5]; -assign sum_IIRout_p1 = IIRout_p1[0] + IIRout_p1[1] +IIRout_p1[2] +IIRout_p1[3] +IIRout_p1[4] +IIRout_p1[5]; -assign sum_IIRout_p2 = IIRout_p2[0] + IIRout_p2[1] +IIRout_p2[2] +IIRout_p2[3] +IIRout_p2[4] +IIRout_p2[5]; -assign sum_IIRout_p3 = IIRout_p3[0] + IIRout_p3[1] +IIRout_p3[2] +IIRout_p3[3] +IIRout_p3[4] +IIRout_p3[5]; -assign sum_IIRout_p4 = IIRout_p4[0] + IIRout_p4[1] +IIRout_p4[2] +IIRout_p4[3] +IIRout_p4[4] +IIRout_p4[5]; -assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] +IIRout_p5[2] +IIRout_p5[3] +IIRout_p5[4] +IIRout_p5[5]; -assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] +IIRout_p6[2] +IIRout_p6[3] +IIRout_p6[4] +IIRout_p6[5]; -assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] +IIRout_p7[2] +IIRout_p7[3] +IIRout_p7[4] +IIRout_p7[5]; - +assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] + IIRout_p0[2] + IIRout_p0[3]; +assign sum_IIRout_p1 = IIRout_p1[0] + IIRout_p1[1] + IIRout_p1[2] + IIRout_p1[3]; +assign sum_IIRout_p2 = IIRout_p2[0] + IIRout_p2[1] + IIRout_p2[2] + IIRout_p2[3]; +assign sum_IIRout_p3 = IIRout_p3[0] + IIRout_p3[1] + IIRout_p3[2] + IIRout_p3[3]; +assign sum_IIRout_p4 = IIRout_p4[0] + IIRout_p4[1] + IIRout_p4[2] + IIRout_p4[3]; +assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] + IIRout_p5[2] + IIRout_p5[3]; +assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] + IIRout_p6[2] + IIRout_p6[3]; +assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] + IIRout_p7[2] + IIRout_p7[3]; +assign sum_IIRout_p8 = IIRout_p8[0] + IIRout_p8[1] + IIRout_p8[2] + IIRout_p8[3]; +assign sum_IIRout_p9 = IIRout_p9[0] + IIRout_p9[1] + IIRout_p9[2] + IIRout_p9[3]; +assign sum_IIRout_pa = IIRout_pa[0] + IIRout_pa[1] + IIRout_pa[2] + IIRout_pa[3]; +assign sum_IIRout_pb = IIRout_pb[0] + IIRout_pb[1] + IIRout_pb[2] + IIRout_pb[3]; +assign sum_IIRout_pc = IIRout_pc[0] + IIRout_pc[1] + IIRout_pc[2] + IIRout_pc[3]; +assign sum_IIRout_pd = IIRout_pd[0] + IIRout_pd[1] + IIRout_pd[2] + IIRout_pd[3]; +assign sum_IIRout_pe = IIRout_pe[0] + IIRout_pe[1] + IIRout_pe[2] + IIRout_pe[3]; +assign sum_IIRout_pf = IIRout_pf[0] + IIRout_pf[1] + IIRout_pf[2] + IIRout_pf[3]; /*trunc #(20, 19, 3) round_u0 (clk, rstn, en, sum_IIRout_p0, sum_IIRout_p0_trunc); trunc #(20, 19, 3) round_u1 (clk, rstn, en, sum_IIRout_p1, sum_IIRout_p1_trunc); trunc #(20, 19, 3) round_u2 (clk, rstn, en, sum_IIRout_p2, sum_IIRout_p2_trunc); @@ -654,28 +1041,60 @@ trunc #(20, 19, 3) round_u7 (clk, rstn, en, sum_IIRout_p7, sum_IIRout_p7_trunc); always @(posedge clk or negedge rstn) begin if (!rstn) begin for (i = 0; i < 2; i = i + 1) begin - sum_IIRout_p6_r[i] <= 'h0; + sum_IIRout_pe_r[i] <= 'h0; end for (i = 0; i < 4; i = i + 1) begin - sum_IIRout_p5_r[i] <= 'h0; + sum_IIRout_pd_r[i] <= 'h0; end for (i = 0; i < 6; i = i + 1) begin - sum_IIRout_p4_r[i] <= 'h0; + sum_IIRout_pc_r[i] <= 'h0; end for (i = 0; i < 8; i = i + 1) begin - sum_IIRout_p3_r[i] <= 'h0; + sum_IIRout_pb_r[i] <= 'h0; end - for (i = 0; i <10; i = i + 1) begin - sum_IIRout_p2_r[i] <= 'h0; + for (i = 0; i < 10; i = i + 1) begin + sum_IIRout_pa_r[i] <= 'h0; end - for (i = 0; i <12; i = i + 1) begin - sum_IIRout_p1_r[i] <= 'h0; + for (i = 0; i < 12; i = i + 1) begin + sum_IIRout_p9_r[i] <= 'h0; end - for (i = 0; i <13; i = i + 1) begin - sum_IIRout_p0_r[i] <= 'h0; + for (i = 0; i < 14; i = i + 1) begin + sum_IIRout_p8_r[i] <= 'h0; + end + for (i = 0; i < 16; i = i + 1) begin + sum_IIRout_p7_r[i] <= 'h0; + end + for (i = 0; i < 18; i = i + 1) begin + sum_IIRout_p6_r[i] <= 'h0; + end + for (i = 0; i < 20; i = i + 1) begin + sum_IIRout_p5_r[i] <= 'h0; + end + for (i = 0; i < 22; i = i + 1) begin + sum_IIRout_p4_r[i] <= 'h0; + end + for (i = 0; i < 24; i = i + 1) begin + sum_IIRout_p3_r[i] <= 'h0; + end + for (i = 0; i < 26; i = i + 1) begin + sum_IIRout_p2_r[i] <= 'h0; + end + for (i = 0; i < 28; i = i + 1) begin + sum_IIRout_p1_r[i] <= 'h0; + end + for (i = 0; i < 29; i = i + 1) begin + sum_IIRout_p0_r[i] <= 'h0; end end else if (en) begin + sum_IIRout_pe_r[0] <= sum_IIRout_pe; + sum_IIRout_pd_r[0] <= sum_IIRout_pd; + sum_IIRout_pc_r[0] <= sum_IIRout_pc; + sum_IIRout_pb_r[0] <= sum_IIRout_pb; + sum_IIRout_pa_r[0] <= sum_IIRout_pa; + sum_IIRout_p9_r[0] <= sum_IIRout_p9; + sum_IIRout_p8_r[0] <= sum_IIRout_p8; + sum_IIRout_p7_r[0] <= sum_IIRout_p7; sum_IIRout_p6_r[0] <= sum_IIRout_p6; sum_IIRout_p5_r[0] <= sum_IIRout_p5; sum_IIRout_p4_r[0] <= sum_IIRout_p4; @@ -684,37 +1103,87 @@ always @(posedge clk or negedge rstn) begin sum_IIRout_p1_r[0] <= sum_IIRout_p1; sum_IIRout_p0_r[0] <= sum_IIRout_p0; for (i = 0; i < 1; i = i + 1) begin - sum_IIRout_p6_r[i+1] <= sum_IIRout_p6_r[i]; + sum_IIRout_pe_r[i+1] <= sum_IIRout_pe_r[i]; end - for (i = 0; i < 3; i = i + 1) begin - sum_IIRout_p5_r[i+1] <= sum_IIRout_p5_r[i]; + for (i = 0; i < 3; i = i + 1) begin + sum_IIRout_pd_r[i+1] <= sum_IIRout_pd_r[i]; end for (i = 0; i < 5; i = i + 1) begin - sum_IIRout_p4_r[i+1] <= sum_IIRout_p4_r[i]; + sum_IIRout_pc_r[i+1] <= sum_IIRout_pc_r[i]; end for (i = 0; i < 7; i = i + 1) begin - sum_IIRout_p3_r[i+1] <= sum_IIRout_p3_r[i]; + sum_IIRout_pb_r[i+1] <= sum_IIRout_pb_r[i]; end - for (i = 0; i < 9; i = i + 1) begin - sum_IIRout_p2_r[i+1] <= sum_IIRout_p2_r[i]; + for (i = 0; i < 9; i = i + 1) begin + sum_IIRout_pa_r[i+1] <= sum_IIRout_pa_r[i]; end - for (i = 0; i <11; i = i + 1) begin - sum_IIRout_p1_r[i+1] <= sum_IIRout_p1_r[i]; + for (i = 0; i < 11; i = i + 1) begin + for (i = 0; i < 1; i = i + 1) begin + sum_IIRout_pe_r[i+1] <= sum_IIRout_pe_r[i]; end - for (i = 0; i <12; i = i + 1) begin - sum_IIRout_p0_r[i+1] <= sum_IIRout_p0_r[i]; + for (i = 0; i < 3; i = i + 1) begin + sum_IIRout_pd_r[i+1] <= sum_IIRout_pd_r[i]; + end + for (i = 0; i < 5; i = i + 1) begin + sum_IIRout_pc_r[i+1] <= sum_IIRout_pc_r[i]; + end + for (i = 0; i < 7; i = i + 1) begin + sum_IIRout_pb_r[i+1] <= sum_IIRout_pb_r[i]; + end + for (i = 0; i < 9; i = i + 1) begin + sum_IIRout_pa_r[i+1] <= sum_IIRout_pa_r[i]; + end + for (i = 0; i < 11; i = i + 1) begin + sum_IIRout_p9_r[i+1] <= sum_IIRout_p9_r[i]; + end + for (i = 0; i < 13; i = i + 1) begin + sum_IIRout_p8_r[i+1] <= sum_IIRout_p8_r[i]; + end + for (i = 0; i < 15; i = i + 1) begin + sum_IIRout_p7_r[i+1] <= sum_IIRout_p7_r[i]; + end + for (i = 0; i < 17; i = i + 1) begin + sum_IIRout_p6_r[i+1] <= sum_IIRout_p6_r[i]; + end + for (i = 0; i < 19; i = i + 1) begin + sum_IIRout_p5_r[i+1] <= sum_IIRout_p5_r[i]; + end + for (i = 0; i < 21; i = i + 1) begin + sum_IIRout_p4_r[i+1] <= sum_IIRout_p4_r[i]; + end + for (i = 0; i < 23; i = i + 1) begin + sum_IIRout_p3_r[i+1] <= sum_IIRout_p3_r[i]; + end + for (i = 0; i < 25; i = i + 1) begin + sum_IIRout_p2_r[i+1] <= sum_IIRout_p2_r[i]; + end + for (i = 0; i < 27; i = i + 1) begin + sum_IIRout_p1_r[i+1] <= sum_IIRout_p1_r[i]; + end + for (i = 0; i < 29; i = i + 1) begin + sum_IIRout_p0_r[i+1] <= sum_IIRout_p0_r[i]; + end sum_IIRout_p9_r[i+1] <= sum_IIRout_p9_r[i]; end end end -assign dout_p0_r0 = {{3{din_p0_r[16][15]}},din_p0_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) -assign dout_p1_r0 = {{3{din_p1_r[16][15]}},din_p1_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) -assign dout_p2_r0 = {{3{din_p2_r[16][15]}},din_p2_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-116) -assign dout_p3_r0 = {{3{din_p3_r[16][15]}},din_p3_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) -assign dout_p4_r0 = {{3{din_p4_r[16][15]}},din_p4_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115) -assign dout_p5_r0 = {{3{din_p5_r[16][15]}},din_p5_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) -assign dout_p6_r0 = {{3{din_p6_r[16][15]}},din_p6_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) -assign dout_p7_r0 = {{3{din_p7_r[16][15]}},din_p7_r[16],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) +assign dout_p0_r0 = {{3{din_p0_r[32][15]}},din_p0_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[27]; // y(8n-119) +assign dout_p1_r0 = {{3{din_p1_r[32][15]}},din_p1_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[25]; // y(8n-118) +assign dout_p2_r0 = {{3{din_p2_r[32][15]}},din_p2_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[23]; // y(8n-117) +assign dout_p3_r0 = {{3{din_p3_r[32][15]}},din_p3_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[21]; // y(8n-116) +assign dout_p4_r0 = {{3{din_p4_r[32][15]}},din_p4_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[19]; // y(8n-115) +assign dout_p5_r0 = {{3{din_p5_r[32][15]}},din_p5_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[17]; // y(8n-114) +assign dout_p6_r0 = {{3{din_p6_r[32][15]}},din_p6_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7_r[15]; // y(8n-113) +assign dout_p7_r0 = {{3{din_p7_r[32][15]}},din_p7_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p8_r[13]; // y(8n-112) +assign dout_p8_r0 = {{3{din_p8_r[32][15]}},din_p8_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p9_r[11]; // y(8n-111) +assign dout_p9_r0 = {{3{din_p9_r[32][15]}},din_p9_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pa_r[ 9]; // y(8n-110) +assign dout_pa_r0 = {{3{din_pa_r[32][15]}},din_pa_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pb_r[ 7]; // y(8n-109) +assign dout_pb_r0 = {{3{din_pb_r[32][15]}},din_pb_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pc_r[ 5]; // y(8n-108) +assign dout_pc_r0 = {{3{din_pc_r[32][15]}},din_pc_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pd_r[ 3]; // y(8n-107) +assign dout_pd_r0 = {{3{din_pd_r[32][15]}},din_pd_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pe_r[ 1]; // y(8n-106) +assign dout_pe_r0 = {{3{din_pe_r[32][15]}},din_pe_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_pf; // y(8n-105) +assign dout_pf_r0 = {{3{din_pf_r[32][15]}},din_pf_r[32],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[28]; // y(8n-104) + trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); @@ -724,6 +1193,14 @@ trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u4 (clk, rs trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u8 (clk, rstn, en, dout_p8_r0, dout_p8); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u9 (clk, rstn, en, dout_p9_r0, dout_p9); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ua (clk, rstn, en, dout_pa_r0, dout_pa); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ub (clk, rstn, en, dout_pb_r0, dout_pb); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_uc (clk, rstn, en, dout_pc_r0, dout_pc); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ud (clk, rstn, en, dout_pd_r0, dout_pd); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_ue (clk, rstn, en, dout_pe_r0, dout_pe); +trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_uf (clk, rstn, en, dout_pf_r0, dout_pf); @@ -760,14 +1237,14 @@ always @(posedge clk or negedge rstn) dout_p0_r6 <= dout_p0_r6; end -reg [18:0] vldo_diff_r; +reg [33:0] vldo_diff_r; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin vldo_diff_r <= 19'b0; end else if(en) begin vldo_diff_r[0] <= vldo_diff; - for(i=0; i<18; i=i+1) begin + for(i=0; i<36; i=i+1) begin vldo_diff_r[i+1] <= vldo_diff_r[i]; end end @@ -791,7 +1268,7 @@ always @(posedge clk or negedge rstn)begin end assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); -assign vldo_r0_h = vldo_diff_r[17] == 0 && vldo_diff_r[16] == 1 ; +assign vldo_r0_h = vldo_diff_r[32] == 0 && vldo_diff_r[31] == 1 ; assign vldo = vldo_r0; endmodule diff --git a/rtl/z_dsp/diff_p.v b/rtl/z_dsp/diff_p.v index d76bdbc..57df340 100644 --- a/rtl/z_dsp/diff_p.v +++ b/rtl/z_dsp/diff_p.v @@ -1,24 +1,27 @@ module diff_p - ( - input rstn -,input clk -,input en -,input vldi -,input signed [15:0] din0 -,input signed [15:0] din1 -,input signed [15:0] din2 -,input signed [15:0] din3 -,output vldo -,output signed [15:0] dout_p0 -,output signed [15:0] dout_p1 -,output signed [15:0] dout_p2 -,output signed [15:0] dout_p3 -,output signed [15:0] dout_p4 -,output signed [15:0] dout_p5 -,output signed [15:0] dout_p6 -,output signed [15:0] dout_p7 + input rstn +,input clk +,input en +,input vldi +,input signed [15:0] din0 +,input signed [15:0] din1 +,input signed [15:0] din2 +,input signed [15:0] din3 +,input signed [15:0] din4 +,input signed [15:0] din5 +,input signed [15:0] din6 +,input signed [15:0] din7 +,input signed [15:0] din8 +,input signed [15:0] din9 +,input signed [15:0] dina +,input signed [15:0] dinb +,input signed [15:0] dinc +,input signed [15:0] dind +,input signed [15:0] dine +,input signed [15:0] dinf +,output vldo ,output signed [15:0] diff_p0 ,output signed [15:0] diff_p1 ,output signed [15:0] diff_p2 @@ -27,81 +30,19 @@ module diff_p ,output signed [15:0] diff_p5 ,output signed [15:0] diff_p6 ,output signed [15:0] diff_p7 +,output signed [15:0] diff_p8 +,output signed [15:0] diff_p9 +,output signed [15:0] diff_pa +,output signed [15:0] diff_pb +,output signed [15:0] diff_pc +,output signed [15:0] diff_pd +,output signed [15:0] diff_pe +,output signed [15:0] diff_pf ); +wire signed [15:0] dinf_r1; -wire signed [15:0] din_p0_r0; -wire signed [15:0] din_p1_r0; -wire signed [15:0] din_p2_r0; -wire signed [15:0] din_p3_r0; -wire signed [15:0] din_p4_r0; -wire signed [15:0] din_p5_r0; -wire signed [15:0] din_p6_r0; -wire signed [15:0] din_p7_r0; -wire vldo_0; -wire vldo_1; -wire vldo_2; -wire vldo_3; -wire vldo_r0; -assign vldo_r0 = vldo_0 || vldo_1 || vldo_2 || vldo_3; -sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn); -s2p_2 inst1_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din0), - .en (vldi), - .dout0 (din_p0_r0), - .dout1 (din_p4_r0) - ,.vldo( vldo_0) - ); -s2p_2 inst2_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din1), - .en (vldi), - .dout0 (din_p1_r0), - .dout1 (din_p5_r0) - ,.vldo( vldo_1) - ); -s2p_2 inst3_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din2), - .en (vldi), - .dout0 (din_p2_r0), - .dout1 (din_p6_r0) - ,.vldo( vldo_2) - ); -s2p_2 inst4_s2p_2 ( - .clk (clk), - .rst_n (rstn), - .din (din3), - .en (vldi), - .dout0 (din_p3_r0), - .dout1 (din_p7_r0) - ,.vldo( vldo_3) - ); - - -wire signed [15:0] din_p0_r1; -wire signed [15:0] din_p1_r1; -wire signed [15:0] din_p2_r1; -wire signed [15:0] din_p3_r1; -wire signed [15:0] din_p4_r1; -wire signed [15:0] din_p5_r1; -wire signed [15:0] din_p6_r1; -wire signed [15:0] din_p7_r1; - -sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn); - -assign dout_p0 = din_p0_r0; -assign dout_p1 = din_p1_r0; -assign dout_p2 = din_p2_r0; -assign dout_p3 = din_p3_r0; -assign dout_p4 = din_p4_r0; -assign dout_p5 = din_p5_r0; -assign dout_p6 = din_p6_r0; -assign dout_p7 = din_p7_r0; +sirv_gnrl_dfflr #(16) din_pf_1(en,dinf, dinf_r1 ,clk,rstn); reg signed [15:0] diff_p0_r1; reg signed [15:0] diff_p1_r1; @@ -111,6 +52,14 @@ reg signed [15:0] diff_p4_r1; reg signed [15:0] diff_p5_r1; reg signed [15:0] diff_p6_r1; reg signed [15:0] diff_p7_r1; +reg signed [15:0] diff_p8_r1; +reg signed [15:0] diff_p9_r1; +reg signed [15:0] diff_pa_r1; +reg signed [15:0] diff_pb_r1; +reg signed [15:0] diff_pc_r1; +reg signed [15:0] diff_pd_r1; +reg signed [15:0] diff_pe_r1; +reg signed [15:0] diff_pf_r1; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin @@ -122,17 +71,32 @@ if(rstn==1'b0)begin diff_p5_r1 <= 0; diff_p6_r1 <= 0; diff_p7_r1 <= 0; - + diff_p8_r1 <= 0; + diff_p9_r1 <= 0; + diff_pa_r1 <= 0; + diff_pb_r1 <= 0; + diff_pc_r1 <= 0; + diff_pd_r1 <= 0; + diff_pe_r1 <= 0; + diff_pf_r1 <= 0; end else if(en)begin - diff_p0_r1 <= din_p0_r0 - din_p7_r1; - diff_p1_r1 <= din_p1_r0 - din_p0_r0; - diff_p2_r1 <= din_p2_r0 - din_p1_r0; - diff_p3_r1 <= din_p3_r0 - din_p2_r0; - diff_p4_r1 <= din_p4_r0 - din_p3_r0; - diff_p5_r1 <= din_p5_r0 - din_p4_r0; - diff_p6_r1 <= din_p6_r0 - din_p5_r0; - diff_p7_r1 <= din_p7_r0 - din_p6_r0; + diff_p0_r1 <= din0 - dinf_r1; + diff_p1_r1 <= din1 - din0; + diff_p2_r1 <= din2 - din1; + diff_p3_r1 <= din3 - din2; + diff_p4_r1 <= din4 - din3; + diff_p5_r1 <= din5 - din4; + diff_p6_r1 <= din6 - din5; + diff_p7_r1 <= din7 - din6; + diff_p8_r1 <= din8 - din7; + diff_p9_r1 <= din9 - din8 ; + diff_pa_r1 <= dina - din9 ; + diff_pb_r1 <= dinb - dina; + diff_pc_r1 <= dinc - dinb; + diff_pd_r1 <= dind - dinc; + diff_pe_r1 <= dine - dind; + diff_pf_r1 <= dinf - dine; end else begin diff_p0_r1 <= diff_p0_r1; @@ -143,6 +107,14 @@ else begin diff_p5_r1 <= diff_p5_r1; diff_p6_r1 <= diff_p6_r1; diff_p7_r1 <= diff_p7_r1; + diff_p8_r1 <= diff_p8_r1; + diff_p9_r1 <= diff_p9_r1; + diff_pa_r1 <= diff_pa_r1; + diff_pb_r1 <= diff_pb_r1; + diff_pc_r1 <= diff_pc_r1; + diff_pd_r1 <= diff_pd_r1; + diff_pe_r1 <= diff_pe_r1; + diff_pf_r1 <= diff_pf_r1; end end @@ -154,6 +126,16 @@ assign diff_p4 = diff_p4_r1; assign diff_p5 = diff_p5_r1; assign diff_p6 = diff_p6_r1; assign diff_p7 = diff_p7_r1; +assign diff_p8 = diff_p8_r1; +assign diff_p9 = diff_p9_r1; +assign diff_pa = diff_pa_r1; +assign diff_pb = diff_pb_r1; +assign diff_pc = diff_pc_r1; +assign diff_pd = diff_pd_r1; +assign diff_pe = diff_pe_r1; +assign diff_pf = diff_pf_r1; + +sirv_gnrl_dffr #(1) vldo_1(vldi, vldo ,clk,rstn); endmodule diff --git a/rtl/z_dsp/mult_C.v b/rtl/z_dsp/mult_C.v new file mode 100644 index 0000000..bf53329 --- /dev/null +++ b/rtl/z_dsp/mult_C.v @@ -0,0 +1,86 @@ +module mult_C #( + parameter integer A_width = 8 +,parameter integer B_width = 8 +,parameter integer C_width = 8 +,parameter integer D_width = 8 +,parameter integer o_width = 31//division + +) + +( + clk, + rstn, + en, + a, + b, + c, + d, + Re, + Im +); + +input rstn; +input clk; +input en; +input signed [A_width-1 :0] a; +input signed [B_width-1 :0] b; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; + +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; + +wire signed [A_width+C_width-1:0] ac; +wire signed [B_width+D_width-1:0] bd; +wire signed [A_width+D_width-1:0] ad; +wire signed [B_width+C_width-1:0] bc; +wire signed [A_width+C_width :0] Re_tmp; +wire signed [A_width+D_width :0] Im_tmp; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; + +wire signed [A_width:0] sum_ab; +wire signed [C_width:0] sum_cd; +wire signed [A_width+C_width+1:0] product_of_sums; + +assign sum_ab = a + b; +assign sum_cd = c + d; + + +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); + +DW02_mult #(B_width,D_width) inst_c2( .A (b ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (bd ) + ); + +DW02_mult #(A_width+1,D_width+1) inst_c3( .A (sum_ab ), + .B (sum_cd ), + .TC (1'b1 ), + .PRODUCT (product_of_sums) + ); + +assign Re_tmp = ac - bd; +assign Im_tmp = product_of_sums - ac - bd; + +trunc #( + .diw (A_width+C_width+1 ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round1 (clk, rstn, en, Re_tmp, Re_trunc); +trunc #( + .diw (A_width+D_width+1 ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round2 (clk, rstn, en, Im_tmp, Im_trunc); + +// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. +assign Re = Re_trunc; +assign Im = Im_trunc; + +endmodule diff --git a/rtl/z_dsp/mult_real.v b/rtl/z_dsp/mult_real.v deleted file mode 100644 index 5ad989e..0000000 --- a/rtl/z_dsp/mult_real.v +++ /dev/null @@ -1,39 +0,0 @@ - -module mult_real #( - parameter integer A_width = 8 -,parameter integer C_width = 8 -,parameter integer o_width = 31//division - -) - -( - input rstn -,input clk -,input en -,input signed [A_width-1 :0] din -,input signed [C_width-1 :0] coef -,output signed [o_width-1 :0] dout - -); - -wire signed [A_width+C_width-1:0] ac; -wire signed [o_width-1 :0] Re_trunc; - - - -DW02_mult #(A_width,C_width) inst_c1 ( - .A (din ), - .B (coef ), - .TC (1'b1 ), - .PRODUCT (ac ) - ); - -trunc #( - .diw (A_width+C_width ) - ,.msb (A_width+C_width-2 ) - ,.lsb (A_width+C_width-o_width-1 ) -) u_round1 (clk, rstn, en, ac, Re_trunc); - -assign dout = Re_trunc; - -endmodule diff --git a/rtl/z_dsp/mult_x.v b/rtl/z_dsp/mult_x.v new file mode 100644 index 0000000..10d0552 --- /dev/null +++ b/rtl/z_dsp/mult_x.v @@ -0,0 +1,66 @@ +module mult_x #( + parameter integer A_width = 8 +,parameter integer C_width = 8 +,parameter integer D_width = 8 +,parameter integer o_width = 31//division + +) + +( + clk, + rstn, + en, + a, + c, + d, + Re, + Im +); + +input rstn; +input clk; +input en; +input signed [A_width-1 :0] a; +input signed [C_width-1 :0] c; +input signed [D_width-1 :0] d; + +output signed [o_width-1 :0] Re; +output signed [o_width-1 :0] Im; + +wire signed [A_width+C_width-1:0] ac; +wire signed [A_width+D_width-1:0] ad; +wire signed [o_width-1 :0] Re_trunc; +wire signed [o_width-1 :0] Im_trunc; + + + +DW02_mult #(A_width,C_width) inst_c1( .A (a ), + .B (c ), + .TC (1'b1 ), + .PRODUCT (ac ) + ); + +DW02_mult #(A_width,D_width) inst_c3( .A (a ), + .B (d ), + .TC (1'b1 ), + .PRODUCT (ad ) + ); + + + +trunc #( + .diw (A_width+C_width ) + ,.msb (A_width+C_width-2 ) + ,.lsb (A_width+C_width-o_width-1 ) +) u_round1 (clk, rstn, en, ac, Re_trunc); +trunc #( + .diw (A_width+D_width ) + ,.msb (A_width+D_width-2 ) + ,.lsb (A_width+D_width-o_width-1 ) +) u_round2 (clk, rstn, en, ad, Im_trunc); + +// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input. +assign Re = Re_trunc; +assign Im = Im_trunc; + +endmodule diff --git a/rtl/z_dsp/rate_adapter.v b/rtl/z_dsp/rate_adapter.v deleted file mode 100644 index 465f258..0000000 --- a/rtl/z_dsp/rate_adapter.v +++ /dev/null @@ -1,57 +0,0 @@ - -module rate_adapter -( - input rstn -,input clk -,input en -,input vldi -,input signed [15:0] din0 -,input signed [15:0] din1 -,input signed [15:0] din2 -,input signed [15:0] din3 -,input signed [15:0] din4 -,input signed [15:0] din5 -,input signed [15:0] din6 -,input signed [15:0] din7 -,output signed [15:0] dout0 -,output signed [15:0] dout1 -,output signed [15:0] dout2 -,output signed [15:0] dout3 -,output vldo - ); - - - -reg signed [15:0] doutf_0; -reg signed [15:0] doutf_1; -reg signed [15:0] doutf_2; -reg signed [15:0] doutf_3; - -always@(posedge clk or negedge rstn) - if(!rstn) begin - doutf_0 <= 0; - doutf_1 <= 0; - doutf_2 <= 0; - doutf_3 <= 0; - end - else if(!en) begin - doutf_0 <= din0; - doutf_1 <= din1; - doutf_2 <= din2; - doutf_3 <= din3; - end - else begin - doutf_0 <= din4; - doutf_1 <= din5; - doutf_2 <= din6; - doutf_3 <= din7; - end - -assign dout0 = doutf_0; -assign dout1 = doutf_1; -assign dout2 = doutf_2; -assign dout3 = doutf_3; - -//sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi, vldo ,clk,rstn); -assign vldo = vldi; -endmodule diff --git a/rtl/z_dsp/s2p_2.v b/rtl/z_dsp/s2p_2.v deleted file mode 100644 index afc6d95..0000000 --- a/rtl/z_dsp/s2p_2.v +++ /dev/null @@ -1,84 +0,0 @@ -module s2p_2 ( - input clk, - input rst_n, - input [15:0] din, - input en, - output [15:0] dout0, - output [15:0] dout1, - output vldo -); - -reg cnt; -wire add_cnt; -wire end_cnt; - -always @(posedge clk or negedge rst_n)begin - if(!rst_n)begin - cnt <= 0; - end - else if(add_cnt)begin - if(end_cnt) - cnt <= 0; - else - cnt <= cnt + 1; - end - else begin - cnt <= 0; - end -end - -assign add_cnt = en == 1'b1; -assign end_cnt = add_cnt && cnt== 2 - 1 ; - -wire en_r1; -wire en_r2; -reg [ 15: 0] dout0_r0; -reg [ 15: 0] dout1_r0; -wire dout0_en; -wire dout1_en; -wire dout0_hold; -wire dout1_hold; - -always @(posedge clk or negedge rst_n)begin - if(!rst_n)begin - dout0_r0 <= 16'b0; - dout1_r0 <= 16'b0; - end - else if(dout0_en)begin - dout0_r0 <= din; - end - else if(dout1_en)begin - dout1_r0 <= din; - end - else if(dout0_hold)begin - dout0_r0 <= dout0_r0; - dout1_r0 <= 16'd0; - end - else if(dout1_hold)begin - dout0_r0 <= 16'd0; - dout1_r0 <= dout1_r0; - end - else begin - dout0_r0 <= 16'd0; - dout1_r0 <= 16'd0; - end -end - -assign dout0_en = add_cnt && cnt == 0; -assign dout1_en = add_cnt && cnt == 1; -assign dout0_hold = en == 0 && en_r1 == 1 && cnt == 1; -assign dout1_hold = en == 0 && en_r1 == 1 && cnt == 0; - -sirv_gnrl_dffr #(1) dff_en_1(en , en_r1 ,clk,rst_n); -sirv_gnrl_dffr #(1) dff_en_2(en_r1, en_r2 ,clk,rst_n); -assign vldo = en_r2; - -wire [ 15: 0] dout0_r1; -sirv_gnrl_dfflr #(16) dff_dout0_1(1'b1,dout0_r0, dout0_r1 ,clk,rst_n); - -assign dout0 = dout0_r1; -assign dout1 = dout1_r0; - - -endmodule - diff --git a/rtl/z_dsp/z_dsp.v b/rtl/z_dsp/z_dsp.v index 680390b..e6f9279 100644 --- a/rtl/z_dsp/z_dsp.v +++ b/rtl/z_dsp/z_dsp.v @@ -4,31 +4,59 @@ module z_dsp input rstn ,input clk ,input en -//,input tc_bypass -,input [ 5:0] vldi_coef +//,input tc_bypass //NC +,input [ 3:0] vldi_coef ,input vldi_data -//,input [1:0] intp_mode -//,input [1:0] dac_mode_sel +//,input [1:0] intp_mode //NC +//,input [1:0] dac_mode_sel //NC ,input signed [15:0] din0 ,input signed [15:0] din1 ,input signed [15:0] din2 ,input signed [15:0] din3 +,input signed [15:0] din4 +,input signed [15:0] din5 +,input signed [15:0] din6 +,input signed [15:0] din7 +,input signed [15:0] din8 +,input signed [15:0] din9 +,input signed [15:0] dina +,input signed [15:0] dinb +,input signed [15:0] dinc +,input signed [15:0] dind +,input signed [15:0] dine +,input signed [15:0] dinf ,input signed [31:0] a0_re +,input signed [31:0] a0_im ,input signed [31:0] b0_re +,input signed [31:0] b0_im ,input signed [31:0] a1_re +,input signed [31:0] a1_im ,input signed [31:0] b1_re +,input signed [31:0] b1_im ,input signed [31:0] a2_re +,input signed [31:0] a2_im ,input signed [31:0] b2_re +,input signed [31:0] b2_im ,input signed [31:0] a3_re +,input signed [31:0] a3_im ,input signed [31:0] b3_re -,input signed [31:0] a4_re -,input signed [31:0] b4_re -,input signed [31:0] a5_re -,input signed [31:0] b5_re +,input signed [31:0] b3_im ,output signed [15:0] dout0 ,output signed [15:0] dout1 ,output signed [15:0] dout2 ,output signed [15:0] dout3 +,output signed [15:0] dout4 +,output signed [15:0] dout5 +,output signed [15:0] dout6 +,output signed [15:0] dout7 +,output signed [15:0] dout8 +,output signed [15:0] dout9 +,output signed [15:0] douta +,output signed [15:0] doutb +,output signed [15:0] doutc +,output signed [15:0] doutd +,output signed [15:0] doute +,output signed [15:0] doutf ,output vldo ); @@ -36,94 +64,213 @@ module z_dsp wire signed [15:0] IIR_out; -wire signed [31:0] ao_re [5:0]; -wire signed [31:0] ab_re [5:0]; -wire signed [31:0] abb_re [5:0]; -wire signed [31:0] ab_pow3_re [5:0]; -wire signed [31:0] ab_pow4_re [5:0]; -wire signed [31:0] ab_pow5_re [5:0]; -wire signed [31:0] ab_pow6_re [5:0]; -wire signed [31:0] ab_pow7_re [5:0]; -wire signed [31:0] bo_re [5:0]; -wire signed [31:0] b_pow8_re [5:0]; +wire signed [31:0] ao_re [3:0]; +wire signed [31:0] ab_re [3:0]; +wire signed [31:0] abb_re [3:0]; +wire signed [31:0] ab_pow3_re [3:0]; +wire signed [31:0] ab_pow4_re [3:0]; +wire signed [31:0] ab_pow5_re [3:0]; +wire signed [31:0] ab_pow6_re [3:0]; +wire signed [31:0] ab_pow7_re [3:0]; +wire signed [31:0] ab_pow8_re [3:0]; +wire signed [31:0] ab_pow9_re [3:0]; +wire signed [31:0] ab_powa_re [3:0]; +wire signed [31:0] ab_powb_re [3:0]; +wire signed [31:0] ab_powc_re [3:0]; +wire signed [31:0] ab_powd_re [3:0]; +wire signed [31:0] ab_powe_re [3:0]; +wire signed [31:0] ab_powf_re [3:0]; +wire signed [31:0] bo_re [3:0]; +wire signed [31:0] b_pow16_re [3:0]; +wire signed [31:0] ao_im [3:0]; +wire signed [31:0] ab_im [3:0]; +wire signed [31:0] abb_im [3:0]; +wire signed [31:0] ab_pow3_im [3:0]; +wire signed [31:0] ab_pow4_im [3:0]; +wire signed [31:0] ab_pow5_im [3:0]; +wire signed [31:0] ab_pow6_im [3:0]; +wire signed [31:0] ab_pow7_im [3:0]; +wire signed [31:0] ab_pow8_im [3:0]; +wire signed [31:0] ab_pow9_im [3:0]; +wire signed [31:0] ab_powa_im [3:0]; +wire signed [31:0] ab_powb_im [3:0]; +wire signed [31:0] ab_powc_im [3:0]; +wire signed [31:0] ab_powd_im [3:0]; +wire signed [31:0] ab_powe_im [3:0]; +wire signed [31:0] ab_powf_im [3:0]; +wire signed [31:0] bo_im [3:0]; +wire signed [31:0] b_pow16_im [3:0]; -CoefGen inst_CoefGen( - .clk (clk ), - .rstn (rstn ), - .vldi (vldi_coef ), - .a0_re (a0_re ), - .b0_re (b0_re ), - .a1_re (a1_re ), - .b1_re (b1_re ), - .a2_re (a2_re ), - .b2_re (b2_re ), - .a3_re (a3_re ), - .b3_re (b3_re ), - .a4_re (a4_re ), - .b4_re (b4_re ), - .a5_re (a5_re ), - .b5_re (b5_re ), - .a_re0 (ao_re[0] ), - .b_re0 (bo_re[0] ), - .ab_re0 (ab_re[0] ), - .abb_re0 (abb_re[0] ), - .ab_pow3_re0 (ab_pow3_re[0]), - .ab_pow4_re0 (ab_pow4_re[0]), - .ab_pow5_re0 (ab_pow5_re[0]), - .ab_pow6_re0 (ab_pow6_re[0]), - .ab_pow7_re0 (ab_pow7_re[0]), - .b_pow8_re0 (b_pow8_re[0] ), - .a_re1 (ao_re[1] ), - .b_re1 (bo_re[1] ), - .ab_re1 (ab_re[1] ), - .abb_re1 (abb_re[1] ), - .ab_pow3_re1 (ab_pow3_re[1]), - .ab_pow4_re1 (ab_pow4_re[1]), - .ab_pow5_re1 (ab_pow5_re[1]), - .ab_pow6_re1 (ab_pow6_re[1]), - .ab_pow7_re1 (ab_pow7_re[1]), - .b_pow8_re1 (b_pow8_re[1] ), - .a_re2 (ao_re[2] ), - .b_re2 (bo_re[2] ), - .ab_re2 (ab_re[2] ), - .abb_re2 (abb_re[2] ), - .ab_pow3_re2 (ab_pow3_re[2]), - .ab_pow4_re2 (ab_pow4_re[2]), - .ab_pow5_re2 (ab_pow5_re[2]), - .ab_pow6_re2 (ab_pow6_re[2]), - .ab_pow7_re2 (ab_pow7_re[2]), - .b_pow8_re2 (b_pow8_re[2] ), - .a_re3 (ao_re[3] ), - .b_re3 (bo_re[3] ), - .ab_re3 (ab_re[3] ), - .abb_re3 (abb_re[3] ), - .ab_pow3_re3 (ab_pow3_re[3]), - .ab_pow4_re3 (ab_pow4_re[3]), - .ab_pow5_re3 (ab_pow5_re[3]), - .ab_pow6_re3 (ab_pow6_re[3]), - .ab_pow7_re3 (ab_pow7_re[3]), - .b_pow8_re3 (b_pow8_re[3] ), - .a_re4 (ao_re[4] ), - .b_re4 (bo_re[4] ), - .ab_re4 (ab_re[4] ), - .abb_re4 (abb_re[4] ), - .ab_pow3_re4 (ab_pow3_re[4]), - .ab_pow4_re4 (ab_pow4_re[4]), - .ab_pow5_re4 (ab_pow5_re[4]), - .ab_pow6_re4 (ab_pow6_re[4]), - .ab_pow7_re4 (ab_pow7_re[4]), - .b_pow8_re4 (b_pow8_re[4] ), - .a_re5 (ao_re[5] ), - .b_re5 (bo_re[5] ), - .ab_re5 (ab_re[5] ), - .abb_re5 (abb_re[5] ), - .ab_pow3_re5 (ab_pow3_re[5]), - .ab_pow4_re5 (ab_pow4_re[5]), - .ab_pow5_re5 (ab_pow5_re[5]), - .ab_pow6_re5 (ab_pow6_re[5]), - .ab_pow7_re5 (ab_pow7_re[5]), - .b_pow8_re5 (b_pow8_re[5] ) - ); +CoefGen#( + .data_in_width ( 32 ), + .coef_width ( 32 ), + .frac_data_out_width ( 20 ), + .frac_coef_width ( 31 ) +) u_CoefGen( + .rstn ( rstn ), + .clk ( clk ), + .vldi ( vldi_coef ), + .a0_re ( a0_re ), + .b0_re ( b0_re ), + .a1_re ( a1_re ), + .b1_re ( b1_re ), + .a2_re ( a2_re ), + .b2_re ( b2_re ), + .a3_re ( a3_re ), + .b3_re ( b3_re ), + .a0_im ( a0_im ), + .b0_im ( b0_im ), + .a1_im ( a1_im ), + .b1_im ( b1_im ), + .a2_im ( a2_im ), + .b2_im ( b2_im ), + .a3_im ( a3_im ), + .b3_im ( b3_im ), + .a_re0 ( ao_re[0] ), + .b_re0 ( bo_re[0] ), + .ab_re0 ( ab_re[0] ), + .abb_re0 ( abb_re[0] ), + .ab_pow3_re0 ( ab_pow3_re[0] ), + .ab_pow4_re0 ( ab_pow4_re[0] ), + .ab_pow5_re0 ( ab_pow5_re[0] ), + .ab_pow6_re0 ( ab_pow6_re[0] ), + .ab_pow7_re0 ( ab_pow7_re[0] ), + .ab_pow8_re0 ( ab_pow8_re[0] ), + .ab_pow9_re0 ( ab_pow9_re[0] ), + .ab_powa_re0 ( ab_powa_re[0] ), + .ab_powb_re0 ( ab_powb_re[0] ), + .ab_powc_re0 ( ab_powc_re[0] ), + .ab_powd_re0 ( ab_powd_re[0] ), + .ab_powe_re0 ( ab_powe_re[0] ), + .ab_powf_re0 ( ab_powf_re[0] ), + .b_pow16_re0 ( b_pow16_re[0] ), + .a_re1 ( ao_re[1] ), + .b_re1 ( bo_re[1] ), + .ab_re1 ( ab_re[1] ), + .abb_re1 ( abb_re[1] ), + .ab_pow3_re1 ( ab_pow3_re[1] ), + .ab_pow4_re1 ( ab_pow4_re[1] ), + .ab_pow5_re1 ( ab_pow5_re[1] ), + .ab_pow6_re1 ( ab_pow6_re[1] ), + .ab_pow7_re1 ( ab_pow7_re[1] ), + .ab_pow8_re1 ( ab_pow8_re[1] ), + .ab_pow9_re1 ( ab_pow9_re[1] ), + .ab_powa_re1 ( ab_powa_re[1] ), + .ab_powb_re1 ( ab_powb_re[1] ), + .ab_powc_re1 ( ab_powc_re[1] ), + .ab_powd_re1 ( ab_powd_re[1] ), + .ab_powe_re1 ( ab_powe_re[1] ), + .ab_powf_re1 ( ab_powf_re[1] ), + .b_pow16_re1 ( b_pow16_re[1] ), + .a_re2 ( ao_re[2] ), + .b_re2 ( bo_re[2] ), + .ab_re2 ( ab_re[2] ), + .abb_re2 ( abb_re[2] ), + .ab_pow3_re2 ( ab_pow3_re[2] ), + .ab_pow4_re2 ( ab_pow4_re[2] ), + .ab_pow5_re2 ( ab_pow5_re[2] ), + .ab_pow6_re2 ( ab_pow6_re[2] ), + .ab_pow7_re2 ( ab_pow7_re[2] ), + .ab_pow8_re2 ( ab_pow8_re[2] ), + .ab_pow9_re2 ( ab_pow9_re[2] ), + .ab_powa_re2 ( ab_powa_re[2] ), + .ab_powb_re2 ( ab_powb_re[2] ), + .ab_powc_re2 ( ab_powc_re[2] ), + .ab_powd_re2 ( ab_powd_re[2] ), + .ab_powe_re2 ( ab_powe_re[2] ), + .ab_powf_re2 ( ab_powf_re[2] ), + .b_pow16_re2 ( b_pow16_re[2] ), + .a_re3 ( ao_re[3] ), + .b_re3 ( bo_re[3] ), + .ab_re3 ( ab_re[3] ), + .abb_re3 ( abb_re[3] ), + .ab_pow3_re3 ( ab_pow3_re[3] ), + .ab_pow4_re3 ( ab_pow4_re[3] ), + .ab_pow5_re3 ( ab_pow5_re[3] ), + .ab_pow6_re3 ( ab_pow6_re[3] ), + .ab_pow7_re3 ( ab_pow7_re[3] ), + .ab_pow8_re3 ( ab_pow8_re[3] ), + .ab_pow9_re3 ( ab_pow9_re[3] ), + .ab_powa_re3 ( ab_powa_re[3] ), + .ab_powb_re3 ( ab_powb_re[3] ), + .ab_powc_re3 ( ab_powc_re[3] ), + .ab_powd_re3 ( ab_powd_re[3] ), + .ab_powe_re3 ( ab_powe_re[3] ), + .ab_powf_re3 ( ab_powf_re[3] ), + .b_pow16_re3 ( b_pow16_re[3] ), + .a_im0 ( ao_im[0] ), + .b_im0 ( bo_im[0] ), + .ab_im0 ( ab_im[0] ), + .abb_im0 ( abb_im[0] ), + .ab_pow3_im0 ( ab_pow3_im[0] ), + .ab_pow4_im0 ( ab_pow4_im[0] ), + .ab_pow5_im0 ( ab_pow5_im[0] ), + .ab_pow6_im0 ( ab_pow6_im[0] ), + .ab_pow7_im0 ( ab_pow7_im[0] ), + .ab_pow8_im0 ( ab_pow8_im[0] ), + .ab_pow9_im0 ( ab_pow9_im[0] ), + .ab_powa_im0 ( ab_powa_im[0] ), + .ab_powb_im0 ( ab_powb_im[0] ), + .ab_powc_im0 ( ab_powc_im[0] ), + .ab_powd_im0 ( ab_powd_im[0] ), + .ab_powe_im0 ( ab_powe_im[0] ), + .ab_powf_im0 ( ab_powf_im[0] ), + .b_pow16_im0 ( b_pow16_im[0] ), + .a_im1 ( ao_im[1] ), + .b_im1 ( bo_im[1] ), + .ab_im1 ( ab_im[1] ), + .abb_im1 ( abb_im[1] ), + .ab_pow3_im1 ( ab_pow3_im[1] ), + .ab_pow4_im1 ( ab_pow4_im[1] ), + .ab_pow5_im1 ( ab_pow5_im[1] ), + .ab_pow6_im1 ( ab_pow6_im[1] ), + .ab_pow7_im1 ( ab_pow7_im[1] ), + .ab_pow8_im1 ( ab_pow8_im[1] ), + .ab_pow9_im1 ( ab_pow9_im[1] ), + .ab_powa_im1 ( ab_powa_im[1] ), + .ab_powb_im1 ( ab_powb_im[1] ), + .ab_powc_im1 ( ab_powc_im[1] ), + .ab_powd_im1 ( ab_powd_im[1] ), + .ab_powe_im1 ( ab_powe_im[1] ), + .ab_powf_im1 ( ab_powf_im[1] ), + .b_pow16_im1 ( b_pow16_im[1] ), + .a_im2 ( ao_im[2] ), + .b_im2 ( bo_im[2] ), + .ab_im2 ( ab_im[2] ), + .abb_im2 ( abb_im[2] ), + .ab_pow3_im2 ( ab_pow3_im[2] ), + .ab_pow4_im2 ( ab_pow4_im[2] ), + .ab_pow5_im2 ( ab_pow5_im[2] ), + .ab_pow6_im2 ( ab_pow6_im[2] ), + .ab_pow7_im2 ( ab_pow7_im[2] ), + .ab_pow8_im2 ( ab_pow8_im[2] ), + .ab_pow9_im2 ( ab_pow9_im[2] ), + .ab_powa_im2 ( ab_powa_im[2] ), + .ab_powb_im2 ( ab_powb_im[2] ), + .ab_powc_im2 ( ab_powc_im[2] ), + .ab_powd_im2 ( ab_powd_im[2] ), + .ab_powe_im2 ( ab_powe_im[2] ), + .ab_powf_im2 ( ab_powf_im[2] ), + .b_pow16_im2 ( b_pow16_im[2] ), + .a_im3 ( ao_im[3] ), + .b_im3 ( bo_im[3] ), + .ab_im3 ( ab_im[3] ), + .abb_im3 ( abb_im[3] ), + .ab_pow3_im3 ( ab_pow3_im[3] ), + .ab_pow4_im3 ( ab_pow4_im[3] ), + .ab_pow5_im3 ( ab_pow5_im[3] ), + .ab_pow6_im3 ( ab_pow6_im[3] ), + .ab_pow7_im3 ( ab_pow7_im[3] ), + .ab_pow8_im3 ( ab_pow8_im[3] ), + .ab_pow9_im3 ( ab_pow9_im[3] ), + .ab_powa_im3 ( ab_powa_im[3] ), + .ab_powb_im3 ( ab_powb_im[3] ), + .ab_powc_im3 ( ab_powc_im[3] ), + .ab_powd_im3 ( ab_powd_im[3] ), + .ab_powe_im3 ( ab_powe_im[3] ), + .ab_powf_im3 ( ab_powf_im[3] ), + .b_pow16_im3 ( b_pow16_im[3] ) +); wire signed [15:0] dout_0; wire signed [15:0] dout_1; @@ -134,109 +281,190 @@ wire signed [15:0] dout_5; wire signed [15:0] dout_6; wire signed [15:0] dout_7; wire vldo_TC; -TailCorr_top inst_TailCorr_top - ( - .clk (clk ), - .en (en ), - .rstn (rstn ), - .vldi (vldi_data ), -// .dac_mode_sel (dac_mode_sel ), -// .intp_mode (intp_mode ), - .din0 (din0 ), - .din1 (din1 ), - .din2 (din2 ), - .din3 (din3 ), - .a_re0 (ao_re[0] ), - .b_re0 (bo_re[0] ), - .ab_re0 (ab_re[0] ), - .abb_re0 (abb_re[0] ), - .ab_pow3_re0 (ab_pow3_re[0]), - .ab_pow4_re0 (ab_pow4_re[0]), - .ab_pow5_re0 (ab_pow5_re[0]), - .ab_pow6_re0 (ab_pow6_re[0]), - .ab_pow7_re0 (ab_pow7_re[0]), - .b_pow8_re0 (b_pow8_re[0] ), - .a_re1 (ao_re[1] ), - .b_re1 (bo_re[1] ), - .ab_re1 (ab_re[1] ), - .abb_re1 (abb_re[1] ), - .ab_pow3_re1 (ab_pow3_re[1]), - .ab_pow4_re1 (ab_pow4_re[1]), - .ab_pow5_re1 (ab_pow5_re[1]), - .ab_pow6_re1 (ab_pow6_re[1]), - .ab_pow7_re1 (ab_pow7_re[1]), - .b_pow8_re1 (b_pow8_re[1] ), - .a_re2 (ao_re[2] ), - .b_re2 (bo_re[2] ), - .ab_re2 (ab_re[2] ), - .abb_re2 (abb_re[2] ), - .ab_pow3_re2 (ab_pow3_re[2]), - .ab_pow4_re2 (ab_pow4_re[2]), - .ab_pow5_re2 (ab_pow5_re[2]), - .ab_pow6_re2 (ab_pow6_re[2]), - .ab_pow7_re2 (ab_pow7_re[2]), - .b_pow8_re2 (b_pow8_re[2] ), - .a_re3 (ao_re[3] ), - .b_re3 (bo_re[3] ), - .ab_re3 (ab_re[3] ), - .abb_re3 (abb_re[3] ), - .ab_pow3_re3 (ab_pow3_re[3]), - .ab_pow4_re3 (ab_pow4_re[3]), - .ab_pow5_re3 (ab_pow5_re[3]), - .ab_pow6_re3 (ab_pow6_re[3]), - .ab_pow7_re3 (ab_pow7_re[3]), - .b_pow8_re3 (b_pow8_re[3] ), - .a_re4 (ao_re[4] ), - .b_re4 (bo_re[4] ), - .ab_re4 (ab_re[4] ), - .abb_re4 (abb_re[4] ), - .ab_pow3_re4 (ab_pow3_re[4]), - .ab_pow4_re4 (ab_pow4_re[4]), - .ab_pow5_re4 (ab_pow5_re[4]), - .ab_pow6_re4 (ab_pow6_re[4]), - .ab_pow7_re4 (ab_pow7_re[4]), - .b_pow8_re4 (b_pow8_re[4] ), - .a_re5 (ao_re[5] ), - .b_re5 (bo_re[5] ), - .ab_re5 (ab_re[5] ), - .abb_re5 (abb_re[5] ), - .ab_pow3_re5 (ab_pow3_re[5]), - .ab_pow4_re5 (ab_pow4_re[5]), - .ab_pow5_re5 (ab_pow5_re[5]), - .ab_pow6_re5 (ab_pow6_re[5]), - .ab_pow7_re5 (ab_pow7_re[5]), - .b_pow8_re5 (b_pow8_re[5] ), - .dout_p0 (dout_0 ), - .dout_p1 (dout_1 ), - .dout_p2 (dout_2 ), - .dout_p3 (dout_3 ), - .dout_p4 (dout_4 ), - .dout_p5 (dout_5 ), - .dout_p6 (dout_6 ), - .dout_p7 (dout_7 ), - .vldo (vldo_TC ) - ); - -//assign vldo = vldo_TC; -rate_adapter inst_rate_adapter( - .rstn (rstn ), - .clk (clk ), - .en (en ), - .vldi (vldo_TC ), - .din0 (dout_0 ), - .din1 (dout_1 ), - .din2 (dout_2 ), - .din3 (dout_3 ), - .din4 (dout_4 ), - .din5 (dout_5 ), - .din6 (dout_6 ), - .din7 (dout_7 ), - .dout0 (dout0 ), - .dout1 (dout1 ), - .dout2 (dout2 ), - .dout3 (dout3 ), - .vldo (vldo ) - ); +TailCorr_top u_TailCorr_top( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .vldi ( vldi_data ), + .din0 ( din0 ), + .din1 ( din1 ), + .din2 ( din2 ), + .din3 ( din3 ), + .din4 ( din4 ), + .din5 ( din5 ), + .din6 ( din6 ), + .din7 ( din7 ), + .din8 ( din8 ), + .din9 ( din9 ), + .dina ( dina ), + .dinb ( dinb ), + .dinc ( dinc ), + .dind ( dind ), + .dine ( dine ), + .dinf ( dinf ), + .a_re0 ( ao_re[0] ), + .b_re0 ( bo_re[0] ), + .ab_re0 ( ab_re[0] ), + .abb_re0 ( abb_re[0] ), + .ab_pow3_re0 ( ab_pow3_re[0] ), + .ab_pow4_re0 ( ab_pow4_re[0] ), + .ab_pow5_re0 ( ab_pow5_re[0] ), + .ab_pow6_re0 ( ab_pow6_re[0] ), + .ab_pow7_re0 ( ab_pow7_re[0] ), + .ab_pow8_re0 ( ab_pow8_re[0] ), + .ab_pow9_re0 ( ab_pow9_re[0] ), + .ab_powa_re0 ( ab_powa_re[0] ), + .ab_powb_re0 ( ab_powb_re[0] ), + .ab_powc_re0 ( ab_powc_re[0] ), + .ab_powd_re0 ( ab_powd_re[0] ), + .ab_powe_re0 ( ab_powe_re[0] ), + .ab_powf_re0 ( ab_powf_re[0] ), + .b_pow16_re0 ( b_pow16_re[0] ), + .a_re1 ( ao_re[1] ), + .b_re1 ( bo_re[1] ), + .ab_re1 ( ab_re[1] ), + .abb_re1 ( abb_re[1] ), + .ab_pow3_re1 ( ab_pow3_re[1] ), + .ab_pow4_re1 ( ab_pow4_re[1] ), + .ab_pow5_re1 ( ab_pow5_re[1] ), + .ab_pow6_re1 ( ab_pow6_re[1] ), + .ab_pow7_re1 ( ab_pow7_re[1] ), + .ab_pow8_re1 ( ab_pow8_re[1] ), + .ab_pow9_re1 ( ab_pow9_re[1] ), + .ab_powa_re1 ( ab_powa_re[1] ), + .ab_powb_re1 ( ab_powb_re[1] ), + .ab_powc_re1 ( ab_powc_re[1] ), + .ab_powd_re1 ( ab_powd_re[1] ), + .ab_powe_re1 ( ab_powe_re[1] ), + .ab_powf_re1 ( ab_powf_re[1] ), + .b_pow16_re1 ( b_pow16_re[1] ), + .a_re2 ( ao_re[2] ), + .b_re2 ( bo_re[2] ), + .ab_re2 ( ab_re[2] ), + .abb_re2 ( abb_re[2] ), + .ab_pow3_re2 ( ab_pow3_re[2] ), + .ab_pow4_re2 ( ab_pow4_re[2] ), + .ab_pow5_re2 ( ab_pow5_re[2] ), + .ab_pow6_re2 ( ab_pow6_re[2] ), + .ab_pow7_re2 ( ab_pow7_re[2] ), + .ab_pow8_re2 ( ab_pow8_re[2] ), + .ab_pow9_re2 ( ab_pow9_re[2] ), + .ab_powa_re2 ( ab_powa_re[2] ), + .ab_powb_re2 ( ab_powb_re[2] ), + .ab_powc_re2 ( ab_powc_re[2] ), + .ab_powd_re2 ( ab_powd_re[2] ), + .ab_powe_re2 ( ab_powe_re[2] ), + .ab_powf_re2 ( ab_powf_re[2] ), + .b_pow16_re2 ( b_pow16_re[2] ), + .a_re3 ( ao_re[3] ), + .b_re3 ( bo_re[3] ), + .ab_re3 ( ab_re[3] ), + .abb_re3 ( abb_re[3] ), + .ab_pow3_re3 ( ab_pow3_re[3] ), + .ab_pow4_re3 ( ab_pow4_re[3] ), + .ab_pow5_re3 ( ab_pow5_re[3] ), + .ab_pow6_re3 ( ab_pow6_re[3] ), + .ab_pow7_re3 ( ab_pow7_re[3] ), + .ab_pow8_re3 ( ab_pow8_re[3] ), + .ab_pow9_re3 ( ab_pow9_re[3] ), + .ab_powa_re3 ( ab_powa_re[3] ), + .ab_powb_re3 ( ab_powb_re[3] ), + .ab_powc_re3 ( ab_powc_re[3] ), + .ab_powd_re3 ( ab_powd_re[3] ), + .ab_powe_re3 ( ab_powe_re[3] ), + .ab_powf_re3 ( ab_powf_re[3] ), + .b_pow16_re3 ( b_pow16_re[3] ), + .a_im0 ( ao_im[0] ), + .b_im0 ( bo_im[0] ), + .ab_im0 ( ab_im[0] ), + .abb_im0 ( abb_im[0] ), + .ab_pow3_im0 ( ab_pow3_im[0] ), + .ab_pow4_im0 ( ab_pow4_im[0] ), + .ab_pow5_im0 ( ab_pow5_im[0] ), + .ab_pow6_im0 ( ab_pow6_im[0] ), + .ab_pow7_im0 ( ab_pow7_im[0] ), + .ab_pow8_im0 ( ab_pow8_im[0] ), + .ab_pow9_im0 ( ab_pow9_im[0] ), + .ab_powa_im0 ( ab_powa_im[0] ), + .ab_powb_im0 ( ab_powb_im[0] ), + .ab_powc_im0 ( ab_powc_im[0] ), + .ab_powd_im0 ( ab_powd_im[0] ), + .ab_powe_im0 ( ab_powe_im[0] ), + .ab_powf_im0 ( ab_powf_im[0] ), + .b_pow16_im0 ( b_pow16_im[0] ), + .a_im1 ( ao_im[1] ), + .b_im1 ( bo_im[1] ), + .ab_im1 ( ab_im[1] ), + .abb_im1 ( abb_im[1] ), + .ab_pow3_im1 ( ab_pow3_im[1] ), + .ab_pow4_im1 ( ab_pow4_im[1] ), + .ab_pow5_im1 ( ab_pow5_im[1] ), + .ab_pow6_im1 ( ab_pow6_im[1] ), + .ab_pow7_im1 ( ab_pow7_im[1] ), + .ab_pow8_im1 ( ab_pow8_im[1] ), + .ab_pow9_im1 ( ab_pow9_im[1] ), + .ab_powa_im1 ( ab_powa_im[1] ), + .ab_powb_im1 ( ab_powb_im[1] ), + .ab_powc_im1 ( ab_powc_im[1] ), + .ab_powd_im1 ( ab_powd_im[1] ), + .ab_powe_im1 ( ab_powe_im[1] ), + .ab_powf_im1 ( ab_powf_im[1] ), + .b_pow16_im1 ( b_pow16_im[1] ), + .a_im2 ( ao_im[2] ), + .b_im2 ( bo_im[2] ), + .ab_im2 ( ab_im[2] ), + .abb_im2 ( abb_im[2] ), + .ab_pow3_im2 ( ab_pow3_im[2] ), + .ab_pow4_im2 ( ab_pow4_im[2] ), + .ab_pow5_im2 ( ab_pow5_im[2] ), + .ab_pow6_im2 ( ab_pow6_im[2] ), + .ab_pow7_im2 ( ab_pow7_im[2] ), + .ab_pow8_im2 ( ab_pow8_im[2] ), + .ab_pow9_im2 ( ab_pow9_im[2] ), + .ab_powa_im2 ( ab_powa_im[2] ), + .ab_powb_im2 ( ab_powb_im[2] ), + .ab_powc_im2 ( ab_powc_im[2] ), + .ab_powd_im2 ( ab_powd_im[2] ), + .ab_powe_im2 ( ab_powe_im[2] ), + .ab_powf_im2 ( ab_powf_im[2] ), + .b_pow16_im2 ( b_pow16_im[2] ), + .a_im3 ( ao_im[3] ), + .b_im3 ( bo_im[3] ), + .ab_im3 ( ab_im[3] ), + .abb_im3 ( abb_im[3] ), + .ab_pow3_im3 ( ab_pow3_im[3] ), + .ab_pow4_im3 ( ab_pow4_im[3] ), + .ab_pow5_im3 ( ab_pow5_im[3] ), + .ab_pow6_im3 ( ab_pow6_im[3] ), + .ab_pow7_im3 ( ab_pow7_im[3] ), + .ab_pow8_im3 ( ab_pow8_im[3] ), + .ab_pow9_im3 ( ab_pow9_im[3] ), + .ab_powa_im3 ( ab_powa_im[3] ), + .ab_powb_im3 ( ab_powb_im[3] ), + .ab_powc_im3 ( ab_powc_im[3] ), + .ab_powd_im3 ( ab_powd_im[3] ), + .ab_powe_im3 ( ab_powe_im[3] ), + .ab_powf_im3 ( ab_powf_im[3] ), + .b_pow16_im3 ( b_pow16_im[3] ), + .dout_p0 ( dout0 ), + .dout_p1 ( dout1 ), + .dout_p2 ( dout2 ), + .dout_p3 ( dout3 ), + .dout_p4 ( dout4 ), + .dout_p5 ( dout5 ), + .dout_p6 ( dout6 ), + .dout_p7 ( dout7 ), + .dout_p8 ( dout8 ), + .dout_p9 ( dout9 ), + .dout_pa ( douta ), + .dout_pb ( doutb ), + .dout_pc ( doutc ), + .dout_pd ( doutd ), + .dout_pe ( doute ), + .dout_pf ( doutf ), + .vldo ( vldo_TC ) +); +assign vldo = vldo_TC; endmodule diff --git a/script_m/TailCorr_Test_Verdi.m b/script_m/TailCorr_Test_Verdi.m index 5d0c71b..65f8030 100644 --- a/script_m/TailCorr_Test_Verdi.m +++ b/script_m/TailCorr_Test_Verdi.m @@ -9,10 +9,10 @@ max_error = zeros(100,1); for time = 1 if strcmp(data_source, 'matlab') - in = floor(cat(1,0,3000*ones(4*2579+4,1))); - for i = 0:3 + in = floor(cat(1,0,3000*randn(16*2500-1,1))); + for i = 0:15 filename = strcat(file_path, "in", num2str(i), "_matlab.dat"); - subset = in(i+1:4:end); + subset = in(i+1:16:end); fileID = fopen(filename, 'w'); fprintf(fileID, '%d\n', subset); fclose(fileID); @@ -20,7 +20,7 @@ if strcmp(data_source, 'matlab') in = [in; zeros(6e4,1)]; system('make all'); elseif strcmp(data_source, 'verdi') -% system('make all'); + system('make all'); in = []; for i = 0:3 filename = strcat(file_path, "in", num2str(i), ".dat"); @@ -36,14 +36,14 @@ end cs_wave = []; -for i = 0:3 +for i = 0:15 filename = strcat(file_path, "dout", num2str(i), ".dat"); dout_data = importdata(filename); if isempty(cs_wave) N = length(dout_data); - cs_wave = zeros(4*N, 1); + cs_wave = zeros(16*N, 1); end - cs_wave(i+1:4:end) = dout_data; + cs_wave(i+1:16:end) = dout_data; end A = [0.025 0.015*1 0.0002*1 0]; @@ -98,12 +98,12 @@ a_bin = dec2bin(a_fix,32); fprintf('a_fix is %d\n',a_fix); fprintf('b_fix is %d\n',b_fix); -fprintf('ab_fix is %d\n',ab_fix); -fprintf('ab2_fix is %d\n', ab2_fix); -fprintf('ab3_fix is %d\n', ab3_fix); -fprintf('ab4_fix is %d\n', ab4_fix); -fprintf('ab5_fix is %d\n', ab5_fix); -fprintf('ab6_fix is %d\n', ab6_fix); -fprintf('ab7_fix is %d\n', ab7_fix); -fprintf('b8_fix is %d\n',b8_fix); +% fprintf('ab_fix is %d\n',ab_fix); +% fprintf('ab2_fix is %d\n', ab2_fix); +% fprintf('ab3_fix is %d\n', ab3_fix); +% fprintf('ab4_fix is %d\n', ab4_fix); +% fprintf('ab5_fix is %d\n', ab5_fix); +% fprintf('ab6_fix is %d\n', ab6_fix); +% fprintf('ab7_fix is %d\n', ab7_fix); +% fprintf('b8_fix is %d\n',b8_fix); diff --git a/sim/z_dsp/files.f b/sim/z_dsp/files.f index c4b94f2..8914d44 100644 --- a/sim/z_dsp/files.f +++ b/sim/z_dsp/files.f @@ -1,14 +1,13 @@ ../../rtl/z_dsp/z_dsp.v ../../rtl/z_dsp/TailCorr_top.v -../../rtl/z_dsp/rate_adapter.v ../../rtl/z_dsp/IIR_top.v ../../rtl/z_dsp/IIR_Filter_p1.v -../../rtl/z_dsp/IIR_Filter_p8.v +../../rtl/z_dsp/IIR_Filter_p16.v ../../rtl/z_dsp/CoefGen.sv ../../rtl/z_dsp/diff_p.v -../../rtl/z_dsp/s2p_2.v ../../rtl/z_dsp/Trunc.v -../../rtl/z_dsp/mult_real.v +../../rtl/z_dsp/mult_x.v +../../rtl/z_dsp/mult_C.v ../../rtl/z_dsp/syncer.v ../../rtl/z_dsp/sirv_gnrl_dffs.v ../../rtl/model/DW02_mult.v diff --git a/sim/z_dsp/tb_z_dsp.v b/sim/z_dsp/tb_z_dsp.v index ac2f4fe..6c060d5 100644 --- a/sim/z_dsp/tb_z_dsp.v +++ b/sim/z_dsp/tb_z_dsp.v @@ -16,7 +16,7 @@ end reg rstn; reg [15:0] din_rect; -reg [ 5:0] vldi_coef; +reg [ 3:0] vldi_coef; reg vldi_data; parameter CYCLE = 20; @@ -30,30 +30,45 @@ initial begin end -reg signed [31:0] a_re [5:0]; -reg signed [31:0] b_re [5:0]; +reg en; +reg signed [31:0] a_re [3:0]; +reg signed [31:0] b_re [3:0]; +reg signed [31:0] a_im [3:0]; +reg signed [31:0] b_im [3:0]; initial begin rstn = 0; vldi_data <= 0; vldi_coef <= 0; din_rect = 16'd0; + a_re[0] <= 0; + b_re[0] <= 0; + a_re[1] <= 0; + b_re[1] <= 0; + a_re[2] <= 0; + b_re[2] <= 0; a_re[3] <= 0; b_re[3] <= 0; - a_re[4] <= 0; - b_re[4] <= 0; - a_re[5] <= 0; - b_re[5] <= 0; + a_im[0] <= 0; + b_im[0] <= 0; + a_im[1] <= 0; + b_im[1] <= 0; + a_im[2] <= 0; + b_im[2] <= 0; + a_im[3] <= 0; + b_im[3] <= 0; + en <= 0; repeat(3) @(posedge clk); vldi_coef[0] <= 1; rstn = 1; + en <= 1; a_re[0] <= 55007237; b_re[0] <= 2143083068; @(posedge clk); vldi_coef[0] <= 0; a_re[0] <= 0; b_re[0] <= 0; - repeat(8) @(posedge clk); + repeat(16) @(posedge clk); vldi_coef[1] <= 1; rstn = 1; a_re[1] <= 32690030; @@ -62,7 +77,7 @@ initial begin vldi_coef[1] <= 0; a_re[1] <= 0; b_re[1] <= 0; - repeat(8) @(posedge clk); + repeat(16) @(posedge clk); vldi_coef[2] <= 1; rstn = 1; a_re[2] <= 429516; @@ -113,35 +128,38 @@ always@(posedge clk or negedge rstn) din_rect <= 16'd0; end -reg signed [15:0] random_in [0:3]; +reg signed [15:0] random_in [0:15]; always @(posedge clk or negedge rstn) begin if (!rstn) begin - for (int i = 0; i < 4; i = i + 1) begin + for (int i = 0; i < 16; i = i + 1) begin random_in[i] <= 16'd0; end end else if (vldi_data) begin - for (int i = 0; i < 4; i = i + 1) begin + for (int i = 0; i < 16; i = i + 1) begin random_in[i] <= $urandom % 30000; end end else begin - for (int i = 0; i < 4; i = i + 1) begin + for (int i = 0; i < 16; i = i + 1) begin random_in[i] <= 16'd0; end end end -integer file[3:0]; -reg [15:0] data[3:0]; -integer status[3:0]; -reg [15:0] reg_array[3:0]; - +integer file[15:0]; +reg [15:0] data[15:0]; +integer status[15:0]; +reg [15:0] reg_array[15:0]; +string filenames[15:0]; initial begin if(source_mode == 3) begin - string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"}; - for (int i = 0; i < 4; i = i + 1) begin +// string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"}; + for (int i = 0; i < 16; i++) begin + $sformat(filenames[i], "in%0d_matlab.dat", i); + end + for (int i = 0; i < 16; i = i + 1) begin file[i] = $fopen(filenames[i], "r"); if (file[i] == 0) begin $display("Failed to open file: %s", filenames[i]); @@ -151,41 +169,41 @@ initial begin end end - always @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 4; i = i + 1) begin - reg_array[i] <= 16'd0; - end - end else if(vldi_data && source_mode == 3) begin - for (int i = 0; i < 4; i = i + 1) begin - status[i] = $fscanf(file[i], "%d\n", data[i]); - if (status[i] == 1 ) begin - reg_array[i] <= data[i]; - end - else begin - reg_array[i] <= 16'd0; - vldi_data <= 0; - end +always @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 16; i = i + 1) begin + reg_array[i] <= 16'd0; + end + end else if(vldi_data && source_mode == 3) begin + for (int i = 0; i < 16; i = i + 1) begin + status[i] = $fscanf(file[i], "%d\n", data[i]); + if (status[i] == 1 ) begin + reg_array[i] <= data[i]; end + else begin + reg_array[i] <= 16'd0; + vldi_data <= 0; + end end end +end -reg signed [15:0] iir_in[3:0]; +reg signed [15:0] iir_in[15:0]; always @(*) case(source_mode) 2'b01 : begin - for (int i = 0; i < 4; i = i + 1) begin + for (int i = 0; i < 16; i = i + 1) begin iir_in[i] = din_rect; end end 2'b10 : begin - for (int i = 0; i < 4; i = i + 1) begin + for (int i = 0; i < 16; i = i + 1) begin iir_in[i] = random_in[i]; end end 2'b11 : begin - for (int i = 0; i < 4; i = i + 1) begin + for (int i = 0; i < 16; i = i + 1) begin iir_in[i] = reg_array[i]; end end @@ -202,76 +220,103 @@ wire vldo; assign tc_bypass = 1'b0; -reg en; -always @(posedge clk or negedge rstn)begin - if(rstn==1'b0)begin - en <= 1; - end - else begin - en <= ~en; - end -end -wire signed [15:0] dout_p[7:0]; +//always @(posedge clk or negedge rstn)begin +// if(rstn==1'b0)begin +// en <= 1; +// end +// else begin +// en <= ~en; +// end +//end +wire signed [15:0] dout_p[15:0]; -z_dsp inst_z_dsp( - .rstn (rstn ), - .clk (clk ), - .en (en ), -// .tc_bypass (tc_bypass ), - .vldi_coef (vldi_coef ), - .vldi_data (vldi_data_r1 ), -// .intp_mode (intp_mode ), -// .dac_mode_sel (dac_mode_sel ), - .din0 (iir_in[0] ), - .din1 (iir_in[1] ), - .din2 (iir_in[2] ), - .din3 (iir_in[3] ), - .a0_re (a_re[0] ), - .b0_re (b_re[0] ), - .a1_re (a_re[1] ), - .b1_re (b_re[1] ), - .a2_re (a_re[2] ), - .b2_re (b_re[2] ), - .a3_re (a_re[3] ), - .b3_re (b_re[3] ), - .a4_re (a_re[4] ), - .b4_re (b_re[4] ), - .a5_re (a_re[5] ), - .b5_re (b_re[5] ), - .dout0 (dout_p[0] ), - .dout1 (dout_p[1] ), - .dout2 (dout_p[2] ), - .dout3 (dout_p[3] ), - .vldo ( vldo ) - ); - - -integer signed In_fid[0:3]; -integer signed dout_fid[0:7]; -string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; -string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"}; +z_dsp u_z_dsp( + .rstn ( rstn ), + .clk ( clk ), + .en ( en ), + .vldi_coef ( vldi_coef ), + .vldi_data ( vldi_data && vldi_data_r1 ), + .din0 ( iir_in[0] ), + .din1 ( iir_in[1] ), + .din2 ( iir_in[2] ), + .din3 ( iir_in[3] ), + .din4 ( iir_in[4] ), + .din5 ( iir_in[5] ), + .din6 ( iir_in[6] ), + .din7 ( iir_in[7] ), + .din8 ( iir_in[8] ), + .din9 ( iir_in[9] ), + .dina ( iir_in[10] ), + .dinb ( iir_in[11] ), + .dinc ( iir_in[12] ), + .dind ( iir_in[13] ), + .dine ( iir_in[14] ), + .dinf ( iir_in[15] ), + .a0_re ( a_re[0] ), + .b0_re ( b_re[0] ), + .a1_re ( a_re[1] ), + .b1_re ( b_re[1] ), + .a2_re ( a_re[2] ), + .b2_re ( b_re[2] ), + .a3_re ( a_re[3] ), + .b3_re ( b_re[3] ), + .a0_im ( a_im[0] ), + .b0_im ( b_im[0] ), + .a1_im ( a_im[1] ), + .b1_im ( b_im[1] ), + .a2_im ( a_im[2] ), + .b2_im ( b_im[2] ), + .a3_im ( a_im[3] ), + .b3_im ( b_im[3] ), + .dout0 ( dout_p[0] ), + .dout1 ( dout_p[1] ), + .dout2 ( dout_p[2] ), + .dout3 ( dout_p[3] ), + .dout4 ( dout_p[4] ), + .dout5 ( dout_p[5] ), + .dout6 ( dout_p[6] ), + .dout7 ( dout_p[7] ), + .dout8 ( dout_p[8] ), + .dout9 ( dout_p[9] ), + .douta ( dout_p[10] ), + .doutb ( dout_p[11] ), + .doutc ( dout_p[12] ), + .doutd ( dout_p[13] ), + .doute ( dout_p[14] ), + .doutf ( dout_p[15] ), + .vldo ( vldo ) +); +//integer signed In_fid[0:3]; +integer signed dout_fid[0:15]; +//string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"}; +string filenames_dout[0:15] = { + "dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", + "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat", + "dout8.dat", "dout9.dat", "dout10.dat", "dout11.dat", + "dout12.dat", "dout13.dat", "dout14.dat", "dout15.dat" +}; initial begin #0; - for (int i = 0; i < 4; i = i + 1) begin - In_fid[i] = $fopen(filenames_in[i]); - end - for (int i = 0; i < 4; i = i + 1) begin +// for (int i = 0; i < 4; i = i + 1) begin +// In_fid[i] = $fopen(filenames_in[i]); +// end + for (int i = 0; i < 16; i = i + 1) begin dout_fid[i] = $fopen(filenames_dout[i]); end end -always @(posedge clk) begin - if (vldi_data_r1) begin - for (int i = 0; i < 4; i = i + 1) begin - $fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); - end - end -end +//always @(posedge clk) begin +// if (vldi_data_r1) begin +// for (int i = 0; i < 4; i = i + 1) begin +// $fwrite(In_fid[i], "%d\n", $signed(iir_in[i])); +// end +// end +//end always @(posedge clk) begin if (vldo) begin - for (int i = 0; i < 4; i = i + 1) begin + for (int i = 0; i < 16; i = i + 1) begin $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i])); end end